Core cavity partial thick gold package shell, packaged device and preparation method

Abstract

The application provides a core cavity local thick gold sealing packaging shell, a packaged device and a preparation method, and belongs to the technical field of ceramic packaging, and comprises a ceramic piece with a core cavity, the bottom of the core cavity is divided into at least one chip mounting area and at least one passive device mounting area; the chip mounting area is provided with a sunken cavity, the bottom of the sunken cavity is at a different horizontal plane from the passive device mounting area; wherein the sunken cavity is a thick gold area, and the passive device mounting area is a thin gold area; the bottom of the sunken cavity is provided with a first gold plating layer, the passive device mounting area is provided with a second gold plating layer, and the thickness of the first gold plating layer is greater than that of the second gold plating layer. The bonding fingers of the thick gold part are sunken in the vertical direction of the ceramic piece, so that the thick gold part is lower than the thin gold part, thereby realizing the effect of different plating layer thicknesses in different areas inside the same ceramic piece, meeting the use requirements of low-temperature solder sintering and gold wire bonding, and meeting the requirements of high reliability of power supply SIP products with gradually increasing current and power consumption.

Description

Technical Field

[0001] This invention belongs to the field of ceramic packaging technology, specifically relating to a partially thick gold encapsulation shell for the core cavity, a packaging device having a chip and passive components, and a method for preparing the partially thick gold encapsulation shell for the core cavity. Background Technology

[0002] Conventional power supply SIP (System-in-Package) products integrate multiple chips and passive components, such as capacitors, resistors, and inductors. The chip bonding area, the pads for resistors, capacitors, and inductors, and the chip bonding area are all on the same plane. The chips, resistors, capacitors, and inductors are connected to the corresponding pads on the ceramic components using adhesive bonding. The gold layer thickness for soldering needs to be controlled between 1.3µm and 5.7µm. However, with increasing current and power consumption, especially in some specialized applications, there is a need for highly reliable, high-level power supply SIP products.

[0003] To achieve high reliability requirements, chips need to be bonded with gold wire, requiring a gold layer thickness of 1.3µm to 5.7µm for the corresponding bonding areas of the ceramic component. Resistors, capacitors, and inductors, to reduce contact resistance and increase reliability, need to be soldered to the corresponding pads on the ceramic component, requiring a gold layer thickness controlled between 0.03µm and 0.5µm for soldering. Conventionally, the gold plating at the chip bonding areas is considered a thick gold area, while the gold plating at passive device areas is considered a thin gold area. Thin and thick gold plating need to be designed in different cavities to achieve high reliability. However, due to the limited internal component layout of most ceramic components, conventional plating and processing methods cannot achieve both thin and thick gold plating within the same ceramic component. Summary of the Invention

[0004] This invention provides a partially thick gold encapsulation shell, encapsulation device, and manufacturing method for a chip cavity. By setting an uneven plane at the bottom of the chip cavity, a suitable mounting plane is provided for the chip and passive devices, thereby achieving high reliability of the encapsulation device.

[0005] In a first aspect, embodiments of the present invention provide a cavity-partially thick gold encapsulation shell, comprising: a ceramic component having a cavity, the bottom of which is divided into at least one chip mounting area and at least one passive device mounting area; the chip mounting area is provided with a recessed cavity, the bottom of which is at a different level from the passive device mounting area; wherein, the recessed cavity contains a thick gold area, and the passive device mounting area contains a thin gold area; the bottom of the recessed cavity is provided with a first gold plating layer, and the passive device mounting area is provided with a second gold plating layer, wherein the thickness of the first gold plating layer is greater than the thickness of the second gold plating layer.

[0006] In conjunction with the first aspect, in one possible implementation, the minimum height difference between the bottom of the recessed cavity and the passive device mounting area is 0.3 mm.

[0007] In conjunction with the first aspect, in one possible implementation, the top surface of the first gold plating layer and the top surface of the second gold plating layer are on different horizontal planes.

[0008] In conjunction with the first aspect, in one possible implementation, when there are multiple sinking cavities, the sinking cavities have different shapes depending on the corresponding chip.

[0009] In conjunction with the first aspect, in one possible implementation, the bottom surfaces of each of the sinking cavities are at the same horizontal plane.

[0010] In conjunction with the first aspect, in one possible implementation, the first gold plating layer within each of the sinking cavities is at the same horizontal plane.

[0011] In conjunction with the first aspect, in one possible implementation, the thickness of the first gold plating layer is 1.3 μm to 5.7 μm.

[0012] In conjunction with the first aspect, in one possible implementation, the thickness of the second gold plating layer is 0.03um to 0.5um.

[0013] Secondly, embodiments of the present invention also provide a cavity partially thick gold packaged device, including the cavity partially thick gold packaged shell, a chip mounted in the chip mounting area, the chip being bonded to the first gold plating layer by bonding wires, and a passive device mounted in the passive device mounting area.

[0014] Thirdly, embodiments of the present invention also provide a method for preparing a partially thick gold encapsulated shell with a core cavity. Based on the partially thick gold encapsulated shell with a core cavity, the preparation method includes the following steps:

[0015] At the bottom of the core cavity of the ceramic component, a chip mounting area and a passive device mounting area are divided according to a preset position;

[0016] In the chip mounting area, a recessed cavity is provided on the outer side of the chip bonding point, so that the bottom of the cavity forms planes of different heights.

[0017] The passive component mounting area is covered with solder resist.

[0018] Gold plating was performed inside the uncovered sunken cavity;

[0019] Remove the solder resist from the passive component mounting area;

[0020] Then, the bottom of the core cavity is plated with gold.

[0021] Compared with the prior art, the core cavity partially thick gold encapsulation shell, encapsulation device and preparation method provided by the present invention have the following advantages: The present invention adopts the method of sinking the bonding fingers of the thick gold part vertically in the ceramic part, so that it is lower than the thin gold part, thereby achieving the effect of different plating thicknesses in different areas inside the same ceramic part, meeting the use requirements of low temperature solder sintering and gold wire bonding, and meeting the high reliability performance requirements of power supply SIP products with gradually increasing current and power consumption, and adapting to the use requirements of some special application fields. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of a partially thick gold encapsulation shell for the core cavity provided in an embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of the structure of a partially thick gold packaged device in the cavity provided in an embodiment of the present invention;

[0024] Explanation of reference numerals in the attached figures:

[0025] 1. Pin; 2. Ceramic component; 3. Capacitor; 4. Recessed cavity; 5. Chip; 6. Bonding wire; 7. Inductor; 8. Passive component mounting area; 9. Core cavity. Detailed Implementation

[0026] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0027] Please refer to the following: Figure 1 and Figure 2 The present invention will now describe the cavity-partially thick gold encapsulation shell provided by the present invention. The cavity-partially thick gold encapsulation shell includes: a ceramic part 2 having a cavity 9, the bottom of the cavity 9 being divided into at least one chip mounting area and at least one passive device mounting area 8; the chip mounting area having a recessed cavity 4, the bottom of the recessed cavity 4 being at a different level from the passive device mounting area 8; wherein, the recessed cavity 4 is a thick gold area, and the passive device mounting area 8 is a thin gold area; the bottom of the recessed cavity 4 is provided with a first gold plating layer, and the passive device mounting area 8 is provided with a second gold plating layer, the thickness of the first gold plating layer being greater than the thickness of the second gold plating layer.

[0028] Compared with the prior art, the core cavity partially thick gold package shell provided in this embodiment adopts the method of sinking the bonding fingers of the thick gold part in the vertical direction of the ceramic part 2, so that it is lower than the thin gold part, thereby achieving the effect of different plating thicknesses in different areas inside the same ceramic part 2, meeting the use requirements of low temperature solder sintering and gold wire bonding, and meeting the high reliability performance requirements of power supply SIP products with gradually increasing current and power consumption, adapting to the use requirements of some special application fields such as aerospace.

[0029] In this embodiment, the bonding cavity of the chip mounting area serves as a thick gold region, i.e., the first gold plating layer, while the passive device mounting area serves as a thin gold region, i.e., the second gold plating layer. The chip is bonded to the first gold plating layer via bonding wire 6, achieving a reliable connection of the chip. Passive devices are soldered to the second gold plating layer to reduce contact resistance and improve reliability.

[0030] The core cavity partially thick gold package shell is mainly composed of ceramic components, sealing rings, leads, insulating ceramic strips (if necessary), and heat sinks (if necessary). The ceramic component material is 90% alumina, and it is made by high-temperature co-firing process of multi-layer alumina ceramic tungsten metallization. The sealing ring material is iron-nickel-cobalt alloy, the lead material is iron-nickel alloy, and the heat sink material is tungsten copper, molybdenum copper, and CPC alloys. The ceramic component is welded to the sealing ring, leads, and heat sink with silver-copper solder.

[0031] The ceramic component provided in this embodiment may have multiple polygonal cavities for accommodating chips or passive devices; it may have a wiring structure of 2 to 100 layers. The packaging form and lead-out form of the package are not limited, and can adopt packaging forms such as CQFP, CSOP, CLCC, CPGA, CDIP, and CLGA.

[0032] In some embodiments, an inductor mounting area, a capacitor mounting area, and multiple chip mounting areas are provided. All passive device mounting areas 8 are on the same horizontal plane.

[0033] In some embodiments, as an improved implementation of the cavity partially thick gold encapsulation shell provided in this embodiment, see [link to relevant documentation]. Figure 1 The minimum vertical height difference between the bottom of the recessed cavity 4 and the passive device mounting area 8 is 0.3mm, which provides structural conditions for the different thicknesses of the gold plating layers in the chip mounting area and the passive device mounting area 8.

[0034] As an improved implementation method, see [link to implementation details]. Figure 1 The top surfaces of the first and second gold plating layers are on different horizontal planes (the gold plating layers are not shown in the figure). After the bottom of the recessed cavity 4 and the core cavity 9 are gold-plated, the recessed cavity 4 remains a recessed structure, and the bottom of the core cavity 9 remains uneven. This achieves the effect of different plating thicknesses and different planes in different areas inside the same ceramic part 2.

[0035] As a modified embodiment of the aforementioned ceramic component 2, see [link to relevant documentation]. Figure 2 When there are multiple recessed cavities 4, each cavity 4 has a different shape depending on the corresponding chip. Different functional chips can be housed within a single ceramic component 2. Due to the different bonding points of these chips, different shaped recessed cavities 4 are required to facilitate bonding between the chip and the gold plating layer. The shapes of the recessed cavities 4 include linear, L-shaped, and semi-enclosed types.

[0036] As a modified embodiment of the aforementioned ceramic component 2, see [link to relevant documentation]. Figure 1 When multiple recessed cavities 4 are provided, the bottom surfaces of each recessed cavity 4 are at the same horizontal plane. This facilitates processing, fabrication, and bonding.

[0037] like Figure 1 , Figure 2 As shown, with the bottom surfaces of each sinking cavity 4 at the same horizontal level, the first gold plating layer inside each sinking cavity 4 is at the same horizontal level.

[0038] As a modified embodiment of the aforementioned ceramic component 2, the thickness of the first gold plating layer is 1.3um to 5.7um to meet the requirements of the bonding alloy layer thickness for high reliability of the chip.

[0039] As a modified embodiment of the aforementioned ceramic component 2, the thickness of the second gold plating layer is 0.03um to 0.5um, in order to meet the requirements of reducing contact resistance and high reliability for passive components such as resistors, inductors 7 and capacitors 3.

[0040] Based on the same inventive concept, see [link to inventive concept] Figure 1 This application also provides a cavity-partially thick gold package device, including a cavity-partially thick gold package shell, a chip mounting area with a chip 5, the chip 5 being bonded to a first gold plating layer via bonding wires 6, and a passive device mounting area 8 containing passive devices. The gold plating layer at the chip bonding area is a thick gold area, while the gold plating layer at the passive device area is a thin gold area. The thick and thin gold plating layers are designed within the same cavity 9 to achieve high reliability requirements. Furthermore, pins 1 are provided around the bottom perimeter of the ceramic component 2, and steps are provided on the outer sidewall of the ceramic component 2 to facilitate the connection of the package cover.

[0041] The packaging device provided in this embodiment has the following advantages:

[0042] (1) Miniaturization: This type of housing encapsulates multiple chips, resistors, capacitors, plastic encapsulation devices and other devices with different functions into a hermetically sealed housing, replacing the original single package, effectively realizing miniaturization of the package.

[0043] (2) Excellent electrical performance. The welding method reduces the welding contact resistance of chips, resistors, capacitors and inductors. In addition, since this type of housing encapsulates multiple bare chips in one housing, compared with ordinary ceramic housing products, it can optimize system wiring to the maximum extent and shorten interconnects, thus significantly reducing signal noise and delay in high-frequency and high-speed circuits.

[0044] (3) High integration: This type of housing has one or more cavities, which can house multiple chips and various passive components, meeting the user's high integration packaging requirements.

[0045] (4) High reliability: Since the internal chips, capacitors, resistors, and inductors are all connected to the corresponding pads on the package using soldering, this soldering method, compared to adhesive bonding, will not experience aging or degradation during subsequent use, nor will it release gases that affect the internal atmosphere of the package. Therefore, the reliability of the device can be effectively improved by adopting this invention. This is especially true in some high-level, high-current, and high-power SIP products.

[0046] Based on the same inventive concept, this application also provides a method for preparing a partially thick gold encapsulation shell with a core cavity. The preparation method includes the following steps:

[0047] Step 1: At the bottom of the core cavity 9 of the ceramic component 2, divide the chip mounting area and the passive device mounting area 8 according to the preset position;

[0048] Step 2: In the chip mounting area, a recessed cavity 4 is set on the outer side of the chip bonding point, so that the bottom of the cavity 9 forms a plane with different heights;

[0049] Step 3: Use solder resist to cover the passive component mounting area 8;

[0050] Step 4: Gold plating inside the uncovered sunken cavity 4;

[0051] Step 5: Remove the solder resist from passive component mounting area 8;

[0052] Step six: Then, plate the bottom of core cavity 9 with gold.

[0053] This invention utilizes a structural design to lower the cavity in the thick gold region, achieving a minimum height difference of 0.30mm in the vertical direction between it and the thin gold region. This effectively separates the bonding and soldering areas, which were originally on the same plane, into two planes. During gold plating, solder resist is first used to cover the thin gold region. Once the thick gold region is plated to a thickness of 2µm ± 1µm, the solder resist is removed, and the entire area is then plated with a thin gold layer. This ultimately achieves the effect of different plating thicknesses in different areas within the same cavity, meeting the requirements for low-temperature solder sintering and gold wire bonding. If the cavity in the thick gold region is not lowered, the solder resist, due to its fluidity, will spread and diffuse during the coating process, potentially covering the thick gold region as well, making it impossible to achieve different plating thicknesses in different areas within the same ceramic component.

[0054] This embodiment employs multilayer co-firing technology using Al2O3, ALN, and glass-ceramic materials. The specific process is as follows: After the outer shell is cast and hot-cut, it is punched with cavities and holes, and the holes are metallized. Then, it is printed, positioned, laminated, and hot-cut into individual green ceramic parts. After sintering and brazing, it forms individual ceramic assemblies. Then, the thin gold area inside the encapsulation shell cavity is covered with solder resist, and the thick gold area is plated. When the gold layer in the thick gold area reaches the required thickness, the photoresist coated inside the shell is cleaned, and then the thin gold area is plated again. Finally, the plating process of all areas of the shell is completed.

[0055] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A partially thick gold encapsulation shell for a core cavity, characterized in that, include: A ceramic component (1) has a core cavity (9), the bottom of which is divided into at least one chip mounting area and at least one passive device mounting area (8). The chip mounting area is provided with a recessed cavity (4), the bottom of which is at a different level from the passive device mounting area (8); wherein, the recessed cavity (4) is a thick gold area and the passive device mounting area (8) is a thin gold area; The bottom of the recessed cavity (4) is provided with a first gold plating layer, and the passive device mounting area (8) is provided with a second gold plating layer. The thickness of the first gold plating layer is greater than the thickness of the second gold plating layer. The bonding fingers of the thick gold region are lowered vertically into the ceramic part, making them lower than the thin gold region; The bonding cavity of the chip mounting area serves as the thick gold area, i.e., the first gold plating layer, and the passive device mounting area (8) serves as the thin gold area, i.e., the second gold plating layer. The chip is bonded to the first gold plating layer by bonding wire (6) to achieve reliable connection of the chip; the passive device is soldered to the second gold plating layer to reduce contact resistance and improve reliability. The cavity in the thick gold region is lowered to achieve a minimum height difference of 0.30mm in the vertical direction with the thin gold region. This divides the bonding and welding areas, which were originally on the same plane, into two planes. During the gold plating process, the thin gold region is first covered with solder resist, and the gold layer in the thick gold region is plated to 2um±1um. Then, the solder resist is removed and the entire area is plated with thin gold. This achieves the effect of different plating thicknesses in different areas within the same cavity, meeting the requirements for low-temperature solder sintering and gold wire bonding.

2. The core cavity partially thick gold encapsulation shell as described in claim 1, characterized in that, The minimum height difference between the bottom of the recessed cavity (4) and the passive device mounting area (8) is 0.3 mm.

3. The core cavity partially thick gold encapsulation shell as described in claim 1, characterized in that, The top surface of the first gold plating layer and the top surface of the second gold plating layer are on different horizontal planes.

4. The core cavity partially thick gold encapsulation shell as described in claim 1, characterized in that, When there are multiple sinking cavities (4), the sinking cavities (4) have different shapes depending on the corresponding chip.

5. The core cavity partially thick gold encapsulation shell as described in claim 1, characterized in that, The bottom surfaces of each of the sinking cavities (4) are at the same horizontal plane.

6. The core cavity partially thick gold encapsulation shell as described in claim 5, characterized in that, The first gold plating layer in each of the sinking cavities (4) is at the same horizontal plane.

7. The core cavity partially thick gold encapsulation shell as described in claim 1, characterized in that, The thickness of the first gold plating layer is 1.3um to 5.7um.

8. The core cavity partially thick gold encapsulation shell as described in claim 1, characterized in that, The thickness of the second gold plating layer is 0.03um to 0.5um.

9. A partially thick gold packaged device with a core cavity, characterized in that, The chip cavity (9) includes a partially thick gold packaged shell as described in any one of claims 1-8, wherein the chip mounting area is provided with a chip (5), the chip (5) is bonded to the first gold plating layer by a bonding wire (6), and the passive device mounting area (8) is provided with a passive device.

10. A method for preparing a cavity partially thick gold encapsulation shell, based on the cavity (9) partially thick gold encapsulation shell as described in any one of claims 1-8, characterized in that, The preparation method includes the following steps: At the bottom of the core cavity (9) of the ceramic part (1), a chip mounting area and a passive device mounting area (8) are divided according to a preset position. In the chip mounting area, a recessed cavity (4) is provided on the outer side of the chip bonding point, so that the bottom of the cavity (9) forms a plane with different heights; The passive device mounting area is covered with solder resist (8); Gold plating was performed inside the uncovered sunken cavity (4); Remove the solder resist from the passive device mounting area (8); Then, the bottom of the core cavity (9) is plated with gold.

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