Universal JTAG debugging method and system with scalable interface

Abstract

The present invention provides a universal JTAG debugging method and system with an expandable interface, comprising: encapsulating a JTAG host controller into an IP device of a peripheral bus port; invoking the hardware resources within a development board, attaching the JTAG host IP to the hardware system, and completing the minimum hardware field programmable gate array design of the debugging system; completing the boot loader porting work according to the characteristics of the development board; compiling within the ported boot loader, and solidifying the binary file into the development board; connecting a debugging device with a host computer, and connecting the debugging device with a target debugging chip; the host computer running hyperterminal software, and completing the target chip debugging work through data JTAG debugging instructions. The present invention can be flexibly integrated into an embedded system having a processor core, RAM, ROM, GPIO pins, JTAG_MASTER, and UART devices, completing the construction of the debugging system hardware part, and has flexibility; the modular JTAGMaster controller can realize JTAG protocol conversion and simultaneously connect multiple JTAG devices with the same or different characteristics.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic equipment maintenance, and in particular to a universal JTAG debugging method and system with an expandable interface. Background Art

[0002] The integrated circuit industry has developed in accordance with Moore's Law, with the scale of integrated circuits increasing, and the circuits that can be integrated on a single chip becoming increasingly complex. This means that during the chip development phase, risks such as unknown failures, material defects, and manufacturing variations are more likely to occur. This can lead to chips returning from tapeout not functioning as expected or performing suboptimally. Therefore, based on chip testability design considerations, the IEEE 1149.1 standard was released in 1990. Currently, commercially available ARM processors, PowerPC processors, and complex control devices such as PCIE PHY, SATA PHY, and EMMC controllers all integrate testability hardware logic based on the IEEE 1149.1 protocol, tailored to their respective device characteristics. These devices also provide a JTAG debug interface, enabling hardware-based in-circuit debugging of the device.

[0003] The debugging systems provided with each device are highly specialized, expensive, and often developed by foreign companies. For example, the JTAG debugging system for the ARM processor series is the J-Link emulator debugger and supporting software provided by Germany's SEGGER. Currently, there are only distributors in China, and no domestic versions exist. The debugging system for the PowerPC processor series is the RISCWatch emulator debugger and supporting software provided by IBM in the United States. TRACE32, later developed by Germany's Lauterbach, supports JTAG and BDM interfaces and debugging of all CPUs, but is even more expensive, costing over 10,000 yuan per unit. All of the aforementioned debugging devices connect to the host PC via a USB port and require accompanying application software as an interactive interface. The installation of this application software requires the host computer's operating system, and support for domestic operating systems like the Kylin processor is limited.

[0004] The current issues that need to be addressed are: 1. The procurement price of debugging equipment is too high and it is provided by foreign companies. Currently, some foreign policies toward China need to be vigilant, and there is a demand for domestic production of tools related to chip research and development; 2. The debuggers on the market, such as Jlink, trace32, and riscwatch, use USB ports, and the host computer needs to run supporting application software, which does not have good support for domestic operating systems; 3. The debugging equipment on the market cannot simultaneously connect to multiple devices with different characteristics for debugging. For example, a chip with an integrated ARM processor core and PCIE controller can be jointly debugged with another PCIE chip. The current practice is to connect three TRACE32 debuggers to the ARM processor JTAG interface and the master and slave PCIE PHYJTAG interfaces respectively. The TRACE32 software environment requires the host computer to have three free USB ports or to connect three host computers separately, which requires a lot of hardware resources. If a TRACE32 is switched back and forth, the test operation may be complicated and the phenomenon cannot be observed simultaneously, which is not conducive to problem location. Therefore, the present invention provides a universal JTAG debugging system with an expandable interface, which is connected to a host computer via a serial port. The interactive interface uses a serial port debugging assistant such as a hyperterminal. It does not require the host computer system environment. It is used to solve the problem of localization of the debugging system and the problem of being able to simultaneously connect multiple debugging devices with different characteristics, thereby realizing the online debugging function of multiple devices.

[0005] Patent document CN113268031A (application number: CN202110631019.6) provides a system and method for electronic equipment remote debugging tools, which relates to the field of electronic equipment maintenance technology. The system includes a JTAG service program, an application running in the Linux operating system, which is used to interact with the remote program and perform client data transmission and reception, providing data transmission and reception functions; a hardware board that provides FPGA resources to form an embedded hardware environment, uses the FPGA resources provided by the hardware board to form an embedded minimum system, and adds the hardware modules necessary for FPGA remote debugging. It adopts the method of completing FPGA debugging over Ethernet, and designs a server program in the JTAG data processing program to make remote operation of the network communication protocol a reality. The FPGA chip is accessed through a specified network address, achieving the purpose of multiple people accessing the same chip and debugging multiple FPGA chips, thereby making the FPGA debugging method more extensive and convenient. However, the development of the firmware of this invention relies on an environment other than the Uboot system, and cannot run well on various operating systems, and its compatibility is insufficient.

[0006] Patent document CN107290656B (application number: CN201710452885.2) discloses an expandable JTAG debugging structure with integrated bidirectional CRC check function, including a debugging master controller and a debugging sub-controller; the debugging master controller receives data from the JTAG interface, performs data verification and instruction parsing, and then sends the verified data to the corresponding debugging sub-controller for further processing and execution. The debugging sub-controller accepts the control of the debugging master controller and, in accordance with the corresponding data instructions, implements debugging operations on the debugging object and returns debugging data; the JTAG debugging structure of the present invention implements a bidirectional 32-bit CRC serial data check function based on support for IEEE1149.1 standard JTAG timing, can detect anomalies that occur during data transmission, and improve the reliability of the data transmission process. However, the invention does not have a modular JTAG Master controller, cannot implement JTAG protocol conversion, and cannot simultaneously connect multiple JTAG devices with the same or different characteristics, and its scalability is insufficient.

[0007] The English abbreviations are explained as follows:

[0008] JTAG (Joint Test Action Group)

[0009] Uboot (Universal Boot Loader)

[0010] JTAG Master (Joint Test Action Group Master, JTAG host)

[0011] ROM (Read-Only Memory)

[0012] RAM (Random Access Memory)

[0013] GPIO (General-Purpose Input / Output)

[0014] AMBA (Advanced Microcontroller Bus Architecture)

[0015] APB (Advanced Peripheral Bus)

[0016] TMS (Test Mode Select)

[0017] TCK (Test Clock)

[0018] TDI (Test Data In)

[0019] TDO (Test Data Out)

[0020] TRSTn (Test Reset)

[0021] TAP (Test Access Port)

[0022] Menuconfig(menu config, menu configuration)

[0023] EDA (Electronic design automation)

[0024] Zynq-7000 (an FPGA product from Xilinx, with no English abbreviation or meaning on the official website)

[0025] DDR (Double Data Rate SDRAM)

[0026] SPI Flash (Serial Peripheral interface flash)

[0027] UART (Universal Asynchronous Receiver / Transmitter)

[0028] FPGA (Field Programmable Gate Array)

[0029] CMD (Command) Summary of the Invention

[0030] In view of the defects in the prior art, the object of the present invention is to provide a universal JTAG debugging method and system with an expandable interface.

[0031] According to the present invention, a universal JTAG debugging method with an expandable interface is provided, comprising:

[0032] Step S1: The JTAG host controller is encapsulated as an IP device of a peripheral bus port;

[0033] Step S2: Call the hardware resources in the development board, connect the JTAG host IP to the hardware system, and complete the minimum hardware field programmable gate array design of the debugging system;

[0034] Step S3: According to the characteristics of the development board, complete the boot loader program transplantation work;

[0035] Step S4: compile the ported boot loader and solidify the binary file into the development board;

[0036] Step S5: The debugging device and the host computer, the debugging device and the target debugging chip, the host computer runs the hyperterminal software, and completes the target chip debugging work through the data JTAG debugging instructions.

[0037] Preferably, the debugging system integrates a CPU core, serial port, ROM, RAM, self-developed JTAG host controller, and general input and output pins;

[0038] The serial port is connected to the interactive port of the host PC; the ROM is used to store the fixed debugging application software; the RAM is used as the storage space required for software operation; the general input and output pins are used for the JTAG external communication interface; and the JTAG host controller is used to implement protocol conversion operations.

[0039] Preferably, in step S1:

[0040] The JTAG host controller converts data into JTAG signal output according to the IEEE1149.1 protocol. The JTAG host controller interface design selects the AMBA APB interface protocol. In order to realize the online simultaneous connection of multiple devices for debugging, the JTAG interface signals are designed, including test mode selection, test clock, test data output, test data input, and test reset;

[0041] According to the TAP state machine design of the IEEE1149.1 protocol, state transition is controlled by TMS. The JTAG MASTER controller defines 16 states for controlling TMS signal output, including: ST_TLR logic reset state, ST_RTI run idle state, ST_SDR select data scan state, ST_CDR data capture state, ST_SHD data shift state, ST_E1D data exit 1 state, ST_E2D data exit 2 state, ST_PDR data transmission pause state, ST_UDR update data value state, ST_SIR select instruction scan state, ST_CIR instruction capture state, ST_SHI instruction shift state, ST_E1I instruction exit 1 state, ST_PIR instruction transmission pause state, ST_E2I instruction exit 2 state, ST_UIR update instruction value state, to realize the conversion of register configuration instructions into JTAG protocol and transmit them to the target debugging device;

[0042] The JTAG host provides registers with corresponding functions for the JTAG interface.

[0043] Preferably, in step S3:

[0044] Firmware development that matches the hardware is based on the Uboot environment. UBoot is a boot program before the embedded operating system starts. The code is open source and can support a variety of embedded processors.

[0045] Preferably, in step S4:

[0046] According to the file format, add command configuration option information of the JTAG host, define a set of debugging instructions for each JTAG interface, and select whether to add the debugging system firmware to the UBoot compilation environment in the JTAG host configuration option. After successful selection, compile and generate a bin file, and solidify the content into the debugging device through electronic design automation tools.

[0047] According to the present invention, a universal JTAG debugging system with an expandable interface is provided, comprising:

[0048] Module M1: JTAG host controller encapsulated as an IP device of the peripheral bus port;

[0049] Module M2: Calls the hardware resources built into the development board, connects the JTAG host IP to the hardware system, and completes the minimum hardware field programmable gate array design of the debugging system;

[0050] Module M3: Complete the boot loader porting work according to the characteristics of the development board;

[0051] Module M4: compiles the ported boot loader and fixes the binary file to the development board;

[0052] Module M5: debugging device and host computer, debugging device and target debugging chip, the host computer runs the hyperterminal software, and completes the target chip debugging work through data JTAG debugging instructions.

[0053] Preferably, the debugging system integrates a CPU core, serial port, ROM, RAM, self-developed JTAG host controller, and general input and output pins;

[0054] The serial port is connected to the interactive port of the host PC; the ROM is used to store the fixed debugging application software; the RAM is used as the storage space required for software operation; the general input and output pins are used for the JTAG external communication interface; and the JTAG host controller is used to implement protocol conversion operations.

[0055] Preferably, in the module M1:

[0056] The JTAG host controller converts data into JTAG signal output according to the IEEE1149.1 protocol. The JTAG host controller interface design selects the AMBA APB interface protocol. In order to realize the online simultaneous connection of multiple devices for debugging, the JTAG interface signals are designed, including test mode selection, test clock, test data output, test data input, and test reset;

[0057] According to the TAP state machine design of the IEEE1149.1 protocol, state transition is controlled by TMS. The JTAG MASTER controller defines 16 states for controlling TMS signal output, including: ST_TLR logic reset state, ST_RTI run idle state, ST_SDR select data scan state, ST_CDR data capture state, ST_SHD data shift state, ST_E1D data exit 1 state, ST_E2D data exit 2 state, ST_PDR data transmission pause state, ST_UDR update data value state, ST_SIR select instruction scan state, ST_CIR instruction capture state, ST_SHI instruction shift state, ST_E1I instruction exit 1 state, ST_PIR instruction transmission pause state, ST_E2I instruction exit 2 state, ST_UIR update instruction value state, to realize the conversion of register configuration instructions into JTAG protocol and transmit them to the target debugging device;

[0058] The JTAG host provides registers with corresponding functions for the JTAG interface.

[0059] Preferably, in the module M3:

[0060] Firmware development that matches the hardware is based on the Uboot environment. UBoot is a boot program before the embedded operating system starts. The code is open source and can support a variety of embedded processors.

[0061] Preferably, in the module M4:

[0062] According to the file format, add command configuration option information of the JTAG host, define a set of debugging instructions for each JTAG interface, and select whether to add the debugging system firmware to the UBoot compilation environment in the JTAG host configuration option. After successful selection, compile and generate a bin file, and solidify the content into the debugging device through electronic design automation tools.

[0063] Compared with the prior art, the present invention has the following beneficial effects:

[0064] 1. It can be flexibly integrated into embedded systems with processor cores, RAM, ROM, GPIO pins, JTAG_MASTER, and UART devices to complete the construction of the hardware part of the debugging system with flexibility;

[0065] 2. The self-developed JTAG Master controller module can realize JTAG protocol conversion and simultaneously connect multiple JTAG devices with the same or different characteristics, realizing multi-device online debugging. The number of online debugging hardware can be customized as needed, which is scalable.

[0066] 3. The development of the firmware relies on the Uboot system. To send debugging commands, the host computer only needs to install a serial port debugging assistant such as a super terminal as an interactive interface. There are almost no excessive requirements for the performance of the host system configuration machine. It can run well on various operating systems and has compatibility.

[0067] 4. UBoot is the boot program before the embedded operating system starts. The code is open source and can support a variety of embedded processors (PowrPC, ARM, MIPS, x86, XScale, etc.). The code is highly reliable and stable, which means that choosing UBoot as the firmware development environment for the debugging system has a good hardware support foundation. It also means that when designing and applying the debugging system hardware, it can support the selection of processor types covering PowerPC, ARM, x86, etc., and has a certain degree of versatility. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] Other features, objects and advantages of the present invention will become more apparent upon reading the detailed description of non-limiting embodiments with reference to the following drawings:

[0069] Figure 1 This is a simplified diagram of the debugging system communication;

[0070] Figure 2 The hardware structure diagram of the debugging system;

[0071] Figure 3 It is the state machine of Jtag_Master controller;

[0072] Figure 4 Build a debugging system for zynq-7000;

[0073] Figure 5 It is the debugging system application interface. DETAILED DESCRIPTION

[0074] The present invention will be described in detail below with reference to specific embodiments. The following examples will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those skilled in the art, several changes and improvements can be made without departing from the scope of the present invention. These all fall within the scope of protection of the present invention.

[0075] Example 1:

[0076] According to the present invention, a universal JTAG debugging method with an expandable interface is provided, comprising:

[0077] Step S1: The JTAG host controller is encapsulated as an IP device of a peripheral bus port;

[0078] Step S2: Call the hardware resources in the development board, connect the JTAG host IP to the hardware system, and complete the minimum hardware field programmable gate array design of the debugging system;

[0079] Step S3: According to the characteristics of the development board, complete the boot loader program transplantation work;

[0080] Step S4: compile the ported boot loader and solidify the binary file into the development board;

[0081] Step S5: The debugging device and the host computer, the debugging device and the target debugging chip, the host computer runs the hyperterminal software, and completes the target chip debugging work through the data JTAG debugging instructions.

[0082] Specifically, the debugging system integrates a CPU core, serial port, ROM, RAM, a self-developed JTAG host controller, and general input and output pins;

[0083] The serial port is connected to the interactive port of the host PC; the ROM is used to store the fixed debugging application software; the RAM is used as the storage space required for software operation; the general input and output pins are used for the JTAG external communication interface; and the JTAG host controller is used to implement protocol conversion operations.

[0084] Specifically, in step S1:

[0085] The JTAG host controller converts data into JTAG signal output according to the IEEE1149.1 protocol. The JTAG host controller interface design selects the AMBA APB interface protocol. In order to realize the online simultaneous connection of multiple devices for debugging, the JTAG interface signals are designed, including test mode selection, test clock, test data output, test data input, and test reset;

[0086] According to the TAP state machine design of the IEEE1149.1 protocol, state transition is controlled by TMS. The JTAG MASTER controller defines 16 states for controlling TMS signal output, including: ST_TLR logic reset state, ST_RTI run idle state, ST_SDR select data scan state, ST_CDR data capture state, ST_SHD data shift state, ST_E1D data exit 1 state, ST_E2D data exit 2 state, ST_PDR data transmission pause state, ST_UDR update data value state, ST_SIR select instruction scan state, ST_CIR instruction capture state, ST_SHI instruction shift state, ST_E1I instruction exit 1 state, ST_PIR instruction transmission pause state, ST_E2I instruction exit 2 state, ST_UIR update instruction value state, to realize the conversion of register configuration instructions into JTAG protocol and transmit them to the target debugging device;

[0087] The JTAG host provides registers with corresponding functions for the JTAG interface.

[0088] Specifically, in step S3:

[0089] Firmware development that matches the hardware is based on the Uboot environment. UBoot is a boot program before the embedded operating system starts. The code is open source and can support a variety of embedded processors.

[0090] Specifically, in step S4:

[0091] According to the file format, add command configuration option information of the JTAG host, define a set of debugging instructions for each JTAG interface, and select whether to add the debugging system firmware to the UBoot compilation environment in the JTAG host configuration option. After successful selection, compile and generate a bin file, and solidify the content into the debugging device through electronic design automation tools.

[0092] Example 2:

[0093] Example 2 is a preferred example of Example 1 and is used to illustrate the present invention in more detail.

[0094] Those skilled in the art may understand the interface-scalable and universal JTAG debugging method provided by the present invention as a specific implementation of the interface-scalable and universal JTAG debugging system, that is, the interface-scalable and universal JTAG debugging system may be implemented by executing the step flow of the interface-scalable and universal JTAG debugging method.

[0095] According to the present invention, a universal JTAG debugging system with an expandable interface is provided, comprising:

[0096] Module M1: JTAG host controller encapsulated as an IP device of the peripheral bus port;

[0097] Module M2: Calls the hardware resources built into the development board, connects the JTAG host IP to the hardware system, and completes the minimum hardware field programmable gate array design of the debugging system;

[0098] Module M3: Complete the boot loader porting work according to the characteristics of the development board;

[0099] Module M4: compiles the ported boot loader and fixes the binary file to the development board;

[0100] Module M5: debugging device and host computer, debugging device and target debugging chip, the host computer runs the hyperterminal software, and completes the target chip debugging work through data JTAG debugging instructions.

[0101] Specifically, the debugging system integrates a CPU core, serial port, ROM, RAM, a self-developed JTAG host controller, and general input and output pins;

[0102] The serial port is connected to the interactive port of the host PC; the ROM is used to store the fixed debugging application software; the RAM is used as the storage space required for software operation; the general input and output pins are used for the JTAG external communication interface; and the JTAG host controller is used to implement protocol conversion operations.

[0103] Specifically, in the module M1:

[0104] The JTAG host controller converts data into JTAG signal output according to the IEEE1149.1 protocol. The JTAG host controller interface design selects the AMBA APB interface protocol. In order to realize the online simultaneous connection of multiple devices for debugging, the JTAG interface signals are designed, including test mode selection, test clock, test data output, test data input, and test reset;

[0105] According to the TAP state machine design of the IEEE1149.1 protocol, state transition is controlled by TMS. The JTAG MASTER controller defines 16 states for controlling TMS signal output, including: ST_TLR logic reset state, ST_RTI run idle state, ST_SDR select data scan state, ST_CDR data capture state, ST_SHD data shift state, ST_E1D data exit 1 state, ST_E2D data exit 2 state, ST_PDR data transmission pause state, ST_UDR update data value state, ST_SIR select instruction scan state, ST_CIR instruction capture state, ST_SHI instruction shift state, ST_E1I instruction exit 1 state, ST_PIR instruction transmission pause state, ST_E2I instruction exit 2 state, ST_UIR update instruction value state, to realize the conversion of register configuration instructions into JTAG protocol and transmit them to the target debugging device;

[0106] The JTAG host provides registers with corresponding functions for the JTAG interface.

[0107] Specifically, in the module M3:

[0108] Firmware development that matches the hardware is based on the Uboot environment. UBoot is a boot program before the embedded operating system starts. The code is open source and can support a variety of embedded processors.

[0109] Specifically, in the module M4:

[0110] According to the file format, add command configuration option information of the JTAG host, define a set of debugging instructions for each JTAG interface, and select whether to add the debugging system firmware to the UBoot compilation environment in the JTAG host configuration option. After successful selection, compile and generate a bin file, and solidify the content into the debugging device through electronic design automation tools.

[0111] Example 3:

[0112] Example 3 is a preferred example of Example 1 and is used to illustrate the present invention in more detail.

[0113] Debug system communication instructions, such as Figure 1As shown, the debugging device is connected to the host PC through a serial port, and can be connected to the debugging target through a JTAG (Joint Test Action Group) interface signal line. The host PC runs serial port debugging software, such as HyperTerminal, Serial Debug Assistant, etc., and configures a suitable baud rate. The debugging device is powered on and starts Uboot (Universal Boot Loader), enters the command input window, and can select the current debugging target board (JTAG port number) according to the pre-defined command. Finally, the signal is converted into a JTAG interface signal that meets the characteristics of the target device through the JTAG Master (Joint Test Action Group Master) controller to complete the multi-device online debugging action.

[0114] Point 1: Flexibility in debugging systems

[0115] The hardware design of the debugging system takes into account cost and flexibility, such as Figure 2 The figure shows the minimum hardware structure of the debugging system. The debugging system only needs to integrate the CPU core, serial port, ROM (Read-Only Memory), RAM (Random Access Memory), a self-developed JTAG Master controller, and GPIO (General-Purpose Input / Output) pins. The serial port supports common baud rates such as 115200bps, 57600bps, and 38400bps, and is an interactive port for the host PC. The ROM is used to store the debug application software. The RAM is used for storage space required for software operation. The GPIO pins are used as the JTAG external communication interface. The JTAG Master controller is used to implement protocol conversion operations.

[0116] Key Point 2: JTAG Master Controller Design - Implementing JTAG Protocol Conversion and Simultaneous Connection of Multiple Devices

[0117] The JTAG Master controller is a self-developed design. According to the IEEE1149.1 protocol, it converts data into JTAG signal output. Considering the versatility, the JTAG Master controller interface design chooses the AMBA APB (AMBA, Advanced Microcontroller Bus Architecture) (APB, Advanced Peripheral Bus) interface protocol. In order to realize the online connection of multiple devices for debugging, four groups of JTAG interface (TMS, TCK, TDO, TDI, TRSTn) signals are designed, including TMS (Test Mode Select), TCK (Test Clock), TDI (Test Data In), TDO (Test Data Out), and TRSTn (Test Reset).

[0118] According to the TAP (Test Access Port) state machine design of the IEEE1149.1 protocol, the state transition is controlled by TMS, such as Figure 3 As shown in the figure, the JTAG MASTER controller defines 16 states for controlling the TMS signal output, including: ST_TLR (logic reset state), ST_RTI (running idle state), ST_SDR (selecting data scan state), ST_CDR (data capture state), ST_SHD (data shift state), ST_E1D (data exit 1 state), ST_E2D (data exit 2 state), ST_PDR (data transmission pause state), ST_UDR (update data value state), ST_SIR (selecting instruction scan state), ST_CIR (instruction capture state), ST_SHI (instruction shift state), ST_E1I (instruction exit 1 state), ST_PIR (instruction transmission pause state), ST_E2I (instruction exit 2 state), ST_UIR (update instruction value state), so as to convert the register configuration instructions into JTAG protocol and transmit them to the target debugging device.

[0119] JTAG Master provides four groups of registers for the four JTAG interfaces, as shown in the following table, to implement JTAG for each interface, as shown in the following register list, to support

[0120] The corresponding JTAG Master controller provides registers with corresponding functions, as shown in the following table.

[0121]

[0122]

[0123] The specific definitions of these registers are introduced below.

[0124] (1) JTAGx_DATD_VALUE (x = 0-3): data register

[0125] The specific definition of this register is as follows:

[0126]

[0127] (2) JTAGx_INSTR_VALUE (x=0-3): instruction register

[0128] The specific definition of this register is as follows:

[0129]

[0130] (3) JTAGx_CONTROL (x = 0-3): control register

[0131] The specific definition of this register is as follows:

[0132]

[0133] (4) JTAGx_INTR_EN (x = 0-3): Interrupt status and enable register

[0134] The specific definition of this register is as follows:

[0135]

[0136] (5) JTAGx_INTR_STATUS (x=0-3): Software mode and status register

[0137] The specific definition of this register is as follows:

[0138] bit field Read and write properties illustrate 31：4 R reserve 3 RW The interrupt status bit of instruction transfer pause is cleared by writing 1 2 RW Instruction transfer completion interrupt status bit, write 1 to clear 1 RW Data transmission pause interrupt status bit, write 1 to clear 0 RW Data transmission completed interrupt status bit, write 1 to clear

[0139] (6) JTAGx_TCK_CONFIG (x = 0-3): TCK control register

[0140] The specific definition of this register is as follows:

[0141]

[0142] Key Point 3: Firmware development uses the Uboot environment and designs debugging instructions based on the Uboot command system

[0143] Firmware development to support the hardware is based on the Uboot environment. UBoot is a bootloader that precedes the startup of embedded operating systems. Its code is open source, supports a wide range of embedded processors (PowerPC, ARM, MIPS, x86, XScale, etc.), and boasts high code reliability and stability. This means that choosing UBoot as the firmware development environment for the debugging system provides a solid foundation of hardware support. This also means that when designing and applying the debugging system hardware, support for processors covering PowerPC, ARM, x86, and other types is possible, providing a certain level of versatility. UBoot was also chosen as the development environment because its existing command system facilitates the development of JTAG debugging instructions based on the C language.

[0144] Add a Command Line Interface -> JTAG Master configuration option to the UBoot source code menuconfig (menu config). Based on the UBoot cmd / Kconfig file format, add JTAGMaster command configuration option information. When launching the menuconfig configuration graphical interface, select the Command Line Interface option and then select the JTAG Master option (Command Line Interface -> JTAGMaster option) in the next directory to add JTAG commands to the UBoot compilation environment. This part is part of firmware development. A set of debug commands is defined for each of the four JTAG interfaces, as shown below. The JTAG Master configuration option selects whether to add the debug system firmware to the UBoot compilation environment. Once selected, a bin file is compiled and solidified into the debugging device using EDA (Electronic Design Automation) tools.

[0145] Table debug instruction list

[0146]

[0147]

[0148]

[0149]

[0150] Example 4:

[0151] Example 4 is a preferred example of Example 1 and is used to illustrate the present invention in more detail.

[0152] Use Zynq-7000 (an FPGA product of Xilinx, the official website does not have an English abbreviation meaning) to build a debugging system, such as Figure 4 As shown, if you don't use the Zynq-7000, you can use an FPGA board that includes processor core resources, memory resources, configurable GPIO pin resources, and UART resources as an alternative. The corresponding firmware development strategy involves using a processor core from any of the PowerPC, ARM, x86, or MIPS series. Common FPGA boards currently available as replacements include the Zynq-7010, Zynq-7020, and Zynq UltraScale+ MPSoC series with ARM processor core resources, and the Xilinx Virtex-II Pro series FPGA boards with PowerPC processor core resources.

[0153] 1. Use EDA tools to encapsulate the self-designed JTAG Master controller mentioned in point 2 into an IP device of the AMBA APB port;

[0154] 2. Call the hardware resources built into the Zynq-7000 board, including the ARM Cortex-a9 CPU core, DDR (Double Data Rate SDRAM) controller and DDR memory chips, SPI Flash (Serial Peripheral interface flash) controller and Flash chips, UART (Universal Asynchronous Receiver / Transmitter) port and GPIO pins, and connect the JTAG_Master IP to the hardware system through the AMBA APB bus to complete the minimum hardware FPGA (Field Programmable Gate Array) design of the debugging system;

[0155] 3. Complete Uboot porting according to the characteristics of the Zynq-7000 board;

[0156] 4. In the transplanted Uboot, use the CMD (Command) system to add the JTAG debugging instructions mentioned in point 3 above. After successful compilation, fix the binary file to the Zynq-7000 board;

[0157] 5. If Figure 1As shown, the debugging device is connected to the host computer through a serial line, and the debugging device is connected to the target debugging chip through a JTAG cable. The host computer runs the HyperTerminal software, which is a computer serial interactive terminal software that can be connected through a serial port, modem or Ethernet port. The target chip debugging work is completed through data JTAG debugging instructions, such as Figure 5 The following is a screenshot of the debugging interaction interface.

[0158] Those skilled in the art will appreciate that, in addition to implementing the system, device, and various modules provided by the present invention in purely computer-readable program code, it is entirely possible to implement the same program in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, embedded microcontrollers, and the like by logically programming the method steps. Therefore, the system, device, and various modules provided by the present invention can be considered a hardware component, and the modules included therein for implementing various programs can also be considered structures within the hardware component; the modules for implementing various functions can also be considered both software programs for implementing the method and structures within the hardware component.

[0159] The above describes specific embodiments of the present invention. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art may make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. The embodiments of this application and the features in the embodiments may be combined with each other in any manner unless there is a conflict.

Claims

1. A universal JTAG debugging method with an extensible interface, characterized in that: include: Step S1: The JTAG host controller is encapsulated as an IP device of a peripheral bus port; Step S2: Call the hardware resources in the development board, connect the JTAG host IP to the hardware system, and complete the minimum hardware field programmable gate array design of the debugging system; Step S3: According to the characteristics of the development board, complete the boot loader program transplantation work; Step S4: compile the ported boot loader and solidify the binary file into the development board; Step S5: The debugging device is connected to the host computer via a serial port, and the debugging device is connected to the target debugging chip via a JTAG interface signal line. The host computer runs the HyperTerminal software and completes the target chip debugging work by sending JTAG debugging instructions. The debugging system integrates CPU core, serial port, ROM, RAM, self-developed JTAG host controller, and general input and output pins; The serial port is connected to the host PC interactive port; ROM is used to store the fixed debugging application software; RAM is used as the storage space required for software operation; general input and output pins are used for JTAG external communication interface; JTAG host controller is used to implement protocol conversion operations; In the step S4: According to the file format, add command configuration option information of the JTAG host, define a set of debugging instructions for each JTAG interface, and select whether to add the debugging system firmware to the UBoot compilation environment in the JTAG host configuration option. After successful selection, compile and generate a bin file, and solidify the content into the debugging device through electronic design automation tools.

2. The JTAG debugging method with scalable and universal interface according to claim 1, characterized in that: In step S1: The JTAG host controller converts data into JTAG signal output according to the IEEE1149.1 protocol. The JTAG host controller interface design selects the AMBA APB interface protocol. In order to realize the online simultaneous connection of multiple devices for debugging, the JTAG interface signals are designed, including test mode selection, test clock, test data output, test data input, and test reset; According to the TAP state machine design of the IEEE1149.1 protocol, state transition is controlled by TMS. The JTAG MASTER controller defines 16 states for controlling TMS signal output, including: ST_TLR logic reset state, ST_RTI run idle state, ST_SDR select data scan state, ST_CDR data capture state, ST_SHD data shift state, ST_E1D data exit 1 state, ST_E2D data exit 2 state, ST_PDR data transmission pause state, ST_UDR update data value state, ST_SIR select instruction scan state, ST_CIR instruction capture state, ST_SHI instruction shift state, ST_E1I instruction exit 1 state, ST_PIR instruction transmission pause state, ST_E2I instruction exit 2 state, ST_UIR update instruction value state, to realize the conversion of register configuration instructions into JTAG protocol and transmit them to the target debugging device; The JTAG host provides registers with corresponding functions for the JTAG interface.

3. The JTAG debugging method with scalable and universal interface according to claim 1, characterized in that: In step S3: Firmware development that matches the hardware is based on the Uboot environment. UBoot is a boot program before the embedded operating system starts. The code is open source and can support a variety of embedded processors.

4. A universal JTAG debugging system with an extensible interface, characterized in that: include: Module M1: JTAG host controller encapsulated as an IP device of the peripheral bus port; Module M2: Calls the hardware resources built into the development board, connects the JTAG host IP to the hardware system, and completes the minimum hardware field programmable gate array design of the debugging system; Module M3: Complete the boot loader porting work according to the characteristics of the development board; Module M4: compiles the ported boot loader and fixes the binary file to the development board; Module M5: The debugging device is connected to the host computer through the serial port, and the debugging device is connected to the target debugging chip through the JTAG interface signal line. The host computer runs the hyperterminal software and completes the target chip debugging work through the data JTAG debugging instructions; The debugging system integrates CPU core, serial port, ROM, RAM, self-developed JTAG host controller, and general input and output pins; The serial port is connected to the host PC interactive port; ROM is used to store the fixed debugging application software; RAM is used as the storage space required for software operation; general input and output pins are used for JTAG external communication interface; JTAG host controller is used to implement protocol conversion operations; In the module M4: According to the file format, add command configuration option information of the JTAG host, define a set of debugging instructions for each JTAG interface, and select whether to add the debugging system firmware to the UBoot compilation environment in the JTAG host configuration option. After successful selection, compile and generate a bin file, and solidify the content into the debugging device through electronic design automation tools.

5. The universal JTAG debugging system with scalable interface according to claim 4, characterized in that: In the module M1: The JTAG host controller converts data into JTAG signal output according to the IEEE1149.1 protocol. The JTAG host controller interface design selects the AMBA APB interface protocol. In order to realize the online simultaneous connection of multiple devices for debugging, the JTAG interface signals are designed, including test mode selection, test clock, test data output, test data input, and test reset; According to the TAP state machine design of the IEEE1149.1 protocol, state transition is controlled by TMS. The JTAG MASTER controller defines 16 states for controlling TMS signal output, including: ST_TLR logic reset state, ST_RTI run idle state, ST_SDR select data scan state, ST_CDR data capture state, ST_SHD data shift state, ST_E1D data exit 1 state, ST_E2D data exit 2 state, ST_PDR data transmission pause state, ST_UDR update data value state, ST_SIR select instruction scan state, ST_CIR instruction capture state, ST_SHI instruction shift state, ST_E1I instruction exit 1 state, ST_PIR instruction transmission pause state, ST_E2I instruction exit 2 state, ST_UIR update instruction value state, to realize the conversion of register configuration instructions into JTAG protocol and transmit them to the target debugging device; The JTAG host provides registers with corresponding functions for the JTAG interface.

6. The universal JTAG debugging system with scalable interface according to claim 4, characterized in that: In the module M3: Firmware development that matches the hardware is based on the Uboot environment. UBoot is a boot program before the embedded operating system starts. The code is open source and can support a variety of embedded processors.

Images