Computer system and method for cache writeback and invalidation based on specified keys

Abstract

Computer systems and methods for cache writeback and invalidation of specified keys. In one embodiment, in response to a first instruction of an instruction set architecture for writeback and invalidation of a hierarchical cache based on a single specified key identification, a decoder translates at least one microinstruction. According to the at least one microinstruction, a writeback and invalidation request is supplied to an in-core cache via a memory order buffer, and in turn by the in-core cache to a last level cache. In response to the writeback and invalidation request, the last level cache finds all matching cache lines that match the specified key identification, writes back to system memory those matching cache lines that have been modified and do not exist in a superior cache, and invalidates all matching cache lines found regardless of whether a state change has occurred. For a second instruction of an instruction set architecture for writeback and invalidation of a hierarchical cache based on multiple specified key identifications, the present application implements multiple writeback and invalidation requests.

Description

Technical Field

[0001] This application relates to management techniques for a processor's hierarchical cache, and more specifically, to a computer system and method for writing back and invalidating a hierarchical cache based on a specified key identification code. Background Technology

[0002] In computer systems, memory can be hierarchically structured. Higher-level memory offers higher speed and lower latency, but has smaller capacity. Most computer systems have the following four memory hierarchies (ordered from top to bottom): registers; cache memory; system memory (main memory, such as DRAM); and disks (SSD or HDD).

[0003] In particular, caches can also be designed hierarchically, arranged from fastest to slowest access, including: Level 1 cache (L1), Level 2 cache (L2), and Level 3 cache (L3, also known as the last level cache, or LLC). The management of hierarchical caches will significantly affect system performance.

[0004] To protect confidential and / or sensitive data, existing technologies have developed transparent total memory encryption (TMC) functions that use multiple keys to encrypt system memory, enabling memory management at the key-level granularity. However, existing hierarchical caches lack corresponding key-level granular management functions, which prevents the operating system (OS) from managing hierarchical caches at the key-level granularity. Summary of the Invention

[0005] To address the aforementioned issues, this application proposes a technique for managing hierarchical caches at the key level, which can be implemented as a computer system or used as a computer system operation method.

[0006] A computer system implemented according to one embodiment of this application includes: a first core; a first processor fabricated on a first die, including a decoder, a sequential memory cache, and a first core cache; and a first last-level cache fabricated on the first processor. In response to a first instruction of an instruction set architecture that performs a write-back and invalidation of a hierarchical cache based on a single specified key identification code, the decoder translates at least one microinstruction. According to the at least one microinstruction, a write-back and invalidation request is supplied to the first core cache through the sequential memory cache, and then passed from the first core cache to the first last-level cache. In response to the write-back and invalidation request, the first last-level cache finds all matching cache lines that match the specified key identification code, writes back any modified cache lines that are not present in the higher-level cache to system memory, and invalidates all found matching cache lines regardless of whether their state has changed.

[0007] In one implementation, the write-back and invalidate request carries the specified key identification code. The first last-level cache finds all matching cache lines that match the specified key identification code in the write-back and invalidate request.

[0008] In one embodiment, the computer system stores the specified key identification code parsed from the first instruction in a first storage unit. The write-back and invalidate request does not carry the specified key identification code. When the first last-level cache receives the write-back and invalidate request, it retrieves the specified key identification code from the first storage unit and uses it to find all matching cache lines that match the specified key identification code.

[0009] One embodiment of this application uses a listening filter technology, as described below.

[0010] In one embodiment, the first processor further includes a first snoop filter. The first lowest-level cache issues a snoop request for each matching cache line, which is then passed to the first core cache via the first snoop filter. Each snoop request carries a flag common to the corresponding matching cache line in the hierarchical cache. In response to each snoop request, the first core cache finds its own cache lines that match the flag carried in the snoop request, writes any modified cache lines back to system memory, and invalidates the found cache lines regardless of whether their state has changed.

[0011] In one embodiment, the first processor further includes a second core, which includes a second in-core cache. Each snooping request is also passed to the second in-core cache by the first snooping filter. In response to each snooping request, the second in-core cache finds a cache line that matches the flag carried in the snooping request, writes any modified cache lines back to system memory, and invalidates the found cache lines regardless of whether their state has changed.

[0012] In one embodiment, the computer system further includes a second processor fabricated on a second die. The second processor includes a third core and a second last-level cache. The third core includes a third in-core cache. The first last-level cache also transmits the write-back and invalidation request from the first in-core cache to the second last-level cache via a channel between the first die and the second die. In response to the received write-back and invalidation request, the second last-level cache finds all matching cache lines that match the specified key identification code, writes back any modified matching cache lines that are not present in the higher-level cache to system memory, and invalidates all found matching cache lines regardless of any changes in their state.

[0013] In one embodiment, the second processor further includes a second snoop filter. The second lowest-level cache issues a snoop request for each matching cache line, which is then passed to the third core cache via the second snoop filter. Each snoop request carries a flag common to the corresponding matching cache line in the hierarchical cache. In response to each snoop request, the third core cache finds its own cache lines that match the flag carried in the snoop request, writes any modified cache lines back to system memory, and invalidates the found cache lines regardless of whether their state has changed.

[0014] One embodiment of this application uses a waiting synchronization signal design, as described below.

[0015] In one implementation, after invalidating all matching cache lines, the first lowest-level cache sends a first notification back to the first core cache. The first core cache that provided the write-back and invalidation request to the first lowest-level cache is in a waiting synchronization signal state until it receives the first notification from the first lowest-level cache. Only then does it find all matching cache lines that match the specified key identification code, write back the modified matching cache lines that do not exist in the upper-level cache to the system memory, and invalidate all found matching cache lines regardless of whether the state has changed.

[0016] In one embodiment, the first processor further includes a second core, which includes a second in-core cache. The write-back and invalidation request is supplied to the second core via the sequential memory cache of the first core, and then passed to the first last-level cache by the second in-core cache of the second core. The write-back and invalidation request responded to by the first last-level cache is the earlier one received by the first core and the second core.

[0017] In one embodiment, the computer system of this application includes an inter-core interrupt processor that receives an interrupt request issued by the first core through the memory sequential cache in response to a write-back and invalidation request, and operates a rearranged cache of the second core accordingly to initiate an interrupt design of a microcode of the second core, so that the write-back and invalidation request is handed over to the cache within the second core.

[0018] In one implementation, the first lowest-level cache also sends the first notification back to the second core cache, and starts the second core cache, which is in a state of waiting for a synchronization signal, to find all matching cache lines that match the specified key identification code. It writes the modified matching cache lines back to the system memory and invalidates all the found matching cache lines regardless of whether the state has changed.

[0019] In one embodiment, the computer system of this application further includes a second processor fabricated on a second die. The second processor includes a third core and a second last-level cache. The third core includes a third in-core cache. The write-back and invalidate request is supplied to the third core via the sequential memory cache of the first core, through a channel between the first die and the second die, and then delivered to the second last-level cache by the third in-core cache of the third core. In response to the received write-back and invalidate request, the second last-level cache finds all matching cache lines that match the specified key identification code, writes back the modified matching cache lines that do not exist in the higher-level cache to the system memory, and invalidates all found matching cache lines regardless of whether their state has changed. After invalidating all matching cache lines, the second lowest-level cache sends a third notification to the third core cache, which is in a state of waiting for a synchronization signal. The third core cache then searches for all matching cache lines that match the specified key identification code, writes any modified matching cache lines back to the system memory, and invalidates all found matching cache lines regardless of whether the state has changed.

[0020] The aforementioned first instruction for a single specified key identification code involves a single operand. This single operand indicates a register, a system memory address, or an immediate value to obtain the specified key identification code requested by the first instruction.

[0021] This application also features a design that responds to multiple specified key identification codes.

[0022] In one implementation, in response to a second instruction of an instruction set architecture that performs write-back and invalidation of a hierarchical cache based on multiple specified key identification codes, the decoder translates at least one microinstruction. According to the at least one microinstruction corresponding to the second instruction, the multiple specified key identification codes are stored in the memory unit of the first core, and multiple write-back and invalidation requests supplied to the cache within the first core via the sequential memory cache ensure that, for the multiple specified key identification codes stored in the memory unit of the first core, the write-back and invalidation of the next specified key identification code is only performed after the current specified key identification code has been written back and invalidated.

[0023] In one embodiment, the second instruction involves two operands for obtaining a preliminary key identification code setting and a mask. After masking the preliminary key identification code setting using the mask, the plurality of specified key identification codes required by the second instruction are formed.

[0024] In one embodiment, the second instruction involves two operands for obtaining a system memory address and a specified number of key identification codes. The system memory address indicates a starting key identification code in a list in the system memory, and the specified number of key identification codes requested by the second instruction are obtained from the list based on the system memory address and the specified number of key identification codes.

[0025] According to the technology of this application, the hierarchical cache is equipped with corresponding key-based management functions; when the transparent full memory encryption function is enabled, the operating system can manage the hierarchical cache at the key-based granularity.

[0026] The following detailed description of the invention is illustrated with specific examples and accompanying drawings. Attached Figure Description

[0027] Figure 1A This is an instruction architecture for the ISA instruction WBINVD_Single_KeyID in this application;

[0028] Figure 1B This is an instruction architecture for the ISA instruction WBINVD_Multiple_KeyIDs in this application;

[0029] Figure 1C This is an instruction architecture for the ISA instruction INVD_Single_KeyID in this application;

[0030] Figure 1D This is an instruction architecture for the ISA instruction INVD_Multiple_KeyIDs in this application;

[0031] Figure 2A This is a block diagram illustrating a processor 200 and a core core_1 thereon, according to one embodiment of the present invention.

[0032] Figure 2B The format 250 of a cache line in a hierarchical cache is illustrated according to one embodiment of this application.

[0033] Figure 3 The illustration shows a computer system 300 implemented according to one embodiment of this application, in which snoop filter technology is used;

[0034] Figure 4A , 4B The illustration shows a computer system 400 implemented according to another embodiment of this application, which relates to a multi-core and multi-grid design without using a snooping filter;

[0035] Figure 5 The diagram illustrates a processor 500 implemented according to another embodiment of this application, wherein the in-core cache includes only a first-level cache L1, and multiple cores share a second-level cache L2; and

[0036] Figure 6 The diagram illustrates a computer system 600 with a multi-core architecture implemented according to one embodiment of this application.

[0037] [Symbol Explanation]

[0038] 102, 112, 132, 142: Opcodes;

[0039] 104, 114, 116, 134, 144, 146: Operands (oprand);

[0040] 106, 108, 110, 118, 120, 122, 136, 138, 140, 148, 150, 152: Instruction set;

[0041] 200: Processor;

[0042] 202: System memory;

[0043] 204: Instruction cache;

[0044] 206: Decoder;

[0045] 208: Instruction Buffer (XIB);

[0046] 210: Instruction Translator (XLATE);

[0047] 212: Register Alias ​​Table (RAT);

[0048] 214, 218: Reserved stations (RS);

[0049] 216: Sequential Memory Buffer (MOB);

[0050] 220: Execution Unit;

[0051] 222: Local key identification code;

[0052] 224: Eavesdropping Filter;

[0053] 226: Notification delivery path;

[0054] 250: Cache line format;

[0055] 252: Significant bits;

[0056] 254: Key identification code;

[0057] 300: Computer System;

[0058] 302: Write-back invalid request / No write-back invalid request;

[0059] 304: Kernel Cache

[0060] 306, 310: Requests for eavesdropping;

[0061] 308, 408, 520: Channels;

[0062] 400: Computer System;

[0063] 402: Kernel cache;

[0064] 500: Processor;

[0065] 502, 504: Level 2 cache;

[0066] 506: Level 3 cache;

[0067] 508: Level 1 cache;

[0068] 510: Eavesdropping filter;

[0069] 600: Computer System;

[0070] 602: Microcode for interrupt design;

[0071] 604: Register List (RAT);

[0072] 606: Reserved Station (RS);

[0073] 608: Memory Sequential Cache (MOB);

[0074] 610: Interruption request;

[0075] 612: Inter-core interrupt handler;

[0076] 614: Reorder Buffer (ROB);

[0077] 616: Microcode for interrupt design;

[0078] core_1…core_N: Cores;

[0079] Die_1, Die_2: grain;

[0080] imm16: Immediate number;

[0081] INVD_Multiple_KeyIDs, INVD_Single_KeyID, WBINVD_Multiple_KeyIDs, WBINVD_Single_KeyID: Instruction Set Architecture (ISA) instructions;

[0082] L1, L2, L3: Level 1, Level 2, and Level 3 caches;

[0083] LLC_1, LLC_2: Lowest level cache;

[0084] MOB: Sequential Memory Buffer (MOB);

[0085] Processor_1, Processor_2: Processors;

[0086] reg: register;

[0087] Sto, Sto_Die1, Sto_Die2: Storage units;

[0088] req: a request that is written back and invalid / a request that is not written back and is invalid;

[0089] r / m: register or system memory;

[0090] snoop_1, snoop_2: eavesdropping filters;

[0091] Sys_Mem: System memory. Detailed Implementation

[0092] The following description illustrates various embodiments of the present invention. This description introduces the basic concepts of the invention and is not intended to limit its scope. The actual scope of the invention should be defined in accordance with the claims.

[0093] Modern computer systems often incorporate transparent total memory encryption (TMI), using multiple keys to encrypt system memory and enhance security. Each key can be represented by a key ID. The computer system may contain a key table to store the mapping between keys and key IDs. During encryption operations, the key corresponding to the key ID can be retrieved by querying the key table.

[0094] In the corresponding system memory multi-key encryption processing, this application enables the computer system to list the key ID as one of the management parameters of the hierarchical cache (e.g., including level 1, level 2, and level 3 caches L1, L2, and L3). In this way, the use of hierarchical caching can be combined with the application of transparent full-memory encryption.

[0095] Taking the write-back and invalidation (WBINVD) or invalidation without writing back (INVD) of a tiered cache as an example, traditional techniques apply this to all cache lines in the tiered cache. However, the scheme provided in this application can perform write-back and invalidation (WBINVD) or invalidation without writing back (INVD) only on cache lines that match a specified key identifier (which can be a single value or several values). For example, the instructions WBINVD_Single_KeyID and WBINVD_Multiple_KeyIDs, which will be introduced later, will perform write-back and invalidation on cache lines that match a specified key identifier; the instructions INVD_Single_KeyID and INVD_Multiple_KeyIDs, which will be introduced later, will perform invalidation without writing back on cache lines that match a specified key identifier. In this way, the operating system (OS) can manage the hierarchical cache at the key level; since cache lines that will be used later can remain in the hierarchical cache, the performance of the computer system is significantly improved.

[0096] This application also proposes various implementations of a computer system, including a single-core single processor, a multi-core single processor, a multi-processor system, etc.

[0097] The processor disclosed in this invention can provide one instruction set architecture (ISA) instruction for each of the aforementioned functions (including: write-back and invalidation of a single specified key identification code; invalidation without write-back of a single specified key identification code; write-back and invalidation of multiple specified key identification codes; invalidation without write-back of multiple specified key identification codes). The processor supports various instruction set architectures, including x86, Advanced RISC Machine (ARM), MIPS (Microprocessor without Interlocked Pipeline Stages), RISC-V (RISC-Five), SPARC, IBM Power, or others.

[0098] In one embodiment, the present invention discloses a processor in which an InstructionSet Architecture (ISA) instruction (hereinafter referred to as WBINVD_Single_KeyID) invalidates cache lines in a hierarchical cache that match a single specified key identifier (Key_ID_S); in particular, cache lines with a state of M (modified, updated) are first written back to system memory before being invalidated. This behavior is referred to as writing back and invalidation of cache lines matching a single specified key identifier (Key_ID_S).

[0099] Figure 1AThis application's ISA instruction WBINVD_Single_KeyID includes an opcode 102 for instruction identification and an operand 104. Operand 104 indicates a single specified key identification code (Key_ID_S). Operand 104 can have various forms. Instruction architecture 106 shows that for the corresponding instruction WBINVD_Single_KeyID, operand 104 carries a register (reg) label to retrieve the specified key identification code (Key_ID_S) from the register (reg). Instruction architecture 108 shows that for the corresponding instruction WBINVD_Single_KeyID, operand 104 carries a register label or a system memory (r / m) address to retrieve the specified key identification code (Key_ID_S) from the register or system memory (r / m). Instruction architecture 110 shows that for the corresponding instruction WBINVD_Single_KeyID, operand 104 is an immediate value (imm16), which is the specified key identification code (Key_ID_S). In program writing, other instructions can be used to fill registers / system memory / immediate values ​​before the instruction WBINVD_Single_KeyID to prepare the specified key identification code (Key_ID_S), which the instruction WBINVD_Single_KeyID can obtain through operand 104. The instruction WBINVD_Single_KeyID may also include a mode setting (including real mode, protected mode, 64-bit mode, etc.) and a determination of the bit width of the specified key identification code (Key_ID_S) indicated by operand 104.

[0100] In one implementation, the high-order bits of the physical address (PA) are the key identification code (Key_ID). The cache line information for each cache line in a hierarchical cache can be as follows: Figure 2B The diagram includes a key identification code (Key_ID). If the key identification code is the same as the specified key identification code (Key_ID_S) indicated by the instruction WBINVD_Single_KeyID, then the cache line matches the specified key identification code (Key_ID_S). In other embodiments, the key identification code (Key_ID) does not correspond to the high-order bits of the physical address (PA), but is obtained based on the high-order bits of the physical address (PA); since the key identification code (Key_ID) still exists in each cache line, it can still be used for cache line matching. Any technique based on comparing key identification codes (Key_ID) can be used for cache line matching in this application.

[0101] In another embodiment, the present invention discloses a processor in which an instruction set architecture (ISA) instruction (hereinafter referred to as WBINVD_Multiple_KeyIDs) is provided to invalidate cache lines in a hierarchical cache that match multiple specified key identification codes (Key_ID_S1…Key_ID_SN); in particular, cache lines with a status of M (modified, updated) are first written back to system memory before being invalidated. This behavior is referred to as writing back and invalidation of cache lines matching multiple specified key identification codes (Key_ID_S1…Key_ID_SN).

[0102] Figure 1B The instruction architecture of the ISA instruction WBINVD_Multiple_KeyIDs in this application, apart from the opcode 112 used for instruction identification, obtains values ​​from two operands 114 and 116 to combine multiple specified key identification codes (Key_ID_S1…Key_ID_SN). Instruction architecture 118 shows that for the corresponding instruction WBINVD_Multiple_KeyIDs, operand 114 carries a register (reg) label, and operand 116 carries a register label or system memory address to obtain the values ​​required to combine multiple specified key identification codes (Key_ID_S1…Key_ID_SN) from the register (reg) and the register or system memory (r / m). Instruction architecture 120 shows that the corresponding instruction WBINVD_Multiple_KeyIDs uses operand 114, which is a register label or system memory address, and operand 116, which is a register (reg) label, to retrieve the values ​​required to combine multiple specified key identification codes (Key_ID_S1…Key_ID_SN) from the register or system memory (r / m) and the register (reg). Instruction architecture 122 shows that the corresponding instruction WBINVD_Multiple_KeyIDs uses operands 114 and 116, both of which are register (reg) labels, to retrieve the values ​​required to combine multiple specified key identification codes (Key_ID_S1…Key_ID_SN) from two registers (reg). In terms of program writing, other instructions can be used to fill registers / memory before the WBINVD_Multiple_KeyIDs instruction to prepare the values ​​required to combine multiple specified key identification codes (Key_ID_S1…Key_ID_SN), so that the WBINVD_Multiple_KeyIDs instruction can obtain them through these operands 114 and 116.

[0103] In one implementation, operand 114 indicates a key identification code initialization (Key_ID_initial), and operand 116 indicates a mask. After the key identification code initialization (Key_ID_initial) is masked, multiple specified key identification codes (Key_ID_S1…Key_ID_SN) can be derived.

[0104] In one embodiment, in the mask, a bit that is "0" will allow the corresponding bit of the initial key identification code (Key_ID_initial) to have two possible values: "1" and "0"; a bit that is "1" in the mask will keep the corresponding bit of the initial key identification code (Key_ID_initial) unchanged. A single initial key identification code (Key_ID_initial) is derived into multiple specified key identification codes (Key_ID_S1...Key_ID_SN). In practical applications, if you want to obtain multiple specified key identification codes (Key_ID_S1...Key_ID_SN) with certain bits having specific values, you can set the values ​​of these bits in the initial key identification code (Key_ID_initial) to specific values, set the corresponding bits in the mask to 1, and set the values ​​of other bits in the mask to 0. For example, if the initial key ID (Key_ID_initial) is "101…010" and the mask is "111…011", then the mask results are "101…010" and "101…110", representing two key IDs. If the initial key ID (Key_ID_initial) is "101…010" and the mask is "111…100", then the mask results are "101…000", "101…001", "101…010", and "101…011", representing four consecutive key IDs.

[0105] In another embodiment, the initial key identification code (Key_ID_initial) and the mask are XORed bit by bit. A bit in the result of the operation that is "0" allows the corresponding bit in the initial key identification code (Key_ID_initial) to have either "1" or "0" values; a bit in the result that is "1" keeps the corresponding bit in the initial key identification code (Key_ID_initial) unchanged. A single initial key identification code (Key_ID_initial) is thus derived into multiple specified key identification codes (Key_ID_S1…Key_ID_SN). In practical applications, if it is desired to obtain multiple specified key identification codes (Key_ID_S1…Key_ID_SN) with certain bit values ​​of specific values, the values ​​of these bits in the initial key identification code (Key_ID_initial) can be set to these specific values, and these specific values ​​can be inverted and used as the values ​​of the corresponding bits in the mask. The values ​​of the other bits in the mask can be set to be the same as the values ​​of the corresponding bits in the initial key identification code (Key_ID_initial). For example, if the initial key ID is set to "101…010" and the mask is "010…110", then the XOR operation between the initial key ID and the mask will result in "111…100". Therefore, the mask results will be "101…000", "101…001", "101…010", and "101…011", representing four consecutive key IDs.

[0106] In one implementation, operand 114 indicates a starting key ID (Key_ID_first), and operand 116 indicates a specified number of key IDs (num_of_KeyIDs). The multiple key IDs (Key_IDs) can be listed in a list in system memory; these key IDs can be consecutive or non-consecutive. Operand 114 can be the address of the starting key ID (Key_ID_first) in system memory, pointing to the position of the starting key ID (Key_ID_first) in the list. Based on the specified number of key IDs (num_of_KeyIDs) indicated by operand 116, multiple specified key IDs (Key_ID_S1…Key_ID_SN) starting from the starting key ID (Key_ID_first) can be read from the list.

[0107] In one implementation, for the write-back and invalidation of cache lines containing multiple specified key identification codes (Key_ID_S1…Key_ID_SN), the processor provides a dedicated instruction WBINVD_Multiple_KeyIDs_1 for the above masking technique, which is different from the instruction WBINVD_Multiple_KeyIDs_2 that retrieves a specific number of key identification codes from a list.

[0108] In one embodiment, the present invention discloses a processor in which an instruction set architecture (ISA) instruction (hereinafter referred to as INVD_Single_KeyID) is provided to invalidate cache lines matching a single specified key identification code (Key_ID_S) in a hierarchical cache without writing back, wherein no write-back is involved and cache consistency is not required.

[0109] Figure 1C This application presents an instruction architecture for the ISA instruction INVD_Single_KeyID, which, in addition to the opcode 132 used for instruction identification, also includes a single operand 134. Operand 134 indicates the specified key identification code (Key_ID_S). Operand 134 can have several forms. Instruction architecture 136 shows that, for the corresponding instruction INVD_Single_KeyID, operand 134 carries a register (reg) label to obtain the specified key identification code (Key_ID_S) from the register (reg). Instruction architecture 138 shows that, for the corresponding instruction INVD_Single_KeyID, operand 134 carries a register label or a system memory address to obtain the specified key identification code (Key_ID_S) from the register or system memory (r / m). Instruction architecture 140 shows that, for the corresponding instruction INVD_Single_KeyID, operand 134 carries an immediate value (imm16), which is the specified key identification code (Key_ID_S). In program writing, the instruction INVD_Single_KeyID can be preceded by other instructions to fill registers / system memory / immediate values, preparing the specified key identification code (Key_ID_S) for the instruction INVD_Single_KeyID to obtain via operand 134. The instruction INVD_Single_KeyID may also include a mode setting (including real mode, protected mode, 64-bit mode, etc.) and a determination of the bit width of the specified key identification code (Key_ID_S) indicated by operand 134.

[0110] In another embodiment, the present invention discloses a processor in which an instruction set architecture (ISA) instruction (hereinafter referred to as INVD_Multiple_KeyIDs) is provided to invalidate cache lines matching multiple specified key identification codes (Key_ID_S1…Key_ID_SN) in a hierarchical cache without writing back, wherein no write-back is involved and cache consistency is not required.

[0111] Figure 1D This application presents an instruction architecture for the ISA instruction INVD_Multiple_KeyIDs. Besides the opcode 142 used for instruction identification, it uses two operands 144 and 146 to obtain values ​​and combine them to generate multiple specified key identification codes (Key_ID_S1…Key_ID_SN). Instruction architecture 148 shows that for the corresponding instruction INVD_Multiple_KeyIDs, operand 144 carries a register (reg) label, and operand 146 carries a register label or system memory address, to obtain the values ​​required to combine multiple specified key identification codes (Key_ID_S1…Key_ID_SN) from the register (reg) and the register or system memory (r / m). Instruction architecture 150 shows that for the corresponding instruction INVD_Multiple_KeyIDs, operand 144 carries a register label or system memory address, and operand 146 carries a register (reg) label, to retrieve the values ​​required to combine multiple specified key identification codes (Key_ID_S1…Key_ID_SN) from registers or system memory (r / m) and registers (reg). Instruction architecture 152 shows that for the corresponding instruction INVD_Multiple_KeyIDs, operands 144 and 146 both carry register (reg) labels, to retrieve the values ​​required to combine multiple specified key identification codes (Key_ID_S1…Key_ID_SN) from two registers (reg). In program writing, other instructions can be used before the INVD_Multiple_KeyIDs instruction to fill registers / memory, preparing the values ​​required to combine multiple specified key identification codes (Key_ID_S1…Key_ID_SN), for the INVD_Multiple_KeyIDs instruction to retrieve using operands 144 and 146.

[0112] In one implementation, operand 144 indicates a key identification code initial setting (Key_ID_initial), and operand 146 indicates a mask; the same as the aforementioned masking technique.

[0113] In one implementation, operand 144 indicates a starting key ID (Key_ID_first), and operand 146 indicates a specified number of key IDs (num_of_KeyIDs); similar to the aforementioned technique of retrieving a specific number of key IDs from a list.

[0114] In one implementation, for invalid (not written back) cache lines of multiple specified key identification codes (Key_ID_S1…Key_ID_SN), the processor provides a dedicated instruction INVD_Multiple_KeyIDs_1 for the above masking technique, which is different from the instruction INVD_Multiple_KeyIDs_2 that retrieves a specific number of key identification codes from a list.

[0115] In one embodiment, the present invention has a design in the processor's microcode (ucode) that includes the instructions WBINVD_Single_KeyID, WBINVD_Multiple_KeyIDs, INVD_Single_KeyID, and INVD_Multiple_KeyIDs (i.e., each of these instructions corresponds to a set of microcodes, which are all contained in the ucode), and can be further modified in the processor hardware accordingly.

[0116] Figure 2A This diagram illustrates a processor 200 and a core core_1 thereon, according to one embodiment of the present invention. The illustrated hierarchical cache includes first, second, and third level caches L1, L2, and L3. The first and second level caches L1 and L2 are the in-core caches of core_1. The third level cache L3 is the last level cache (LLC) that can be shared by other cores. In a multi-core processor design, the in-core cache may only include the first level cache L1, while the second level cache L2 is located outside the core and shared by multiple cores; related examples will be provided later.

[0117] An instruction is loaded from system memory 202 into an instruction cache 204 and then passed to a decoder 206 for decoding. The decoder 206 includes an instruction buffer (XIB) 208 and an instruction translator (XLATE) 210. The instruction buffer (XIB) 208 identifies and segments the invalid instructions (WBINVD_Single_KeyID, WBINVD_Multiple_KeyIDs, INVD_Single_KeyID, or INVD_Multiple_KeyIDs) as proposed in this application, while the instruction translator (XLATE) 210 translates the instruction into at least one microinstruction recognizable by the pipeline hardware, driving subsequent hardware to write back and invalidate, or invalidate without writing back, based on the key identification code, for the first, second, and third level caches L1, L2, and L3. The action may be a single designated key identification code (Key_ID_S) or multiple designated key identification codes (Key_ID_S1…Key_ID_SN). In one embodiment, the instruction translator (XLATE) 210 translates the instruction into at least one microinstruction recognizable by the pipeline hardware based on microcode (ucode, stored in a microcode memory).

[0118] The at least one microinstruction decoded by decoder 206 is stored in the corresponding reservation station (RS) according to a register alias table (RAT) 212 before being applied. This at least one microinstruction includes an invalid microinstruction (a write-back invalid microinstruction matching a single key identifier, a write-back invalid microinstruction matching multiple key identifiers, a non-write-back invalid microinstruction matching a single key identifier, or a non-write-back invalid microinstruction matching multiple key identifiers). This invalid microinstruction triggers an operation of a memory order buffer (MOB) 216 via reservation station 214, invalidating cache lines in the first, second, and third level caches L1, L2, and L3 that match a single specified key identifier (Key_ID_S) or multiple specified key identifiers (Key_ID_S1…Key_ID_SN). In some implementations, certain microinstructions trigger the execution unit 220 via the reservation station 218 to temporarily store a single designated key identification code (Key_ID_S) or multiple designated key identification codes (Key_ID_S1…Key_ID_SN) in the storage unit Sto (which can be static random access memory, dynamic random access memory, or a register) as local key identification codes 222, and then retrieve and process them one by one. In one embodiment, the at least one microinstruction also includes microinstructions for functions such as exception checking (e.g., privilege level checking) and memory address jumping (i.e., jumping to the instruction following an invalid instruction). The storage unit Sto can be the memory within core_1 as shown in the figure, or it can have other implementations. In a multi-core design, the local key identification code 222 can be stored in a shared storage unit for multiple cores, which can be located in the processor's uncore. In another embodiment, the local key identification code 222 can be stored in the storage space within the first, second, and third level caches (L1, L2, and L3) of each core. Specifically, when the sequential memory cache 216 sends an invalidation request to the first-level cache L1, it carries a local key identification code 222. The first-level cache L1 stores the received local key identification code 222 in its internal storage space. Then, the first-level cache L1 sends an invalidation request to the second-level cache L2, carrying the local key identification code 222. The second-level cache L2 stores the received local key identification code 222 in its internal storage space. Then, the second-level cache L2 sends an invalidation request to the third-level cache L3, carrying the local key identification code 222. The third-level cache L3 stores the received local key identification code 222 in its internal storage space.In one embodiment, before temporarily storing a single specified key identification code (Key_ID_S) or multiple specified key identification codes (Key_ID_S1…Key_ID_SN) in the storage unit Sto, the execution unit 220 will first delete the contents previously saved in the storage unit Sto.

[0119] The following describes the four ISA instructions WBINVD_Single_KeyID, WBINVD_Multiple_KeyIDs, INVD_Single_KeyID, and INVD_Multiple_KeyIDs corresponding to this application. Figure 2A The hardware operation. It should be noted that when using the four ISA instructions mentioned above in the program code, at least one setting instruction (such as the MOV instruction) needs to be used before the aforementioned ISA instructions to fill in the operands of the aforementioned ISA instructions in order to prepare for the execution of the aforementioned ISA instructions.

[0120] First, we discuss the ISA instruction WBINVD_Single_KeyID, which performs a write-back and invalidation of the hierarchical cache based on a single specified key identifier (Key_ID_S).

[0121] Referring to the diagram, a single specified key identification code (Key_ID_S), retrieved from a register, system memory 202, or interpreted from an immediate value, can be carried in a write-back invalidation request and sent to the first-level cache L1 via the communication interface implemented by the memory sequential buffer (MOB) 216. This write-back invalidation request carrying the single specified key identification code (Key_ID_S) can then be passed to the third-level cache L3 via the first-level cache L1 and the second-level cache L2. Upon receiving the write-back and invalidate request, the third-level cache L3 finds all (potentially multiple) cache lines that match the specified key identification code (Key_ID_S) carried in the write-back and invalidate request. It writes back the cache lines that have been modified (cache lines in state M) and do not exist in the higher-level caches (L2 and / or L1) to system memory 202. Then, regardless of whether the cache lines have been modified, it invalidates all cache lines matching the specified key identification code (Key_ID_S) (e.g., invalidating a valid bit of the matching cache line). This will be discussed in conjunction with... Figure 2B This describes how a hierarchical cache (applicable to level 1, 2, and 3 caches) finds all cache lines that match it based on a specified key identifier (Key_ID_S).

[0122] The third-level cache (L3) records the flags of all matching cache lines (hereinafter referred to as matching cache line flags). In general tiered cache designs, cache line usage is indicated by flags. For example, cache lines corresponding to the same physical address (PA) at different levels use the same flag. The same cached content uses the same flag in tiered caches. Therefore, the matching cache line flags found by the third-level cache (L3) can be used for matching cache lines in the second-level cache (L2) and the first-level cache (L1). Matching cache lines in the second-level cache (L2) and the first-level cache (L1) no longer needs to refer to the specified key identification code (Key_ID_S), but instead refers to the matching cache line flags analyzed by the third-level cache (L3). In one embodiment, the matching cache line flag includes the key identification code (Key_ID), tag, index, etc. In another embodiment, the matching cache line flag includes the physical address (PA).

[0123] Since there may be multiple cache lines matching the specified key identification code (Key_ID_S) in the third-level cache (L3), there may also be multiple matching cache line flags. The third-level cache (L3) sends multiple snoop requests to the snoop filter (Snoop filter) 224; each snoop request carries a matching cache line flag. These snoop requests are then supplied by the snoop filter 224 to the second-level cache (L2), and then to the first-level cache (L1).

[0124] In response to the snooping requests from L3 (Level 3 cache), L2 (Level 2 cache) finds a cache line with the same identifier as the matching cache line (if it exists). If the cache line has been modified (M state) and does not exist in the parent cache (L1), it is written back to system memory 202 and then invalidated (e.g., a valid bit of the cache line is set to invalid). If the cache line has not been modified (not M state), it is directly invalidated. Similarly, in response to the snooping requests from L2 (Level 2 cache), L1 (Level 1 cache) finds a cache line with the same identifier as the matching cache line (if it exists). If the cache line has been modified (M state), it is written back to system memory 202 and then invalidated (e.g., a valid bit of the cache line is set to invalid). If the cache line has not been modified (not M state), it is directly invalidated.

[0125] By passing the write-back and invalidation request, carrying a single specified key identification code (Key_ID_S), through L1, L2, and L3, and by sending back various matching cache line flags from L3 to L2 and L1, cache lines matching this specified key identification code (Key_ID_S) in all hierarchical caches L1, L2, and L3 are indeed written back to system memory 202 and are consistently invalidated. The instruction WBINVD_Single_KeyID completes.

[0126] In another implementation, a write-back and invalidation request delivered from the memory sequential cache (MOB) 216 to the hierarchical caches (including L1, L2, and L3) does not carry a specified key identification code (Key_ID_S). The microinstruction, through the reservation station (RS) 218, operates the execution unit 220 to store the specified key identification code (Key_ID_S) in the storage unit Sto as a local key identification code 222. The L3 cache, upon receiving the write-back and invalidation request, retrieves the local key identification code 222 from the storage unit Sto, obtains the single specified key identification code (Key_ID_S), and performs subsequent actions (a write-back and invalidation of its own matching cache line, and a write-back and invalidation of the matching cache line in the kernel cache via a listening request). The instruction WBINVD_Single_KeyID completes this. In one embodiment, the L3 cache can retrieve the local key identification code from the storage unit Sto via an interrupt. For example, the L3 cache can send an interrupt signal to core_1, which then executes an interrupt handler to write the local key identification code 222 stored in memory unit Sto into a register of the L3 cache. In another embodiment, the L3 cache can directly read the local key identification code from memory unit Sto.

[0127] Figure 2B This diagram illustrates the format 250 of a cache line in a hierarchical cache according to one embodiment of this application. Referring to the format 250 of the cache line in a hierarchical cache, field 252 is the validity bit (VALID), where a value of 0 indicates that the cache line is invalid, and a value of 1 indicates that the cache line is valid. The aforementioned invalid cache line is created by setting the validity bit (VALID) of the cache line to invalid (setting the value of the validity bit to 0). Field 254 records the key identification code (Key_ID). When the hierarchical cache searches for a matching cache line based on the specified key identification code (Key_ID_S), if the cache line is valid and its key identification code (Key_ID) is the same as the specified key identification code (Key_ID_S), then the corresponding cache line is considered a matching cache line.

[0128] Next, we will discuss the ISA instruction WBINVD_Multiple_KeyIDs, which performs a write-back and invalidation of the hierarchical cache based on multiple specified key identification codes (Key_ID_S1…Key_ID_SN).

[0129] Please also refer to Figure 1B , 2A The values ​​indicated by the two operands 114 and 116 of the instruction WBINVD_Multiple_KeyIDs are retrieved from the register or system memory 202 and then processed by the execution unit 220 (masking or list lookup, see above for specific processing methods) to obtain multiple specified key identification codes (Key_ID_S1…Key_ID_SN), which are then stored in the storage unit Sto as local key identification codes 222. Unlike the instruction WBINVD_Single_KeyID, which resolves only a single write-back and invalidation request (corresponding to a single specified key identifier (Key_ID_S), the corresponding instruction WBINVD_Multiple_KeyIDs resolves multiple write-back and invalidation requests, corresponding to multiple specified key identifiers (Key_ID_S1…Key_ID_SN) managed by the local key identifier 222. In one implementation, the memory sequential cache (MOB) 216 transmits one write-back and invalidation request at a time, and only after the write-back and invalidation request has been processed is the next write-back and invalidation request passed to the third-level cache L3 through the first-level cache L1 and the second-level cache L2.

[0130] In one implementation, each write-back and invalidation request is formed using the local key identification code 222 of the reference storage unit Sto, carrying one of the aforementioned multiple specified key identification codes (Key_ID_S1…Key_ID_SN). Based on the single specified key identification code (Key_ID_S#) carried by each write-back and invalidation request, the third-level cache L3 performs subsequent actions (write-back and invalidation of its own matching cache line, and write-back and invalidation of matching cache lines in the kernel cache based on a snooping request; details of the specific actions are described above). After the processes triggered by multiple write-back and invalidation requests carrying the aforementioned multiple specified key identification codes (Key_ID_S1…Key_ID_SN) have been completed, in the hierarchical caches L1, L2, and L3, cache lines matching all specified key identification codes (Key_ID_S1…Key_ID_SN) are indeed written back to system memory 202 and are consistently invalidated. The instruction WBINVD_Multiple_KeyIDs is completed.

[0131] In another implementation, the multiple write-back and invalidation requests passed from the memory sequential cache (MOB) 216 to the hierarchical caches (including L1, L2, and L3) do not carry the aforementioned multiple specified key identification codes (Key_ID_S1…Key_ID_SN). A write-back and invalidation request without a specified key identification code (Key_ID_S#) is also passed from the first-level cache L1, the second-level cache L2, and all the way to the third-level cache L3. The third-level cache L3, upon receiving the write-back and invalidation request, retrieves the specified key identification code (Key_ID_S#) from the local key identification code 222 of the storage unit Sto, and performs subsequent actions (write-back and invalidation of its own matching cache line, and write-back and invalidation of the matching cache line in the kernel cache using a listening request; details of the specific actions are described above). Through multiple write-back and invalidation requests, the third-level cache (L3) repeatedly accesses memory unit Sto, sequentially retrieving the specified key identification codes (Key_ID_S1…Key_ID_SN) from local key identification code 222 and performing operations. In the hierarchical caches L1, L2, and L3, all cache lines matching the specified key identification codes (Key_ID_S1…Key_ID_SN) are indeed written back to system memory 202 and are consistently invalidated. The instruction WBINVD_Multiple_KeyIDs is completed.

[0132] Next, we will discuss the ISA instruction INVD_Single_KeyID, which invalidates the hierarchical cache without writing back based on a single specified key identification code (Key_ID_S).

[0133] Please also refer to Figure 1C , 2A And 2B, a single specified key identification code (Key_ID_S) taken from a register, or system memory 202, or interpreted from an immediate value, can be carried in a no-write-back invalidation request and sent to the first-level cache L1 through the communication interface implemented by the memory sequential buffer (MOB) 216. This no-write-back invalidation request carrying the single specified key identification code (Key_ID_S) can be passed through the first-level cache L1 and the second-level cache L2 to the third-level cache L3. Upon receiving the no-write-back invalidation request, the third-level cache L3 finds all (potentially multiple) cache lines that match the specified key identification code (Key_ID_S) carried in the no-write-back invalidation request, without performing a write-back to system memory 202 (no need to consider cache consistency), and directly invalidates all cache lines that match the specified key identification code (Key_ID_S) (for example, invalidating the valid bits (VALID) 252 of the matching cache lines). Figure 2B (As shown) is set to invalid).

[0134] Similar to the aforementioned techniques, the third-level cache L3 records the flags of all matching cache lines (matching cache line flags). All matching cache line flags found by the third-level cache L3 are carried one-to-one in multiple snoop requests and sent to the snoop filter 224, which then supplies them to the second-level cache L2, and finally to the first-level cache L1.

[0135] In response to the various snooping requests from the Level 3 cache (L3), the Level 2 cache (L2) finds a cache line that also matches the cache line flag (if it exists). Without performing a 202 write-back to system memory (no need to worry about cache consistency), it directly invalidates the cache line (for example, by setting the validity bit (VALID) of the cache line to 252). Figure 2B (As shown) set to invalid). In response to each snooping request from the second-level cache L2, the first-level cache L1 finds a cache line that also matches the cache line flag (if it exists), and without performing a system memory write-back (no need to consider cache consistency), directly invalidates that cache line (for example, invalidates the cache line's valid bit (VALID) 252 (as shown). Figure 2B (As shown) is set to invalid).

[0136] The invalidation request, which carries a single specified key identification code (Key_ID_S) and is passed through L1, L2, and L3, and the eavesdropping request that is passed back from L3 to L2 and L1, means that cache lines matching this specified key identification code (Key_ID_S) in all hierarchical caches L1, L2, and L3 are directly invalidated without a system memory write-back (202). This is accomplished by the instruction INVD_Single_KeyID.

[0137] In another implementation, the write-back invalidation request submitted by the memory sequential cache (MOB) 216 to the hierarchical caches (including L1, L2, and L3) does not include a specified key identification code (Key_ID_S). The microinstruction, through the reservation station (RS) 218, operates the execution unit 220 to store the specified key identification code (Key_ID_S) in the storage unit Sto as a local key identification code 222. The third-level cache L3, upon receiving the write-back invalidation request, retrieves the local key identification code 222 from the storage unit Sto, obtains the single specified key identification code (Key_ID_S), and performs subsequent actions (invalidating the write-back invalidation for its own matching cache line, and invalidating the write-back invalidation for the matching cache line in the kernel cache using a snooping request; details of these actions are described above). The instruction INVD_Single_KeyID completes the process.

[0138] Next, we will discuss the ISA instruction INVD_Multiple_KeyIDs, which invalidates the hierarchical cache without writing back based on multiple specified key identification codes (Key_ID_S1…Key_ID_SN).

[0139] Please also refer to Figure 1D , 2A And 2B, the values ​​indicated by the double operands 144 and 146 of the instruction INVD_Multiple_KeyIDs are retrieved from the register or system memory 202, and then processed by the execution unit 220 (masking or list lookup) to obtain multiple specified key identification codes (Key_ID_S1…Key_ID_SN), which are stored in the storage unit Sto as local key identification codes 222.

[0140] In one implementation, the memory sequential cache (MOB) 216 passes multiple write-back invalidation requests through the first-level cache L1 and the second-level cache L2 to the third-level cache L3. Each write-back invalidation request is formed based on the local key identification code 222 of the storage unit Sto, and carries one of the aforementioned multiple specified key identification codes (Key_ID_S1…Key_ID_SN). Based on the single specified key identification code (Key_ID_S#) carried by each write-back invalidation request, the third-level cache L3 performs subsequent actions (invalidating the write-back invalidation for its own matching cache line, and invalidating the write-back invalidation for the matching cache line in the core cache by listening for a request; details of the specific actions are described above). Once all the processes triggered by multiple invalidation requests that do not require a write-back for the specified key identification codes (Key_ID_S1…Key_ID_SN) have been completed, the cache lines in the hierarchical caches L1, L2, and L3 that match all specified key identification codes (Key_ID_S1…Key_ID_SN) will be invalidated directly without requiring a write-back to system memory. This is completed by the instruction INVD_Multiple_KeyIDs.

[0141] In another implementation, the multiple write-back invalidation requests passed from the memory sequential cache (MOB) 216 to the hierarchical caches (including L1, L2, and L3) do not carry the aforementioned multiple specified key identification codes (Key_ID_S1…Key_ID_SN). The write-back invalidation requests without specified key identification codes (Key_ID_S#) are passed from the first-level cache L1, the second-level cache L2, and all the way to the third-level cache L3. The third-level cache L3, upon receiving the write-back invalidation request, retrieves the specified key identification code (Key_ID_S#) from the local key identification code 222 of the storage unit Sto, and performs subsequent actions (invalidating the write-back of its own matching cache line, and invalidating the write-back of the matching cache line in the kernel cache by probing the request; details of the specific actions are described above). By invoking the requirement that multiple entries must be written back to be invalid, the third-level cache (L3) repeatedly accesses the memory unit Sto, sequentially retrieving the specified key identification codes (Key_ID_S1…Key_ID_SN) from the local key identification code 222 and performing operations accordingly. In the hierarchical caches L1, L2, and L3, all cache lines matching the specified key identification codes (Key_ID_S1…Key_ID_SN) are directly invalidated without being written back to system memory 202. This is accomplished by the instruction INVD_Multiple_KeyIDs.

[0142] In addition to the aforementioned snooping filter 224, this application provides another implementation method to achieve write-back and invalidation of the kernel cache (including L1 and L2) (or invalidation without write-back). Please refer to... Figure 2AThe implementation involves the following steps: When the core cache (including L1 and L2) receives a write-back and invalidation request (or a non-write-back invalidation request), it saves the received write-back and invalidation request (or non-write-back invalidation request) to an internal register (not shown in the diagram) of the core cache (including L1 and L2) and enters a waiting-for-synchronization (sync) state (no further operations are performed). The write-back and invalidation request (or non-write-back invalidation request) is passed through the core cache (including L1 and L2) to the last-level cache (L3), causing the last-level cache (L3) to complete the write-back and invalidation (or non-write-back invalidation) of its matching cache line, and then sends a notification back to the core cache via path 226. The second-level cache L2, which is in the waiting-for-synchronization state, does not perform any operations until it receives the notification, at which point it executes the write-back and invalidation request (or non-write-back invalidation request) of the matching cache line previously saved in the internal register (not shown in the diagram). After the second-level cache L2 completes the write-back and invalidation (or invalidation without write-back) of the matching cache line, it sends a notification to the first-level cache L1, causing the first-level cache L1, which is in a state of waiting for a synchronization signal, to start and execute the write-back and invalidation (or invalidation without write-back) of the matching cache line previously stored in an internal register (not shown in the figure). In this embodiment, the write-back and invalidation request (or invalidation without write-back) passed to the hierarchical memory (L1 to L2 to L3) can also have the aforementioned design with / without a specified key identification code (Key_ID_S#). In one embodiment, the notification sent by the third-level cache L3 to the second-level cache L2, and by the second-level cache L2 to the first-level cache L1, is a one-bit value of 1. Compared with the embodiment using a snoop filter, in this embodiment, the last-level cache (L3) can directly pass the notification to the core caches (including L1 and L2) without passing it through a snoop filter.

[0143] This application also provides another implementation that does not use the aforementioned snooping filter 224 to achieve write-back and invalidation of the kernel cache (including L1 and L2) (or invalidation without write-back). Please refer to Figure 2AThe implementation method involves the kernel cache (including L1 and L2) receiving a write-back and invalidate request (or a write-back-is-invalidate request), and then initiating a write-back and invalidate (or write-back-is-invalidate) operation on its own matching cache line. The received write-back and invalidate request (or write-back-is-invalidate request) is then passed to the last-level cache (L3), causing the last-level cache (L3) to also perform a write-back and invalidate (or write-back-is-invalidate) operation on its own matching cache line. In this implementation, the write-back and invalidate (or write-back-is-invalidate) requests passed to the hierarchical memory (L1 to L2 to L3) can also have the aforementioned design with / without a specified key identification code (Key_ID_S). In this embodiment, the kernel cache (including L1 and L2) does not need to enter a waiting state for a synchronization signal; instead, it performs the write-back and invalidate (or write-back-is-invalidate) operation on the matching cache line simultaneously with the last-level cache (L3), thus achieving higher efficiency.

[0144] The following section introduces multi-core computer systems.

[0145] Figure 3The diagram illustrates a computer system 300 implemented according to one embodiment of this application, wherein snoop filter technology is used. Die_1 and Die_2 each include a processor_1 and a processor_2. Each processor_1 / Processor_2 includes multiple cores core_1 to core_N. Each core includes an in-core cache (e.g., L1 and L2 level caches). Processor_1 allows its multiple cores core_1 to core_N to share a last-level cache (e.g., L3 level cache) LLC_1; and in conjunction with the last-level cache LLC_1, processor_1 sets up a snoop filter Snoop_1. Processor_2's multiple cores core_1 to core_N share a last-level cache LLC_2; and in conjunction with the last-level cache LLC_2, processor_2 sets up a snoop filter Snoop_2. The two processors, Processor_1 and Processor_2, provided by Die_1 and Die_2, are both connected to a system memory, Sys_Mem. The diagram illustrates how the core_i of Processor_1 in Die_1 executes the instructions WBINVD_Single_KeyID, WBINVD_Multiple_KeyIDs, INVD_Single_KeyID, or INVD_Multiple_KeyIDs, performing a write-back and invalidation, or invalidation without writing back, based on the key identification code and a hierarchical cache.

[0146] The core_i, through the communication interface formed by its sequential memory cache MOB, transmits write-back and invalidation requests (or non-write-back invalidation requests) 302 to the core cache 304, and then to the last-level cache LLC_1. Based on the received request, the last-level cache LLC_1 finds the cache line that matches the specified key identification code (Key_ID_S#). Regarding write-back and invalidation requests, the last-level cache LLC_1 writes back the cache line that has been modified (in the M state) and does not exist in the parent cache to system memory Sys_Mem, invalidating the matching cache line regardless of its state. Regarding non-write-back invalidation requests, the last-level cache LLC_1 does not write back the matching cache line to system memory Sys_Mem. The last-level cache LLC_1 may find multiple matching cache line flags, which can be loaded into multiple snoop requests 306 and passed to the snoop filter snoop_1. Snoop_1 then passes these snoop requests to the core caches of each core (core_1 to core_N) in Processor_1, causing the cache lines matching these matching cache line flags to be written back and invalidated (or invalidated without being written back). In this way, the write-back and invalidation (or invalidation without being written back) of cache lines matching the specified key identification code (Key_ID_S#) is completed in the core caches of all cores (core_1 to core_N) within Processor_1, as well as in the last-level cache LLC_1 shared by all cores (core_1 to core_N).

[0147] Specifically, through channel 308 between die_1 and die_2, the last-level cache LLC_1 passes the request from the core cache 304 to the last-level cache LLC_2. Based on the received request, the last-level cache LLC_2 identifies the cache line matching the specified key identification code (Key_ID_S#). For write-back and invalidation requests, the last-level cache LLC_2 writes back the cache line that has been modified (M-state cache line) and is not present in the parent cache to system memory Sys_Mem, invalidating the matching cache line regardless of its state. For non-write-back and invalidation requests, the last-level cache LLC_2 does not write back the matching cache line to system memory Sys_Mem, thus invalidating it. The flag of the matching cache line found by the last-level cache LLC_2 is also carried in the snoop request 310 and passed to the snoop filter snoop_2. The snoop request 310 is passed by the snoop filter snoop_2 to the core caches of each core_1 to core_N in processor_2, causing cache lines matching the specified key ID (Key_ID_S#) to be written back and invalidated (or invalidated without being written back). In this way, the write-back and invalidation (or invalidation without being written back) of cache lines matching the specified key ID (Key_ID_S#) is completed in the core caches of all cores_1 to core_N within processor_2, as well as in the lowest-level cache LLC_2 shared by all cores_1 to core_N.

[0148] In this embodiment, similar to the aforementioned technology, the requirement 302 may or may not include a specified key identification code (Key_ID_S#). This key identification code is stored in a memory location accessible by all hierarchical caches and serves as a local key identification code for hierarchical cache access. When the requirement 302 does not include the specified key identification code (Key_ID_S#), the core_i of processor_1 must first transmit the specified key identification code (Key_ID_S#) to processor_2 via channel 308 between die_1 and die_2, and then transmit the write-back invalid request (or non-write-back invalid request) 302 to the core cache 304. Processor_2 can save the received specified key identification code (Key_ID_S#) to any of its core memory locations or non-core memory locations.

[0149] Figure 4A , 4B The illustration shows a computer system 400 implemented according to another embodiment of this application, which relates to a multi-core and multi-grid design without using a snooping filter.

[0150] The core_i, through the communication interface formed by its sequential memory cache (MOB), transmits a write-back and invalidation request (or invalidation without write-back) `req` to the core cache (including L1 and L2) 402. The core cache 402 then transmits the write-back and invalidation request (or invalidation without write-back) to the lowest-level cache (LLC_1), and then the core cache 402 enters a state waiting for a synchronization signal (sync). In particular, the core_i can utilize the interrupt design provided in this application (which will be discussed later in conjunction with...) Figure 6 (Detailed explanation) The same request `req` is passed to other cores (other cores on Processor_1 and all cores `core_1...core_N` on Processor_2). These other cores then provide the same request `req` to their respective core caches. The core caches then pass the write-back and invalid request (or invalid without write-back) to the lowest-level cache. The core caches then enter a sync state. All core caches on the entire computer system 400 receive the same request `req` and are all set to a sync state.

[0151] Taking Processor_1 as an example, all core caches transmit the received request (req) to the lowest-level cache LLC_1. Based on the earliest received request (req), the lowest-level cache LLC_1 finds its cache line matching the specified key identification code (Key_ID_S#). The specified key identification code (Key_ID_S#) can be transmitted from the request (req) or provided by a local key identification code stored in the shared memory unit Sto_Die1 (not shown in the diagram, located in a non-core part of Processor_1 in one embodiment). In one embodiment, before core_i transmits the request (req) to the core cache, it first resets the shared memory unit Sto_Die1 and then stores the local key identification code therein. Another implementation involves storing local key identification codes in all cores (core_1…core_N) of Processor_1. The lowest-level cache, LLC_1, queries the local key identification code of the core that first provided the request (req) to obtain the specified key identification code (Key_ID_S#). For write-back and invalidation requests, the lowest-level cache LLC_1 writes back the cache line that has been modified (cache line in state M) and is not present in the upper-level cache to system memory Sys_Mem, invalidating the matching cache line regardless of its state. For non-write-back and invalidation requests, the lowest-level cache LLC_1 invalidates the matching cache line without writing it back to system memory Sys_Mem. After completing the request (req), the lowest-level cache LLC_1 sends a notification to the core caches of all cores (core_1…core_N) of Processor_1. In the kernel cache, after receiving the notification, the second-level cache (L2) executes the request (req) in the waiting state, writing back and invalidating the cache line matching the specified key identification code (Key_ID_S#) (or invalidating it without writing it back). The specified key identification code (Key_ID_S#) can be included in the request, provided by the local key identification code of the storage unit Sto_Die1, or a local key identification code stored in its own kernel. After completing the request, L2 sends a notification to its parent cache (L1). After receiving the notification, L1 executes the request (req) in the waiting state, writing back and invalidating the cache line matching the specified key identification code (Key_ID_S#) (or invalidating it without writing it back). Similarly, the specified key identification code (Key_ID_S#) can be included in the request, provided by the local key identification code of the storage unit Sto_Die1, or a local key identification code stored in its own kernel.

[0152] Taking Processor_2 as an example, all core caches transmit the received request (req) to the lowest-level cache LLC_2. Based on the earliest received request (req), the lowest-level cache LLC_2 finds the cache line matching the specified key identification code (Key_ID_S#) and performs an action. The specified key identification code (Key_ID_S#) can be the one transmitted by the request (req), or it can be provided by the local key identification code in the shared memory unit Sto_Die2 (not shown in the figure, located in a non-core of Processor_2 in one embodiment), or it can be obtained by querying the local key identification code of the core that first provided the request (req). In one embodiment, before core_i transmits the request (req) to the core cache, it can use the interrupt design provided in this application (which will be discussed later in conjunction with...) Figure 6 (Detailed explanation follows) The local key identification code is passed to the master core of Processor_2. The master core first resets the shared memory unit Sto_Die2 and then stores the local key identification code there. After the lowest level cache LLC_2 completes the request, it sends a notification to the core caches of all cores core_1…core_N of Processor_2. As mentioned above, the second level cache L2 of all cores core_1…core_N of Processor_2 exits the waiting state, completes the request, and sends a notification to its upper-level cache L1. After receiving the notification, the first level cache L1 also exits the waiting state and completes the request. All hierarchical caches of all cores core_1…core_N of Processor_2 have completed the request made by core_i of Processor_1.

[0153] It is worth noting that, in Figure 4A , 4BIn the illustrated embodiment, if core_i of computer system 400 executes a write-back and invalidation request (req), core_i will first pass the write-back and invalidation request (req) to other cores (other cores on processor_1 in die_1, and all cores core_1...core_N on processor_2 in die_2) before passing it to the core cache 402. In one embodiment, core_i passes the write-back and invalidation request (req) to all cores core_1...core_N on processor_2 in die_2 via inter-die channel 408. Then, all cores of computer system 400 execute the write-back and invalidation request (req) synchronously. Synchronous execution of the write-back and invalidation request (req) by all cores means that all cores of computer system 400 simultaneously pass the write-back and invalidation request (req) to their respective core caches for execution. In another embodiment, the synchronous execution of write-back and invalidation request req by all cores further includes: after each core's internal cache receives the write-back and invalidation request req, it simultaneously passes the write-back and invalidation request req to the last-level cache, and then each core's internal cache enters a state waiting for a synchronization signal (sync).

[0154] Furthermore, in a hierarchical cache write-back and invalidation design that does not use snooping filters, if a cache line has been modified (a cache line in the M state), each core needs to write that cache line, stored in the top-level hierarchical cache, back to system memory. For example, if core_i's L1, L2, and L3 caches all contain the modified (M-state) cache line `cacheline1`, then core_i needs to write the cache line `cacheline1` stored in L1 back to system memory. If core_i's L2 and L3 caches both contain the modified (M-state) cache line `cacheline1`, but L1 does not contain it, then core_i needs to write the cache line `cacheline1` stored in L2 back to system memory.

[0155] In another embodiment, Figure 4A , 4BWhen the kernel caches (including L1 and L2) of each core in the computer system 400 receive a write-back and invalidate request (or a write-back-and-invalidate request), they begin the write-back and invalidate (or write-back-and-invalidate) operation for their own matching cache lines. They then pass the received write-back and invalidate (or write-back-and-invalidate) request to the last-level cache (L3), causing the last-level cache (L3) to also perform its own write-back and invalidate (or write-back-and-invalidate) operation for its matching cache lines. In this embodiment, the kernel caches (including L1 and L2) do not need to enter a waiting state for a synchronization signal; instead, they execute the write-back and invalidate (or write-back-and-invalidate) operation for matching cache lines simultaneously with the last-level cache (L3), thus achieving higher efficiency.

[0156] Figure 5 The diagram illustrates a processor 500 implemented according to another embodiment of this application, wherein the in-core cache includes only the first level cache L1, and multiple cores share the second level cache L2.

[0157] In processor 500, cores core_1 and core_2 share a L2 cache 502, and cores core_3 and core_4 share a L2 cache 504. Cores core_1 through core_4 share a L3 cache 506. Core_1, which initiates this application instruction, provides a request (req) to L1 cache 508, which then passes the request (req) to L2 cache 502, which in turn passes the request (req) to L3 cache 506.

[0158] Based on the received request `req`, the third-level cache 506 finds the cache line that matches the specified key identification code (Key_ID_S#) and completes the request action. The specified key identification code (Key_ID_S#) can be the one sent in the request, or a local key identification code stored in the shared memory unit of these cores core_1…core_4 (the shared memory unit can be located in a non-core part of processor 500), or a local key identification code stored in the internal memory unit of these cores core_1…core_4. After completing the request, the third-level cache 506 sends a string of probe requests with matching cache line flags to the probe filter 510, which then passes it to the second-level caches 502 and 504, and further to the first-level caches of each core_1…core_4. Upon receiving each probe request, the second-level caches 502 / 504 write back and invalidate the cache line that matches the matching cache line flag (if it exists) (or invalidate it without writing it back). Upon receiving a snooping request, the first-level cache of each core (core_1…core_4) writes back and invalidates the cache line that matches its cache line flag (if it exists) (or invalidates it without writing it back). The hierarchical cache completes cache line management for the specified key identification code.

[0159] Another implementation does not involve the snooping filter 510. The core core_1, which initiates this application instruction, will also, when providing a request req to the first-level cache 508, use a method such as... Figure 5 The core inter-channel 520 shown, or the interrupt design provided in this application (which will be discussed later) Figure 6 (Detailed explanation) The same request request (req) is passed to other cores core_2...core_4. After receiving the same request request, each of the other cores core_2...core_4 passes the received request request to its own L1 cache. After all the L1 caches of all cores core_1...core_4 on the entire processor 500 receive the same request request, in addition to passing the request request to the next level of cache, they are all set to a state waiting for a synchronization signal (sync).

[0160] Level 2 cache 502 receives request requests from the Level 1 caches of core_1 and core_2. Based on the earliest received request, Level 2 cache 502 sets itself to a sync state and forwards the request to Level 3 cache 506. Level 2 cache 504 receives request requests from the Level 1 caches of core_3 and core_4. Based on the earliest received request, Level 2 cache 504 sets itself to a sync state and forwards the request to Level 3 cache 506.

[0161] Based on the earliest received request (req), the third-level cache 506 finds the cache line that matches the specified key identification code (Key_ID_S#), completes the request, and writes back and invalidates the cache line that matches the specified key identification code (Key_ID_S#) (or invalidates it if it is not written back). The specified key identification code (Key_ID_S#) can be the one sent in the request, a local key identification code stored in the shared storage unit of these cores (core_1…core_4), or a local key identification code stored in the internal storage unit of these cores (core_1…core_4). After completing the request, the third-level cache 506 sends a notification to the second-level caches 502 and 504. Upon receiving the notification, the second-level caches 502 / 504 exit the waiting state, execute the request, and write back and invalidates the cache line that matches the specified key identification code (Key_ID_S#) (or invalidates it if it is not written back). Similarly, the specified key identification code (Key_ID_S#) can be the one sent in the request, a local key identification code stored in the shared storage unit of these cores (core_1…core_4), or a local key identification code stored in the internal storage unit of these cores (core_1…core_4). After completing the request, the second-level cache 502 sends a notification to the first-level cache (L1) of cores core_1 and core_2. After completing the request, the second-level cache 504 sends a notification to the first-level cache (L1) of cores core_3 and core_4. Upon receiving the notification, the first-level cache (L1) exits the waiting state, executes the request, and writes back and invalidates the cache line matching the specified key identification code (Key_ID_S#) (or invalidates it without writing it back). The specified key identification code (Key_ID_S#) can be the one requested from req, a local key identification code stored in the shared storage unit of these cores core_1…core_4, or a local key identification code stored in the internal storage unit of the core to which it belongs.

[0162] For two processors (such as processor 500) fabricated on two separate dies, when either processor initiates the instructions of this application to manage the hierarchical flash memory using a specified key identifier, it will, through the inter-die channel, enable all cores in the other processor to send the same request (req) to the Level 1 cache (L1). In this way, the hierarchical caches on different dies are managed uniformly.

[0163] In another embodiment that does not involve the eavesdropping filter 510, Figure 5 When the core caches (including L1 and L2) of each core in the processor 500 receive a write-back and invalidate request (or a write-back-and-invalidate request), they begin the write-back and invalidate (or write-back-and-invalidate) operation for their own matching cache lines. They then pass the received write-back and invalidate (or write-back-and-invalidate) request to the last-level cache (L3), causing the last-level cache (L3) to also perform its own write-back and invalidate (or write-back-and-invalidate) operation for its matching cache lines. In this embodiment, the core caches (including L1 and L2) do not need to enter a waiting state for a synchronization signal; instead, they execute the write-back and invalidate (or write-back-and-invalidate) operation for matching cache lines simultaneously with the last-level cache (L3), thus achieving higher efficiency.

[0164] This application provides an interrupt design that enables multi-core architectures to handle situations where any core initiates the instructions of this application.

[0165] Figure 6 The diagram illustrates a computer system 600 with a multi-core architecture implemented according to one embodiment of this application. For example... Figure 6 As shown, the relevant microcode ucode (and) Figure 2AThe ucode in the diagram can be the same ucode, including the microinstructions of interrupt design 602. Core_1 initiates the application instructions, and at least one microinstruction generated after decoding by a decoder (e.g., decoder 206) contains the microinstructions of interrupt design 602. This at least one microinstruction is passed to the execution unit (not shown in the figure) and the memory sequential buffer (MOB) 608 for execution via register list (RAT) 604 and reserved station (RS) 606. The execution unit (not shown in the figure) can send an interrupt request 610 to an inter-core interrupt processor 612 by executing the microinstructions of interrupt design 602 through the memory sequential buffer (MOB) 608. The message carried by the interrupt request 610 may include: the target core (e.g., core_2) and the interrupt reason (e.g., this application makes a write-back and invalid request / non-write-back and invalid request req), which can be generated by the execution unit (e.g., ALU, etc., not shown in the figure) by executing other microinstructions before sending the interrupt request 610. Inter-core interrupt processor 612 analyzes interrupt request 610 and issues an interrupt to target core_2, specifying the interrupt vector number and interrupt cause (req). Through the rearranged buffer (ROB) 614 of core_2, after the currently executing ISA instruction of core_2 retires, core_2 responds to the interrupt cause (req) by executing the microinstruction of interrupt design 616 in the microcode corresponding to the interrupt vector number; for example, it loads the same request req into the core_2's internal cache. In a specific implementation, a reserved or undefined interrupt vector number can be selected from the interrupt vector table as the interrupt vector number of this invention. Those skilled in the art can use microcode to write interrupt designs 602 and 616 that meet the requirements of this invention based on the functions of interrupt designs 602 and 616 in this invention.

[0166] In another implementation, the interrupt cause (req) is stored in a memory space within core_2. Core_2 periodically checks this memory space (for example, it can use a polling mechanism to check it at fixed intervals), causing the same request req to be sent to the core_2's on-core cache.

[0167] Any computer system (single-core processor, multi-core processor, or multi-processor) that uses ISA instructions to implement hierarchical cache management (write-back and invalid, or no write-back and invalid) of specified key identification codes (single or multiple specified) falls within the scope of this application.

[0168] According to the technology of this application, the hierarchical cache is equipped with corresponding key-based management functions; when the transparent full memory encryption function is enabled, the operating system can manage the hierarchical cache at the key-based granularity.

[0169] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the claims.

Claims

1. A computer system for hierarchical cache write-back and invalidation based on a specified key identification code, comprising: The first core, the first processor fabricated on the first die, includes a decoder, a sequential memory cache, and a high-speed cache within the first core; as well as The first and final level cache is manufactured in this first processor; in: In response to the first instruction of the instruction set architecture that writes back and invalidates the hierarchical cache based on a single specified key identification code, the decoder translates into at least one microinstruction; According to at least one microinstruction, the write-back and invalidation request is supplied to the first core cache through the memory sequential cache area, and then the first core cache is handed over to the first last-level cache. In response to the write-back and invalidation request, the first-last-level cache finds all matching cache lines that match the specified key identification code, writes back the modified matching cache lines that do not exist in the upper-level cache to system memory, and invalidates all the found matching cache lines regardless of whether the state has changed.

2. The computer system for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 1, wherein: When the valid bit of a cache line is set to invalid, the cache line becomes invalid.

3. The computer system for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 1, wherein: The write-back and invalidation requirement must contain the specified key identification code; and The first-most cache finds all matching cache lines that match the specified key identification code in the write-back and invalidation request.

4. The computer system for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 1, further comprising: The first storage unit stores the designated key identification code parsed from the first instruction; in: The write-back and invalidation requirement does not contain the specified key identification code; When the first last-level cache receives the write-back and invalidation request, it obtains the specified key identification code from the first storage unit and uses it to find all matching cache lines that match the specified key identification code.

5. The computer system for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 4, wherein: The first storage unit is located in the first core and is used by the first core itself, or the first storage unit is located in a non-core of the first processor and is shared by multiple cores of the first processor.

6. The computer system for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 1, wherein: The first processor also includes a first eavesdropping filter; The first lowest-level cache sends a snooping request to each matching cache line and passes it to the first core cache through the first snooping filter. Each snoop request carries a flag common to the corresponding matching cache line in the hierarchical cache; and In response to each snooping request, the first core cache finds the cache line that matches the flag in the snooping request, writes the modified cache line back to the system memory, and invalidates the found cache line regardless of whether the state has changed.

7. The computer system for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 6, wherein: The first core cache includes a level 1 cache and a level 2 cache; This first and last level cache is the third level cache; The write-back and invalidation request is passed from the first-level cache to the second-level cache, and then from the second-level cache to the third-level cache; Each snooping request is received by the second-level cache from the first snooping filter, and then passed by the second-level cache to the first-level cache; Based on each snooping request, the second-level cache finds a cache line that matches the flag specified in the snooping request, writes the modified cache line, which is not present in the upper-level cache, back to the system memory, and invalidates the cache line regardless of whether its state has changed; and According to each snooping request, the first-level cache finds the cache line that matches the flag carried in the snooping request, writes the modified cache line back to the system memory, and invalidates the cache line regardless of whether the state of the cache line has changed.

8. The computer system for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 6, wherein: The first processor also includes a second core, which includes a second-core cache; Each snooping request is also passed from the first snooping filter to the second core cache; In response to each snooping request, the second core cache finds the cache line that matches the flag in the snooping request, writes the modified cache line back to the system memory, and invalidates the found cache line regardless of whether the state has changed.

9. The computer system for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 8, wherein: The first core and the second core each use a first-level cache as their respective internal caches; The first processor provides a second-level cache for the first core, and the second core shares the cache. This first and last level cache is the third level cache; The write-back and invalidation request is passed from the first-level cache of the first core to the second-level cache shared by the first core and the second core, and then from the second-level cache to the third-level cache; The first snooping filter delivers each snooping request to the second level cache shared by the first core and the second core, and then the second level cache passes it to the first level cache of the first core and the first level cache of the second core. According to each snooping request, the second-level cache finds the cache line that matches the flag carried in the snooping request, writes the modified cache line that does not exist in the upper-level cache back to the system memory, and invalidates the cache line regardless of whether the state of the cache line has changed. According to each probe request, the first core's first-level cache finds the cache line that matches the flag carried in the probe request, writes the modified cache line back to the system memory, and invalidates the cache line regardless of whether its state has changed; and According to each snooping request, the first-level cache of the second core finds the cache line that matches the flag carried in the snooping request, writes the modified cache line back to the system memory, and invalidates the cache line regardless of whether the state of the cache line has changed.

10. The computer system for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 1, further comprising: A second processor fabricated on a second die, the second processor including a third core and a second last-level cache, the third core including a third in-core cache; in: The first last-level cache also passes the write-back and invalidation request from the first core cache to the second last-level cache via the channel between the first die and the second die; and In response to the received write-back and invalidation request, the second lowest-level cache finds all matching cache lines that match the specified key identification code, writes back the modified matching cache lines that do not exist in the upper-level cache to the system memory, and invalidates all found matching cache lines regardless of whether the state has changed.

11. The computer system for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 10, wherein: The second processor also includes a second eavesdropping filter; The second lowest-level cache sends a snooping request to each matching cache line and passes it to the third core cache through the second snooping filter. Each snoop request carries a flag common to the corresponding matching cache line in the hierarchical cache; and In response to each snooping request, the third core cache finds the cache line that matches the flag in the snooping request, writes the modified cache line back to the system memory, and invalidates the found cache line regardless of whether the state has changed.

12. The computer system for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 1, wherein: After invalidating all matching cache lines, the first last-level cache sends a first notification back to the first core cache. and The first core cache that supplies the write-back and invalidation request to the first last-level cache is in a waiting synchronization signal state until it receives the first notification returned by the first last-level cache. Then, it finds all matching cache lines that match the specified key identification code, writes back the modified matching cache lines that do not exist in the upper-level cache to the system memory, and invalidates all the found matching cache lines regardless of whether the state has changed.

13. The computer system for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 12, wherein: The first core cache includes a level 1 cache and a level 2 cache; This first and last level cache is the third level cache; The write-back and invalidation request is passed from the first-level cache to the second-level cache, and then from the second-level cache to the third-level cache; The third-level cache passes the first notification to the second-level cache; According to the first notification, the second-level cache, which is in the state of waiting for a synchronization signal, is started, finds all matching cache lines that match the specified key identification code, writes the modified matching cache lines that do not exist in the upper-level cache back to the system memory, and invalidates all the found matching cache lines regardless of whether the state has changed. After invalidating all matching cache lines, the second-level cache sends a second notification back to the third-level cache; and According to the second notification, the first-level cache, which is in a state of waiting for a synchronization signal, is activated, finds all matching cache lines that match the specified key identification code, writes the modified matching cache lines back to the system memory, and invalidates all the found matching cache lines regardless of whether the state has changed.

14. The computer system for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 12, wherein: The first processor also includes a second core, which includes a second-core cache; The write-back and invalidation request is supplied to the second core through the memory sequential cache of the first core, and then passed to the first last-level cache by the second core's internal cache. and The write-back and invalidation request responded to by the first lowest-level cache is the earlier one that came from the first core and the second core.

15. The computer system for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 14, further comprising: The inter-core interrupt handler receives the interrupt request issued by the first core through the memory sequential cache for the write-back and invalidation request, and operates the second core's rearranged cache accordingly, initiating the interrupt design of the second core's microcode, so that the write-back and invalidation request is handed over to the cache within the second core.

16. The computer system for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 14, wherein: The first last-level cache also sends the first notification back to the second core cache, which is in a state of waiting for a synchronization signal. The second core cache then searches for all matching cache lines that match the specified key identification code, writes the modified matching cache lines back to the system memory, and invalidates all the found matching cache lines regardless of whether the state has changed.

17. The computer system for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 16, wherein: The first core and the second core each use a first-level cache as their respective internal caches; The first processor provides a second-level cache for the first core, and the second core shares the cache. This first and last level cache is the third level cache; The write-back and invalidation request is passed from the first-level cache of the first core to the second-level cache shared by the first core and the second core, and then from the second-level cache to the third-level cache; The third-level cache transmits the first notification to the first core and the second-level cache shared by the second core; According to the first notification, the second-level cache, which is in the state of waiting for a synchronization signal, is started, finds all matching cache lines that match the specified key identification code, writes the modified matching cache lines that do not exist in the upper-level cache back to the system memory, and invalidates all the found matching cache lines regardless of whether the state has changed. After invalidating all matching cache lines of the second-level cache, a second notification is sent back to the third-level cache. According to the second notification, in the first core, the first-level cache, which is in a state of waiting for a synchronization signal, is activated, finds all matching cache lines that match the specified key identification code, writes any modified matching cache lines back to the system memory, and invalidates all found matching cache lines regardless of whether their state has changed; and According to the second notification, in the second core, the first-level cache that is in the state of waiting for the synchronization signal is started, finds all matching cache lines that match the specified key identification code, writes the modified matching cache lines back to the system memory, and invalidates all the found matching cache lines regardless of whether the state has changed.

18. The computer system for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 12, further comprising: A second processor fabricated on a second die, the second processor including a third core and a second last-level cache, the third core including a third in-core cache; in: The write-back and invalidation request is supplied to the third core through the memory sequential cache of the first core, through the channel between the first die and the second die, and then passed to the second last-level cache by the third core's internal cache. In response to the received write-back and invalidation request, the second lowest-level cache finds all matching cache lines that match the specified key identification code, writes back any modified matching cache lines that do not exist in the higher-level cache to the system memory, and invalidates all found matching cache lines regardless of whether their state has changed; and After invalidating all matching cache lines, the second lowest-level cache sends a third notification back to the third core cache, which is in a state of waiting for a synchronization signal. The third core cache then searches for all matching cache lines that match the specified key identification code, writes any modified matching cache lines back to the system memory, and invalidates all found matching cache lines regardless of whether the state has changed.

19. The computer system for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 1, wherein: The first instruction involves a single operand, an instruction register, a system memory address, or an immediate value, to obtain the specified key identification code required by the first instruction.

20. A computer system for hierarchical cache write-back and invalidation based on a specified key identification code, comprising: The first core, the first processor fabricated on the first die, includes a decoder, a sequential memory cache, and a high-speed cache within the first core; as well as The first and final level cache is manufactured in this first processor; in: In response to a second instruction in an instruction set architecture that writes back and invalidates a hierarchical cache based on multiple specified key identification codes, the decoder translates at least one microinstruction. According to the at least one microinstruction corresponding to the second instruction, the plurality of specified key identification codes are stored in the storage unit of the first core, and multiple write-back and invalidation requests are supplied to the cache within the first core through the memory sequential cache area, and then the cache within the first core is handed over to the first last-level cache. The multiple write-back and invalidation requests correspond to the plurality of specified key identification codes stored in the storage unit of the first core, so that the write-back and invalidation based on the current specified key identification code is completed before the write-back and invalidation based on the next specified key identification code is performed. The write-back and invalidation based on the currently specified key identification code includes responding to the write-back and invalidation request corresponding to the currently specified key identification code. The first last-level cache finds all matching cache lines that match the currently specified key identification code, writes back the modified matching cache lines that do not exist in the upper-level cache to the system memory, and invalidates all the found matching cache lines regardless of whether the state has changed.

21. The computer system for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 20, wherein: The second instruction involves two operands to obtain a preliminary key identification code setting and a mask. After masking the preliminary key identification code setting using the mask, the plurality of specified key identification codes required by the second instruction are formed.

22. The computer system for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 20, wherein: The second instruction involves two operands for obtaining a system memory address and a specified number of key identification codes. The system memory address indicates a starting key identification code in a list in the system memory. The specified number of key identification codes requested by the second instruction are obtained from the list based on the system memory address and the specified number of key identification codes.

23. A method for hierarchical cache write-back and invalidation based on a specified key identification code, comprising: In response to a first instruction of the instruction set architecture fetched by the first core, which writes back and invalidates the hierarchical cache based on a single specified key identification code, the decoder of the first core converts at least one microinstruction, wherein the first core is a first processor fabricated on a first die; According to at least one microinstruction, write-back and invalid requests are supplied to the first core cache of the first core via the first core's sequential memory cache, and then passed from the first core cache to the first least significant cache. The first least significant cache is manufactured on the first processor, outside the first core. In response to the write-back and invalidation request, the first and last level cache is operated to find all matching cache lines that match the specified key identification code. Among them, the matching cache lines that have been modified and do not exist in the upper level cache are written back to the system memory, and all the found matching cache lines are invalidated regardless of whether the state has changed.

24. The method for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 23, wherein: The write-back and invalidation requirement must contain the specified key identification code; and The first-most cache finds all matching cache lines that match the specified key identification code in the write-back and invalidation request.

25. The method for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 23, further comprising: The designated key identification code parsed from the first instruction is stored in the first storage unit; in: The write-back and invalidation requirement does not contain the specified key identification code; When the first last-level cache receives the write-back and invalidation request, it obtains the specified key identification code from the first storage unit and uses it to find all matching cache lines that match the specified key identification code.

26. The method for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 23, further comprising: The first, lowest-level cache sends a snooping request to each matching cache line, which is then passed through the first snooping filter on the first processor to the cache within the first core. Each snooping request carries a flag common to the corresponding matching cache line in the hierarchical cache; and In response to each snooping request, the first core cache finds the cache line that matches the flag in the snooping request, writes the modified cache line back to the system memory, and invalidates the found cache line regardless of whether the state has changed.

27. The method for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 26, wherein: The first processor also includes a second core, which includes a second-core cache; Each snooping request is also passed from the first snooping filter to the second core cache; In response to each snooping request, the second core cache finds the cache line that matches the flag in the snooping request, writes the modified cache line back to the system memory, and invalidates the found cache line regardless of whether the state has changed.

28. The method for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 23, further comprising: The first least significant cache also transmits the write-back and invalidation request from the first core cache to the second least significant cache of the second processor on the second die via the channel between the first die and the second die. The second processor further includes a third core, and the third core includes a third core cache. In response to the received write-back and invalidation request, the second lowest-level cache finds all matching cache lines that match the specified key identification code, writes back the modified matching cache lines that do not exist in the upper-level cache to the system memory, and invalidates all found matching cache lines regardless of whether the state has changed.

29. The method for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 28, wherein: The second processor also includes a second eavesdropping filter; The second lowest-level cache sends a snooping request to each matching cache line and passes it to the third core cache through the second snooping filter. Each snoop request carries a flag common to the corresponding matching cache line in the hierarchical cache; and In response to each snooping request, the third core cache finds the cache line that matches the flag in the snooping request, writes the modified cache line back to the system memory, and invalidates the found cache line regardless of whether the state has changed.

30. The method for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 23, wherein: After invalidating all matching cache lines, the first last-level cache sends a first notification back to the first core cache. and The first core cache that supplies the write-back and invalidation request to the first last-level cache is in a waiting synchronization signal state until it receives the first notification returned by the first last-level cache. Only then does it find all matching cache lines that match the specified key identification code, write back the modified matching cache lines that do not exist in the upper-level cache to the system memory, and invalidate all the found matching cache lines regardless of whether the state has changed.

31. The method for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 30, wherein: The first processor also includes a second core, which includes a second-core cache; The write-back and invalidation request is supplied to the second core through the memory sequential cache of the first core, and then passed to the first last-level cache by the second core's internal cache. and The write-back and invalidation request responded to by the first lowest-level cache is the earlier one that came from the first core and the second core.

32. The method for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 31, wherein: The first last-level cache also sends the first notification back to the second core cache, which is in a state of waiting for a synchronization signal. The second core cache then searches for all matching cache lines that match the specified key identification code, writes the modified matching cache lines back to the system memory, and invalidates all the found matching cache lines regardless of whether the state has changed.

33. The method for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 30, further comprising: The write-back and invalidation request is supplied through the memory sequential cache of the first core, through the channel between the first die and the second die, to the third core cache of the second processor on the second die, and then from the third core cache of the third core to the second processor's second last-level cache. In response to the received write-back and invalidation request, the second lowest-level cache finds all matching cache lines that match the specified key identification code, writes back any modified cache lines that are not present in the higher-level cache to the system memory, and invalidates all found matching cache lines regardless of whether their state has changed; and After invalidating all matching cache lines of the second lowest-level cache, a third notification is sent back to the third core cache, which is in a state of waiting for a synchronization signal. The third core cache is then started, and all matching cache lines that match the specified key identification code are found. Any modified matching cache lines are written back to the system memory, and all found matching cache lines are invalidated regardless of whether the state has changed.

34. A method for hierarchical cache write-back and invalidation based on a specified key identification code, comprising: In response to a second instruction of an instruction set architecture fetched by a first core and written back to and invalidated by a hierarchical cache based on multiple specified key identification codes, the decoder of the first core converts at least one microinstruction, wherein the first core is a first processor fabricated on a first die; According to the at least one microinstruction corresponding to the second instruction, the plurality of specified key identification codes are stored in the storage unit of the first core, and the multiple write-back and invalidation requests are supplied to the first core cache of the first core through the memory sequential cache area of ​​the first core, and then passed to the first last-level cache of the first core by the first core cache. The multiple write-back and invalidation requests correspond to the plurality of specified key identification codes stored in the storage unit of the first core, so that the write-back and invalidation based on the current specified key identification code is completed before the write-back and invalidation based on the next specified key identification code is performed. The write-back and invalidation based on the currently specified key identification code includes responding to the write-back and invalidation request corresponding to the currently specified key identification code. The first last-level cache finds all matching cache lines that match the currently specified key identification code, writes back the modified matching cache lines that do not exist in the upper-level cache to the system memory, and invalidates all the found matching cache lines regardless of whether the state has changed.

35. The method for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 34, wherein: The second instruction involves two operands for obtaining a preliminary key identification code setting and a mask. After masking the preliminary key identification code setting using the mask, the plurality of specified key identification codes required by the second instruction are formed.

36. The method for hierarchical cache write-back and invalidation based on a specified key identification code as described in claim 34, wherein: The second instruction involves two operands for obtaining a system memory address and a specified number of key identification codes. The system memory address indicates a starting key identification code in a list in the system memory, and the specified number of key identification codes requested by the second instruction are obtained from the list based on the system memory address and the specified number of key identification codes.

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