A high-performance PSoC chip based on SiP technology and its packaging structure
Through the high-performance PSoC chip based on SiP technology, combined with RDL and EHS-FCBGA packaging structure, the problems of large area and low integration of existing systems are solved, and the embedded board is miniaturized, highly integrated and reliable. , improves storage rate and system stability.
Patent Information
- Application Number
- CN202111503588.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-12-09
- Publication Date
- 2024-12-20
- Estimated Expiration
- 2041-12-09
AI Technical Summary
The existing system integrating processing, control and storage adopts a separate device design, resulting in a large overall area, low integration, and difficult resistance to electromagnetic interference, which cannot meet the needs of electronic equipment for miniaturization, high integration and high reliability.
Adopt high-performance PSoC chip based on SiP technology, ARM is realized through the packaging of processor die, multi-chip DDR die, Flash die, dual-power bus transceiver die and power chip, combined with RDL, SMT, FC and other technologies The single chip with FPGA and its on-chip storage is highly integrated, and adopts an EHS-FCBGA package structure and a non-standard rectangular heat sink cover design to reduce hardware costs and design difficulty.
It realizes the miniaturization, high integration and high reliability of embedded boards, reduces the difficulty and cost of board design, improves the flexibility and stability of storage rates and system, and reduces maintenance costs.
Smart Images
Figure CN114065678B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of digital signal processing and control chips, in particular to a high-performance PSoC chip based on SiP technology. Background Art
[0002] As electronic equipment rapidly develops towards short, light, small, thin, high reliability, high performance, high speed and low cost, the demand for miniaturization and modularization of processing and control systems is becoming more and more urgent. Therefore, it is urgent to adopt multi-chip component technology to interconnect and assemble ICs such as microprocessors, FPGAs, memories and interfaces on a high-density multi-layer interconnect substrate to form a functional and highly reliable electronic component system to achieve miniaturization and high-density integration of processing and control systems.
[0003] Currently, most of the existing systems integrating processing, control and storage on the market adopt the architecture of MCU controller + FPGA + storage or directly adopt the external storage method of FPGA containing ARM processor. All of them are separate device design solutions with large overall area, low integration and great difficulty in resisting electromagnetic interference.
[0004] Therefore, there is an urgent need for a high-performance PSoC chip based on SiP technology that adopts a programmable mixed signal array architecture to effectively save the board area of the embedded board, reduce hardware costs, and reduce the difficulty of board design. It can achieve miniaturization, high integration, and high reliability of the embedded board, taking into account the programmable hardware acceleration processing function of FPGA and the flexible control and management function of MCU. Summary of the invention
[0005] The present invention proposes a high-performance PSoC chip based on SiP technology, and the technical solution adopted is as follows:
[0006] A high-performance PSoC chip based on SiP technology, comprising a processor bare core, multiple DDR bare cores, multiple Flash bare cores, a dual-power bus transceiver bare core, a power chip and a number of discrete resistors and capacitors, all bare cores, finished chips and a number of discrete resistors and capacitors are packaged as one through SiP technology; the processor bare core is connected to the multiple DDR bare cores respectively, the processing system PS in the processor bare core is connected to a part of the DDR bare core for software application cache, and the related signals are only interconnected internally and are not led out of the PSoC chip; the programmable logic system PL in the processor bare core is connected to another part of the DDR bare core for hardware logic cache, and the related signals are only interconnected internally and are not led out of the PSoC chip; The processor core is connected to multiple Flash cores respectively. The processing system PS in the processor core is connected to a part of the Flash core for program loading. The relevant signals are not only interconnected internally but also led out to the outside of the PSoC chip for loading configuration. The programmable logic system PL in the processor core is connected to a part of the Flash core for parameter storage. The relevant signals of the processor core are only interconnected internally and are not led out to the outside of the PSoC chip. The processor core is connected to the dual power bus transceiver core for level conversion and driving. The processor core is connected to the power chip, and the power chip is connected to multiple DDR cores.
[0007] The PSoC chip of the present invention realizes the single chip high integration of FPGA with ARM and its on-chip storage based on SiP technologies such as RDL, SMT, FC, etc. The use of this high-performance PSoC chip on embedded boards can effectively save the board area of the board, reduce hardware costs, reduce the difficulty of board design, and realize the miniaturization, high integration and high reliability of embedded boards.
[0008] In the preferred embodiment of the technical solution of the present invention, the processor die itself is subjected to the FC flip chip process, and the DDR die, Flash die and dual power bus transceiver die are converted from the Wire Bond wire bonding process to the FC flip chip process through the RDL technology, so that all the die in the high-performance PSoC chip are converted from the FC and Wire Bond mixed process to the FC single structure. The integrated circuit die inside the PSoC chip is all based on the FC flip chip welding process based on the chip bump, which not only avoids the disadvantage of the WireBond wire bonding process that it is difficult to control the signal impedance, but also reduces the difficulty of substrate and packaging production.
[0009] Preferably, the DDR bare core and the Flash bare core in the PSoC chip are arranged around the processor bare core, and multiple DDR bare cores are distributed on both sides of the processor bare core, and are arranged in the upper middle part of the substrate close to the signal PAD position corresponding to the processor bare core.
[0010] In the preferred embodiment of the technical solution of the present invention, the arrangement areas of the DDR bare cores on both sides of the PSoC chip are expanded a certain distance to both sides of the substrate. The DDR bare core areas on both sides are expanded to the rectangular heat dissipation cover area, which takes into account both the chip size and the DDR substrate routing space.
[0011] The present invention further discloses a high-performance PSoC chip packaging structure based on SiP technology, which adopts an EHS-FCBGA packaging method and includes a heat dissipation cover. The four edges of the heat dissipation cover are the first bonding area. The heat dissipation cover is concave at the position corresponding to the bare core to form a special-shaped groove. The depth of the special-shaped groove is equal to the sum of the vertical height of the highest bare core after RDL and the thickness of the thermal conductive adhesive. The bottom of the special-shaped groove is arranged to replace the boss of the thermal conductive adhesive between the bottom of the groove and the top surface of other bare cores.
[0012] In the preferred embodiment of the technical solution of the present invention, a second bonding area is added to the left and right sides of the lower middle part of the heat dissipation cover. The second bonding area is expanded to the blank area of the substrate resistor and capacitor, which makes up for the reduction of the heat dissipation cover area caused by the expansion of the DDR bare core layout and increases the bonding strength.
[0013] The beneficial effects of the present invention compared with the prior art are:
[0014] 1. The chip of the present invention has integrated a processor, DDR and its LDO power chip and termination resistor, FLASH, dual power bus transceiver, etc. Users can reduce the additional configuration of peripherals at the board level, effectively save the board area, reduce hardware costs, reduce the difficulty of board design, and realize the miniaturization, high integration and high reliability of embedded boards.
[0015] 2. The chip of the present invention, from the perspective of the memory bare core, directly adopts the substrate interconnection method of "bare core-substrate-bare core" to replace the conventional PCB interconnection method of "bare core-substrate-package-PCB-package-substrate-bare core", without considering pindelay compensation, which can effectively shorten the wiring length between the processor and the memory and improve the storage rate. At the same time, users can directly reuse relevant configuration parameters and files to achieve strong flexibility, high stability and low maintenance cost of embedded boards.
[0016] 3. The chip packaging structure of the present invention is a flat structure, combined with RDL technology, so that the internal packaging structure of the SiP chip is converted into SMT bonding process and FC flip-chip process. In addition, from the perspective of bare core layout and routing, the substrate packaging cover area adopts a non-standard rectangular area, and the DDR on both sides is expanded 1.25mm to the heat dissipation cover area, which not only reduces the chip size, but also takes into account the bonding strength and heat dissipation performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1The schematic diagram is a schematic diagram of the principle architecture of a high-performance PSoC chip based on SiP technology and its packaging structure of the present invention.
[0018] Figure 2 Schematic diagram of the cavity layout of the high-performance PSoC chip based on SiP technology and its packaging structure of the present invention (the dotted line in the figure encloses the cavity of the packaging structure of the prior art).
[0019] Figure 3 This is a horizontal (TOP VIEW) cutaway view of the heat sink.
[0020] Figure 4 This is the longitudinal (SIDE VIEW) view of the heat sink. DETAILED DESCRIPTION
[0021] The technical solution of the present invention is described in detail below, but the protection scope of the present invention is not limited to the embodiments.
[0022] To make the content of the present invention more clearly understood, the following Figure 1-Figure 4 The specific implementation manner is further described.
[0023] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.
[0024] In this embodiment, a PSoC chip composed of a processor die 1, four DDR die, two Flash die, a dual-power bus transceiver die, a power chip 9 and several discrete resistors and capacitors is taken as an example for further description.
[0025] In this embodiment, the four DDR bare cores are preferably DDR3 bare cores. By definition, the four DDR3 bare cores are divided into a first DDR3 bare core 2, a second DDR3 bare core 3, a third DDR3 bare core 4 and a fourth DDR3 bare core 5. The two Flash bare cores are respectively a first Flash bare core 6 and a second Flash bare core 7.
[0026] like Figure 1 and 2 As shown, in this embodiment, a processor bare core 1, four DDR3 bare cores, two Flash bare cores, a dual-power bus transceiver bare core, a power chip 9 and a number of discrete resistors and capacitors are packaged as one through SiP technology, and the internal part is integrated into a SiP chip through substrate interconnection or lead-out.
[0027] like Figure 2As shown, four DDR3 bare cores and two Flash bare cores in the PSoC chip are arranged around the processor bare core 1. The four DDR3 bare cores are symmetrically distributed on both sides of the processor bare core 1 and are arranged in the upper middle part of the substrate close to the signal PAD position corresponding to the processor bare core 1.
[0028] like Figure 2 As shown, the first DDR3 die 2 and the second DDR3 die 3 in the four DDR3 die are distributed on the right side of the processor die 1, the third DDR3 die 4 and the fourth DDR3 die 5 are distributed on the left side of the processor die 1, two Flash die are distributed in the upper area of the processor die 1, a power chip 9 is arranged in the upper area of the processor die 1 and is located outside the two Flash die; a dual power bus transceiver die is arranged in the middle and lower part of the right side of the processor die 1. The arrangement areas of the DDR die on both sides of the PSoC chip are expanded outwards to both sides of the substrate 11 by a certain distance.
[0029] In this embodiment, the bare cores of integrated circuits in the PSoC chip are all FC flip-chip soldered based on chip bumps. All DDR3 bare cores, Flash bare cores, and dual power bus transceiver bare cores need to convert the Wire Bond wire bonding process into the FC flip-chip process through RDL, so that all bare cores in the high-performance PSoC chip are converted from the FC and Wire Bond mixed process into a FC single structure for substrate design and packaging. The FC flip-chip soldering process mentioned in this embodiment is a known technology for those skilled in the art.
[0030] like Figure 1 As shown, in this embodiment, the processor bare core 1 itself undergoes FC packaging process, and the processor bare core 1 preferably adopts the bare core of model FMQL45T900 sold by Shanghai Fudan Microelectronics Group Co., Ltd.
[0031] like Figure 1 and 2 As shown, the processor die 1 is connected to four DDR3 die respectively, and the related signals of the processor die 1 are only interconnected internally and are not led out to the outside of the PSoC chip; the processing system PS in the processor die 1 is connected to the third DDR3 die 4 and the fourth DDR3 die 5 for software application cache. In this embodiment, the third DDR3 die 4 and the fourth DDR3 die 5 are preferably domestically produced DDR3 die, with a single-chip data width of 16 bits and a storage capacity of 4Gb, a single-group data width of 32 bits and a storage capacity of 8Gb.
[0032] like Figure 1 and 2As shown, the programmable logic system PL in the processor core 1 is connected to the first DDR3 core 2 and the second DDR3 core 3 for hardware logic cache. In this embodiment, the first DDR3 core 2 and the second DDR3 core 3 preferably use domestic DDR3 cores, with a single-chip data width of 16 bits and a storage capacity of 4Gb, a single-group data width of 32 bits and a storage capacity of 8Gb. Figure 1 As shown, in this embodiment, the connection signals between the programmable logic system PL in the processor die 1 and the first DDR3 die 2 and the second DDR3 die 3 are located in HP BANK33 and HP BANK34 of the processor die 1.
[0033] like Figure 1 and 2 As shown, the first Flash bare core 6 in this embodiment is a QSPI Flash bare core, preferably a domestically produced model JFM25F128A die sold by Shanghai Fudan Microelectronics Group Co., Ltd., with a storage capacity of 128Mb and a power supply voltage of 3.3V, which is used for program loading; the second Flash bare core 7 is a QSPI Flash bare core, with a storage capacity of 256Mb and a power supply voltage of 1.8V, which is used for parameter storage.
[0034] like Figure 1 As shown, the processing system PS in the processor bare core 1 is connected to the first Flash bare core 6; the programmable logic system PL in the processor bare core 1 is connected to the second Flash bare core 7, as shown in FIG. Figure 1 As shown, in this embodiment, the connection signal between the processing system PS in the processor bare core 1 and the first Flash bare core 6 is located in BANK500 of the processor bare core 1, and the connection signal between the programmable logic system PL in the processor bare core 1 and the second Flash bare core 7 is located in HP BANK35 of the processor bare core 1.
[0035] like Figure 1 As shown, the processor die 1 is connected to a dual-power bus transceiver die inside the high-performance PSoC chip. One side of the power supply is the corresponding HR BANK10 voltage, and the other side of the power supply is a user-defined interface voltage, which supports a maximum data bit width of 16 bits and is used for level conversion and driving.
[0036] like Figure 1 As shown, the processor bare core 1 is connected to the power chip 9, and the power chip 9 is connected to four DDR bare cores; the power chip 9 generates the PS and PL DDR controllers, VTT and VREF required by the DDR3 circuit inside the high-performance PSoC chip, and the chip integrates DDR3 decoupling capacitors and termination resistors.
[0037] In this embodiment, the processor bare core decoupling capacitor uses a low ESL 8-pin capacitor and an inverted seal capacitor according to the power integrity simulation result.
[0038] like Figure 1 , 2 As shown in , 3 and 4, the high-performance PSoC chip packaging structure based on SiP technology in this embodiment adopts EHS-FCBGA packaging, heat dissipation cover 10, and adopts special-shaped stamping. The chip size is 40mm*40mm; the bottom structure of the PSoC chip packaging structure includes 1521 signal balls, with a diameter of 0.6mm and a pitch spacing of 1.0mm. Specifically, GTX, HP BANK, HR BANK, PS BANK, dual power bus transceiver, and corresponding reference voltages are distributed in the surrounding area, and three power supplies and grounds of VDD1V0, VDD1V8 and VDD1V5 are distributed in the middle pre-area.
[0039] The schematic diagram of the cavity layout of the high-performance PSoC chip and its packaging structure based on SiP technology in this embodiment includes: chip or discrete device area, bare core underfill area, design rule spacing, wiring area, and packaging cover area.
[0040] like Figure 2 As shown, specifically, the high-performance PSoC chip packaging structure is a tiled structure, but from the perspective of bare core layout and routing, the substrate packaging cover area adopts a non-standard rectangular area, and the DDR on both sides expands 1.25mm to the heat dissipation cover area, which not only reduces the chip size but also takes into account the bonding strength and heat dissipation performance.
[0041] like Figure 3 and 4 As shown, the heat dissipation cover 10 of the packaging structure of this embodiment has four peripheral edges forming the first bonding area 10-3, and the heat dissipation cover 10 is concave at the position corresponding to the bare core to form a special-shaped groove 10-1, and the depth of the special-shaped groove 10-1 is equal to the sum of the vertical height of the highest bare core after RDL and the thickness of the thermal conductive adhesive; the setting of the special-shaped groove 10-1 covers all the bare cores on the PSoC chip; that is, the heat dissipation cover of the PSoC chip of this embodiment adopts a non-standard rectangular cavity structure in the horizontal direction (TOP VIEW).
[0042] like Figure 2 As shown, the layout area of the DDR bare cores on both sides of the PSoC chip is expanded a certain distance to both sides of the substrate 11. In this embodiment, the left and right sides of the special-shaped slot 10-1 are matched with the outward expansion layout of the substrate, and the heat sink cavity area 10-4 is added. In this embodiment, the heat sink cavity area 10-4 is 1.25mm in size. The DDR3 bare core areas on both sides of the PSoC chip are expanded 1.25mm to the rectangular heat sink area, which takes into account both the chip size and the DDR3 substrate routing space.
[0043] like Figure 3 and4 As shown, a second bonding area 10-2 is added to the left and right sides of the lower middle part of the heat dissipation cover 10; specifically, the arrangement and placement of the bare core in the PSoC chip of this embodiment, because the left and right sides of the special-shaped groove 10-1 are to match the outward expansion layout of the substrate, the heat dissipation cover cavity area 10-4 is added, and the first bonding area 10-3 on the four edges of the heat dissipation cover is reduced. Therefore, the heat dissipation cover area is expanded to the blank area of the substrate resistor and capacitor in the lower left and lower right, which makes up for the reduction of the heat dissipation cover area caused by the outward expansion of the DDR3 bare core layout, and increases the bonding strength.
[0044] like Figure 3 and 4 As shown, the heat dissipation cover of the PSoC chip in this embodiment has a boss 10-5 at the bottom of the special-shaped groove that is used to replace the thermal conductive glue between the bottom of the groove and the top surface of other bare cores, that is, the heat dissipation cover adopts a boss-type cavity structure in the vertical direction. In this embodiment, based on the height of the processor bare core 1, the heat dissipation cover is designed to have a thickness of 0.8mm, and the cavity is processed on the top of the power chip and the QSPI Flash7 ultra-high device, and the heat dissipation cover is designed to have a thickness of 0.6mm, which not only meets the requirements of the height of the cavity for the finished package and the device height after RDL, but also takes into account the heat dissipation performance of the main device.
[0045] The above embodiments are only for illustrating the technical idea of the present invention, and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.
Claims
1. A high-performance PSoC chip based on SiP technology, characterized by: It comprises a processor bare core (1), multiple DDR bare cores, multiple Flash bare cores, a dual power bus transceiver bare core, a power chip (9) and a number of resistor and capacitor discrete devices, wherein all bare cores, finished chips and a number of resistor and capacitor discrete devices are packaged into one by using SiP technology; The processor bare core (1) is respectively connected to a plurality of DDR bare cores, the processing system PS in the processor bare core (1) is connected to a part of the DDR bare cores for software application cache, and the related signals are only interconnected internally and are not led out to the outside of the PSoC chip; the programmable logic system PL in the processor bare core (1) is connected to another part of the DDR bare cores for hardware logic cache, and the related signals are only interconnected internally and are not led out to the outside of the PSoC chip; The processor bare core (1) is respectively connected to a plurality of Flash bare cores, the processing system PS in the processor bare core (1) is connected to a part of the Flash bare core for program loading, and the related signals are not only interconnected internally, but also led out to the outside of the PSoC chip for loading configuration; the programmable logic system PL in the processor bare core (1) is connected to a part of the Flash bare core for parameter storage, and the related signals of the processor bare core (1) are only interconnected internally and are not led out to the outside of the PSoC chip; The processor bare core (1) is connected to the dual power bus transceiver bare core for level conversion and driving, the processor bare core (1) is connected to the power chip (9), and the power chip (9) is connected to multiple DDR bare cores; The processor die (1) itself is subjected to the FC flip-chip process, and the DDR die, Flash die, and dual-power bus transceiver die are converted from the Wire Bond process to the FC flip-chip process through the RDL technology, so that all the die in the high-performance PSoC chip are converted from the FC and Wire Bond mixed process to a FC single structure; The DDR bare core and the Flash bare core in the PSoC chip are arranged around the processor bare core (1), and a plurality of DDR bare cores are distributed on both sides of the processor bare core (1) and arranged in the upper middle part of the substrate close to the signal PAD position corresponding to the processor bare core (1).
2. The high-performance PSoC chip based on SiP technology according to claim 1, characterized in that: The layout areas of the DDR bare cores on both sides of the PSoC chip are expanded a certain distance outwards to both sides of the substrate.
3. A packaging structure of a high-performance PSoC chip based on SiP technology according to any one of claims 1-2, characterized in that: An EHS-FCBGA packaging method is adopted, including a heat dissipation cover (10), wherein the four edges of the heat dissipation cover (10) are first bonding areas (10-3), and the heat dissipation cover (10) is concave at the position corresponding to the bare core to form a special-shaped groove (10-1), wherein the depth of the special-shaped groove is equal to the sum of the vertical height of the highest bare core after RDL and the thickness of the thermal conductive adhesive; and the bottom of the special-shaped groove is provided to replace the boss (10-5) of the thermal conductive adhesive between the bottom of the groove and the top surface of other bare cores.
4. The packaging structure of a high-performance PSoC chip based on SiP technology according to claim 3, characterized in that: A second bonding area (10-2) is provided on the left and right sides of the lower middle portion of the heat dissipation cover (10).