Control system with serial drive circuit and driving method thereof

Abstract

The present invention discloses a control system, a driving circuit, and a method for driving a control device. The control system includes a plurality of driving circuits connected in series, and the plurality of driving circuits include a first driving circuit and a second driving circuit. The first driving circuit includes a first receiver, a first transmitter, and a replica receiver, wherein the first transmitter is coupled to the first receiver, and the replica receiver is coupled to an output end of the first transmitter. The second driving circuit is coupled to the first driving circuit, and includes a second receiver and a second transmitter, wherein the second receiver is coupled to the first transmitter, and the second transmitter is coupled to the second receiver.

Description

Technical Field

[0001] The present invention relates to a control system with a serial drive circuit and a driving method thereof, and in particular to a synchronization technology and a related synchronization method that can be executed in a control system with a serial drive circuit. Background Art

[0002] As the amount of data that the control system needs to process gradually increases, multi-chip systems have become an indispensable solution. The multi-chip setting enables a large amount of data to be processed smoothly. In a multi-chip system, the chips can be coupled to each other to form a cascade structure, in which each chip can receive a signal from the chip at the previous level and transmit the signal to the next level. The signal transmitted to each chip in the system can be used to achieve a specific purpose, such as driving the panel to emit light or optimizing the display image. In this case, due to the high resolution of the existing display system, a single chip often cannot handle a large amount of display data, so a multi-chip system is a more feasible solution.

[0003] Because the chips are connected in series, the signal to be processed by a chip usually comes from the chip of the previous level, and the signal will be delayed from one chip to another, resulting in a time difference between the signals received by different chips. In order for the chips to operate normally, the signal processing needs to be synchronized. For example, in a display system that drives a panel through multiple chips, the display data output by different chips should be synchronized with each other. Therefore, how to synchronize the operation of chips in a multi-chip system has become an important issue in this field. Summary of the invention

[0004] Therefore, the main purpose of the present invention is to provide a control system composed of serially connected chips and a driving method for synchronization between the chips.

[0005] An embodiment of the present invention discloses a control system, which includes a plurality of driving circuits connected in series.

[0006] The plurality of driving circuits include a first driving circuit and a second driving circuit. The first driving circuit includes a first receiver, a first transmitter and a replica receiver, wherein the first transmitter is coupled to the first receiver, and the replica receiver is coupled to an output end of the first transmitter. The second driving circuit is coupled to the first driving circuit, and includes a second receiver and a second transmitter, wherein the second receiver is coupled to the first transmitter, and the second transmitter is coupled to the second receiver.

[0007] Another embodiment of the present invention discloses a control system, which includes a plurality of serially connected drive circuits. The plurality of drive circuits include a first drive circuit and a second drive circuit. The first drive circuit includes a first receiver, a first transmitter and a first delay circuit, wherein the first transmitter is coupled to the first receiver, and the first delay circuit is coupled between the first receiver and the first transmitter. The second drive circuit is coupled to the first drive circuit and includes a second receiver, a second transmitter and a second delay circuit, wherein the second transmitter is coupled to the second receiver, and the second delay circuit is coupled between the second receiver and the second transmitter. The first delay circuit and the second delay circuit are used to synchronize a first drive signal output by the first drive circuit with a second drive signal output by the second drive circuit.

[0008] Another embodiment of the present invention discloses a method for driving a control device, which is used in a control system having a plurality of serially connected drive circuits, including a first drive circuit and a second drive circuit. The method includes the following steps: the first drive circuit receives a first signal from a previous stage; the first drive circuit transmits the first signal to the second drive circuit; in the first drive circuit and the second drive circuit, the first signal is delayed by a first delay circuit to generate a second signal; in the first drive circuit and the second drive circuit, a clock signal is selected from a plurality of clock signals with different phases in a second delay circuit; and the selected clock signal is used to control the timing of outputting the second signal to the control device to synchronize the second signal output by the first drive circuit and the second drive circuit.

[0009] Another embodiment of the present invention discloses a driving circuit, which includes a receiver, a transmitter and a replica receiver. The transmitter is coupled to the receiver, and the replica receiver is coupled to an output end of the transmitter.

[0010] Another embodiment of the present invention discloses a driving circuit, which includes a receiver, a transmitter and a delay circuit. The transmitter is coupled to the receiver, and the delay circuit is coupled between the receiver and the transmitter to output a driving signal. The delay circuit includes a selection circuit, which is coupled to the output ends of a plurality of flip-flops. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic diagram of a control system.

[0012] Figures 2 to 4 Schematic diagram of a control system according to an embodiment of the present invention.

[0013] Figure 5 and 6 Shows Figure 4 An exemplary implementation of a delay circuit in.

[0014] Figure 7 A waveform diagram illustrating the waveform of a clock signal.

[0015] Figure 8 Schematic diagram of a control system according to an embodiment of the present invention.

[0016] Fig. 9 The figure is a flowchart of a synchronization process according to an embodiment of the present invention.

[0017] The reference numerals are described as follows:

[0018] 10, 20, 30, 40 control systems

[0019] 102, 104, 202, 302, 402 control device

[0020] N0, N1, M0, M1, D1, D2, D3 drive circuit

[0021] S1, S2, S3 drive signal

[0022] RX1, RX2, RX1A, RX2A, RX3A Receivers

[0023] TX1, TX2, TX1A, TX2A, TX3A transmitters

[0024] BF1, BF2, BF3 Output Buffers

[0025] RRX1, RX1B, RX1C, RX2B replica receivers

[0026] TX1B Copy Transmitter

[0027] RX2C, RX3B, RX3C Dummy Receiver

[0028] TX1C, TX2B, TX2C, TX3B, TX3C Dummy Transmitters

[0029] DL1, DL2 delay circuit

[0030] 510, 610 selection circuit

[0031] 520, 620 processing circuit

[0032] DFF_1~DFF_K、DFF_A~DFF_D D-type flip-flop

[0033] FS flag signal

[0034] CLK, CLK_A~CLK_D clock signals

[0035] CTRL1, CTRL2 control signals

[0036] 90 Synchronous Process

[0037] Steps 900-912 DETAILED DESCRIPTION

[0038] Please refer to Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a control system 10. Figure 1 As shown, the control system 10 includes control devices 102 and 104, and driving circuits N0, N1, M0 and M1 for controlling the control devices 102 and 104, respectively. In detail, the driving circuits N0 and N1 can be used to drive the control device 102, and the driving circuits M0 and M1 can be used to drive the control device 104. Each driving circuit can be an integrated circuit (IC) implemented in a chip, so the driving circuits N0 and N1 can be a chipset configured to control the control device 102, and the driving circuits M0 and M1 can be a chipset configured to control the control device 104. The control devices 102 and 104 generally refer to various types of control circuits, which can serve as loads to receive control of the driving circuits and / or provide control functions.

[0039] In detail, the driving circuits in the control system 10 are connected in series. The signal source can provide a data or clock signal to each driving circuit, and transmit the data or clock signal to the driving circuit at the first level, which then forwards the data or clock signal to the driving circuit at the next level, and so on. For each driving circuit, the data or clock signal can be received from the signal source or the driving circuit at the previous level. In addition, each driving circuit (except the last level) can transmit data or clock signals to the next level.

[0040] Therefore, since each control device is controlled by multiple drive circuits, these drive circuits used to control the same control device need to be synchronized. In other words, the drive signals transmitted by these drive circuits to the same control device need to be synchronized with each other. In the control system 10, the drive circuits N0 and N1 used to control the control device 102 need to be synchronized, and the drive circuits M0 and M1 used to control the control device 104 need to be synchronized.

[0041] It is worth noting that Figure 1The control system 10 shown is only used to illustrate an example of a control system in which each control device is controlled by two drive circuits. In another embodiment, a control device can be controlled by more than two drive circuits, and / or the control system can include any number of control devices that can be controlled by drive circuits. If a control device is controlled by more than two drive circuits, all drive circuits should be synchronized with each other.

[0042] In one embodiment, each control device 102 and 104 can be a light board, which can be used as a part of the spliced ​​screen of the display screen, and the display screen can be, for example, a liquid crystal display (LCD), a light-emitting diode (LED) display screen, or a micro-LED display screen. Therefore, the data or clock signal transmitted between the driving circuits may include display data and / or control signals for controlling various parameters on the display screen, such as parameters related to image display, optical characteristics, sound effect characteristics, etc. Alternatively, the data or clock signal can also be used to generate display data and / or control signals. However, in the control system 10, the signal is transmitted between the driving circuits one level at a time, so that there is a time difference in the signal reception between each driving circuit. That is, the driving circuit at the front stage often receives the signal earlier, while the driving circuit at the rear stage often receives the signal later. Therefore, the driving circuit should be properly synchronized so that the driving signal used to control the control device and its corresponding display screen in the driving circuit has a synchronized output timing, so that the image is displayed correctly.

[0043] In another embodiment, the control system 10 may also be other types of electronic systems, which should not be limited to the display system described in this specification. According to the application of the control device, if the output signals of multiple drive circuits can work together to achieve a predetermined function, these output signals should be synchronized. As mentioned above, each drive circuit can be an integrated circuit implemented on a chip, which means that the above synchronization is performed between chips.

[0044] In one embodiment, the driver circuits may be synchronized using a delay replica scheme. Figure 2 , Figure 2 FIG. 2 is a schematic diagram of a control system 20 according to an embodiment of the present invention. Figure 2As shown, the control system 20 includes a control device 202 and two driving circuits D1 and D2. The control device 202 can receive driving signals S1 and S2 from the driving circuits D1 and D2 respectively. The driving circuits D1 and D2 can be two driving circuits coupled to each other among a plurality of driving circuits in the control system 20, wherein the driving circuit D1 can receive a data or clock signal from a signal source or a previous driving circuit, and transfer the data or clock signal to the driving circuit D2.

[0045] In detail, the driving circuit D1 includes a receiver RX1, a transmitter TX1 and an output buffer BF1, and the driving circuit D2 includes a receiver RX2, a transmitter TX2 and an output buffer BF2. The receiver RX2 of the driving circuit D2 is coupled to the transmitter TX1 of the driving circuit D1, so that the driving circuit D2 can receive data or clock signals from the driving circuit D1. The receivers RX1 and RX2 include circuit structures for receiving signals from the previous stage, and the transmitters TX1 and TX2 include circuit structures for transmitting signals to the next stage. The output buffers BF1 and BF2 can be used to output driving signals S1 and S2 respectively to drive the control device 202. The output driving signals S1 and S2 need to be synchronized, that is, the timing of the driving circuit D2 outputting the driving signal S2 to the control device 202 needs to be synchronized with the timing of the driving circuit D1 outputting the driving signal S1 to the control device 202. It should be noted that each of the output buffers BF1 and BF2 may be formed by a buffer circuit, which may be, for example, a register, a D flip-flop, or any other type of circuit that can be used to transfer the received data or clock signal. Alternatively, the output buffer BF1 or BF2 may also include a processing circuit that can identify and process the data signal and generate the driving signals S1 and S2 that can be used for the control device 202 based on the received data signal. In one embodiment, if the control device 202 includes a display screen for receiving the driving signals S1 and S2 from the driving circuits D1 and D2, each of the output buffers BF1 and BF2 may include a level shifter for converting the signal to a level compatible with the display screen and / or an operational amplifier for driving a large load on the panel. In another embodiment, the output buffers BF1 and BF2 may be omitted, and the signal from the receiver or the replica receiver may be directly output to the control device 202.

[0046] In this example, the output buffer BF1 of the driving circuit D1 can output the driving signal S1 by receiving the data or clock signal, and the output buffer BF2 of the driving circuit D2 can output the driving signal S2 by receiving the same data or clock signal. Since the driving circuit D1 is at the previous stage of the driving circuit D2, the driving circuit D1 can receive the data or clock signal before the driving circuit D2. In order to achieve synchronization of the driving signals S1 and S2, the driving circuit D1 may also include a replica receiver RRX1, which is coupled to the output end of the transmitter TX1 (and also coupled to the input end of the receiver RX2 of the driving circuit D2). The circuit structure of the replica receiver RRX1 is similar to the circuit structure of the receiver RX2, so the delay time generated by the replica receiver RRX1 is the same as the delay time generated by the receiver RX2. In addition, the replica receiver RRX1 can be set on the output path of the data or clock signal, for example, coupled to the output end of the transmitter TX1. Therefore, the data or clock signal from the input end of the driving circuit D1 can be transmitted to the output buffer BF1 through the receiver RX1, the transmitter TX1 and the replica receiver RRX1, and the same data or clock signal from the input end of the driving circuit D1 can also be transmitted to the output buffer BF2 through the receiver RX1, the transmitter TX1 and the receiver RX2, so that the data or clock signal can reach the output buffers BF1 and BF2 at the same time. In addition, the output buffers BF1 and BF2 can have the same circuit structure to output the driving signals in good synchronization.

[0047] In this case, only an additional replica receiver needs to be added, and synchronization can be easily achieved without a large area and high cost. Preferably, the circuit structure of the replica receiver RRX1 can be exactly the same as the circuit structure of the receiver RX2. In addition, layout technology can also be used to minimize the process variation between the replica receiver RRX1 and the receiver RX2. For example, a dummy transmitter can be added to the driving circuit D1 and coupled to the output end of the replica receiver RRX1, wherein the circuit structure of the dummy transmitter is the same as the circuit structure of the transmitter TX2 in the driving circuit D2, so that the output load of the replica receiver RRX1 is the same as the output load of the receiver RX2. In this way, the replica receiver RRX1 and the receiver RX2 can produce almost the same delay time for the signal, so that the signal is well synchronized.

[0048] It is worth noting that the delayed replication scheme of the present invention can also be applied to the synchronization of more than two driving circuits in a control system. Figure 3 , Figure 3 FIG. 3 is a schematic diagram of another control system 30 according to an embodiment of the present invention. Figure 3As shown, the control system 30 includes a control device 302 and three driving circuits D1-D3. The driving circuits D1-D3 are connected in series in sequence and are used to output driving signals S1-S3 to control the control device 302. Data or clock signals can be transmitted from the driving circuit D1 to D2 and D3 in sequence. In order to smoothly control the control device 302, the output driving signals S1-S3 need to be synchronized with each other.

[0049] Similarly, the driving circuits D1 to D3 include an output buffer BF1 to BF3, respectively. In order to synchronize the output driving signals S1 to S3, the data or clock signal should be received by the output buffers BF1 to BF3 at the same time. Therefore, in addition to the original receivers and transmitters, several replica receivers and / or replica transmitters need to be set up. In detail, the driving circuit D3 includes a receiver RX3A and a transmitter TX3A; the driving circuit D2 includes a replica receiver RX2B in addition to a receiver RX2A and a transmitter TX2A; the driving circuit D1 includes two replica receivers RX1B, RX1C and a replica transmitter TX1B in addition to a receiver RX1A and a transmitter TX1A. In this way, the data or clock signal starting from the input end of the driving circuit D1 can reach each output buffer BF1 to BF3 after passing through three receivers and two transmitters, and can be received by the output buffers BF1 to BF3 at the same time (i.e., with the same delay time).

[0050] In addition, the driving circuit D1 may further include a dummy transmitter TX1C, the driving circuit D2 may further include a dummy receiver RX2C and dummy transmitters TX2B, TX2C, and / or the driving circuit D3 may further include dummy receivers RX3B, RX3C and dummy transmitters TX3B, TX3C. These dummy transmitters and receivers may be selectively configured to achieve equal output loads in each driving circuit D1-D3, so as to further improve the consistency of delay time.

[0051] In one embodiment, each driving circuit may have the same transceiver implementation, which is arranged with the same number of receivers and transmitters. At least one multiplexer (MUX) may be set according to the location of the driving circuit (for example, a multiplexer is used to implement Figure 2 or Figure 3 The multiplexer is controlled so that the signal output by the driving circuit has the same delay time. In other words, by setting the multiplexer, the signal of the driving circuit can be output to the control device after passing through the same number of receivers (including duplicate receivers) and the same number of transmitters (including duplicate transmitters).

[0052] In another embodiment, the driving circuits may be synchronized using a delay frame start scheme. In a control system where a control device is controlled by a plurality of serially connected driving circuits, each driving circuit may output a flag signal after completing the reception of data or clock signals. For display screen applications, the flag signal may be regarded as a frame start signal used to indicate the start of display of a frame of image. Based on the time point of the flag signal output, the delay time between each driving circuit may be detected. When no synchronization operation is performed, the flag signal of the driving circuit at the front stage is often output earlier, while the flag signal of the driving circuit at the rear stage is often output later, and the time difference of the flag signal output represents the delay time between the two driving circuits. According to the delay frame start scheme, the flag signal may be synchronized by selecting different delay times for different driving circuits to output the flag signal, so that the driving circuits output the driving signals at the same time.

[0053] Please refer to Figure 4 , Figure 4 FIG. 4 is a schematic diagram of another control system 40 according to an embodiment of the present invention. Figure 4 As shown, the control system 40 includes a control device 402 and two driving circuits D1 and D2. The control device 402 can receive driving signals S1 and S2 from the driving circuits D1 and D2 respectively. The driving circuits D1 and D2 can be two driving circuits coupled to each other among a plurality of driving circuits in the control system 40, wherein the driving circuit D1 can receive a data or clock signal from a signal source or a driving circuit of a previous stage, and transfer the data or clock signal to the driving circuit D2. Similarly, the driving circuit D1 includes a receiver RX1, a transmitter TX1 and an output buffer BF1, and the driving circuit D2 includes a receiver RX2, a transmitter TX2 and an output buffer BF2. The receiver RX2 of the driving circuit D2 is coupled to the transmitter TX1 of the driving circuit D1, so that the driving circuit D2 can receive the data or clock signal from the driving circuit D1.

[0054] In the control system 40, the driving circuit D1 may further include a delay circuit DL1 coupled between the receiver RX1, the transmitter TX1 and the output buffer BF1. The driving circuit D2 may further include a delay circuit DL2 coupled between the receiver RX2, the transmitter TX2 and the output buffer BF2. As described above, the output time of the flag signal needs to be synchronized, so the delay circuits DL1 and DL2 may generate a delay time, and the length of the delay time should be able to be set and adjusted to achieve synchronization between the driving circuits D1 and D2.

[0055] It should be noted that the delay circuit may be implemented in any manner. In one embodiment, each of the delay circuits DL1 and DL2 may include a multiplexer for selecting a delay time to output a flag signal. Figure 5 Shows Figure 4 An exemplary implementation of the delay circuit DL1 or DL2 in FIG. Figure 5 As shown, the delay circuit DL1 or DL2 includes a selection circuit 510, a processing circuit 520, and a plurality of D-type flip-flops DFF_1 to DFF_K, where K can be any positive integer greater than 1. The selection circuit 510 can be a multiplexer, and the plurality of D-type flip-flops DFF_1 to DFF_K can be respectively coupled to the input terminals of the selection circuit 510, and the processing circuit 520 is coupled to the output terminal of the selection circuit 510. The selection circuit 510 can also include a selection terminal (not shown) for controlling the selection circuit 510 to select one of the D-type flip-flops DFF_1 to DFF_K to output a flag signal FS to the processing circuit 520.

[0056] Specifically, the processing circuit 520 may be used to process the data or clock signal received by the corresponding driving circuit D1 or D2, and then output the corresponding driving signal to the output buffer BF1 or BF2. In one embodiment, the processing circuit 520 starts processing the data or clock signal when receiving the flag signal FS from the selection circuit 510. According to the selection of the selection circuit 510, the processing circuit 520 may receive the flag signal FS at a specific delay time.

[0057] like Figure 5 As shown, the D-type flip-flops DFF_1 to DFF_K are connected in series in sequence. More specifically, the data input terminal of the D-type flip-flop DFF_1 at the first stage can be used to receive the original flag signal FS, and the data input terminals of the other D-type flip-flops DFF_2 to DFF_K are respectively coupled to the data output terminals of the D-type flip-flops at the previous stage. The clock terminal of each D-type flip-flop DFF_1 to DFF_K can be used to receive a clock signal CLK, so that the D-type flip-flops DFF_1 to DFF_K at each stage can generate a delay time of a clock cycle. The D-type flip-flops at the previous stage (such as DFF_1, DFF_2, etc.) output the flag signal FS earlier; while the D-type flip-flops at the subsequent stage (such as DFF_(K-1), DFF_K, etc.) output the flag signal FS later.

[0058] In this case, for different driving circuits, the selection circuit 510 can select different D-type flip-flops DFF_1 to DFF_K to output the flag signal FS to synchronize the driving signals output by the driving circuits. Figure 5In the embodiment shown, the data or clock signal of the driving circuit D1 at the front stage can be received at a shorter delay time, so the selection circuit 510 can choose to obtain the flag signal FS from the D-type flip-flop with a longer delay time as compensation; the data or clock signal of the driving circuit D2 at the rear stage can be received at a longer delay time, so the selection circuit 510 can choose to obtain the flag signal FS from the D-type flip-flop with a shorter delay time. In this way, the processing circuit 520 can receive the flag signal FS at the same time and start processing the received data or clock signal at the same time. Therefore, the output buffers BF1 and BF2 can also receive the corresponding signals at the same time, so as to output the driving signals at the same time. In this way, the driving signal S1 output by the driving circuit D1 and the driving signal S2 output by the driving circuit D2 can be synchronized with each other.

[0059] In the above embodiment, the delay time of the delay circuit DL1 or DL2 is adjusted based on a period of the clock signal CLK as a resolution. In another embodiment, a delay time less than one clock period can also be achieved. Figure 6 Shows Figure 4 Another exemplary implementation of the delay circuit DL1 or DL2 in FIG. Figure 6 As shown, the delay circuit DL1 or DL2 includes a selection circuit 610, a processing circuit 620, and four D-type flip-flops DFF_A to DFF_D. The selection circuit 610 may be a multiplexer, the D-type flip-flops DFF_A to DFF_D may be coupled to the input terminals of the selection circuit 610, respectively, and the processing circuit 620 may be coupled to the output terminal of the selection circuit 610. The selection circuit 610 may select one of the D-type flip-flops DFF_A to DFF_D to output the flag signal FS to the processing circuit 620.

[0060] In order to achieve a higher delay resolution, the D-type flip-flops DFF_A-DFF_D can receive clock signals CLK_A-CLK_D with different phases. Figure 7 2 is a waveform diagram illustrating the waveforms of clock signals CLK_A, CLK_B, CLK_C and CLK_D. Figure 7As shown, compared with the clock signal CLK_A, the clock signal CLK_B has a delay time of 1 / 4 cycle, the clock signal CLK_C has a delay time of 1 / 2 cycle, and the clock signal CLK_D has a delay time of 3 / 4 cycle. Thus, compared with the flag signal FS from the D-type flip-flop DFF_A, the delay time of the flag signal FS from the D-type flip-flop DFF_B is (1 / 4)T, the delay time of the flag signal FS from the D-type flip-flop DFF_C is (1 / 2)T, and the delay time of the flag signal FS from the D-type flip-flop DFF_D is (3 / 4)T, where T represents the length of a clock cycle. The selection circuit 510 can select the flag signal FS output from different D-type flip-flops DFF_A to DFF_D to generate different delay times, thereby synchronizing the drive signals S1 and S2 output by the drive circuits D1 and D2.

[0061] In the above embodiment, different delay times are generated by a plurality of D-type flip-flops connected in series. It should be noted that the implementation of the delay circuit of the present invention is not limited thereto. For example, the delay time can also be generated by other types of flip-flops or any other delay circuits.

[0062] In one embodiment, the flag signal FS of the driving circuits D1 and D2 can be output to a display, and the user or operator can adjust the setting of the selection circuit 510 or 610 accordingly. For example, the information of the flag signal FS can be displayed on a display screen included in the control device or on a display device externally connected to the driving circuit. In the test process of the control system, the operator can control the delay circuits DL1 and DL2 in each driving circuit D1 and D2 to have the same setting, and monitor the flag signal FS of each driving circuit D1 and D2 to determine the delay time length between the driving circuits D1 and D2. Therefore, based on the monitored flag signal FS, the operator can determine which D-type flip-flop the selection circuit 510 or 610 in the delay circuit DL1 and DL2 should select the flag signal FS from, and accordingly set the selection circuit 510 or 610 so that the driving circuits D1 and D2 can output the driving signals S1 and S2 at the same time. In the operation of the control system, after the selection circuit is set or adjusted, the driving signals S1 and S2 can be output synchronously well.

[0063] In another embodiment, the control device 402 can be used to monitor the flag signal FS or the driving signals S1 and S2 output by the driving circuits D1 and D2, so as to output a control signal to adjust the setting of the selection circuit 510 or 610 in the delay circuits DL1 and DL2. For example, as described above, when the processing circuit 520 or 620 in the delay circuits DL1 and DL2 receives the flag signal FS, the processing circuit 520 or 620 can start processing the data or clock signal so that the output buffer BF1 or BF2 outputs the driving signal S1 or S2. Therefore, the control device 402 can detect the time when the driving signals S1 and S2 are received to determine the reception time difference. In this way, based on the detected time difference, the control device 402 can determine which D-type flip-flop the selection circuit 510 or 610 in the delay circuits DL1 and DL2 should select the flag signal FS from, and accordingly set the selection circuit 510 or 610 so that the driving circuits D1 and D2 can output the driving signals S1 and S2 at the same time.

[0064] In one embodiment, the control device 402 may also be coupled to the delay circuits DL1 and DL2. Figure 8 As shown, the control device 402 can send control signals CTRL1 and CTRL2 to control the selection circuits (such as multiplexers) in the delay circuits DL1 and DL2. The control signals CTRL1 and CTRL2 can be transmitted to the selection terminals of the selection circuits to set the selection circuits to output the flag signal FS from the selected D-type flip-flops. In another embodiment, the control device 402 can also be coupled to the input terminals of the receivers RX1 and RX2, and the control signals can be received by the receivers RX1 and RX2 and then forwarded to the delay circuits DL1 and DL2.

[0065] It is noteworthy that the purpose of the present invention is to provide a synchronization method for serially connected drive circuits in a control system. Those skilled in the art may make modifications or changes accordingly, but are not limited to this. For example, in an embodiment of the present invention, the delayed replication scheme and the delayed frame start scheme can be applied to a control system including any number of drive circuits. In addition, the signals transmitted between the drive circuits may include data signals, clock signals, and / or control signals used to implement various functions, which may be transmitted in various feasible forms such as electronics, light, magnetic fields, sound waves, etc. In addition, in the delayed frame start scheme, the delay time in the selection circuit can be adjusted to any appropriate value. In one embodiment, the delay time adjustment based on the clock cycle (such as Figure 5 ) and delay adjustment based on clock phase (such as Figure 6 ) can be used in combination with each other, and / or the delayed replication scheme and the delayed frame start scheme can also be used in combination with each other.

[0066] Please refer to Fig. 9 , Fig. 9FIG. 9 is a flowchart of a synchronization process 90 according to an embodiment of the present invention. Fig. 9 As shown, the synchronization process 90 can be implemented in a control circuit of the present invention to synchronize a first driving circuit and a second driving circuit in the control circuit, wherein the first driving circuit and the second driving circuit are both used to control a control device. The synchronization process 90 includes the following steps:

[0067] Step 900: Start.

[0068] Step 902: The first driving circuit receives a data or clock signal from a previous stage.

[0069] Step 904: The first driving circuit transmits data or a clock signal to the second driving circuit.

[0070] Step 906: In the first driving circuit and / or the second driving circuit, delay the data or clock signal via a coarse delay circuit to generate a driving signal.

[0071] Step 908: In the first driving circuit and / or the second driving circuit, select a clock signal from a plurality of clock signals with different phases in a fine delay circuit.

[0072] Step 910: Use the selected clock signal to control the timing of outputting the driving signal to the control device to synchronize the driving signals output by the first driving circuit and the second driving circuit.

[0073] Step 912: End.

[0074] According to the synchronization process 90, the first driving circuit can receive data or clock signals from the previous stage and transfer the data or clock signals to the second driving circuit. Therefore, the first driving circuit can be regarded as the driving circuit D1 in the above embodiment, and the second driving circuit can be regarded as the driving circuit D2 in the above embodiment. In the driving circuits D1 and D2, the coarse delay circuit can be used to perform a coarse delay adjustment on the data or clock signal to generate a driving signal, and then the fine delay circuit can be used to perform a fine delay adjustment on the driving signal, so as to synchronize the driving signals output by the driving circuits D1 and D2.

[0075] The coarse delay circuit may adopt the above-mentioned delay replication scheme and / or delay frame start scheme. If the delay replication scheme is adopted, the coarse delay circuit may include a replica receiver, and the data or clock signal in the driving circuit D1 may be deliberately generated with a delay time through the replica receiver, which is the same as the delay time generated by the receiver of the driving circuit D2. If the delay frame start scheme is adopted, the coarse delay circuit may include a selection circuit, which may synchronize the data or clock signals in the driving circuits D1 and D2 by selecting different flag signals corresponding to different clock cycles in the driving circuits D1 and D2.

[0076] The fine-tuning delay circuit can adopt the clock phase selection method in the delayed frame start scheme to achieve fine adjustment of the delay time. In detail, the fine-tuning delay circuit can include a selection circuit, which can synchronize the driving signals of the driving circuits D1 and D2 by selecting different flag signals corresponding to different clock phases in the driving circuits D1 and D2.

[0077] It is worth noting that although the synchronization process 90 is for synchronizing the driving signals output by the two driving circuits D1 and D2, the synchronization process 90 can also be applied to the synchronization of more than two driving circuits connected in series with each other. Those skilled in the art can easily infer its detailed implementation method based on the contents of this specification, which will not be repeated here.

[0078] In summary, the present invention provides a synchronization method for serially connected drive circuits that can be used in a control system, wherein the serially connected drive circuits can be used to drive or control the same control device to achieve a predetermined function, such as controlling a display screen to display an image. Since the drive circuits are serially connected to each other in sequence, each drive circuit can receive a data or clock signal from the previous stage and transfer the data or clock signal to the next stage. The drive signals output by these drive circuits should be well synchronized to eliminate the time difference between the output drive signals. In one embodiment, a delayed replication scheme can be used for synchronization, wherein a replica receiver can be set in the drive circuit at the previous stage to deliberately generate a delay time, which is the same as the delay time generated by the receiver in the subsequent drive circuit. In one embodiment, a delayed frame start scheme can be used for synchronization, wherein different delay times can be selected between different drive circuits to output a flag signal, so that the drive signals of the drive circuits can be output at the same time. For different drive circuits, different delay times can be set in the delay circuit as compensation for the signal transfer delay between the serially connected drive circuits. In one embodiment, each driving circuit may be an integrated circuit included in a chip. In this way, the synchronization mechanism may be applied to a multi-chip system to effectively achieve synchronization between chips.

[0079] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A control system, comprising: A plurality of serially connected driving circuits include: A first driving circuit, comprising: a first receiver; a first transmitter coupled to the first receiver; and a replica receiver coupled to an output terminal of the first transmitter; and A second driving circuit, coupled to the first driving circuit, comprises: a second receiver coupled to the first transmitter; and a second transmitter, coupled to the second receiver; The delay time generated by the duplicate receiver is the same as the delay time generated by the second receiver.

2. The control system according to claim 1, characterized in that: The first driving circuit also includes an output buffer, and the output buffer is used to drive a control device according to a data or clock signal.

3. The control system according to claim 2, characterized in that: The data or clock signal is transmitted to the output buffer through the first receiver, the first transmitter and the replica receiver.

4. The control system according to claim 2, characterized in that: The replica receiver is located on an output path of the data or clock signal used to drive the control device.

5. The control system according to claim 1, characterized in that: The first driving circuit and the second driving circuit respectively use a first driving signal and a second driving signal to drive a control device, and the timing of the second driving circuit outputting the second driving signal to the control device is synchronized with the timing of the first driving circuit outputting the first driving signal to the control device.

6. A driving circuit, comprising: a receiver; a transmitter coupled to the receiver; as well as a replica receiver coupled to an output terminal of the transmitter; wherein the receiver, the transmitter and the replica receiver are included in the same chip; The delay time generated by the replica receiver is the same as the delay time generated by a receiver in another driving circuit connected in series to the rear end of the driving circuit.

7. The driving circuit according to claim 6, characterized in that: The driving circuit also includes an output buffer, which is used to drive a control device according to a data or clock signal.

8. The driving circuit according to claim 7, characterized in that: The data or clock signal is transmitted to the output buffer through the receiver, the transmitter and the replica receiver.

9. The driving circuit according to claim 7, characterized in that: The replica receiver is located on an output path of the data or clock signal used to drive the control device.

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