Memory devices and storage devices including the same

Abstract

The present application relates to memory devices and storage devices including the same. An electronic device includes a plurality of memory devices, and a storage controller configured to provide a program command instructing to store data in the memory devices, each memory device including a memory block including a plurality of memory cells, a peripheral circuit configured to perform, in response to the program command, a first program operation and a second program operation to store data in selected memory cells, the selected memory cells being memory cells selected from among the plurality of memory cells, and a program operation controller configured to control the first program operation and the second program operation, the first program operation being performed using one logical page data among page data to be stored in the selected memory cells, and the second program operation being performed using remaining logical page data among the page data except for the one logical page data.

Description

Technical Field

[0001] This disclosure relates to electronic devices, and more specifically, to a storage device and a method of operating the storage device. Background Technology

[0002] A storage device is a means of storing data under the control of a host device such as a computer or smartphone. A storage device may include a memory device for storing data and a memory controller for controlling the memory device. Memory devices can be classified as volatile memory devices and non-volatile memory devices.

[0003] A volatile memory device is a device that stores data only when powered on and loses the stored data when the power supply is cut off. Volatile memory devices may include static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0004] Non-volatile memory devices are devices that retain data even when power is cut off. Non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, etc. Summary of the Invention

[0005] A memory device according to embodiments of the present disclosure may include: a memory cell block including a plurality of memory cells; peripheral circuitry configured to perform a first programming operation and a second programming operation in a selected memory cell connected to a selected word line, storing data in the plurality of memory cells; and a programming operation controller configured to control the first programming operation and the second programming operation, wherein the first programming operation may be performed using one logical page data among page data to be stored in the selected memory cell, and the second programming operation may be performed using the remaining logical page data among the page data other than the one logical page data.

[0006] A memory device according to embodiments of the present disclosure may include: a memory block connected to physical word lines, each comprising a plurality of pages; peripheral circuitry configured to perform programming operations that store data in the plurality of pages; and control logic configured to control the peripheral circuitry, wherein the programming operations may include a first programming operation that programs a threshold voltage of a memory cell included in the plurality of pages to a threshold voltage having an erase state or an intermediate state, and a second programming operation that programs a memory cell to a threshold voltage having an erase state and any one of a first to an nth programming state (n is a natural number equal to or greater than 2), and the control logic may control the peripheral circuitry to perform the first programming operation on one of the plurality of pages included in a selected physical word line, and then perform the second programming operation on one of the plurality of pages included in a physical word line before the selected physical word line.

[0007] A storage device according to embodiments of the present disclosure may include: a memory device; and a storage controller configured to provide programming commands instructing data to be stored in the memory device. Each memory device may include: a memory block including a plurality of memory cells; peripheral circuitry configured to perform a first programming operation and a second programming operation in response to the programming commands, wherein the selected memory cell is a memory cell selected from the plurality of memory cells; and a programming operation controller configured to control the first programming operation and the second programming operation, wherein the first programming operation may be performed using one logical page data among page data to be stored in the selected memory cell, and the second programming operation may be performed using the remaining logical page data among the page data other than the one logical page data. Attached Figure Description

[0008] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0009] Figure 2 It is shown Figure 1 A diagram of the structure of a memory device.

[0010] Figure 3 It is shown Figure 2 A diagram of the structure of any one of the storage blocks.

[0011] Figure 4A and Figure 4B This is a graph showing the threshold voltage distribution of a TLC.

[0012] Figure 5A and Figure 5B This is a diagram illustrating programming operations according to embodiments of the present disclosure.

[0013] Figure 6AThis is a diagram illustrating the operation of reading LSB page data.

[0014] Figure 6B This is a diagram illustrating the operation of reading CSB page data.

[0015] Figure 6C This is a diagram illustrating the operation of reading MSB page data.

[0016] Figure 7 This is a diagram illustrating the voltages applied to the word lines and bit lines during programming operations according to an embodiment of the present disclosure.

[0017] Figure 8 This is a diagram illustrating the programming order of pages included in a storage block.

[0018] Figure 9A This is a diagram illustrating programming sequence information according to embodiments of the present disclosure.

[0019] Figure 9B This is a diagram illustrating programming sequence information according to another embodiment of this disclosure.

[0020] Figure 10 This is a diagram illustrating the types of programming methods 2-8 according to embodiments of this disclosure.

[0021] Figure 11 It is shown Figure 1 A block diagram illustrating an example of the connection relationships between a storage controller and multiple memory devices.

[0022] Figure 12 It is a timing diagram illustrating programming operations based on data interweaving.

[0023] Figure 13 This is a diagram illustrating the configuration of the memory device that performs programming operations according to the present disclosure.

[0024] Figure 14 It is a diagram showing the voltage applied during the first programming operation and the second programming operation.

[0025] Figure 15 It is shown Figure 13 A diagram illustrating an implementation of the programming voltage information storage unit.

[0026] Figure 16 It is shown Figure 13 A diagram of another embodiment of the programming voltage information storage unit.

[0027] Figure 17 It is shown Figure 13 A diagram of another embodiment of the programming voltage information storage unit.

[0028] Figure 18 It is shown Figure 13A diagram illustrating an implementation of the programming time information storage unit.

[0029] Figure 19 It is shown Figure 1 A diagram of another embodiment of the storage controller.

[0030] Figure 20 This is a block diagram illustrating a memory card system using a storage device according to an embodiment of the present disclosure.

[0031] Figure 21 This is a block diagram illustrating a solid-state drive (SSD) system using a storage device according to an embodiment of the present disclosure.

[0032] Figure 22 This is a block diagram illustrating a user system employing a storage device according to an embodiment of the present disclosure. Detailed Implementation

[0033] This specification or application only illustrates specific structural or functional descriptions of embodiments based on the concepts disclosed herein to describe embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be performed in various forms, and these descriptions are not limited to the embodiments described in this specification or application.

[0034] Embodiments of this disclosure provide a storage device with improved reliability and improved operating speed, and a method for operating the storage device.

[0035] According to this technology, a storage device and its operation method with improved reliability and improved operating speed are provided.

[0036] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0037] Reference Figure 1 The storage device 50 may include a memory device 100 and a storage controller 200 for controlling the operation of the memory device. The storage device 50 may be a device for storing data under the control of a host 300 (e.g., a cellular phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system).

[0038] Depending on the host interface, which serves as the communication method with the host 300, the storage device 50 can be manufactured as one of various types of storage devices. For example, the storage device 50 can be configured as any of various types of storage devices, such as multimedia cards in the form of SSD, MMC, eMMC, RS-MMC and micro-MMC, secure digital cards in the form of SD, mini-SD and micro-SD, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, PCMCIA card-type storage devices, peripheral component interconnect (PCI) card-type storage devices, high-speed PCI (PCI-E) card-type storage devices, compact flash memory (CF) cards, smart media cards, and memory sticks.

[0039] The storage device 50 can be manufactured in any of a variety of package types. For example, the storage device 50 can be manufactured in any of a variety of package types such as point-of-purchase (POP), system-in-package (SIP), system-on-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0040] The memory device 100 can store data. The memory device 100 operates under the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown), which includes a plurality of memory cells for storing data.

[0041] Each memory cell can be configured as a single-level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a three-level cell (TLC) that stores three data bits, or a four-level cell (QLC) that can store four data bits.

[0042] A memory cell array (not shown) may include multiple memory blocks. Each memory block may include multiple memory cells. A memory block may include multiple pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or retrieving data stored in the memory device 100. A memory block may be a unit for erasing data.

[0043] In embodiments, the memory device 100 may be Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin-Torque Random Access Memory (STT-RAM), etc. In this specification, for ease of description, it is assumed that the memory device 100 is NAND flash memory.

[0044] Memory device 100 is configured to receive a command CMD and an address ADDR from memory controller 200 and access an address-selected region in the memory cell array. Memory device 100 can perform the operation indicated by command CMD on the region selected by address ADDR. For example, memory device 100 can perform programming, reading, and erasing operations. During a programming operation, memory device 100 can store data in the region selected by address ADDR. During a reading operation, memory device 100 can read data from the region selected by address ADDR. During an erasing operation, memory device 100 can erase data stored in the region selected by address ADDR.

[0045] In an embodiment, the memory device 100 may include multiple planes. A plane may be a unit capable of performing operations independently. For example, the memory device 100 may include 2, 4, or 8 planes. Multiple planes may simultaneously and independently perform programming, reading, or erasing operations. The terms "simultaneously" and "at the same time" as used herein refer to events occurring over overlapping time intervals. For example, if a first event occurs within a first time interval and a second event occurs simultaneously within a second time interval, then the first and second intervals at least partially overlap, such that there exists a time when both the first and second events occur.

[0046] The storage controller 200 controls the overall operation of the storage device 50.

[0047] When power is applied to storage device 50, storage controller 200 can execute firmware (FW). When storage device 100 is a flash memory device, the firmware (FW) may include a host interface layer (HIL) that controls communication with host 300, a flash translation layer (FTL) that controls communication between storage controller 200 and host 300, and a flash interface layer (FIL) that controls communication with storage device 100.

[0048] The storage controller 200 can receive write data and logical block addresses (LBAs) from the host 300 and can convert the LBAs into physical block addresses (PBAs) indicating the addresses of memory cells in which data included in the memory device 100 is to be stored. In this specification, LBA and "logical address" may be used interchangeably. In this specification, PBA and "physical address" may be used interchangeably.

[0049] The storage controller 200 can control the storage device 100 to perform programming operations, read operations, erase operations, etc., according to the request of the host 300. During a programming operation, the storage controller 200 can provide the storage device 100 with programming commands, PBA, and data. During a read operation, the storage controller 200 can provide the storage device 100 with read commands and PBA. During an erase operation, the storage controller 200 can provide the storage device 100 with erase commands and PBA.

[0050] In this implementation, the storage controller 200 can generate commands, addresses, and data independently of requests from the host 300, and send these commands, addresses, and data to the memory device 100. For example, the storage controller 200 can provide commands, addresses, and data to the memory device 100 for performing read and programming operations, accompanied by wear leveling, read reclamation, garbage collection, etc.

[0051] In one implementation, the memory controller 200 can control at least two or more memory devices 100. In this case, the memory controller 200 can control the memory devices 100 according to an interleaving method to improve operational performance. The interleaving method can be a method in which the operation of controlling at least two memory devices 100 overlaps with each other. Alternatively, the interleaving method can be a method in which at least two or more memory devices 100 operate in parallel.

[0052] A buffer memory (not shown) may temporarily store data provided from the host 300 (i.e., data to be stored in the memory device 100), or may temporarily store data read from the memory device 100. In an embodiment, the buffer memory (not shown) may be a volatile memory device. For example, the buffer memory (not shown) may be dynamic random access memory (DRAM) or static random access memory (SRAM).

[0053] The host 300 may communicate with the storage device 50 using at least one of various communication methods such as Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduction DIMM (LRDIMM).

[0054] Figure 2 It is shown Figure 1 A diagram showing the structure of the memory device 100.

[0055] Reference Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130. The control logic 130 may be implemented in hardware, software, or a combination of both. For example, the control logic 130 may be control logic circuitry operating according to an algorithm and / or a processor executing control logic code.

[0056] Memory cell array 110 includes multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to row decoder 121 via row lines RL. The multiple memory blocks BLK1 to BLKz are connected to page buffer group 123 via bit lines BL1 to BLn. Each of the multiple memory blocks BLK1 to BLKz includes multiple memory cells. As an implementation, the multiple memory cells may be non-volatile memory cells. Memory cells connected to the same word line may be defined as a page. Therefore, a memory block may include multiple pages.

[0057] A row line RL may include at least one source select line, multiple word lines, and at least one drain select line.

[0058] Each memory cell included in the memory cell array 110 can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0059] Peripheral circuitry 120 can be configured to perform programming, reading, or erasing operations on selected regions of memory cell array 110 under the control of control logic 130. Peripheral circuitry 120 can drive memory cell array 110. For example, peripheral circuitry 120 can apply various operating voltages to row lines RL and bit lines BL1 to BLn or discharge the applied voltages under the control of control logic 130.

[0060] The peripheral circuitry 120 may include a row decoder 121, a voltage generator 122, a page buffer group 123, a column decoder 124, and an input / output circuitry 125.

[0061] The row decoder 121 is connected to the memory cell array 110 via row lines RL. The row line RL may include at least one source select line, multiple word lines, and at least one drain select line. In some embodiments, the word lines may include normal word lines and dummy word lines. In some embodiments, the row line RL may also include transistor select lines.

[0062] The line decoder 121 is configured to operate in response to control of the control logic 130. The line decoder 121 receives the line address RADD from the control logic 130.

[0063] The row decoder 121 is configured to decode the row address RADD received from the control logic 130. The row decoder 121 selects at least one memory block from BLK1 to BLKz based on the decoded address. Additionally, the row decoder 121 can select at least one word line of the memory block based on the decoded address to apply the voltage generated by the voltage generator 122 to at least one word line WL.

[0064] For example, during a programming operation, the line decoder 121 can apply a programming voltage to the selected word line and a programming pass voltage with a level lower than the programming voltage to the unselected word line. During a programming verification operation, the line decoder 121 can apply a verification voltage to the selected word line and a verification pass voltage with a level higher than the verification voltage to the unselected word line. During a read operation, the line decoder 121 can apply a read voltage to the selected word line and a read pass voltage with a level higher than the read voltage to the unselected word line.

[0065] In this embodiment, the erase operation of the memory device 100 is performed on a block-by-block basis. During the erase operation, the line decoder 121 may select a memory block based on the decoded address. During the erase operation, the line decoder 121 may apply a ground voltage to the word line connected to the selected memory block.

[0066] Voltage generator 122 operates in response to control of control logic 130. Voltage generator 122 is configured to generate multiple voltages using the external power supply voltage supplied to memory device 100. For example, voltage generator 122 may generate various operating voltages Vop for programming, reading, and erasing operations in response to the operation signal OPSIG. For example, voltage generator 122 may generate programming voltage, verification voltage, pass voltage, read voltage, erase voltage, etc., in response to control of control logic 130.

[0067] As an implementation, the voltage generator 122 can generate an internal power supply voltage by adjusting the external power supply voltage. The internal power supply voltage generated by the voltage generator 122 is used as the operating voltage of the memory device 100.

[0068] As an implementation, voltage generator 122 can use external power supply voltage or internal power supply voltage to generate multiple voltages.

[0069] For example, voltage generator 122 may include multiple pump capacitors that receive internal power supply voltages, and multiple pump capacitors may be selectively enabled in response to control of control logic 130 to generate multiple voltages.

[0070] The generated voltages can be supplied to the memory cell array 110 by the row decoder 121.

[0071] Page buffer group 123 includes first page buffers PB1 through nth page buffers PBn. First page buffers PB1 through nth page buffers PBn are connected to memory cell array 110 via first bit line BL1 through nth bit line BLn, respectively. First page buffers PB1 through nth page buffers PBn operate in response to control logic 130. For example, first page buffers PB1 through nth page buffers PBn may operate in response to page buffer control signal PBSIGNALS. For example, first page buffers PB1 through nth page buffers PBn may temporarily store data received via first bit line BL1 through nth bit line BLn, or may sense the voltage or current of bit lines BL1 through BLn during read or verification operations.

[0072] For example, during a programming operation, when a programming pulse is applied to the selected word line, the first page buffer PB1 to the nth page buffer PBn can transmit data DATA received from the input / output circuit 125 to the selected memory cell via the first bit line BL1 to the nth bit line BLn. The memory cell of the selected page is programmed according to the transmitted data DATA. The threshold voltage of the memory cell connected to the bit line to which a programming enable voltage (e.g., ground voltage) is applied can be increased. The threshold voltage of the memory cell connected to the bit line to which a programming disable voltage (e.g., power supply voltage) is applied can be maintained. During a programming verification operation, the first page buffer PB1 to the nth page buffer PBn can read data stored in the memory cell from the selected memory cell via the first bit line BL1 to the nth bit line BLn.

[0073] During the read operation, under the control of the column decoder 124, the first page buffer PB1 to the nth page buffer PBn read data DATA from the memory cell of the selected page through the first bit line BL1 to the nth bit line BLn, and output the read data DATA to the input / output circuit 125.

[0074] During the erase operation, the first page buffer PB1 to the nth page buffer PBn can float the first bit line BL1 to the nth bit line BLn.

[0075] The column decoder 124 can transfer data between the input / output circuitry 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 can exchange data with the first page buffer PB1 to the nth page buffer PBn via the data line DL, or it can exchange data with the input / output circuitry 125 via the column line CL.

[0076] Input / output circuit 125 can transfer data from a reference circuit. Figure 1 The described storage controller 200 receives commands CMD and addresses ADDR and transmits them to control logic 130, or can exchange data DATA with column decoder 124.

[0077] The sensing circuit 126 can generate a reference current in response to the enable bit signal VRYBIT during a read operation or a programming verification operation, and compare the sensed voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current to output a pass signal PASS or a failure signal FAIL.

[0078] Temperature sensor 127 measures the temperature of memory device 100. Temperature sensor 127 provides a temperature signal TEMP with different voltage levels to control logic 130 based on the measured temperature. Control logic 130 generates temperature information TEMP INFO indicating the temperature of memory device 100 based on the temperature signal TEMP and outputs the generated temperature information TEMP INFO to an external source.

[0079] Control logic 130 can output operation signal OPSIG, row address RADD, page buffer control signal PBSIGNALS, and enable bit VRYBIT in response to command CMD and address ADDR to control peripheral circuit 120. Additionally, control logic 130 can determine whether the verification operation passed or failed in response to pass signal PASS or failure signal FAIL.

[0080] According to embodiments of this disclosure, the control logic 130 may further include a programmable operation controller 131. The programmable operation controller 131 can control the peripheral circuitry 120 to perform programming operations that store data in a memory unit. For example, the programmable operation controller 131 can provide control signals to the peripheral circuitry 120.

[0081] Programming operations can be performed on a page-by-page basis. Memory cells connected to a single word line can be configured with physical pages. In implementations, a physical page may include at least one or more logical pages. Therefore, page data, which is the data stored in the physical page, may include at least one or more logical page data. For example, when the memory cell is programmed in SLC mode, the physical page may include one logical page, and the page data may include one logical page data. Alternatively, when the memory cell is programmed in MLC mode, the physical page may include two logical pages, and the page data may include two logical page data. In this case, the two logical page data may be least significant bit (LSB) page data and most significant bit (MSB) page data. Alternatively, when the memory cell is programmed in TLC mode, the physical page may include three logical pages, and the page data may include three logical page data. In this case, the three logical page data may be least significant bit (LSB) page data, center significant bit (CSB) page data, and most significant bit (MSB) page data. In implementations related to TLC mode, one of the logical page data may be any one of LSB page data, CSB page data, or MSB page data. Therefore, the remaining logical page data can be any page data in the page data except for the logical page data selected for the operation. For example, in TLC mode, if the logical page data selected for the operation in the page data is LSB page data, then the remaining logical page data that can be selected for another operation is CSB page data and MSB page data. For example, if the logical page data selected for the operation in the page data is CSB page data, then the remaining logical page data that can be selected for another operation is LSB page data and MSB page data. In the implementation related to MLC mode, one of the logical page data in the page data can be either LSB page data or MSB page data. Therefore, in MLC mode, if the logical page data selected for the operation in the page data is LSB page data, then the remaining logical page data that can be selected for another operation is MSB page data.

[0082] For ease of description, it is assumed that the memory cells are programmed in TLC mode. However, this is for the sake of description, and the embodiments of this disclosure are not limited thereto.

[0083] Before performing a programming operation, a memory cell may have a threshold voltage corresponding to an erase state. When a programming operation is performed, based on the data stored in each memory cell, the memory cells included in the selected page may have a threshold voltage corresponding to either the erase state or any of the first to seventh programming states. For example, based on the data to be stored in each memory cell, the memory cell may have either the erase state or any of the first to seventh programming states as the target programming state. A programming operation can be performed on each memory cell to have a threshold voltage corresponding to the target programming state.

[0084] Traditional programming operations are performed using a so-called one-time programming method. This method can include multiple programming cycles. A programming cycle includes a programming voltage application step, which applies a programming voltage to the selected word line, and a verification step, which senses whether the threshold voltage of each memory cell has reached the threshold voltage corresponding to the target programming state. In each programming cycle, the programming voltage applied to the word line can be increased by a step voltage compared to the programming voltage in the previous programming cycle. Here, the step voltage can be a preset voltage value. This is called the Incremental Step Pulse Programming (ISPP) scheme. Even if a programming cycle corresponding to a preset maximum number of cycles is executed, the programming operation can still be determined to have failed if all memory cells connected to the selected word line have not reached the target programming state.

[0085] According to embodiments of this disclosure, the programming operation may include a first programming operation and a second programming operation. The first programming operation may be an operation that causes the threshold voltage of a memory cell to have a threshold voltage corresponding to either an erase state or an intermediate state. The second programming operation may be an operation that programs the threshold voltage of a memory cell belonging to an erase state or an intermediate state to have a threshold voltage corresponding to either an erase state or a first to a seventh programming state. In this programming method, when the first programming operation is performed, the number of threshold voltage distributions formed by the memory cells is 2, and when the second programming operation is performed, the number of threshold voltage distributions formed by the memory cells is 8. Therefore, this programming method is also referred to as a 2-8 programming scheme.

[0086] See the description below. Figures 4A to 7 The programming operations according to embodiments of this disclosure are described.

[0087] Figure 3 It is shown Figure 2 A diagram showing the structure of any one of the storage blocks BLK1 to BLKz, BLKi.

[0088] Reference Figure 3 Multiple word lines arranged parallel to each other can be connected between a first select line and a second select line. Here, the first select line can be a source select line (SSL), and the second select line can be a drain select line (DSL). For example, a memory block BLKi may include multiple string STs connected between bit lines BL1 to BLn and the source line SL. Bit lines BL1 to BLn can be connected to string STs individually, and the source line SL can be connected together to string STs. Since string STs can be configured to be identical to each other, as an example, a string ST connected to the first bit line BL1 will be described.

[0089] A string ST may include a source selection transistor SST connected in series between the source line SL and the first bit line BL1, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST. A string ST may include at least one or more source selection transistors SST and drain selection transistors DST, and may include memory cells MC1 to MC16 (more than the number shown in the figure).

[0090] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells MC1 to MC16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gate of the source select transistor SST included in different string STs can be connected to the source select line SSL, the gate of the drain select transistor DST can be connected to the drain select line DSL, and the gate of the memory cells MC1 to MC16 can be connected to multiple word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different string STs can be referred to as a page PG. Therefore, the memory block BLKi can include the number of page PGs equal to the number of word lines WL1 to WL16.

[0091] A memory cell can store one bit of data. This is often referred to as a single-level cell (SLC). In this case, a physical page (PG) can store one logical page (LPG) of data. A logical page (LPG) of data can include the same number of data bits as the cells included in a physical page (PG).

[0092] A memory cell can store two or more bits of data. In this case, a physical page (PG) can store two or more logical pages (LPG) of data.

[0093] Figure 4A and Figure 4B This is a graph showing the threshold voltage distribution of a TLC.

[0094] Reference Figure 4A and Figure 4B The horizontal axis of each curve represents the threshold voltage, and the vertical axis represents the number of memory cells.

[0095] Before performing a programming operation, the memory cell may have a threshold voltage for the erase state (E). After the programming operation is completed, the memory cell may have a threshold voltage for either the erase state E or any one of the first programming states P1 to the seventh programming states P7.

[0096] After data is stored in a memory cell, the operation of reading the stored data can be an operation of reading the voltage sensing memory cell to distinguish each state.

[0097] The first read voltage R1 can be a voltage used to distinguish between the erase state E and the first programmable state P1. Since a memory cell having a threshold voltage corresponding to the erase state E has a threshold voltage lower than the first read voltage R1, the memory cell can be read as an on cell. Since a memory cell having the first programmable state P1 has a threshold voltage higher than the first read voltage R1, the memory cell can be read as an off cell.

[0098] The second read voltage R2 through the seventh read voltage R7 can be read voltages used to distinguish each of the first programming states P1 through the seventh programming state P7. The second read voltage R2 can be a read voltage used to distinguish the first programming state P1 from the second programming state P2. The third read voltage R3 can be a read voltage used to distinguish the second programming state P2 from the third programming state P3. Similarly, the seventh read voltage R7 can be a read voltage used to distinguish the sixth programming state P6 from the seventh programming state P7.

[0099] As the number of data bits stored in a memory cell increases, the number of programming states and the number of read voltages used to distinguish each programming state can also increase.

[0100] Figure 5A and Figure 5B This is a diagram illustrating programming operations according to embodiments of the present disclosure.

[0101] Reference Figure 5A and Figure 5B The first programming operation may be an operation that programs memory cells according to data to be stored in each memory cell, such that the threshold voltage of the memory cell connected to the selected word line has a threshold voltage corresponding to either the erase state E or the intermediate state IM. In an embodiment, the magnitude of the threshold voltage corresponding to the intermediate state IM may be greater than the magnitude of the threshold voltage corresponding to the erase state E. In an embodiment, the memory cell to be programmed to the intermediate state IM in the first programming operation may be a memory cell whose target programming state is any one of the fourth programming states P4 to the seventh programming states P7. Conversely, the target programming state of the memory cell that maintains the erase state E in the first programming operation may be any one of the erase state E and the first programming states P1 to the third programming states P3.

[0102] In some embodiments, the first programming operation 1st PGM may be an operation that provides a fixed programming voltage of a predetermined magnitude to a memory cell at least once or more. That is, in its simplest form, the first programming operation 1st PGM may be an operation that provides a fixed programming voltage to a word line once. In some embodiments, the first programming operation 1st PGM may also include multiple programming cycles. In this case, even if programming cycles included in the first programming operation 1st PGM are performed, the level of the programming voltage applied to the word line does not increase, and the programming voltage may be a fixed programming voltage with a fixed voltage level. In some embodiments, the first programming operation 1st PGM may be a programming operation that does not perform a verification step. The term "predetermined" (e.g., predetermined size, predetermined dimension, and predetermined voltage level) used herein for parameters means that the value of the parameter is determined before it is used in the processing or algorithm. For some embodiments, the value of the parameter is determined before the processing or algorithm begins. In other embodiments, the value of the parameter is determined during the processing or algorithm but before it is used in the processing or algorithm.

[0103] When a fixed programming voltage is applied to a word line, either a programming enable voltage or a programming disable voltage can be applied to the bit line to which the selected memory cell is connected. For example, depending on the application of the fixed programming voltage, the threshold voltage of a memory cell to which a programming enable voltage is applied may have a voltage corresponding to the intermediate state IM. Conversely, the threshold voltage of a memory cell to which a programming disable voltage is applied may maintain the erase state E.

[0104] The second programming operation, 2nd PGM, can be an operation that programs memory cells having threshold voltages corresponding to the erase state E and the intermediate state IM to each having a threshold voltage corresponding to the target programming state.

[0105] After the second programming operation 2nd PGM is performed, the memory cell that maintained the erase state E in the first programming operation 1st PGM may have a threshold voltage corresponding to any one of the first programming states P1 to the third programming states P3. Alternatively, the memory cell that was programmed to the intermediate state IM in the first programming operation may have a threshold voltage corresponding to any one of the fourth programming states P to the seventh programming states P7.

[0106] Reference Figure 5BAfter executing the second programming operation 2nd PGM, the memory cell corresponding to the erase state E can store the data "111", and the memory cells corresponding to the first programming states P1 to the seventh programming states P7 can store the data "101", "100", "110", "010", "011", "001", and "000", respectively. Therefore, when executing the first programming operation 1st PGM, the memory cell corresponding to the erase state E can be a memory cell that stores one of "111", "101", "100", and "110" after the second programming operation 2nd PGM is executed thereafter, and the memory cell corresponding to the intermediate state IM can be a memory cell that stores the data "010", "011", "001", and "000" after the second programming operation 2nd PGM is executed thereafter.

[0107] That is, the erase state E and the intermediate state IM can be distinguished solely by the LSB page data within the page data. This means that the first programming operation 1st PGM can be performed using only the LSB page data.

[0108] The following describes the read operation of reading data from a programmed memory cell.

[0109] Figures 6A to 6C This is a diagram illustrating data stored in a memory cell and a method for reading data according to an embodiment of the present disclosure.

[0110] Figure 6A This is a diagram illustrating the operation of reading LSB page data.

[0111] In reference Figure 5A and Figure 5B In the described programming operation scenario, the first programming operation (1st PGM) can be performed using only LSB page data. For this purpose, it is necessary to distinguish the LSB page data based on a read voltage, and as a result of this distinction, a similar number of target programming states for memory cells with LSB page data of "1" or LSB page data of "0" is helpful for reliability.

[0112] Therefore, taking this into consideration, such as Figure 6A As shown, it is necessary to use the fourth read voltage R4 to read the LSB page data through a single sensing to perform the reference. Figure 5A and Figure 5B The programming operations described.

[0113] The LSB page data of the memory cell corresponding to the erase state E and the first programming states P1 to the third programming states P3 can be "1", and the LSB page data of the memory cell corresponding to the fourth programming state P4 to the seventh programming state P7 can be "0".

[0114] Figure 6B This is a diagram illustrating the operation of reading CSB page data.

[0115] Reference Figure 6B It can obtain CSB page data through sensing operations based on three different read voltages.

[0116] For example, CSB page data can be obtained by sensing using a first read voltage R1, a third read voltage R3, and a sixth read voltage R6. The CSB data of a memory cell determined to be an active cell by the first read voltage R1 can be "1". The CSB data of a memory cell determined to be an off cell by read voltage R1 and an active cell by the third read voltage R3 can be "0". The CSB data of a memory cell determined to be an off cell by the third read voltage R3 and an active cell by the sixth read voltage R6 can be "1". The CSB data of a memory cell determined to be an off cell by the sixth read voltage R6 can be "0".

[0117] Figure 6C This is a diagram illustrating the operation of reading MSB page data.

[0118] Reference Figure 6C MSB page data can be obtained through sensing operations based on three different read voltages.

[0119] For example, MSB page data can be obtained by sensing using the second read voltage R2, the fifth read voltage R5, and the seventh read voltage R7. The MSB data of a memory cell determined to be an active cell by the second read voltage R2 can be "1". The MSB data of a memory cell determined to be an off cell by the second read voltage R2 and an active cell by the fifth read voltage R5 can be "0". The MSB data of a memory cell determined to be an off cell by the fifth read voltage R5 and an active cell by the seventh read voltage R7 can be "1". The CSB data of a memory cell determined to be an off cell by the seventh read voltage R7 can be "0".

[0120] When based on reference Figures 6A to 6C The described Gray code may not have any disadvantages when performing read operations compared to other types of Gray code for storing data.

[0121] That is, the number of read voltages used to perform CSB read operations to obtain CSB page data and the number of read voltages used to perform MSB read operations to obtain MSB page data are both 3. However, considering that the read voltages used for LSB read, CSB read, and MSB read are the same as 7 to read data stored in the TLC, the first programming operation 1st PGM can be performed using only LSB page data without degrading the overall read performance, thus improving programming speed.

[0122] Figure 7 This is a diagram illustrating the voltages applied to the word lines and bit lines during programming operations according to an embodiment of the present disclosure.

[0123] Reference Figure 7 The first programming operation 1st PGM can be an operation that programs memory cells according to data to be stored in each memory cell so that the threshold voltage of the memory cell connected to the selected word line has a threshold voltage corresponding to either the erase state E or the intermediate state IM. In an embodiment, the magnitude of the threshold voltage corresponding to the intermediate state IM can be greater than the magnitude of the threshold voltage corresponding to the erase state E. In an embodiment, the memory cell to be programmed to the intermediate state IM in the first programming operation 1st PGM can be a memory cell whose target programming state is any one of the fourth programming state P to the seventh programming state P7. Conversely, the target programming state of the memory cell that maintains the erase state E in the first programming operation can be any one of the erase state E and the first programming state P1 to the third programming state P3.

[0124] exist Figure 7 In this context, it is assumed that the target threshold voltage of the memory cell connected to the first bit line BL1, the second bit line BL2, and the fourth bit line BL4 is in the third programming state P3.

[0125] In the first programming operation 1st PGM, a fixed programming voltage VPGMx of a predetermined magnitude can be applied to the selected word line. Figure 7 The illustration shows a case where a fixed programming voltage VPGMx is applied once during the first programming operation 1st PGM. In various embodiments, the fixed programming voltage VPGMx may be provided to the memory cell two or more times. In embodiments, the first programming operation 1st PGM may also include multiple programming cycles. In this case, even if programming cycles included in the first programming operation 1st PGM are performed, the level of the programming voltage applied to the word line does not increase, and the programming voltage may be a fixed programming voltage with a fixed voltage level. In embodiments, the first programming operation 1st PGM may be a programming operation that does not perform a verification step.

[0126] When a fixed programming voltage VPGMx is applied to the word lines, a programming disable voltage Vinh can be applied to the bit lines BL1, BL2, and BL4 to which the memory cell with an erase state E and a first programming state P1 to a third programming state P3 as target programming states are connected. In an embodiment, the programming disable voltage Vinh may have the level of the power supply voltage Vcc of the memory device. When the fixed programming voltage VPGMx is applied to the word lines, a programming enable voltage (0V) can be applied to the bit lines BL3 and BL5 to which the memory cell with any of the fourth programming states P4 to the seventh programming states P7 as target programming states are connected.

[0127] In various implementations, the first programming operation 1st PGM can be performed by applying a fixed programming voltage VPGMx, executing a verification step, and then applying an additional programming voltage. That is, according to reference... Figure 7 In the described implementation, there is no limitation on the number of times the programming voltage is applied during the first programming operation 1st PGM and whether a verification step is performed.

[0128] The second programming operation, 2nd PGM, may include multiple programming cycles PL1 to PLn. A programming cycle includes a programming voltage application step, PGM Step, which applies a programming voltage to a selected word line, and a verification step, which senses whether the threshold voltage of each memory cell has reached the threshold voltage corresponding to the target programming state. Each programming cycle increases the programming voltage applied to the word line by a step voltage Vstep compared to the programming voltage in the previous programming cycle. Here, the step voltage may be a preset voltage value. This is called the Incremental Step Pulse Programming (ISPP) scheme. Even if programming cycles corresponding to a preset maximum number of cycles are executed, programming operation failure can be determined if all memory cells connected to the selected word line have not reached the target programming state. In various embodiments, the number of programming states verified in each programming cycle may be at least two or more.

[0129] Figure 8 This is a diagram illustrating the programming order of pages included in a storage block.

[0130] Reference Figure 8 A memory block BLKx can be connected to multiple physical word lines. A physical word line can be connected to four logic word lines. A memory cell connected to any one logic word line can be configured as a page. For example, each of the first physical word lines WL1 to the fourth physical word line WL4 can be connected to the first logic word line LWL1 to the fourth logic word line LWL4.

[0131] In this implementation, the first string ST1 to the fourth string ST4 can be connected to the same position line. The fifth string ST5 to the eighth string ST8 can be connected to the same position line.

[0132] Figure 8 The example shown includes a structure in which four strings are connected to the same bit line in a single memory block, but this is for ease of description and the number of strings connected to the bit line may be less or more than four.

[0133] For example, the number of logic word lines connected to a physical word line can be determined based on the number of strings commonly connected to a bit line. For instance, when five strings are commonly connected to a bit line, a physical word line can be commonly connected to five local word lines. In this case, a physical word line can include five pages. Within these five pages, a string selection signal (e.g., applied to...) can be used... Figure 3 The signal of the drain select line or source select line is used to determine the programmed string and the unprogrammed string.

[0134] The first logic word line LWL1 can be selected by the first string ST1 and the fifth string ST5. The second logic word line LWL2 can be selected by the second string ST2 and the sixth string ST6. The third logic word line LWL3 can be selected by the third string ST3 and the seventh string ST7. The fourth logic word line LWL4 can be selected by the fourth string ST4 and the eighth string ST8. A page can be selected by one logic word line and one physical word line.

[0135] That is, the first physical word line WL1 may include pages 1 through 4 (PG1). The second physical word line WL2 may include pages 5 through 8 (PG8). The third physical word line WL3 may include pages 9 through 12 (PG12). The fourth physical word line WL4 may include pages 13 through 16 (PG16).

[0136] Figure 9A This is a diagram illustrating programming sequence information according to embodiments of the present disclosure.

[0137] Reference Figure 9A Programming order information may include information about Figure 2 Information on the programming order of the pages included in the storage blocks BLK1 to BLKz.

[0138] In this implementation, programming order information can be stored in a reference. Figure 2 In the described control logic, for example, the control logic may include a programming sequence information storage unit that stores programming sequence information. Here, the programming sequence information storage unit may be implemented as a register.

[0139] Reference Figure 2 The described programming operation controller can perform programming operations based on programming sequence information stored in the programming sequence information storage unit.

[0140] Reference Figure 8 and Figure 9AFirst, the first programming operation 1stPGM (1 to 4) can be executed sequentially on pages 1 through 4 (PG1). Then, after executing the second programming operation 2ndPGM on pages 1 through 4 (PG4), the first programming operation 1stPGM (5-8) can be executed on pages 5 through 8 (PG8). Next, the second programming operation 2ndPGM (9-12) can be executed on pages 1 through 4 (PG4). That is, according to... Figure 9A In the implementation of this method, after sequentially performing a first programming operation 1st PGM on each page configured in a plurality of logical word lines included in the selected physical word line, a second programming operation 2nd PGM can be performed on each page configured in a plurality of logical word lines included in the physical word line in which the first programming operation 1st PGM was performed before the selected physical word line. According to the... Figure 9A In the implementation of sequential data storage, programming operations are performed on the next physical word line after the first programming operation 1st PGM or the second programming operation 2nd PGM is executed on that physical word line. Therefore, changes in the threshold voltage caused by programming disturbances between physical word lines, or by disturbances themselves, can be reduced.

[0141] Figure 9B This is a diagram illustrating programming sequence information according to another embodiment of this disclosure.

[0142] Reference Figure 9B Programming order information may include information about Figure 2 Information on the programming order of the pages included in the storage blocks BLK1 to BLKz.

[0143] In this implementation, programming order information can be stored in a reference. Figure 2 In the described control logic, for example, the control logic may include a programming sequence information storage unit that stores programming sequence information. Here, the programming sequence information storage unit may be implemented as a register.

[0144] Reference Figure 2 The described programming operation controller can perform programming operations based on programming sequence information stored in the programming sequence information storage unit.

[0145] Reference Figure 8 and Figure 9B First, the first programming operation 1stPGM (1 to 4) can be performed sequentially on pages PG1 to PG4. Thereafter, while alternately selecting the second physical word line WL2 and the first physical word line WL1, programming operations can be performed sequentially on each of the logic word lines LWL1 to LWL4.

[0146] For example, before performing the second programming operation 2nd PGM on pages PG1 through PG4, pages 1 through 4, a first programming operation 1st PGM on page PG5, which is connected to the first logic word line WL2, can be performed. Afterward, a second programming operation 2nd PGM on page PG1 can be performed. Next, a first programming operation 1st PGM on page PG6, a second programming operation 2nd PGM on page PG2, a first programming operation 1st PGM on page PG7, a second programming operation 2nd PGM on page PG3, a first programming operation 1st PGM on page PG8, and a second programming operation 2nd PGM on page PG4 can be performed.

[0147] That is, according to the basis Figure 9B In the implementation of the programming sequence, a first programming operation 1st PGM for a page configured on each of a plurality of logical word lines included in the selected physical word lines can be alternately performed with a second programming operation 2nd PGM for a page configured on each logical word line on which the first programming operation 1st PGM was previously performed.

[0148] Based on the basis Figure 9B In the case of storing data in the programming order of the implementation method, and according to the method... Figure 9A Similar to the sequential data storage method in this implementation, after performing the first programming operation 1st PGM or the second programming operation 2nd PGM on a physical word line, the programming operation for the next physical word line is performed. Therefore, changes in the threshold voltage caused by programming disturbances between physical word lines or by disturbances can be reduced.

[0149] Figure 10 This is a diagram illustrating the types of programming methods 2-8 according to embodiments of this disclosure.

[0150] Reference Figure 10 S1001 indicates the programming operation time T1 when all LSB page data, CSB page data, and MSB page data are required during the execution of the first programming operation 1st PGM and the second programming operation 2nd PGM.

[0151] S1003 indicates the programming operation time T2 if only LSB page data is needed in the first programming operation 1st PGM and all LSB page data, CSB page data and MSB page data are needed in the second programming operation 2nd PGM.

[0152] Comparing S1001 and S1003, the time required to perform the first programming operation 1st PGM and the second programming operation 2nd PGM is similar in both cases. However, according to the embodiment of this disclosure, since only LSB page data is required to perform the first programming operation 1st PGM, the length of the data input period before the first programming operation 1st PGM is shorter than that in S1001.

[0153] As a result, the programming operation time T3 can be reduced according to the programming method based on the embodiments of this disclosure.

[0154] Figure 11 It is shown Figure 1 A block diagram illustrating an example of the connection relationships between a storage controller and multiple memory devices.

[0155] Reference Figure 11 The memory controller 200 can be connected to multiple memory devices (memory devices_00 to memory devices_33) via multiple channels CH0 to CH3. In the embodiments, it will be understood that the number of channels or the number of memory devices connected to each channel may vary. However, for ease of description, this specification assumes that the memory controller 200 is connected to the memory devices via four channels and that the four memory devices are connected to each channel.

[0156] Memory devices 00, 01, 02, and 03 can be connected to channel 0CH0. Memory devices 00, 01, 02, and 03 can communicate with the memory controller 200 via channel 0CH0. Because memory devices 00, 01, 02, and 03 are connected to channel 0CH0, only one memory device can communicate with the memory controller 200 at a time. However, each of memory devices 00, 01, 02, and 03 can perform internal operations simultaneously.

[0157] Memory devices 10, 11, 12, and 13 can be connected to channel 1CH1. Memory devices 10, 11, 12, and 13 can communicate with the memory controller 200 via channel 1CH1. Because memory devices 10, 11, 12, and 13 are connected to channel 1CH1, only one memory device can communicate with the memory controller 200 at a time. However, each of memory devices 10, 11, 12, and 13 can perform internal operations simultaneously.

[0158] Memory devices 20, 21, 22, and 23 can be connected to channel 2CH2. Memory devices 20, 21, 22, and 23 can communicate with the memory controller 200 via channel 2CH2. Because memory devices 20, 21, 22, and 23 are connected to channel 2CH2, only one memory device can communicate with the memory controller 200 at a time. However, each of memory devices 20, 21, 22, and 23 can perform internal operations simultaneously.

[0159] Memory devices 30, 31, 32, and 33 can be connected to channel 3CH3. Memory devices 30, 31, 32, and 33 can communicate with the memory controller 200 via channel 3CH3. Because memory devices 30, 31, 32, and 33 are connected to channel 3CH3, only one memory device can communicate with the memory controller 200 at a time. However, each of memory devices 30, 31, 32, and 33 can perform internal operations simultaneously.

[0160] Storage devices using multiple memory devices can improve performance using data interleaving (data communication using an interleaving method). Data interleaving allows read or write operations to be performed while moving paths in a structure where two or more paths share a channel. For data interleaving, memory devices can be managed on a channel and path basis. To maximize the parallelism of memory devices connected to various channels, the storage controller 200 can distribute contiguous logical memory regions across channels and paths and allocate contiguous logical memory regions.

[0161] For example, the memory controller 200 can send control signals, including commands and addresses, as well as data to the memory device 00 via channel 0CH0. When the memory device 00 programs the data sent therein into the memory cell, the memory controller 200 sends control signals, including commands and addresses, as well as data to the memory device 01.

[0162] like Figure 11As shown, multiple memory devices can be configured using four paths WAY0 to WAY3. Path 0WAY0 may include memory device_00, memory device_10, memory device_20, and memory device_30. Path 1WAY1 may include memory device_01, memory device_11, memory device_21, and memory device_31. Path 2WAY2 may include memory device_02, memory device_12, memory device_22, and memory device_32. Path 3WAY3 may include memory device_03, memory device_13, memory device_23, and memory device_33.

[0163] Each of channels CH0 to CH3 can be a bus of signals shared and used by memory devices connected to the corresponding channel.

[0164] Reference Figure 11 This describes data interleaving with a 4-channel / 4-path structure. However, as the number of channels and paths increases, the interleaving efficiency can become more efficient.

[0165] Figure 12 It is a timing diagram illustrating programming operations based on data interweaving.

[0166] exist Figure 12 For ease of description, we assume that the common connection is... Figure 11 The memory devices _00 to _03 of channel 0CH0 perform programming operations.

[0167] During t0 to t1, data input DIN#00 can be performed to memory device _00. When performing data input DIN#00, memory device _00 can receive programming commands, addresses, and data via channel 0CH0. Since memory devices _00, _01, _02, and _03 are all connected to channel 0CH0, when performing data input DIN#00 to memory device _00, memory devices _01, _02, and _03, being the remaining memory devices, may not use channel 0CH0.

[0168] During periods t1 to t2, data input DIN#01 can be performed to memory device _01. When performing data input DIN#01, memory device _01 can receive programming commands, addresses, and data via channel 0CH0. Since memory devices _00, _01, _02, and _03 are all connected to channel 0CH0, when performing data input DIN#01 to memory device _01, memory devices _00, _02, and _03, as the remaining memory devices, may not use channel 0CH0. However, since memory device _00 receives data (DIN#00) during periods t0 to t1, memory device _00 can begin programming operations (tPROG#00) from t1.

[0169] During periods t2 to t3, data input DIN#02 can be performed to memory device _02. When performing data input DIN#02, memory device _02 can receive programming commands, addresses, and data via channel 0CH0. Since memory devices _00, _01, _02, and _03 are all connected to channel 0CH0, when performing data input DIN#02 to memory device _02, memory devices _00, _01, and _03, as the remaining memory devices, may not use channel 0CH0. However, since memory device _00 receives data (DIN#00) during periods t0 to t1, memory device _00 can begin programming operations (tPROG#00) from t1. Additionally, since memory device _01 receives data (DIN#01) during periods t1 to t2, memory device _01 can begin programming operations (tPROG#01) from t2.

[0170] During periods t3 to t4, data input DIN#03 can be performed to memory device _03. When performing data input DIN#03, memory device _03 can receive programming commands, addresses, and data via channel 0CH0. Since memory devices _00, _01, _02, and _03 are all connected to channel 0CH0, memory devices _00, _01, and _02, being the remaining memory devices, may not use channel 0CH0 when performing data input DIN#03 to memory device _03. However, since memory device _00 receives data (DIN#00) during periods t0 to t1, it can begin programming operations (tPROG#00) from t1. Similarly, since memory device _01 receives data (DIN#01) during periods t1 to t2, it can begin programming operations (tPROG#01) from t2. In addition, since memory device _02 receives data (DIN#02) during time period t2 to t3, memory device _02 can perform programming operations (tPROG#02) starting from t3.

[0171] At t4, the programming operation of memory device _00 can be completed (tPROG#00).

[0172] Subsequently, from t4 to t8, data inputs DIN#00, DIN#01, DIN#02 and DIN#03 to memory devices_00 to_03 can be performed in the same manner as those performed from t0 to t4.

[0173] Reference Figures 10 to 12 When based on Figure 10 When the data input method of the implementation method performs operations according to the first programming operation 1st PGM and the second programming operation 2nd PGM, a bottleneck phenomenon may occur between the storage controller and the memory device due to the first programming operation 1st PGM having a relatively short data input period.

[0174] However, this is based on the passage Figure 8 as well as Figure 9A and Figure 9B When the programming sequence is executed, the complete page data is input when the CSB and MSB data of page N are combined with the LSB of page (N+1). Therefore, data storage efficiency can be faster when the first programming operation 1st PGM and the second programming operation 2nd PGM are executed via an interleaving method.

[0175] In various implementations, the memory device can independently use the voltage used in the first programming operation and the voltage used in the second programming operation.

[0176] The following is for reference Figures 13 to 18 Describe in detail the method for controlling the voltage used in the first programming operation and the second programming operation.

[0177] Figure 13 This is a diagram illustrating the configuration of a memory device that performs the programming operations of this disclosure.

[0178] Reference Figure 13 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0179] The memory cell array 110 and peripheral circuitry 120 can be referenced Figure 2 The memory cell array 110 and peripheral circuitry 120 are configured and operate identically.

[0180] The control logic 130 may include a programming operation controller 131 and a programming information storage unit 132. The programming operation controller 131 can control the programming operation of the memory device 100. The programming operation controller 131 may include a first programming operation controller 131_1 that controls a first programming operation and a second programming operation controller 131_2 that controls a second programming operation.

[0181] The programming information storage unit 132 can store various information used for programming operations. The programming information storage unit 132 may include a programming sequence information storage unit 132_1, a programming voltage information storage unit 132_2, and a programming time information storage unit 132_3.

[0182] Programming sequence information storage unit 132_1 can store references Figure 9A and Figure 9B The programming sequence information is described. This programming sequence information can be pre-stored in a Content Addressable Memory (CAM) block, which is one of multiple memory blocks included in the memory cell array 110, and then loaded into the programming sequence information storage unit 132_1 when the memory device 100 is booted. The programming operation controller 131 can control the peripheral circuitry 120 to perform a first programming operation and a second programming operation based on the programming sequence information stored in the programming sequence information storage unit 132_1.

[0183] The programming voltage information storage unit 132_2 can store information about the voltage used in the programming operation. In an embodiment, the information about the voltage used in the programming operation may include offset voltage information, second programming operation start voltage information, step voltage information, and pass voltage information.

[0184] The voltage applied to the selected word line during the first programming operation can be a fixed programming voltage of a predetermined magnitude. In various embodiments, the voltage applied to the selected word line during the first programming operation can be a voltage obtained by adding a predetermined offset voltage to a programming start voltage applied during the second programming operation. In another embodiment, the voltage applied to the selected word line during the first programming operation can be a voltage obtained by adding a predetermined offset voltage, which has a different magnitude depending on the position of the selected word line, to a programming start voltage applied during the second programming operation.

[0185] During the first programming operation, a first pass voltage may be applied to the unselected word line. During the second programming operation, a second pass voltage may be applied to the unselected word line. In an embodiment, the magnitude of the first pass voltage may be different from the magnitude of the second pass voltage. For example, the magnitude of the first pass voltage may be higher than the voltage level of the second pass voltage. Alternatively, the magnitude of the first pass voltage may be lower than the voltage level of the second pass voltage.

[0186] When performing the first programming operation and the second programming operation, the memory device may apply a pass voltage having a different voltage level than the pass voltage applied to the unselected word lines adjacent to the selected word lines to the remaining unselected word lines. At this time, the magnitudes of the pass voltage applied during the first programming operation and the pass voltage applied during the second programming operation may be different.

[0187] The programming time information storage unit 132_3 can store information about the application time of the voltage applied during the programming operation.

[0188] Figure 14 It is a diagram showing the voltage applied during the first programming operation and the second programming operation.

[0189] Reference Figure 14 During the period from t0 to t4, the memory device may perform a first programming operation, and during the period from t5 to t9, the memory device may perform a programming voltage application step of the first programming cycle of a second programming operation.

[0190] At t0, a first precharge voltage VPRE1 can be applied to the bit line to which the memory cell to be disabled for programming is connected. The first precharge voltage VPRE1 can be applied during the period from t0 to t3, which can be the first precharge period Tpre1.

[0191] At t1, the first pass voltage VPASS1 can be applied to the selected word lines (WL) and the unselected word lines (WLs). The first pass voltage VPASS1 can be applied during the period from t1 to t3, which can be the first pass voltage period Tpass1.

[0192] During the period from t2 to t3, the first programming voltage 1ST PGM VPGM can be applied to the selected word line Selected WL. The magnitude of the first programming voltage 1ST PGM VPGM can be a voltage that is higher than the offset voltage VOFFSET of the second programming voltage 2ND PGM VPGM1 (the programming voltage applied in the first programming cycle of the second programming operation).

[0193] During the period from t3 to t4, the applied voltage to the bit line, selected word line (WL), and unselected word line (WLs) can be discharged. This period can be the first discharge period Tdis1.

[0194] At t5, a second precharge voltage VPRE2 can be applied to the bit line to which the memory cell to be disabled for programming is connected. The second precharge voltage VPRE2 can be applied during the period from t5 to t8, and this period can be the second precharge period Tpre2.

[0195] In an implementation, the second pre-charge voltage VPRE2 can be a voltage having a different voltage level than the first pre-charge voltage VPRE1. For example, the second pre-charge voltage VPRE2 can be a voltage lower than the first pre-charge voltage VPRE1. However, in Figure 14 In this embodiment, the magnitude of the second pre-charge voltage VPRE2 is not limited. In various embodiments, the magnitude of the second pre-charge voltage VPRE2 may be higher than the magnitude of the first pre-charge voltage VPRE1.

[0196] The length of the second pre-charge period Tpre2, in which the second pre-charge voltage VPRE2 is applied during the second programming operation, may be different from the length of the first pre-charge period Tpre1, in which the first pre-charge voltage VPRE1 is applied during the first programming operation. For example, the length of the second pre-charge period Tpre2 may be longer than the length of the first pre-charge period Tpre1. However, according to... Figure 14 In this implementation, the length of the second pre-charge period Tpre2 is not limited, and the length of the second pre-charge period Tpre2 can be shorter than the length of the first pre-charge period Tpre1.

[0197] At t6, a second pass voltage VPASS2 can be applied to the selected word lines (WL) and the unselected word lines (WLs). The second pass voltage VPASS2 can be applied during the period from t6 to t8, and this period can be the second pass voltage period Tpass2.

[0198] In an implementation, the second pass voltage VPASS2 can be a voltage having a different voltage level than the first pass voltage VPASS1. For example, the second pass voltage VPASS2 can be a voltage higher than the first pass voltage VPASS1. However, in Figure 14 In some embodiments, the magnitude of the second through voltage VPASS2 is not limited. In various embodiments, the magnitude of the second through voltage VPASS2 may be lower than the magnitude of the first through voltage VPASS1.

[0199] In the second programming operation, the length of the second through voltage period Tpass2, where the second through voltage VPASS2 is applied, can be different from the length of the first through voltage period Tpass1, where the first through voltage VPASS1 is applied, in the first programming operation. For example, the length of the second through voltage period Tpass2 can be longer than the length of the first through voltage period Tpass1. However, according to... Figure 14 In this implementation, the length of the second voltage period Tpass2 is not limited, and the length of the second voltage period Tpass2 can be shorter than the length of the first voltage period Tpass1.

[0200] During t7 to t8, a second programming voltage 2ND PGM VPGM1, which is the programming voltage applied in the first programming cycle of the second programming operation, can be applied to the selected word line WL. The magnitude of the second programming voltage 2ND PGM VPGM1 can be a voltage that is lower than the level of the first programming voltage 1ST PGM VPGM by an offset voltage VOFFSET.

[0201] During the period from t8 to t9, the applied voltage to the bit line, selected word line (WL), and unselected word line (WLs) can be discharged. This period can be the second discharge period Tdis2.

[0202] In the second programming operation, the length of the second discharge period Tdis2, which discharges the voltage of each line, can be different from the length of the first discharge period Tdis1, which discharges the voltage of each line in the first programming operation. For example, the length of the second discharge period Tdis2 can be longer than the length of the first discharge period Tdis1. However, according to... Figure 14 In this implementation, the length of the second discharge period Tdis2 is not limited, and the length of the second discharge period Tdis2 can be shorter than the length of the first discharge period Tdis1.

[0203] Figure 15 It is shown Figure 13 A diagram illustrating an implementation of the programming voltage information storage unit.

[0204] Reference Figure 15 The programming voltage information storage unit 132_2 may include offset voltage information OFFSET VOLTAGE, second programming operation start voltage information 2ND PGM START VOLTAGE, step voltage information STEP VOLTAGE, and through voltage information 1ST PASS VOLTAGE and 2ND PASS VOLTAGE.

[0205] The offset voltage information OFFSET VOLTAGE may include information VOFFSET about the magnitude of the offset voltage used to determine the programming voltage applied to the selected word line during the first programming operation. For example, the programming voltage applied to the selected word line during the first programming operation may be a voltage obtained by adding the offset voltage to the programming start voltage applied during the second programming operation.

[0206] The second programming start voltage information 2ND PGM START VOLTAGE may include information about the magnitude of the programming voltage applied in the first programming cycle of the second programming operation, VPGM_START.

[0207] The step voltage information STEP VOLTAGE may include information about the magnitude of the step voltage increased for each programming cycle in the second programming operation.

[0208] The voltage information 1ST PASS VOLTAGE and 2ND PASS VOLTAGE may include the first voltage information 1ST PASS VOLTAGE and the second voltage information 2ND PASS VOLTAGE.

[0209] The first pass voltage information 1ST PASS VOLTAGE may include information VPASS1 regarding the magnitude of the pass voltage applied to the unselected word line during the first programming operation. The second pass voltage information 2ND PASS VOLTAGE may include information VPASS2 regarding the magnitude of the pass voltage applied to the unselected word line during the second programming operation. The second pass voltage may be a voltage having a different voltage level than the first pass voltage. For example, the second pass voltage may be higher than the first pass voltage. Alternatively, the magnitude of the second pass voltage may be lower than the first pass voltage.

[0210] Figure 16 It is shown Figure 13 A diagram of another embodiment of the programming voltage information storage unit.

[0211] Figure 16The programming voltage information storage unit 132_2' may include offset voltage information OFFSET VOLTAGE for applying different offset voltages according to the selected word line.

[0212] Multiple memory cells connected to a memory block can have different electrical characteristics depending on the location of the word lines they are connected to. Therefore, to determine the optimal programming operation voltage, the optimal offset voltage can be determined during the manufacturing of the memory device by testing the process based on the location of each word line.

[0213] Reference Figure 16 Each offset voltage from word line 00WL00 to word line 16WL16 can have different voltage values ​​as offset voltage 00VOFFSET00 to offset voltage 16VOFFSET16. In an embodiment, word lines included in a memory block can be divided into multiple groups, and different offset voltages can be used for each group.

[0214] Can Figure 16 In the same implementation, the programming voltage information is used to perform the operation of a more optimized first programming voltage.

[0215] Figure 17 It is shown Figure 13 A diagram of another embodiment of the programming voltage information storage unit.

[0216] Figure 17 The programming voltage information storage unit 132_2” may include voltage information 1ST PASS VOLTAGE(N+1,N-1), 1ST PASS VOLTAGE(OTHER), 2ND PASS VOLTAGE(N+1,N-1) and 2ND PASS VOLTAGE(OTHER).

[0217] Reference Figure 17 The voltage information 1ST PASS VOLTAGE(N+1,N-1), 1ST PASS VOLTAGE(OTHER), 2ND PASS VOLTAGE(N+1,N-1) and 2ND PASS VOLTAGE(OTHER) may include information about the pass voltage applied to the adjacent unselected word line during the first programming operation, information about the pass voltage applied to the remaining unselected word line during the first programming operation, information about the pass voltage applied to the adjacent unselected word line during the second programming operation, and information about the pass voltage applied to the remaining unselected word line during the second programming operation.

[0218] Assuming the selected word line is the Nth word line, then the (N+1)th and (N-1)th word lines adjacent to the Nth word line can be unselected word lines adjacent to the selected word line. Among the unselected word lines, the remaining word lines besides the adjacent unselected word lines can be the remaining unselected word lines (OTHER).

[0219] Different through voltages can be applied to adjacent unselected word lines and the remaining unselected word lines, respectively. In various embodiments, different through voltages can also be applied to adjacent unselected word lines and the remaining unselected word lines during the first programming operation and the second programming operation, respectively.

[0220] For example, during the first programming operation, a third pass voltage VPASS3 may be applied to the adjacent unselected word line, and a fourth pass voltage VPASS4 may be applied to the remaining unselected word lines. During the second programming operation, a fifth pass voltage VPASS5 may be applied to the adjacent unselected word line, and a sixth pass voltage VPASS6 may be applied to the remaining unselected word lines.

[0221] Figure 18 It is shown Figure 13 A diagram illustrating an implementation of the programming time information storage unit.

[0222] Reference Figure 18 The programming time information storage unit 132_3 may include information about the length of the precharge time (PRECHARGETIME) indicating the period during which a precharge voltage is applied during the first programming operation 1STPROGRAM and the second programming operation 2NDPROGRAM, the pass voltage time (PASS VOLTAGE APPLICATION TIME) indicating the period during which a pass voltage is applied, and the discharge time (DISCHARGE TIME) indicating the period during which the voltage of each line is discharged.

[0223] For reference Figure 14 As described, the precharge period PRECHARGE TIME in the first programming operation 1ST PROGRAM can be the first precharge period Tpre1, the pass voltage application TIME can be the first pass voltage application TIME Tpass1, and the discharge period DISCHARGE TIME can be the first discharge period Tdis1.

[0224] In addition, the precharge period PRECHARGE TIME in the second programming operation 2ND PROGRAM can be the second precharge period Tpre2, the pass voltage application period PASS VOLTAGE APPLICATION TIME can be the second pass voltage application period Tpass2, and the discharge period DISCHARGE TIME can be the second discharge period Tdis2.

[0225] During the first programming operation 1ST PROGRAM and the second programming operation 2ND PROGRAM, the lengths of the precharge time, pass voltage application time, and discharge time can be different. By varying the duration of voltage application or discharge during the first programming operation 1ST PROGRAM and the second programming operation 2ND PROGRAM, the memory device can efficiently control the execution time of the entire programming operation.

[0226] Figure 19 It is shown Figure 1 A diagram of another embodiment of the storage controller.

[0227] Reference Figure 1 and Figure 19 The storage controller 1200 may include a processor 1210, RAM 1220, error correction circuitry 1230, ROM 1260, host interface 1270, and flash memory interface 1280.

[0228] The processor 1210 controls the overall operation of the memory controller 1200. The RAM 1220 can be used as a buffer memory, cache memory, operation memory, etc. of the memory controller 1200.

[0229] ROM 1260 can store various information required for the operation of storage controller 1200 in firmware form.

[0230] The storage controller 1200 can communicate with external devices (e.g., reference 1270) via the host interface 1270. Figure 1 The description refers to communication between the host 300, application processor, etc.

[0231] The storage controller 1200 can connect to the reference via the flash memory interface 1280. Figure 1 The described memory device 100 communicates. The memory controller 1200 can send commands (CMD), addresses (ADDR), control signals (CTRL), etc., to the memory device 100 and receive data (DATA) via a flash memory interface 1280. For example, the flash memory interface 1280 may include a NAND interface.

[0232] Figure 20 This is a block diagram illustrating a memory card system using a storage device according to an embodiment of the present disclosure.

[0233] Reference Figure 20 The memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0234] Storage controller 2100 is connected to memory device 2200. Storage controller 2100 is configured to access memory device 2200. For example, storage controller 2100 may be configured to control read operations, write operations, erase operations, and background operations of memory device 2200. Storage controller 2100 is configured to provide an interface between memory device 2200 and a host. Storage controller 2100 is configured to drive firmware for controlling memory device 2200. Storage controller 2100 may be referenced... Figure 1 The described storage controller 200 is implemented equivalently.

[0235] For example, the storage controller 2100 may include components such as random access memory (RAM), a processor, a host interface, a memory interface, and an error corrector.

[0236] Storage controller 2100 can communicate with external devices via connector 2300. Storage controller 2100 can communicate with external devices (e.g., a host) according to specific communication standards. For example, storage controller 2100 is configured to communicate with external devices via at least one of various communication standards such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe. For example, connector 2300 can be defined by at least one of the aforementioned communication standards.

[0237] For example, the memory device 2200 may be configured with various non-volatile memory elements such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM).

[0238] The storage controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to configure a memory card. For example, the storage controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to configure memory cards such as PC cards (Personal Computer Memory Card International Association (PCMCIA)), compact flash memory cards (CF), smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro or eMMC), SD cards (SD, miniSD, microSD or SDHC), and universal flash memory (UFS).

[0239] Figure 21 This is a block diagram illustrating a solid-state drive (SSD) system using a storage device according to an embodiment of the present disclosure.

[0240] Reference Figure 21 The SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals SIG with the host 3100 through a signal connector 3001 and receives power PWR through a power connector 3002. The SSD 3200 includes an SSD controller 3210, multiple flash memory modules 3221 to 322n, an auxiliary power supply unit 3230, and a cache memory 3240.

[0241] According to embodiments of this disclosure, the SSD controller 3210 can execute reference... Figure 1 The functions of the storage controller 200 are described.

[0242] SSD controller 3210 can control multiple flash memory modules 3221 to 322n in response to a signal SIG received from host 3100. For example, the signal SIG can be a signal based on the interface between host 3100 and SSD 3200. For example, the signal SIG can be a signal defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0243] An auxiliary power supply unit 3230 is connected to the host 3100 via a power connector 3002. The auxiliary power supply unit 3230 can receive power (PWR) from the host 3100 and can be used for charging. When the power supply from the host 3100 is unstable, the auxiliary power supply unit 3230 can provide power to the SSD 3200. For example, the auxiliary power supply unit 3230 can be located inside the SSD 3200 or external to the SSD 3200. For example, the auxiliary power supply unit 3230 can be located on the motherboard and can provide auxiliary power to the SSD 3200.

[0244] Buffer memory 3240 operates as a buffer memory for SSD 3200. For example, buffer memory 3240 may temporarily store data received from host 3100 or data received from multiple flash memory modules 3221 to 322n, or it may temporarily store metadata (e.g., a mapping table) of flash memory modules 3221 to 322n. Buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0245] Figure 22 This is a block diagram illustrating a user system employing a storage device according to an embodiment of the present disclosure.

[0246] Reference Figure 22 The user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0247] Application processor 4100 can drive components, operating system (OS), user programs, etc., included in user system 4000. For example, application processor 4100 may include controllers, interfaces, graphics engines, etc., that control components included in user system 4000. Application processor 4100 may be provided as a system-on-chip (SoC).

[0248] Memory module 4200 can operate as main memory, working memory, buffer memory, or cache memory of user system 4000. Memory module 4200 may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, application processor 4100 and memory module 4200 may be packaged in a stacked package (POP) and provided as a single semiconductor package.

[0249] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), LTE, WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. For example, network module 4300 may be included in application processor 4100.

[0250] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can send data stored in storage module 4400 to application processor 4100. For example, storage module 4400 can be implemented as a non-volatile semiconductor memory element such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, and three-dimensional NAND flash memory. For example, storage module 4400 can be provided as a removable storage device (removable drive) such as a memory card and as an external drive for user system 4000.

[0251] For example, storage module 4400 may include multiple non-volatile memory devices, and the multiple non-volatile memory devices may be referenced. Figure 1 The memory device 100 described operates in the same manner. The memory module 4400 is compatible with the referenced... Figure 1 The storage device 50 described operates in the same manner.

[0252] User interface 4500 may include interfaces for inputting data or instructions to application processor 4100 or for outputting data to external devices. For example, user interface 4500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric element. User interface 4500 may include user output interfaces such as liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0253] Cross-reference to related applications

[0254] This application claims priority to Korean Patent Application No. 10-2020-0097006, filed with the Korean Intellectual Property Office on August 3, 2020, and Korean Patent Application No. 10-2021-0003589, filed with the Korean Intellectual Property Office on January 11, 2021, the full disclosure of which is incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: a memory block including a plurality of physical pages, each physical page including a plurality of memory cells; a peripheral circuit configured to receive one of a plurality of logical page data from a memory controller, perform a first program operation on a selected physical page among the plurality of physical pages using the one of the plurality of logical page data, receive remaining logical page data from the memory controller after the first program operation except for the one of the plurality of logical page data, and perform a second program operation on the selected physical page using the remaining logical page data, wherein the first program operation and the second program operation are operations of storing data into selected memory cells connected to a selected word line among the plurality of memory cells; and a program operation controller configured to control the first program operation and the second program operation, wherein the first program operation includes a program pulse application step of applying a fixed program voltage having a predetermined voltage level to the selected word line only once and does not include a verify step, wherein the second program operation includes a plurality of program loops, each program loop including a program voltage application step of applying a program voltage to a word line to which the selected memory cells are commonly connected and a verify step of verifying a target program state of the selected memory cells, and wherein the level of the fixed program voltage is greater than a voltage applied to the word line in a first program loop among the plurality of program loops by an offset voltage.

2. The memory device of claim 1, wherein, The first program operation is an operation of programming a threshold voltage of the selected memory cells to correspond to any one of an erased state or an intermediate state.

3. The memory device of claim 2, wherein, A number of target program states of memory cells among the plurality of selected memory cells to be programmed to the erased state and a number of target program states of memory cells to be programmed to the intermediate state are the same.

4. The memory device of claim 1, wherein, The selected memory cells have any one of an erased state and first to n-th program states as a target program state, where n is a natural number equal to or greater than 2.

5. The memory device of claim 4, wherein, The peripheral circuit performs a read operation of reading data stored in the selected memory cells.

6. The memory device according to claim 5, further comprising: control logic configured to control the read operation.

7. The memory device of claim 6, wherein, The data includes the plurality of logical page data, and The control logic controls the peripheral circuit to read using one read voltage when reading any one of the plurality of logical page data.

8. The memory device of claim 1, wherein, The one of the logical page data corresponds to least significant bit (LSB) page data.

9. The memory device of claim 8, wherein, The remaining logical page data corresponds to at least one of central significant bit (CSB) page data and most significant bit (MSB) page data.

10. The memory device of claim 1, wherein, The offset voltage has different voltage levels according to a position of the word line.

11. The memory device of claim 1, wherein, A magnitude of a pass voltage applied to unselected word lines among the plurality of memory cells during the first programming operation and a magnitude of a pass voltage applied to unselected word lines among the plurality of memory cells during the second programming operation have different voltage levels.

12. The memory device of claim 11, wherein, The programming operation controller applies pass voltages having different voltage levels to unselected word lines among the unselected word lines adjacent to the selected word line and the remaining unselected word lines.

13. The memory device of claim 1, wherein, The programming operation controller controls a time of applying the fixed programming voltage in the first programming operation and a time of applying the programming voltage in the second programming operation differently.

14. A memory device, comprising: a memory block connected to a plurality of physical word lines each comprising a plurality of pages; a peripheral circuit configured to perform a programming operation of storing data in the plurality of pages; and control logic configured to control the peripheral circuit, wherein the programming operation comprises a first programming operation and a second programming operation, the first programming operation comprises a programming pulse application step of applying a fixed programming voltage having a predetermined voltage level to a selected physical word line only once and does not comprise a verify step, and the second programming operation comprises a plurality of programming loops, each programming loop comprising a programming voltage application step of applying a programming voltage to a physical word line to which selected memory cells are commonly connected and a verify step of verifying a target programmed state of the selected memory cells, and wherein a level of the fixed programming voltage is greater than a voltage applied to the physical word line in a first programming loop among the plurality of programming loops by an offset voltage.

15. The memory device of claim 14, wherein, The plurality of pages are commonly connected to any of a plurality of the physical word lines.

16. The memory device of claim 14, wherein, Each of the physical word lines comprises a plurality of logical word lines connected to the plurality of pages, respectively.

17. The memory device of claim 14, wherein, The offset voltage has different voltage levels according to locations of the physical word lines.

18. The memory device of claim 14, wherein, A magnitude of a pass voltage applied to unselected pages among the plurality of pages during the first programming operation and a magnitude of a pass voltage applied to unselected pages among the plurality of pages during the second programming operation have different voltage levels.

19. The memory device of claim 14, wherein, The control logic controls a time of applying a programming voltage in the first programming operation and a time of applying the programming voltage in the second programming operation differently.

20. A storage device, comprising: a plurality of memory devices; and a storage controller configured to provide a programming command instructing storing data in the memory devices, wherein each of the memory devices comprises: a memory cell block comprising a plurality of physical pages each comprising a plurality of memory cells; a peripheral circuit configured to perform a programming operation of storing data in the plurality of pages; and control logic configured to control the peripheral circuit, wherein the programming operation comprises a first programming operation and a second programming operation, the first programming operation comprises a programming pulse application step of applying a fixed programming voltage having a predetermined voltage level to a selected physical word line only once and does not comprise a verify step, and the second programming operation comprises a plurality of programming loops, each programming loop comprising a programming voltage application step of applying a programming voltage to a physical word line to which selected memory cells are commonly connected and a verify step of verifying a target programmed state of the selected memory cells, and wherein a level of the fixed programming voltage is greater than a voltage applied to the physical word line in a first programming loop among the plurality of programming loops by an offset voltage. The plurality of pages are commonly connected to any of a plurality of the physical word lines. Each of the physical word lines comprises a plurality of logical word lines connected to the plurality of pages, respectively. The offset voltage has different voltage levels according to locations of the physical word lines. A magnitude of a pass voltage applied to unselected pages among the plurality of pages during the first programming operation and a magnitude of a pass voltage applied to unselected pages among the plurality of pages during the second programming operation have different voltage levels. The control logic controls a time of applying a programming voltage in the first programming operation and a time of applying the programming voltage in the second programming operation differently. a peripheral circuit configured to receive one of a plurality of logical page data from the memory controller in response to the program command, perform a first program operation on a selected one of the plurality of physical pages using the one of the plurality of logical page data, receive remaining ones of the plurality of logical page data from the memory controller after the first program operation, and perform a second program operation on the selected physical page using the remaining ones of the plurality of logical page data, wherein the first program operation and the second program operation are operations to store the data into selected memory cells selected from the plurality of memory cells; and a program operation controller configured to control the first program operation and the second program operation, wherein the first program operation includes a program pulse application step of applying a fixed program voltage to a word line to which the selected memory cells are commonly connected only once and does not include a verify step, and wherein the second program operation includes a plurality of program loops, each program loop including a program voltage application step of applying a program voltage to the word line and a verify step of verifying a target program state of the selected memory cells, and wherein a level of the fixed program voltage is greater than a voltage applied to the word line in a first program loop among the plurality of program loops by an offset voltage.

21. The memory device of claim 20, wherein, the first program operation is an operation to program a threshold voltage of the selected memory cells to correspond to any one of an erased state or an intermediate state.

22. The memory device of claim 21, wherein, a number of target program states of memory cells among the plurality of selected memory cells to be programmed to the erased state and a number of target program states of memory cells to be programmed to the intermediate state are the same.

23. The memory device of claim 20, wherein, the offset voltage has different voltage levels according to positions of the word line.

24. The memory device of claim 20, wherein, a pass voltage applied to unselected word lines among the plurality of memory cells during the first program operation and a pass voltage applied to the unselected word lines among the plurality of memory cells during the second program operation have different voltage levels.

25. The memory device of claim 24, wherein, the program operation controller applies pass voltages having different voltage levels to unselected word lines adjacent to a selected word line and remaining unselected word lines among the unselected word lines.

26. The memory device of claim 20, wherein, the program operation controller controls times of applying the fixed program voltage in the first program operation and times of applying the program voltage in the second program operation differently. the first program operation is an operation to program a threshold voltage of the selected memory cells to correspond to any one of an erased state or an intermediate state. a number of target program states of memory cells among the plurality of selected memory cells to be programmed to the erased state and a number of target program states of memory cells to be programmed to the intermediate state are the same. the offset voltage has different voltage levels according to positions of the word line. a pass voltage applied to unselected word lines among the plurality of memory cells during the first program operation and a pass voltage applied to the unselected word lines among the plurality of memory cells during the second program operation have different voltage levels. the program operation controller applies pass voltages having different voltage levels to unselected word lines adjacent to a selected word line and remaining unselected word lines among the unselected word lines. the program operation controller controls times of applying the fixed program voltage in the first program operation and times of applying the program voltage in the second program operation differently.

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