Electronic packaging component and its carrier structure

Abstract

The present invention discloses an electronic packaging component and its carrier structure. The carrier structure includes a chip seat, a ground frame, a pin group, and a ground wing portion. The ground frame surrounds the chip seat. The pin group includes a plurality of pins spaced apart from each other, and the plurality of pins radially extend outwardly and are disposed around the ground frame. The ground wing portion is connected to the ground frame and is located in the space below the pin group. The ground wing portion includes an extending portion and a pin portion. The extending portion extends away from the chip seat, and the position of the top end of the extending portion is higher than the position of a bottom surface of the chip seat. The carrier structure and the electronic packaging component applying the same according to the embodiments of the present invention can improve the signal transmission quality and can improve the power integrity.

Description

Technical Field

[0001] The present invention relates to an electronic packaging component and its carrier structure, in particular to an electronic packaging component and its carrier structure applicable to the transmission of high-frequency signals. Background Art

[0002] In the existing packaging technology, a chip is usually disposed on a die paddle of a lead frame, and then through wire bonding technology, multiple pads on the chip are respectively connected to multiple signal pins and multiple power pins of the lead frame. Then, a molding compound is used to encapsulate the chip, multiple leads, and the lead frame together to form an electronic packaging structure, such as a Quad Flat Package (QFP) structure.

[0003] However, when the electronic packaging structure is assembled onto a circuit board and operates in cooperation with the circuit board, the area (hereinafter referred to as the loop cross-sectional area) enclosed by the leads and pins used to transmit signals or power and the current path formed by the grounded die paddle and leads is positively correlated with the magnitude of the parasitic inductance. That is, when the loop cross-sectional area is larger, the parasitic inductance is larger, and excessive parasitic inductance will cause signal impedance mismatch or power noise and reduce power integrity. Therefore, how to reduce parasitic inductance and power noise and improve power integrity remains one of the problems to be solved by those skilled in the art. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide an electronic packaging component and its carrier structure to improve power integrity when the electronic packaging component operates.

[0005] To solve the above technical problem, one of the technical solutions adopted by the present invention is to provide a carrier structure, which includes a chip seat, a grounding frame, a pin group, and a grounding wing portion. The grounding frame surrounds the chip seat. The pin group includes multiple pins arranged at intervals, and the multiple pins radially extend outward and are disposed around the grounding frame. The grounding wing portion is connected to the grounding frame and is located in the space below the pin group. The grounding wing portion includes an extending portion and a pin portion. The extending portion extends in a direction away from the chip seat, and the position of the top end of the extending portion is higher than the position of a bottom surface of the chip seat.

[0006] Furthermore, a part of the pins straddle above the grounding wing portion, and another part of the pins do not overlap with the grounding wing portion in a vertical direction.

[0007] Further, each pin has a body portion and a bent portion connected to the body portion, wherein a shortest vertical distance between the body portion of a pin straddling over the grounding wing portion and an extension portion of the grounding wing portion is less than a pitch between two adjacent pins.

[0008] Further, each pin has a body portion and a bent portion connected to the body portion, wherein a maximum horizontal distance between the bent portion of a pin straddling over the grounding wing portion and a pin portion is less than a pitch between two adjacent pins.

[0009] Further, the carrier structure further includes another grounding wing portion, and the two grounding wing portions are respectively located on different sides of the grounding frame.

[0010] Further, the carrier structure further includes another grounding wing portion, and the two grounding wing portions are located on the same side of the grounding frame and are separated from each other.

[0011] Further, the grounding wing portion extends outwardly centered on the grounding frame and completely surrounds the grounding frame.

[0012] Further, the grounding frame includes a frame body, at least one first connecting member, and at least one second connecting member. At least one first connecting member extends downward from the frame body to the chip socket, and at least one second connecting member extends upward from the frame body to the grounding wing portion.

[0013] Further, a maximum height difference between the extension portion and the bottom surface of the chip socket is greater than a shortest vertical distance between the extension portion and one of the pins.

[0014] To solve the above technical problems, another technical solution adopted by the present invention is to provide an electronic packaging component, which includes: a carrier structure, a chip, a plurality of first wires, a plurality of second wires, and a molding layer. The carrier structure includes a chip socket, a grounding frame, a pin group, and a grounding wing portion. The grounding frame surrounds the chip socket. The pin group includes a plurality of pins arranged at intervals, and the plurality of pins extend radially outward and are arranged around the grounding frame. The grounding wing portion is connected to the grounding frame and is located in the space below the pin group. The grounding wing portion includes an extension portion and a pin portion. The extension portion extends away from the chip socket, and a position where the top end of the extension portion is located is higher than a position where the bottom surface of the chip socket is located. The chip is disposed on the chip socket of the carrier structure. The plurality of first wires are connected to the chip and the grounding frame, and the plurality of second wires are connected to the chip and are respectively connected to the plurality of pins. The molding layer covers the chip, the plurality of first wires, and the plurality of second wires and partially covers the carrier structure. The pin portion of the grounding wing portion is not covered by the molding layer and is exposed outside the molding layer.

[0015] Furthermore, each pin has a main body portion and a bent portion connected to the main body portion, and the encapsulation layer covers the main body portion of each pin but does not cover the bent portion.

[0016] Furthermore, the bottom surface of the chip socket is exposed on one surface of the encapsulation layer.

[0017] One of the beneficial effects of the present invention is that the electronic packaging component and its carrier structure provided by the embodiments of the present invention reduce the cross-sectional area of the loop surrounded by the current path and improve the power integrity by means of "the grounding wing is connected to the grounding frame and is located in the space below the pin group, wherein the grounding wing has an extending portion and a pin portion, and the position where the top end of the extending portion is located is higher than the position of the bottom surface of the chip socket".

[0018] To enable a further understanding of the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the provided drawings are only for reference and illustration and are not used to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a top view schematic diagram of the carrier structure of the first embodiment of the present invention.

[0020] Figure 2 For Figure 1 is a three-dimensional schematic diagram of the carrier structure omitting the pin group.

[0021] Figure 3 For Figure 1 is a partial cross-sectional schematic diagram along line III-III in

[0022] Figure 4 It is a top view schematic diagram of the carrier structure of the second embodiment of the present invention.

[0023] Figure 5 It is a top view schematic diagram of the carrier structure of the third embodiment of the present invention.

[0024] Figure 6 It is a three-dimensional schematic diagram of the electronic packaging component according to the embodiment of the present invention.

[0025] Figure 7 For Figure 6 is a three-dimensional schematic diagram of the electronic packaging component from another angle.

[0026] Figure 8 For Figure 6 is a partial cross-sectional schematic diagram of the electronic packaging component.

[0027] Figure 9 For Figure 6 is a partial cross-sectional schematic diagram of the electronic packaging component assembled on a circuit board.

[0028] Figure 10 A partial cross-sectional schematic view of an electronic packaging component according to another embodiment of the present invention.

[0029] Figure 11 A partial cross-sectional schematic view of an electronic packaging component according to yet another embodiment of the present invention. Detailed implementation manners

[0030] The following are specific examples to illustrate the implementation manners of the present invention regarding "electronic packaging components and their carrier structures". Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. Additionally, the drawings of the present invention are only simple schematic illustrations and are not drawn according to actual dimensions, hereby stating in advance. The following implementation manners will further detail the related technical content of the present invention, but the disclosed content is not intended to limit the protection scope of the present invention.

[0031] Please refer to Figure 1 and Figure 2 , Figure 1 A top view schematic of the carrier structure according to the first embodiment of the present invention. Figure 2 is Figure 1 A three-dimensional schematic of the carrier structure of

[0032] As Figure 1 shown, the carrier structure 1 of the embodiment of the present invention includes a chip seat 10, a grounding frame 11, a pin group 12, and at least one grounding wing portion 13.

[0033] In this embodiment, the chip seat 10 is used to carry a chip and has a carrying surface 10a and a bottom surface 10b opposite to the carrying surface 10a. The grounding frame 11 surrounds and connects to the chip seat 10. As Figure 1 and Figure 2 shown, the grounding frame 11 includes a frame body 110, at least one first connecting member 111 ( Figure 2 shows multiple) and at least one second connecting member 112 ( Figure 2 shows multiple).

[0034] The frame body 110 is annular and has a wire bonding surface 110s. And the chip seat 10 is located in the central area defined by the frame body 110. However, please refer to Figure 2, in this embodiment, there is a height difference between the chip socket 10 and the frame 110. That is to say, the position of the wire bonding surface 110s of the frame 110 is higher than the position of the bearing surface 10a of the chip socket 10.

[0035] In addition, as Figure 2 shown, the first connecting member 111 and the second connecting member 112 are respectively connected to the inner edge and the outer edge of the frame 110. The first connecting member 111 is connected between the chip socket 10 and the frame 110. Since there is a height difference between the chip socket 10 and the grounding frame 11 in this embodiment, the first connecting member 111 extends downward from the inner edge of the frame 110 to the edge of the chip socket 10. The second connecting member 112 is connected between the frame 110 and the grounding wing 13, that is, it extends from the outer edge of the frame 110 to the grounding wing 13.

[0036] Please refer to Figure 1 again. The carrier structure 1 of this embodiment further includes a plurality of connecting bars 14, and the plurality of connecting bars 14 respectively extend outward from the four corners of the grounding frame 11, but the present invention is not limited thereto.

[0037] As Figure 1 shown, the pin group 12 includes a plurality of pins 120 that are separated from each other, and the plurality of pins 120 extend radially from the inside to the outside. It should be noted that the plurality of pins 120 are arranged around the grounding frame 11 but are not physically connected to the grounding frame 11. In addition, the plurality of pins 120 can be arranged on different sides of the chip socket 10 (or the grounding frame 11) to respectively transmit power or different signals. For example, the plurality of pins 120 can be designated as clock signal pins, address signal pins, command signal pins, data signal pins, input / output power (IO power) pins, core power pins, etc. according to actual needs.

[0038] Please refer to Figure 3 , Figure 3 is Figure 1 a partial cross-sectional schematic view along line III-III in Figure 3 . Specifically, each pin 120 has a main body portion 120a and a bent portion 120b connected to the main body portion 120a. AsFigure 1 As shown, there is a spacing d1 between the bent portions 120b of two adjacent pins 120, which is approximately 100 μm.

[0039] Please refer to Figures 1 to 3 , the ground wing 13 is connected to the ground frame 11 and is located in the space below the pin group 12. That is, the ground wing 13 is disposed below the plurality of pins 120 to shield these pins 120. As Figure 2 and Figure 3 shown, the ground wing 13 includes an extension portion 130 and a pin portion 131. The extension portion 130 extends away from the chip socket 10, and there is a height difference between the extension portion 130 and the chip socket 10.

[0040] Specifically, the position of the top end of the extension portion 130 is higher than the position of the bottom surface 10b of the chip socket 10. In a preferred embodiment, a maximum height difference H1 between the extension portion 130 and the bottom surface 10b of the chip socket 10 is greater than the shortest vertical distance H2 between the extension portion 130 and one of the pins 120. In addition, the position of the bottom end of the extension portion 130 is at the same height as the position of the bottom surface 10b of the chip socket 10. In this embodiment, the extension portion 130 extends away from the chip socket 10 along a horizontal direction, but the present invention is not limited thereto.

[0041] In other embodiments, the extension portion 130 may have a stepped structure, an inclined portion, or a combination thereof. As long as the position of the top end of the extension portion 130 is higher than the position of the bottom surface 10b of the chip socket 10, the present invention does not limit the shape of the extension portion 130. Thus, the ground wing 13 can reduce the cross-sectional area of the loop surrounded by the current path, thereby reducing the parasitic inductance. The effects generated by the ground wing 13 will be described in detail later.

[0042] In addition, the ground wing 13 is connected to the second connecting member 112 of the ground frame 11. As Figure 3 shown, the extension portion 130 of the ground wing 13 is connected to the frame body 110 through the second connecting member 112. In this embodiment, the second connecting member 112 extends upward from the outer edge of the frame body 110 to the extension portion 130, but the present invention is not limited thereto.

[0043] In another embodiment, when the position of the extension portion 130 is higher than the position of the chip socket 10 but is flush with the frame body 110 or lower than the position of the frame body 110, the second connecting member 112 may extend horizontally or downward from the outer edge of the frame body 110 to the extension portion 130 of the ground wing 13. However, as long as the ground wing 13 can be connected to the ground frame 11, the present invention does not limit the shape of the second connecting member 112.

[0044] As shown Figure 3 in the figure, at least one pin 120 straddles above the grounding wing 13 and overlaps with the grounding wing 13 in the vertical direction. Please refer to Figure 1 and Figure 3 . In this embodiment, for one of the pins 120 straddling above the grounding wing 13, a shortest vertical distance H2 between the main body portion 120a and the extension portion 130 of the grounding wing 13 is less than the pitch d1 between two adjacent pins 120. For example, the pitch d1 between two adjacent pins 120 is 100 μm, and the vertical distance H2 between the main body portion 120a and the grounding wing 13 is less than 100 μm, preferably less than 80 μm.

[0045] It should be noted first that in the existing electronic packaging structure, the pitch between multiple signal / power pins arranged side by side is too small, and there is no grounding plane near these pins to provide shielding, resulting in serious crosstalk between multiple pins (including signal pins and power pins) during signal transmission, which affects the signal transmission quality. If multiple grounding pins are added to reduce the crosstalk between pins, not only will the total number of pins increase, but also the overall volume of the electronic packaging structure will increase.

[0046] However, in the embodiment of the present invention, since the grounding wing 13 is closer to the pin 120, when the pin 120 transmits a signal or power, the signals or powers transmitted by two adjacent pins 120 are less likely to be coupled with each other to generate mutual interference. That is to say, the grounding wing 13 can be used to provide shielding for these pins 120. Compared with the existing electronic packaging structure, in the carrier structure 1 of the embodiment of the present invention, the grounding wing 13 can suppress signal mutual interference and improve signal transmission quality.

[0047] In addition, as Figure 3 shown, a maximum horizontal distance D1 between the bent portion 120b of the pin 120 straddling above the grounding wing 13 and the pin portion 131 is also less than the pitch d1 between two adjacent pins 120. Thus, the grounding wing 13 can provide better shielding for the pin 120 and further reduce signal mutual interference. It should be noted that the present invention does not limit that the maximum horizontal distance D1 between the bent portion 120b of the pin 120 straddling above the grounding wing 13 and the pin portion 131 must be less than the pitch d1 between two adjacent pins 120. That is to say, in the present invention, as long as at least one of the aforementioned shortest vertical distance H2 or maximum horizontal distance D1 is less than the pitch d1 between two adjacent pins 120, the signal transmission quality can be improved.

[0048] It should be noted that the grounding wing portion 13 can be selectively disposed under a part of the pins 120, for example, only under the pins 120 that most need to be shielded. For example, the grounding wing portion 13 can be disposed only under the pins 120 for transmitting high-speed signals, and there is no need to dispose the grounding wing portion 13 under all the pins 120.

[0049] Please refer to Figure 1 and Figure 2 , in this embodiment, the carrier structure 1 includes two grounding wing portions 13, and the two grounding wing portions 13 are respectively located on different sides of the grounding frame 11. As Figure 1 shown, the two grounding wing portions 13 are respectively connected to different side edges of the grounding frame 11. Accordingly, a part of the pins 120 straddle over the grounding wing portion 13, and another part of the pins 120 do not overlap with the grounding wing portion 13 in the vertical direction.

[0050] In addition, the number of pins 120 shielded by each grounding wing portion 13 is not limited. Please refer to Figure 4 , which is a top view schematic diagram of the carrier structure of the second embodiment of the present invention. In Figure 4 the embodiment, the two grounding wing portions 13A and 13B of the carrier structure 1a are located on the same side of the grounding frame 11, and the two grounding wing portions 13A and 13B are separated from each other. In addition, the two grounding wing portions 13A and 13B also have different sizes, and can be respectively used to shield different numbers of pins 120.

[0051] However, the present invention is not limited to the foregoing embodiments. Please refer to Figure 5 , which is a top view schematic diagram of the carrier structure of the third embodiment of the present invention. In Figure 5 the embodiment, all the pins 120 need to be shielded, and the carrier structure 1b can also include four grounding wing portions 13, which are respectively connected to four side edges of the grounding frame 11. In another embodiment, the grounding wing portion 13 can also be integrally formed with four connecting bars 14. That is to say, the grounding wing portion 13 can extend outward with the grounding frame 11 as the center and completely surround the grounding frame 11. In this way, the grounding wing portion 13 can shield all the pins 120 of the pin group 12, and can further reduce signal interference and improve signal transmission quality.

[0052] Please refer to Figures 6 to 8 . Figure 6 is a three-dimensional schematic diagram of the electronic packaging component of the embodiment of the present invention. Figure 7 is Figure 6 a three-dimensional schematic diagram of the electronic packaging component from another angle. Figure 8 is Figure 6 a partial cross-sectional schematic diagram of the electronic packaging component.

[0053] The electronic packaging component M1 according to an embodiment of the present invention includes a carrier structure 1, a chip 2, a plurality of first wires 3, a plurality of second wires 4, and a molding layer 5. It should be noted first that the carrier structure 1 can also be replaced with the carrier structures 1a or 1b of the foregoing second or third embodiments. In this embodiment, the carrier structure 1 shown in Figure 1 is taken as an example for illustration, and the details of the carrier structure 1 will not be elaborated here.

[0054] Please first refer to Figure 8 . The chip 2 is, for example, a system on chip (SoC). In addition, the chip 2 according to an embodiment of the present invention is suitable for transmitting signals at a high speed (e.g., at a rate of more than 1800 MHz). The chip 2 usually has a plurality of pads, and these pads may include signal / power pads 21 and ground pads 20. The chip 2 is disposed on the chip seat 10 of the carrier structure 1, and through a plurality of first wires 3 and a plurality of second wires 4, each pad 20, 21 of the chip 2 is electrically connected to a corresponding pin 120.

[0055] Please refer to Figure 8 . The plurality of first wires 3 are connected between the chip 2 and the ground frame 11. Further, the ground pads 20 of the chip 2 are electrically connected to the ground frame 11 through the corresponding first wires 3. Each first wire 3 is connected to the bonding surface 110s of the ground frame 11. In addition, the plurality of second wires 4 are connected to the chip 2 and are respectively connected to a plurality of pins 120. As shown in Figure 8 , the signal / power pads 21 of the chip 2 are connected to the corresponding pins 120 through the corresponding second wires 4.

[0056] Please refer to Figures 6 to 8 . The molding layer 5 covers the chip 2, the plurality of first wires 3, and the plurality of second wires 4, and the molding layer 5 partially covers the carrier structure 1. Specifically, the molding layer 5 covers the main body portion 120a of each pin 120 and does not cover the bent portion 120b. In addition, the molding layer 5 covers the extended portion 130 of the ground wing 13 and exposes the pin portion 131 of the ground wing 13. Overall, the pin portion 131 of the ground wing 13 and the bent portion 120b of each pin 120 are not covered by the molding layer 5 and are exposed outside the molding layer 5. In addition, as shown in Figure 7 , the bottom surface 10b of the chip seat 10 is also exposed on one surface (bottom surface) of the molding layer 5. Accordingly, the electronic packaging component M1 can be assembled on a circuit board and operate in cooperation with other electronic components on the circuit board.

[0057] Please refer to Figure 9 . Figure 9 For Figure 6Partial cross-sectional schematic diagram of an electronic packaging component assembled on a circuit board. It should be noted in advance that the circuit board P1 already has multiple lines (not shown in the figure) so that the electronic packaging component M1 can be electrically connected to other electronic components (not shown in the figure). The aforementioned electronic components are, for example, memory components, passive components, or discrete components, etc., and the present invention is not limited thereto. Memory components are, for example, dynamic random access memory (DRAM), flash memory, etc. Passive components are, for example, resistors, capacitors, or inductors, and discrete components are, for example, transistors or diodes, but the present invention is not limited thereto.

[0058] That is to say, when the electronic packaging component M1 is assembled on the circuit board P1, the electronic packaging component M1 and the electronic component (not shown in the figure) can be electrically connected through the circuit board P1 and transmit signals to each other. In one embodiment, the signal transmission rate between the electronic packaging component M1 and the electronic component is relatively high. For example, signals are transmitted at a rate exceeding 1800 MHz.

[0059] The circuit board P1 further includes a first ground pad P11 provided on the assembly side, at least one second ground pad P12, and at least one signal / power pad P13. As Figure 9 shown, when the electronic packaging component M1 is disposed on the circuit board P1, the bottom surface 10b of the chip carrier 10 will align with the first ground pad P11, and the pin portion 131 of the ground wing 13 will align with the second ground pad P12. In addition, the bent portion 120b of each pin 120 will align with the corresponding signal / power pad P13.

[0060] As Figure 9 shown, when the electronic packaging component M1 operates, the cross-sectional area of the loop surrounded by the current path formed by the second wire 4, the pin 120, the ground wing 13, the ground frame 11, and the first wire 3 can be reduced. Reducing the cross-sectional area of the loop can reduce the parasitic inductance, and further reduce the power supply noise and the factors causing signal impedance mismatch, and can improve the power integrity. That is to say, compared with the existing lead frame, the ground wing 13 of the carrier structure 1 in the embodiment of the present invention can provide a ground path closer to the pin 120, thereby reducing the cross-sectional area of the loop.

[0061] As described above, the shape of the ground wing 13 is not limited to Figure 9 the embodiment shown. Please refer to Figure 10 , which is a partial cross-sectional schematic diagram of an electronic packaging component of another embodiment of the present invention. The electronic packaging component M2 in this embodiment and Figure 8 the electronic packaging component M1 of the same component have the same reference numerals, and the same parts will not be described again.

[0062] This embodiment and Figure 8The difference from the illustrated embodiment is that the grounding frame 11 of this embodiment does not have the second connecting member 112, and the extending portion 130' of the grounding wing 13 extends directly from the frame body 110 of the grounding frame 11 towards the main body portion 120a of the pin 120, and has an inclined surface 130's.

[0063] In this embodiment, the position where the top end of the extending portion 130' is located is higher than the position of the bottom surface 10b of the chip socket 10, which can reduce the cross-sectional area of the loop, thereby reducing the parasitic inductance. In one embodiment, the maximum height difference H1 between the extending portion 130' and the bottom surface 10b of the chip socket 10 is greater than the shortest vertical distance H2 between the extending portion 130' and the pin 120.

[0064] In addition, the shortest vertical distance H2 between the extending portion 130 and one of the pins 120 is less than the pitch d1 between two adjacent pins 120. Thus, the grounding wing 13 of this embodiment can shield the pins 120, reducing the signal interference between two adjacent pins 120. Further, the maximum horizontal distance D1 between the bent portion 120b of the pin 120 straddling above the grounding wing 13 and the pin portion 131 can be less than the pitch d1 between two adjacent pins 120, but the present invention is not limited thereto.

[0065] Please refer to Figure 11 , which is a partial cross-sectional schematic view of an electronic packaging component according to another embodiment of the present invention. The electronic packaging component M3 of this embodiment has the same reference numerals as the components of Figure 8 the electronic packaging component M1 that are the same, and the same parts will not be described again.

[0066] The difference between this embodiment and Figure 8 the illustrated embodiment is that the extending portion 130” of the grounding wing 13 of this embodiment includes a stepped structure 130S. Accordingly, the top surface of the extending portion 130” is not a flat surface. Specifically, the extending portion 130” includes a lower-order portion 130a farther from the pin 120 and a higher-order portion 130b closer to the pin 120, and there is a height step between the top surface of the higher-order portion 130b and the top surface of the lower-order portion 130a, forming the stepped structure 130S. In this embodiment, the lower-order portion 130a is connected to the second connecting member 112 of the grounding frame 11, and the higher-order portion 130b is connected to the pin portion 131, but the present invention is not limited thereto. In other embodiments, it may also be that the higher-order portion 130b is connected to the second connecting member 112 of the grounding frame 11, and the lower-order portion 130b is connected to the pin portion 131.

[0067] In this embodiment, the position of the top end of the extension portion 130" is higher than the position of the bottom surface 10b of the chip carrier 10, which can reduce the cross-sectional area of the loop, thereby reducing the parasitic inductance. In a preferred embodiment, the maximum height difference H1 between the extension portion 130" and the bottom surface 10b of the chip carrier 10 is greater than the shortest vertical distance H2 between the extension portion 130 and the pin 120.

[0068] Similar to the previous embodiment, the shortest vertical distance H2 between the extension portion 130" and one of the pins 120 is less than the pitch d1 between two adjacent pins 120, which can shield the pins 120 by the ground wing 13, and further reduce the signal interference between two adjacent pins 120.

[0069] After actual simulation tests, compared with the electronic packaging structure using the existing lead frame (without the ground wing), when the electronic packaging components M1 to M3 of the embodiment of the present invention (the carrier structure 1 thereof includes the ground wing 13) are arranged on the circuit board P1 for operation, the signal interference between the pins 120 can be significantly improved. In addition, the variation degrees of the ground bounce and the power bounce are significantly reduced. That is to say, by using the carrier structures 1 to 1b of the embodiment of the present invention, the power noise and the ground noise can be reduced, thereby improving the power integrity. Thus, the electronic packaging components M1 to M3 also have excellent performance when transmitting high-speed signals.

[0070] In summary, one of the beneficial effects of the present invention is that the electronic packaging components M1 to M3 and their carrier structures 1 to 1b provided by the embodiments of the present invention, by means of the technical means that "the ground wing 13 is connected to the ground frame 11 and is located in the space below the pin group 12, wherein the ground wing 13 has extension portions 130, 130', 130" and a pin portion 131, and the extension portions 130, 130', 130" extend away from the chip carrier 10, and the position of the top end of the extension portions 130, 130', 130" is higher than the position of a bottom surface 10b of the chip carrier 10", can reduce the cross-sectional area of the loop surrounded by the current path. Thus, the path impedance of power transmission, the power noise and the ground noise can be reduced, thereby improving the power integrity.

[0071] On the other hand, the shortest vertical distance H2 between the extending portions 130, 130', 130" of the grounding wing portion 13 of the present embodiment and the main body portion 120a of the pin 120, or the maximum horizontal distance D1 between the pin portion 131 of the grounding wing portion 13 and the bent portion 120b of the pin 120 is less than the pitch d1 between two adjacent pins 120, which can provide preferable shielding for the pin 120. Thus, without additionally providing a grounding pin, signal mutual interference can be reduced and the signal transmission quality can be improved.

[0072] The content disclosed above is only a preferred and feasible embodiment of the present invention, and does not limit the protection scope of the claims of the present invention. Therefore, all equivalent technical changes made by using the content of the specification and drawings of the present invention are included in the protection scope of the claims of the present invention.

Claims

1. A carrier structure, characterized in that: The carrier structure comprises: a chip holder; a ground frame surrounding the chip base; a pin assembly comprising a plurality of pins spaced apart from each other, each pin having a main body and a bent portion connected to the main body, wherein the plurality of pins extend radially outward and are arranged around the ground frame; and a grounding wing connected to the grounding frame and located in the space below the pin group, wherein the grounding wing includes an extension portion and a pin portion, the extension portion extends in a direction away from the chip holder, the top of the extension portion is located higher than the position of a bottom surface of the chip holder, and a shortest vertical distance between the main body of one of the pins spanning above the grounding wing and the extension portion of the grounding wing is less than the spacing between two adjacent pins.

2. The carrier structure according to claim 1, characterized in that A portion of the pins is arranged above the grounding wing, and another portion of the pins does not overlap with the grounding wing in a vertical direction.

3. The carrier structure according to claim 1, characterized in that Each of the pins has a main body and a bent portion connected to the main body, wherein a maximum horizontal distance between the bent portion of one of the pins spanning above the ground wing and the pin portion is smaller than the spacing between two adjacent pins.

4. The carrier structure according to claim 1, characterized in that The carrier structure further includes another grounding wing, and the two grounding wings are respectively located on different sides of the grounding frame.

5. The carrier structure according to claim 1, characterized in that The carrier structure further includes another grounding wing, and the two grounding wings are located on the same side of the grounding frame and are separated from each other.

6. The carrier structure according to claim 1, characterized in that The grounding wing extends outward with the grounding frame as the center and completely surrounds the grounding frame.

7. The carrier structure according to claim 1, characterized in that The ground frame includes a frame body, at least one first connecting member and at least one second connecting member. The at least one first connecting member extends downward from the frame body to the chip seat, and the at least one second connecting member extends upward from the frame body to the ground wing.

8. The carrier structure according to claim 1, characterized in that A maximum height difference between the extending portion and the bottom surface of the chip seat is greater than a shortest vertical distance between the extending portion and one of the pins.

9. An electronic packaging component, characterized in that: The electronic packaging assembly comprises: A carrier structure comprising: a chip holder; a ground frame surrounding the chip base; a pin assembly comprising a plurality of pins spaced apart from each other, each pin having a main body and a bent portion connected to the main body, wherein the plurality of pins extend outward and are disposed around the ground frame; and a grounding wing connected to the grounding frame and located in the space below the pin assembly, wherein the grounding wing has an extension portion and a pin portion, the extension portion extending in a direction away from the chip holder, a top end of the extension portion being located higher than a bottom surface of the chip holder, and a vertical distance between the main portion of one of the pins spanning above the grounding wing and the extension portion of the grounding wing being less than a spacing between two adjacent pins; a chip disposed on the chip seat of the carrier structure; a plurality of first conductive lines connected to the chip and the ground frame; a plurality of second wires connected to the chip and respectively connected to the plurality of pins; and A molding layer covers the chip, the plurality of first conductive lines, and the plurality of second conductive lines and partially covers the carrier structure, wherein the pin portion of the ground wing is not covered by the molding layer and is exposed outside the molding layer.

10. The electronic packaging assembly according to claim 9, wherein: A portion of the pins is arranged above the grounding wing, and another portion of the pins does not overlap with the grounding wing in a vertical direction.

11. The electronic packaging assembly according to claim 9, wherein: Each of the pins has a main body and a bent portion connected to the main body, wherein a maximum horizontal distance between the bent portion of one of the pins spanning above the ground wing and the pin portion is smaller than the spacing between two adjacent pins.

12. The electronic packaging assembly according to claim 9, wherein: The carrier structure further includes another grounding wing, and the two grounding wings are respectively located on two different sides of the grounding frame.

13. The electronic packaging assembly according to claim 9, wherein: The carrier structure further includes another grounding wing, and the two grounding wings are located on the same side of the grounding frame and are separated from each other.

14. The electronic packaging assembly according to claim 9, wherein: The grounding wing extends outwardly with the grounding frame as the center and completely surrounds the grounding frame.

15. The electronic packaging assembly according to claim 9, wherein: A maximum height difference between the extending portion and the bottom surface of the chip seat is greater than a shortest vertical distance between the extending portion and one of the pins.

16. The electronic packaging assembly according to claim 9, wherein: Each of the pins has a main body portion and a bending portion connected to the main body portion. The molding layer covers the main body portion of each of the pins but does not cover the bending portion.

17. The electronic packaging assembly according to claim 9, wherein: The bottom surface of the chip seat is exposed on one surface of the molding layer.

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