Semiconductor structure and method for forming the same

Abstract

The present invention provides a semiconductor structure and a method for forming the same, comprising: forming an active layer on a substrate, the substrate having adjacent word line predetermined regions and selection gate predetermined regions; forming a hard mask layer including a third hard mask layer stacked on the active layer; patterning the third hard mask layer to form a third hard mask layer, wherein there is a first spacing between two adjacent third hard masks in the word line predetermined region closest to the selection gate predetermined region, the first spacing being smaller than the second spacing between any other two; forming a spacer on the sidewall of the third hard mask layer, wherein two spacers on the opposite sidewalls of the two adjacent third hard masks are combined into a combined spacer; forming a patterned mask structure in the selection gate predetermined region; transferring the pattern of the spacer and the patterned mask structure to the active layer to form a word line and a selection gate. The step of transferring the pattern of the spacer to the active layer comprises transferring the pattern of the combined spacer to the active layer to form a first word line closest to the selection gate.

Description

Technical Field

[0001] The present invention relates to a semiconductor technology, and in particular to a semiconductor structure of a flash memory device and a forming method thereof. Background Art

[0002] In recent years, due to its advantages of high density, low cost, rewritability and electrical erasability, flash memory has become the mainstream of non-volatile memory components and is widely used in various portable electronic products, such as notebook computers, digital walkmans, digital cameras, mobile phones, game consoles and other related portable electronic products. In order to increase the component density in flash memory devices and improve their overall performance, the current manufacturing technology of dynamic random access memory devices continues to strive towards miniaturization of component size.

[0003] However, as device dimensions continue to shrink, many challenges arise. For example, in semiconductor manufacturing processes, photolithography and etching processes are often used to form patterned mask layers used to define components in the active layer. However, when forming small-sized semiconductor structures, they are easily damaged or broken by surrounding structures, thus affecting subsequent electrical performance.

[0004] Although the existing flash memory forming methods generally meet the requirements, they are not satisfactory in all aspects. Therefore, there is still a need to improve the flash memory device forming method to overcome the problems caused by the reduction of component size, improve the process tolerance, and reduce the process cost. Summary of the invention

[0005] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising: forming an active layer on a substrate, wherein the substrate has a word line predetermined region and a selection gate predetermined region adjacent to each other; forming a hard mask stack on the active layer, wherein the hard mask stack includes a first hard mask layer, a second hard mask layer, and a third hard mask layer sequentially formed on the active layer; patterning the third hard mask layer to form a plurality of third hard masks in the selection gate predetermined region and the word line predetermined region, wherein a first spacing is provided between two adjacent third hard masks in the word line predetermined region closest to the selection gate predetermined region, and the first spacing is smaller than a second spacing between any other two of the third hard masks; forming The invention relates to a method for forming a plurality of spacers on the sidewalls of the third hard mask, wherein two spacers on the opposite sidewalls of the two adjacent third hard masks are merged into a combined spacer; removing the third hard mask; forming a patterned mask structure in a predetermined area for selecting a gate and covering the second hard mask layer and the spacers; and transferring the pattern of the spacer to the active layer to form a plurality of word lines in a predetermined area for selecting a gate, and transferring the pattern of the patterned mask structure to the active layer to form a selection gate in the predetermined area for selecting a gate, wherein the step of transferring the pattern of the spacer to the active layer includes transferring the pattern of the combined spacer to the active layer to form a first word line closest to the selection gate.

[0006] An embodiment of the present invention provides a semiconductor structure, comprising: a substrate; a plurality of word lines disposed on the substrate; a selection gate disposed on the substrate, wherein the width of a first word line closest to the selection gate among the word lines is greater than the width of any other word line; and a doped region disposed in the substrate between adjacent word lines and in the substrate between the word lines and the selection gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are only used for illustration. In fact, the size of the components may be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention.

[0008] Figures 1 to 16 FIG. 4 is a schematic cross-sectional view of various stages of forming a semiconductor structure according to an embodiment of the present invention.

[0009] Fig.17 FIG. 1 is a partial top view of a semiconductor structure according to an embodiment of the present invention.

[0010] Fig.18 FIG. 1 is a cross-sectional view of a semiconductor structure according to an embodiment of the present invention.

[0011] Explanation of symbols:

[0012] 10: semiconductor structure 110: doping region

[0013] 100: substrate 200: active layer

[0014] 200A: word line 900: mask structure

[0015] 200A1: first word line 900B: patterned mask structure

[0016] 200B: selection gate 910: dielectric layer

[0017] 300: first hard mask layer 910B: patterned dielectric layer

[0018] 300A, 300A1, 300B: first hard mask 920: sacrificial layer

[0019] 920B: Patterned sacrificial layer

[0020] 400: Second hard mask layer 1000: Hard mask stack

[0021] 400A, 400A1, 400B: second hard mask 1100B: patterned photoresist

[0022] A-A': section line (section)

[0023] 500: third hard mask layer R WL Word line reserved area

[0024] 500A: Third hard mask R SG :Select gate predetermined area

[0025] 510: Dielectric layer W S :spacing

[0026] 510A: Dielectric mask W SN :spacing

[0027] 520: Sacrificial layer W SW :spacing

[0028] 520A: Sacrificial Mask W S3 :spacing

[0029] 600: Anti-reflective coating W S3N :spacing

[0030] 600A: Patterned anti-reflective coating W S3W :spacing

[0031] 700A: Patterned Photoresist W WL :width

[0032] 800: spacer material layer W SWL :spacing

[0033] 800A: Spacer W WL1 :width

[0034] 800A1: Combined spacer W SG :width DETAILED DESCRIPTION

[0035] Various different embodiments or examples are provided below for implementing different elements of the provided semiconductor structure. When the description mentions that a first component is formed on a second component, it may include an embodiment in which the first and second components are directly in contact, and it may also include an embodiment in which an additional component is formed between the first and second components so that the first and second components are not in direct contact. In addition, embodiments of the present invention may use repeated component symbols in many examples. These repetitions are only for the purpose of simplicity and clarity, and do not represent a specific relationship between the various embodiments and / or configurations discussed.

[0036] In a NAND flash memory, a cell structure is defined by a self-aligned double patterning (SADP) process, and a select gate next to the cell structure is defined by a photoresist. In the prior art, the first array near the select gate is susceptible to plasma damage during the etching process due to the difference in the structural environment, and is damaged or disconnected, thereby affecting subsequent electrical performance. The above problem is not solved. The embodiment of the present invention reduces the spacing of the hard mask near the predetermined area of ​​the select gate, so that the two spacers in the spacing can be merged into a larger combined spacer to prevent the subsequent plasma damage during the etching process from affecting the electrical performance.

[0037] Figures 1 to 16 1 is a cross-sectional view of a semiconductor structure 10 at various stages according to an embodiment of the present invention. Figure 1 , an active layer 200 is formed on a substrate 100, a hard mask stack 1000 is formed on the active layer 200, an anti-reflection coating 600 is formed on the hard mask stack 1000, and a patterned photoresist 700A is formed on the anti-reflection coating 600. The hard mask stack 1000 includes a first hard mask layer 300, a second hard mask layer 400, and a third hard mask layer 500 sequentially formed on the active layer 200. In addition, a word line predetermined region R is provided on the substrate 100. WL and the selection gate predetermined region R SG , in order to distinguish the positions of the components formed subsequently.

[0038] In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. In other embodiments, the semiconductor substrate may be an elemental semiconductor, including germanium; a compound semiconductor, including gallium nitride (GaN), silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, etc. In other embodiments, the substrate 100 may also be a semiconductor on insulator (SOI) substrate, and the semiconductor on insulator substrate may include a base plate, a buried oxide layer disposed on the base plate, and a semiconductor layer disposed on the buried oxide layer.

[0039] In some embodiments, the active layer 200 may include a conductive material, a dielectric material, or a combination thereof. The conductive material may include doped polysilicon, a metal (e.g., tungsten), or a metal nitride (e.g., tungsten nitride), etc. The dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), tetraethoxysilane (TEOS), a low-k dielectric material, and / or other suitable dielectric materials, etc.

[0040] In an embodiment, the active layer 200 may include a tunneling oxide layer, a floating gate layer, a control gate layer, and an inter-gate dielectric layer (not shown). In order to clearly and concisely describe some embodiments of the present invention and highlight the technical features of the present invention, not all components in the active layer 200 are shown here.

[0041] In some embodiments, the first hard mask layer 300 and the second hard mask layer 400 are sequentially formed on the active layer 200. The first hard mask layer 300 includes an oxide or an oxynitride, such as tetraethylorthosilicate (TEOS) oxide or silicon oxynitride (SiON). In some embodiments, the second hard mask layer 400 includes a material having an etching selectivity relative to the underlying film layer, such as polysilicon. The formation of the first hard mask layer 300 and the second hard mask layer 400 is similar to the deposition process of the active layer 200, and will not be repeated here.

[0042] In some embodiments, the third hard mask layer 500 is formed on the second hard mask layer 400. The third hard mask layer 500 includes a dielectric layer 510 and a sacrificial layer 520 on the dielectric layer 510.

[0043] In some embodiments, the dielectric layer 510 may include a photoresist-like material, which may include a carbon-containing material or an oxygen-containing material, such as spin on carbon (SOC), carbon or tetraethoxysilane (TEOS) oxide, etc. The sacrificial layer 520 may include a nitride oxide, such as silicon oxynitride (SiON). The formation of the dielectric layer 510 and the sacrificial layer 520 in the third hard mask layer 500 is similar to the deposition process of the active layer 200, which will not be repeated here.

[0044] Since the dielectric layer 510 and the upper photoresist material have similar properties, the sacrificial layer 520 is disposed therein to serve as an anti-etching layer, that is, an etching stop layer.

[0045] It should be understood that some embodiments of the present invention utilize the difference in etching selectivity between the first hard mask layer 300, the second hard mask layer 400, and the third hard mask layer 500 to etch a specific film layer in each subsequent etching process (details will be discussed below). Therefore, the materials of each film layer in the hard mask stack 1000 mentioned here are only exemplary, and suitable mask materials can be matched according to process conditions, and the embodiments of the present invention are not limited thereto.

[0046] In some embodiments, an anti-reflective coating 600 is formed on the third hard mask layer 500. The anti-reflective coating 600 may include spin-on carbon (SOC), silicon oxynitride (SiON), other suitable anti-reflective materials, or combinations thereof.

[0047] In some embodiments, the anti-reflective coating 600 formed on the third hard mask layer 500 may include, for example, spin-on carbon (SOC), silicon oxynitride (SiON), other suitable anti-reflective materials, or a combination thereof. The formation of the anti-reflective coating 600 is similar to the deposition process of the active layer 200, which will not be described in detail herein.

[0048] The anti-reflection coating 600 can prevent the underlying film layer from reflecting during exposure, thereby facilitating the transfer of the pattern.

[0049] In some embodiments, a plurality of patterned photoresists 700A are formed on the anti-reflective coating 600 .

[0050] In this embodiment, the predetermined region R closest to the select gate SG The word line reserved area R WL There is a spacing W between two adjacent patterned photoresists 700A. SN . Word line reserved area R WL There is a spacing W between any other two patterned photoresists 700A in S. The closest word line predetermined area R WL The select gate predetermined region R SG There is a spacing W between two adjacent patterned photoresists 700A. SW .Depend on Figure 1 It can be seen that W SN <W SW And W SN <W S As can be seen from the following description, due to the spacing W SN Smaller, the subsequent spacer materials located here will merge to form a wider spacer.

[0051] Next, refer to Figure 2-Figure 3 , transferring the patterns of the plurality of patterned photoresists 700A to the anti-reflective coating layer 600 and the third hard mask layer 500 to form a plurality of patterned anti-reflective coating layers 600A and a plurality of third hard masks 500A, as shown in FIG. Figure 2 Then remove the patterned photoresist 700A and the patterned anti-reflection coating 600A to obtain Figure 3 In the above, transferring the patterns of the plurality of patterned photoresists 700A to the third hard mask layer 500 includes transferring the patterns of the plurality of patterned photoresists 700A to the dielectric layer 510 and the sacrificial layer 520 in the third hard mask layer 500 to form a plurality of dielectric masks 510A and a sacrificial mask 520A.

[0052] exist Figure 3 In the embodiment of the present invention, the spacing W of the third hard mask 500A is S3 , W S3N , W S3W Corresponding to the spacing W of the patterned photoresist 700A S , W SN , W SW . Where W S3N <W S3W And W S3N <W S3 As can be seen from the following description, due to the spacing W S3N The spacer material located here will merge to form a wider spacer. S3 With spacing W S3N The ratio is between 1.5 and less than 3. When the ratio is less than 1.5, two spacers cannot be combined into a combined spacer in the subsequent process, and when the ratio is greater than 3, a combined spacer having a width greater than that of other spacers cannot be defined in the subsequent process.

[0053] In some embodiments, the third hard mask 500A may also be referred to as a mandrel to facilitate the subsequent formation of spacers with a pitch smaller than the photolithography resolution on both sides.

[0054] In some embodiments, the removal of the patterned photoresist 700A and the patterned anti-reflective coating 600A may include a stripping process, an ash process, a suitable removal process, or a combination thereof.

[0055] Next, refer to Figure 4 , conformally depositing a spacer material layer 800 on the top and sidewalls of the third hard masks 500A and on the second hard mask layer 400. Specifically, depositing the spacer material layer 800 on the third hard mask layers 500 includes depositing on the sidewalls of the dielectric mask 510A in the third hard masks 500A and on the top and sidewalls of the sacrificial mask 520A.

[0056] In some embodiments, the deposition of the spacer material layer 800 includes a deposition process similar to that of the active layer 200 , which will not be described in detail herein. In another embodiment, the material of the spacer material layer 800 includes a dielectric material similar to that described above.

[0057] In this embodiment, the smaller spacing W between the third hard mask layers 500 corresponds to S3N In other words, in the select gate predetermined region closest to the word line predetermined region, there is no gap between the spacer material layers on the opposite sidewalls of two adjacent third hard mask layers 500 .

[0058] Next, refer to Figure 5 , the spacer material layer 800 is anisotropically etched until a portion of the top surface of the second hard mask layer 400 is exposed to form a plurality of spacers 800A. Specifically, the anisotropic etching of the spacer material layer 800 includes removing the spacer material layer 800 above the sacrificial mask 520A and on the sidewalls of the sacrificial mask 520A. In addition, the spacer material layer 800 is anisotropically etched until a portion of the top surface of the second hard mask layer 400 is exposed to form a plurality of spacers 800A. Specifically, the anisotropic etching of the spacer material layer 800 includes removing the spacer material layer 800 above the sacrificial mask 520A and on the sidewalls of the sacrificial mask 520A. S3N It should be noted that, for the sake of simpler description, unless otherwise specifically mentioned in the following, the spacer 800A includes the combined spacer 800A1.

[0059] In this embodiment, the top surface of each spacer 800A is flush with the interface between each dielectric shield 510A and the sacrificial shield 520A. In other embodiments, the top surface of each spacer 800A may be higher or lower than the interface (not shown) between each dielectric shield 510A and the sacrificial shield 520A.

[0060] In some embodiments, due to the influence of the etching process, the top of the combined spacer 800A1 has a V-shaped profile. Since the spacer material layer 800 is formed along the sidewalls of the third hard mask layer 500, the two sides of the combined spacer 800A1 have substantially straight sidewalls. The combined spacer 800A1 has a width greater than that of other spacers 800A, and the ratio thereof is approximately between greater than 1 and 2. By forming a combined spacer wider than other spacers, a larger critical dimension is provided when a select gate is subsequently defined to resist plasma damage.

[0061] In some embodiments, the anisotropic etching includes the etching process described above, which will not be described in detail herein.

[0062] Compared with the third hard mask consisting of only a dielectric mask, the third hard mask of this embodiment includes a dielectric mask and a sacrificial mask. The sacrificial mask can be used as an etch stop layer to prevent the previous step of removing the photoresist from affecting the dielectric layer and causing pattern distortion.

[0063] When the top surface of the spacer 800A is flush with the interface between each dielectric mask 510A and the sacrificial mask 520A, the sacrificial mask 520A can be completely exposed above the spacer 800A, so that the sacrificial mask 520A can be completely removed in a single step without affecting the dielectric mask 510A.

[0064] Next, refer to Figure 6-Figure 7 , remove the third hard mask 500A. Specifically, the sacrificial mask 520A and the dielectric mask 510A are removed in sequence. The removal of the sacrificial mask 520A includes an etching process similar to that described previously. The removal of the dielectric mask 510A includes an etching process similar to that described previously, a stripping process, an ashing process, a suitable removal process, or a combination thereof.

[0065] In this embodiment, the dielectric mask 510A and the sacrificial mask 520A have different material properties. For example, the former is a photoresist-like material, and the latter is a silicon rich material. Figure 5-Figure 7 In the embodiment of FIG. 5 , the sacrificial mask 520A may be removed first to expose the top surface of the dielectric mask 510A, and then the dielectric mask 510A may be removed to leave the spacers 800A, which will subsequently define the word lines.

[0066] Next, refer to Figure 8 , forming a mask structure 900 covering the second hard mask layer 400 and the spacer 800A, and selecting the gate predetermined region R SGAnother patterned photoresist 1100B is formed on the mask structure 900 in the third hard mask layer 500. In detail, the mask structure 900 includes a dielectric layer 910 and a sacrificial layer 920, which are formed and made of materials similar to the dielectric layer 510 and the sacrificial layer 520 in the third hard mask layer 500.

[0067] It should be noted that the height of the dielectric layer 910 is higher than the height of the spacer 800A to protect the first hard mask layer 300 from being damaged by etching. Specifically, the ratio of the height of the dielectric layer 910 to the height of the spacer 800A is greater than 1.5 to ensure that the spacer 800A can be completely covered so that the top surface of the dielectric layer 910 is substantially flat. For example, the height of the spacer 800A is about 100nm, and the height of the dielectric layer 910 is at least 150nm, preferably greater than 200nm. In addition, due to cost and production capacity (efficiency) considerations, the ratio of the height of the dielectric layer 910 to the height of the spacer 800A is preferably less than 10.

[0068] In addition, the sacrificial layer 920 is preferably formed on the dielectric layer 910 , and its function is similar to that of the sacrificial layer 520 , which will not be described in detail. The height of the sacrificial layer 920 is not particularly limited, and it can generally block the patterned photoresist 1100B and the dielectric layer 910 .

[0069] Compared to directly forming the patterned photoresist 1100B, the embodiment of the present invention first forms a mask structure 900 under the patterned photoresist 1100B to facilitate developing the photoresist. In addition, the mask structure 900 can also serve as a covering layer, covering the spacer 800A and the second hard mask layer 400, so that the top surface of the mask structure 900 is substantially flat, which is more conducive to forming the patterned photoresist 1100B.

[0070] Next, refer to Fig. 9 , the pattern of the patterned photoresist 1100B is transferred to the mask structure 900 to form the patterned mask structure 900B, and then the patterned photoresist 1100B is removed. Specifically, the pattern transfer includes transferring the pattern of the patterned photoresist 1100B to the dielectric layer 910 and the sacrificial layer 920 to form the patterned dielectric layer 910B and the patterned sacrificial layer 920B. In some embodiments, the pattern transfer includes the etching process as described above, which will not be repeated here.

[0071] Next, refer to Fig.10 , the pattern of the spacer 800A and the patterned mask structure 900B is transferred to the second hard mask layer 400 to form a predetermined word line region R WL A plurality of second hard masks 400A are formed in the predetermined region R of the selection gate. SG The pattern of the combined spacer 800A1 is also transferred to the second hard mask layer 400 to form a second hard mask 400B in the word line predetermined area R WLIn this embodiment, the transfer of the patterns of the spacers 800A and the patterned mask structure 900B includes etching the second hard mask layer 400 using the spacers 800A and the patterned mask structure 900B as etching masks in a similar manner to the etching process described above.

[0072] exist Fig.10 In the pattern transfer process, since the height of the patterned mask structure 900B is higher than the height of the spacer 800A, the corners on both sides of the patterned mask structure 900B will be etched together during etching. In other words, the corners of the patterned mask structure 900B will be rounded (corner rounding) first during the etching process, and the etching plasma will easily damage the pattern contour of the combined spacer 800A1 along the rounded corners and change (reduce) its size. Therefore, compared with the spacers with the same width in the past, the embodiment of the present invention provides a combined spacer 800A1 that is wider than other spacers 800A, which is adjacent to the patterned mask structure 900B, so that the combined spacer 800A1 can withstand the damage of plasma during the etching process, thereby solving the problem of broken wires.

[0073] In the embodiment of FIG. 10 , it can be seen that the word line predetermined region R WL The spacer 800A in the second hard mask layer 400 also reduces its height as its pattern is transferred to the second hard mask layer 400. SG The spacer 800A has a higher height due to the protection of the patterned dielectric layer 910B. Figure 5 The combined spacer 800A1 formed in the embodiment has a V-shaped profile. Fig.10 During the pattern transfer process, the combined spacer 800A1 may become an arc-shaped profile due to etching.

[0074] In addition, during the pattern transfer process, the patterned sacrificial layer 920B located above may be consumed by etching, such as Fig.10 Alternatively, the patterned sacrificial layer 920B may be removed by another etching process after the pattern transfer process (not shown).

[0075] Next, refer to Fig.11 , remove the patterned mask structure 900 to expose all the spacers 800A. Fig.11 In the embodiment of FIG. 1 , since the patterned sacrificial layer 920B is removed during the pattern transfer process, only the patterned dielectric layer 910B needs to be removed. In this embodiment, the removal of the patterned mask structure 900 includes a removal process similar to the third hard mask 500A, which will not be described in detail.

[0076] Next, refer to Fig.12, all the spacers 800A are removed to expose the top surfaces of all the second hard masks 400A. The removal of the spacers 800A includes the etching process as described above, which will not be described again.

[0077] Next, refer to Figure 13-Figure 16 , the patterns of the second hard masks 400A and 400B are transferred to the active layer 200 to form a word line in the predetermined region R WL A plurality of word lines 200A are formed in the predetermined region R of the select gate. SG The pattern of the second hard mask 400A1 is also transferred to the active layer 200 to form a select gate 200B in the word line predetermined region R WL In some embodiments, the transfer of the patterns of the second hard masks 400A and 400B includes etching the first hard mask layer 300 using the second hard masks 400A and 400B as etching masks to form a plurality of first hard masks 300A and 300B; removing the second hard mask; and etching the active layer 200 using the first hard masks 300A and 300B as etching masks. In some embodiments, the etching process and the removal process included in the transfer of the patterns of the second hard masks 400A and 400B are as described above and will not be repeated here.

[0078] In some embodiments, the word line 200A is used to store charges, the first word line 200A1 is floating and used as a switch (on-off), and the selection gate 200B is used to control the switch.

[0079] Next, refer to Fig.17 , which is a partial top view of the semiconductor structure 10, and the cross section of the line segment AA' is Fig.16 Schematic cross-section diagram of .

[0080] Depend on Fig.17 As can be seen from the embodiment, the selection gate predetermined area R SG Located in the word line predetermined area R WL The first word line 200A1 is located at the word line predetermined region R WL It should be understood that different embodiments may have different configurations according to actual needs.

[0081] exist Fig.17 In the embodiment, the top of word line 200A has a width W WL , the spacing between word lines is W SWL , the top of the first word line 200A1 has a width W WL1 , the top of the select gate 200B has a width W SG For the sake of simplicity, the widths mentioned below refer to the top widths of the components.

[0082] In some embodiments, the width W of each word line 200A is WL The first word line 200A1 may or may not include the first word line 200A1, so that the electrical properties of the word lines generated later are the same. It should be noted that the first word line 200A1 is used as a switch and does not affect the electrical properties of other word lines 200A.

[0083] In addition, in this embodiment, the top width W of the first word line 200A1 is WL1 The top of word line 200A has a width W WL The ratio is greater than 1 and between 2. Since the word line 200A (including the first word line 200A1) is defined by the spacer 800A (including the combined spacer 800A1), and the ratio of the width of the combined spacer 800A1 to the spacer 800A is greater than 1 and between 2, the ratio of the defined word line should also be within this range.

[0084] Next, refer to Fig.18 , continued Fig.16 The semiconductor structure 10 shown in FIG. 1 includes a doped region 110 disposed in the substrate 100 between the word lines 200A and between the first word line 200A1 and the select gate 200B. In some embodiments, the doped region 110 may induce electron-hole pairs generated by ion collisions to maintain the formation of a channel (not shown). The doped region 110 may include N-type or P-type dopants, such as nitrogen, arsenic, phosphorus, antimony ions, or boron, aluminum, gallium, indium, boron trifluoride (BF 3+ ).

[0085] In summary, the method for forming a semiconductor structure provided by the embodiment of the present invention includes forming a combined spacer with a width wider than other spacers to prevent damage or disconnection in subsequent processes and affect subsequent electrical performance. Therefore, the wider combined spacer in the embodiment of the present invention can resist plasma damage in the etching process and improve semiconductor performance.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Forming an active layer on a substrate, wherein the substrate has a word line predetermined region and a selection gate predetermined region adjacent to each other; forming a hard mask stack on the active layer, wherein the hard mask stack comprises a first hard mask layer, a second hard mask layer, and a third hard mask layer sequentially formed on the active layer; Patterning the third hard mask layer to form a plurality of third hard masks in the select gate predetermined region and the word line predetermined region, wherein there is a first spacing between two adjacent third hard masks in the word line predetermined region closest to the select gate predetermined region, and the first spacing is smaller than a second spacing between any other two of the third hard masks; forming a plurality of spacers on the sidewalls of the plurality of third hard masks, wherein two spacers on opposite sidewalls of the two adjacent third hard masks are combined into a combined spacer; removing the third hard mask; forming a patterned mask structure in the predetermined region of the select gate and covering the second hard mask layer and the spacer; as well as The pattern of the spacer is transferred to the active layer to form a plurality of word lines in the word line predetermined area, and the pattern of the patterned mask structure is transferred to the active layer to form a selection gate in the selection gate predetermined area, wherein the step of transferring the pattern of the spacer to the active layer includes transferring the pattern of the combined spacer to the active layer to form a first word line closest to the selection gate.

2. The method for forming a semiconductor structure according to claim 1, wherein: The ratio of the second spacing to the first spacing is between 1.5 and less than 3.

3. The method for forming a semiconductor structure according to claim 1, wherein: The top of the combined spacer has a V-shaped profile.

4. The method for forming a semiconductor structure according to claim 1, wherein: The ratio of the width of the combined spacer to the width of any other spacer is greater than 1 and between 2.

5. The method for forming a semiconductor structure according to claim 1, wherein: The ratio of the height of the patterned mask structure to the height of any spacer among the spacers is greater than 1.

5.

6. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the spacer on the sidewall of the third hard mask comprises: Conformally depositing a spacer material layer over and on the sidewalls of the third hard mask and on the second hard mask layer; and The spacer material layer is anisotropically etched until a portion of the top surface of the second hard mask layer is exposed.

7. The method for forming a semiconductor structure according to claim 6, wherein: Each third hard mask includes a dielectric mask and a sacrificial mask on the dielectric mask.

8. The method for forming a semiconductor structure according to claim 7, characterized in that: The step of conformally depositing the spacer material layer over and on the sidewalls of the third hard mask includes depositing the spacer material layer over the sacrificial mask in each third hard mask and on the sidewalls of the sacrificial mask and the dielectric mask; and The step of anisotropically etching the spacer material layer includes removing the spacer material layer above the sacrificial mask and on the sidewalls of the sacrificial mask.

9. The method for forming a semiconductor structure according to claim 7, wherein: The top surface of each spacer is flush with the interface between each dielectric mask and the sacrificial mask.

10. A semiconductor structure, characterized in that: include: a substrate; A plurality of word lines are disposed on the substrate; a selection gate disposed on the substrate, wherein the selection gate and the word line are located in adjacent areas on the substrate, wherein a first word line among the word lines closest to the selection gate has a width greater than a width of any other word line; as well as A doped region is disposed in the substrate between adjacent word lines and in the substrate between the word line and the selection gate.

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