Devices with staggered body contacts

Abstract

The present disclosure relates to semiconductor structures, and more particularly to devices and methods of manufacturing with staggered body contacts. The device includes: a gate structure located on a semiconductor substrate material, the gate structure including a gate body having a width and a length; a plurality of body contacts that are in electrical contact with a channel region below the gate body on at least one side of the gate body along the width of the gate body; and an isolation structure that isolates the plurality of body contacts from associated source and drain regions of the gate structure.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures, and more particularly to devices and methods of fabrication having staggered body contacts. Background Art

[0002] Due to the limited thickness of the epitaxial silicon layer on the oxide layer in semiconductor-on-insulator (SOI) technology, the body resistance varies with the applied terminal voltage and the distance itself. It should be understood that the body resistance is the equivalent impedance seen at the body contact terminal from any given distance (d) along the width of the device (e.g., gate structure). Due to the variable body resistance that depends on the bias, the holes generated by impact ionization continue to accumulate along the width of the device. This phenomenon causes a floating body effect (usually visible in floating body devices) in body contact devices with different structures (e.g., T-type gate devices, H-type body devices, H-type gate devices, L-type gate devices, and floating body devices). The floating body effect (FBE) in body contact devices can be regarded as a "kink" in the Ids-Vd or Gds-Vd diagram. The FBE in body contact devices can adversely affect the linearity and breakdown voltage of the device.

[0003] The Ids-Vd kink can be reduced by lowering the well doping to increase the diode saturation current. This makes the device more fully depleted, reducing the built-in potential of the surface barrier (SB) junction. However, lowering the doping increases Ioff. On the other hand, it is technically impossible to raise the well doping to very high levels to create a perfect conductor at any high Vd, because Vth will increase to very high levels and the device may not conduct. In addition, introducing a pre-amorphization implant into the body region will eliminate the generated minority carriers and may even reduce the kink, but not for all Vg cases. Summary of the invention

[0004] In one aspect of the present disclosure, a structure includes: a gate structure located on a semiconductor substrate material, the gate structure including a gate body having a width and a length; a plurality of body contacts that are electrically in contact with a channel region below the gate body on at least one side of the gate body along the width of the gate body; and an isolation structure that isolates the plurality of body contacts from associated source and drain regions of the gate structure.

[0005] In one aspect of the present disclosure, a structure includes: a semiconductor substrate on an insulator; an insulator layer located below the semiconductor substrate on an insulator; at least one gate structure located on the semiconductor substrate on an insulator; a source region and a drain region located on opposite sides of the at least one gate structure, the source region and the drain region extending to the insulator layer; a plurality of body contacts, which are electrically in contact with the at least one gate body on at least one side along the width of the at least one gate body; and an isolation structure, which extends to the insulator layer and isolates the plurality of body contacts from the source region and the drain region and from each other.

[0006] In one aspect of the present disclosure, a structure includes: at least one gate structure located on a semiconductor substrate material; an insulator layer located directly below the semiconductor substrate material; a source region located on a first side of the at least one gate structure; a drain region located on a second side of the at least one gate structure; a plurality of staggered body contacts that are offset from each other and are respectively arranged on the first side and the second side along the width of the at least one gate structure; and an isolation structure that extends to the insulator layer and isolates the staggered body contacts from the source region and the drain region, and isolates each of the plurality of staggered body contacts. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the following detailed description, the disclosure is described by way of non-limiting examples of exemplary embodiments of the disclosure with reference to the various figures mentioned.

[0008] Figure 1 A top view of a device having staggered body contacts and a corresponding fabrication process is shown, among other features, in accordance with some aspects of the present disclosure.

[0009] Figure 2A and Figure 2B Magnified views of different configurations of staggered body contacts connected to gate structures and corresponding fabrication processes are shown, among other features, in accordance with aspects of the present disclosure.

[0010] Figure 3 A top view of a symmetrical device with body contacts and a corresponding fabrication process is shown, among other features, according to further aspects of the present disclosure.

[0011] Figure 4 A top view of an asymmetric device with body contact and a corresponding fabrication process is shown, among other features, according to further aspects of the present disclosure.

[0012] Figure 5A is a top view of a symmetrical device with staggered body contacts according to yet another aspect of the present disclosure, among other features.

[0013] Figure 5B It is taken along the line A-AA Figure 5A Cross-sectional view of .

[0014] Figure 5C It is taken along the line B-BB Figure 5A Cross-sectional view of .

[0015] Figure 5D It is taken along the line C-CC Figure 5A Cross-sectional view of .

[0016] Figure 5E It is taken along the line D-DD Figure 5A Cross-sectional view of .

[0017] Figure 6 An asymmetric multi-finger device with body-source shorting is shown, among other features, in accordance with some aspects of the present disclosure.

[0018] Figure 7 An asymmetric multi-finger device with separated body terminals is shown, among other features, in accordance with some aspects of the present disclosure.

[0019] Figure 8 An asymmetric multi-finger device with separate body and end terminals is shown, among other features, in accordance with some aspects of the present disclosure.

[0020] Fig. 9 A symmetric multi-finger device with separate body terminals and optional end terminals is shown, among other features, in accordance with some aspects of the present disclosure.

[0021] Fig.10 A symmetric multi-finger device with common contacts from an annular body contact is shown, among other features, in accordance with some aspects of the present disclosure.

[0022] Fig.11 The maximum number of gate structures that can be used inside a ring-shaped body contact according to some aspects of the present disclosure is graphically illustrated.

[0023] FIG. 12A to FIG. 12C Several graphs are shown for determining an optimal spacing (eg, distance "x") for body contacts in accordance with aspects of the present disclosure.

[0024] Fig.13 is a comparative graph showing the Ids linearity of devices including body contacts according to some aspects of the present disclosure.

[0025] Fig.14 is a comparative graph showing the Gds linearity of devices incorporating body contacts according to some aspects of the present disclosure.

[0026] Fig.15 is a comparative graph showing the maximum self-gain of devices incorporating body contacts according to some aspects of the present disclosure.

[0027] Fig.16 is a comparative graph showing minimum noise for devices incorporating body contacts according to some aspects of the present disclosure.

[0028] Fig.17 is a comparative graph showing the maximum off-state breakdown voltage of devices incorporating body contacts according to aspects of the present disclosure. DETAILED DESCRIPTION

[0029] The present disclosure relates to semiconductor structures, and more particularly to devices and methods of manufacturing having staggered body contacts. More particularly, the present disclosure relates to field effect transistors (FETs) formed on semiconductor-on-insulator (SOI) substrates having multiple body contacts arranged in a staggered layout / arrangement along the width of the device. In an embodiment, shallow trench isolation structures are positioned adjacent to the staggered body contacts to isolate the staggered body contacts. For example, a SOI body-contact MOSFET includes staggered body contacts including one or more P+ islands sandwiched between shallow trench isolation structures that extend to and contact an underlying insulator layer (e.g., a buried oxide layer) to optimize device performance.

[0030] Advantageously, the use of body contacts along the width of the device (e.g., gate structure) can be independently biased and also optimizes the performance of the device (e.g., RF performance). For example, by implementing staggered body contacts along the width of the device, improved linearity and breakdown voltage (BV) can now be achieved regardless of any process limitations. More specifically, in an embodiment, the use of a staggered body contact arrangement can eliminate the Id-Vd kink (floating body effect) and improve the breakdown voltage in body-contacted SOI MOSFETs. In addition, by implementing staggered body contacts, a maximum RF performance matrix (e.g., cutoff frequency (Ft), self-gain) can be obtained. In addition, there is no area penalty for asymmetric configuration (LNA / PA) applications. Moreover, in a separate body switch configuration, each device can have a larger area, but due to the increase in BV, the stacked switch area is still reduced compared to the traditional layout.

[0031] The devices of the present disclosure can be manufactured in a variety of ways using a variety of different tools. However, in general, methods and tools are used to form structures with micrometer and nanometer dimensions. The methods (i.e., techniques) for manufacturing the devices of the present disclosure have been adopted based on integrated circuit (IC) technology. For example, these structures are built on a wafer and implemented in a material film patterned by a photolithography process on top of the wafer. Specifically, the manufacture of the device uses three basic building blocks: (i) depositing a thin film material on a substrate; (ii) applying a patterned mask on top of the film by photolithography imaging; and (iii) selectively etching the film to the mask.

[0032] Figure 1 A top view of a device having staggered body contacts and a corresponding manufacturing process according to some aspects of the present disclosure, among other features, is shown. More specifically, Figure 1 The device 10 includes a substrate 12, which includes SOI technology, or alternatively includes a bulk substrate wafer. For example, in SOI technology, the substrate 12 includes an insulator layer located on top of a semiconductor wafer and a semiconductor layer located on top of the insulator layer. An exemplary insulator layer is a buried oxide layer (BOX); but other materials such as sapphire, SiO2, etc. are also contemplated herein. The semiconductor layer and the semiconductor wafer (or alternatively a bulk substrate wafer) can be any suitable semiconductor material, including but not limited to Si, SiGe, SiGeC, SiC, GaAs, InAs, InP and other III / V or II / VI compound semiconductors. The semiconductor layer and the insulator layer can be formed by any suitable process known to those skilled in the art, so that the present disclosure can be fully understood without further explanation here.

[0033] Still refer to Figure 1 A gate structure 14 is formed on the substrate 12, the gate structure 14 having source / drain regions 16a, 16b along its width. In an embodiment, the gate structure 14 may be an nMOSFET or a pMOSFET using different materials and dopant types as noted in the table below.

[0034] surface

[0035]

[0036] In the present embodiment, for example, the gate structure 14 represents an nMOSFET, wherein the source region 16a and the drain region 16b are n+ doped regions fabricated using known dopants and ion implantation processes (e.g., n-type dopants, including arsenic (As), phosphorus (P), and antimony (Sb), as well as other suitable examples). Thus, the gate body of the gate structure 14 is an n+ type material (e.g., n+ polycrystalline material) formed on the p-type substrate 12. The gate dielectric material may be a high-k gate dielectric material, such as HfO2, Al2O3, Ta2O3, TiO2, La2O3, SrTiO3, LaAlO3, ZrO2, Y2O3, Gd2O3, and combinations including multilayers thereof.

[0037] In an embodiment, the gate structure 14 may be formed using a gate-first process or a gate-last process. In a gate-first process, for example, a gate dielectric material and a gate body material are deposited on the substrate 12 using a conventional deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD) including sputtering, atomic layer deposition (ALD), or other suitable methods. After the deposition process, the material is patterned using conventional photolithography and etching (reactive ion etching (RIE)) processes known to those skilled in the art, so that the present disclosure can be fully understood without further explanation. Sidewall spacers (e.g., nitride materials) can be formed on the sidewalls of the gate structure 14 by a conventional deposition process and a subsequent anisotropic etching process known to those of ordinary skill in the art.

[0038] Still refer to Figure 1 , an annular body contact 18 surrounds the gate structure 14 and the source and drain regions 16a, 16b. In an embodiment, the body contact 18 is an annular contact made using a p+ dopant for an nMOSFET (or alternatively, using an n+ dopant for a pMOSFET). The annular body contact 18 is electrically connected to each end of the gate structure 14 through a contact bridge (e.g., an extended tab) 18a, 18b. In addition, the annular body contact 18 is electrically connected to the gate structure 14 along the width of the gate structure 14 through staggered body contacts 20a, 20b and 20c. In an embodiment, the contacts 18a, 18b, 20a, 20b, 20c have the same dopant type as the contact 18, for example, a P+ dopant for an nMOSFET, or alternatively an N+ dopant for a pMOSFET. Moreover, similar to the staggered body contacts 20a, 20b, 20c, 20d, the end contacts 18a, 18b are electrically connected to the channel region 14a in the gate structure 14.

[0039] Body contacts 20a, 20b are disposed on the drain side of gate structure 14; and body contact 20c is disposed on the source side of gate structure 14. As in each embodiment, the body contacts can be independently biased and connected to the gate channel region below gate structure 14. In addition, although Figure 1 Three staggered body contacts are shown, but it should be understood that, as in each embodiment, multiple (e.g., two (2) or more) body contacts are provided along the width of the gate structure on one or both sides of the gate structure, depending on the width of the gate structure 14 and the lowest ground rules applicable to a particular technology node. For example, as in each embodiment described herein, the body contacts 20a, 20b are staggered or relatively offset (e.g., misaligned) from the contact 20c by a distance "x", such as 2*body contact (bc) spacing. In an illustrative, non-limiting example, the distance "x" may be 2 microns; however, as described below, other distances are also contemplated.

[0040] The contacts 18, 18a, 18b, 20a, 20b, 20c and the source / drain regions 16a, 16b are formed by conventional ion implantation processes (and preferably extend to the underlying insulator layer in SOI technology). For example, the source / drain regions 16a, 16b and the contacts 18, 18a, 18b, 20a, 20b, 20c are formed by introducing a certain concentration of different dopants of opposite conductivity type in the substrate 12 using a corresponding patterned implantation mask to define the selected areas for implantation exposure. The well implants can be formed in the same manner. The implantation mask can include a layer of photosensitive material (e.g., an organic photoresist) that is applied by a spin coating process, pre-baking, exposure to light projected through a photomask, post-exposure baking, and development with a chemical developer. Each implantation mask has a thickness and stopping power sufficient to block the masked area from receiving a certain dose of implanted ions.

[0041] Figure 1 Also shown are shallow trench isolation structures 22 that extend to the underlying insulator layer of substrate 12 and isolate body contacts 20a, 20b, 20c from each other and from source / drain regions 16a, 16b. In this manner, body contacts 20a, 20b, and 20c are p+ islands sandwiched between shallow trench isolation structures 22 that extend and are electrically connected to the gate channel region. Shallow trench isolation structures 22 can be formed by conventional photolithography, etching, and deposition methods known to those skilled in the art.

[0042] By way of example of forming shallow trench isolation structures 22, a resist formed over substrate 12 is exposed to energy (light) to form a pattern (opening). An etching process with selective chemistry (e.g., reactive ion etching (RIE)) is used to form one or more trenches in substrate 12 through the openings in the resist. After the resist is removed by a conventional oxygen ashing process or other known stripping agent, a conductive material may be deposited by any conventional deposition process (e.g., a CVD process). Any residual material on the surface of substrate 12 may be removed by a conventional chemical mechanical polishing (CMP) process.

[0043] Figure 2A and Figure 2B 1 shows an enlarged view of different contact configurations of staggered body contacts 20a, 20b, 20c connected to the gate channel region located below the gate structure 14. These contact connections can be used in any of the different aspects described herein. More specifically, in Figure 2A , the staggered body contacts 20a / 20b / 20c extend below the gate structure 14 to contact the gate channel region, thereby forming a slightly overlapping region 15a. Figure 2A The embodiment shown can be used to offset the etching bias of the gate structure 14 and the P+ mask. Figure 2B In the embodiment, the gate structure 14 includes a notch or tongue portion 15b extending laterally outward from one side of the gate structure 14. In this embodiment, the staggered body contacts 20a / 20b / 20c will make contact with the gate channel region through the area under the gate body tongue, and the P+ mask will overlap with the notch portion 15b. It should be understood by those skilled in the art that the notch portion 15b is composed of the same material (e.g., polycrystalline material) as the gate structure 14 and is formed by the same deposition, patterning and etching processes.

[0044] Figure 3 A top view of a symmetrical device with body contacts is shown, among other features. More specifically, Figure 3 The device 10a is a symmetrical device that can be used as an RF switch. In an embodiment, the device 10a includes an equal number of staggered body contacts 20a-20d on each side of the gate structure 14 along the width of the gate structure 14. In this embodiment, the body contacts 20a-20d are isolated from their corresponding source and drain regions 16a, 16b by shallow trench isolation structures 22. In addition, the body contacts 20a, 20b are staggered or relatively offset by a distance "x" from the corresponding body contacts 20c, 20d. Although two (2) contacts are shown on each side of the gate structure 14, it should be understood that more than two (2) contacts can be provided while maintaining the preferred spacing of "x", such as 2*body contact (bc) spacing.

[0045] Figure 4 A top view of an asymmetric device having staggered body contacts is shown, among other features. More specifically, Figure 4 The device 10b includes an asymmetric construction having unequal numbers of body contacts 20c, 20d along the width of the gate structure 14. In this embodiment, the body contacts 20c, 20d are disposed on the source side of the gate structure 14, and no contacts are disposed on the drain side of the gate structure 14. Alternatively, an additional body contact may be disposed on the drain side of the gate structure 14. For example, two (2) or more body contacts may be disposed on a single side, or any combination of unequal numbers of body contacts may be disposed on different sides of the gate structure 14 while maintaining a preferred spacing and / or offset of "x", such as 2*body contact (bc) spacing. Moreover, the body contacts 20c, 20d are isolated from the source region 16a (and / or drain region 16) by a shallow trench isolation structure 22.

[0046] Figure 5A is a top view of an asymmetric device 10c having staggered body contacts 20a-20c. Figure 5B It is taken along the line A-AA Figure 5A Cross-sectional view of . Figure 5C It is taken along the line B-BB Figure 5A Cross-sectional view of . Figure 5D It is taken along the line C-CC Figure 5A Cross-sectional view of . Figure 5E It is taken along the line D-DD Figure 5A A cross-sectional view of Figure 5B-5E As shown in the cross-sectional view of FIG. 1 , the substrate 12 comprises SOI technology, i.e., comprises an insulator layer 12 b located on top of a semiconductor wafer 12 a and a semiconductor layer 12 c located on top of the insulator layer 12 b. In an embodiment, as already described herein, the semiconductor layer 12 c is implanted with dopants (n+ and p+) to form staggered body contacts 20 a-20 c and source / drain regions 16 a, 16 b.

[0047] The gate structure 14 further includes a channel region 14a, a gate dielectric material 14b and a gate body material 14c. It should be understood that the semiconductor layer 12c is a lightly doped substrate that forms the channel region 14a. The staggered body contacts 20a-20c, the optional end point body contacts 18a, 18b and the source / drain regions 16a, 16b are also separated or isolated from each other by a shallow trench isolation structure 22. The staggered body contacts 20a-20c and the source / drain regions 16a, 16b have a depth "y" that is preferably less than the thickness of the insulator layer 12b and the semiconductor wafer 12a. Moreover, the contacts 20a-20c and the source / drain regions 16a, 16b extend to the underlying insulator layer 12b (e.g., BOX).

[0048] like Figure 5B-5E As further shown, the staggered body contacts 20a-20c and the source / drain regions 16a, 16b each include a silicide contact 24. Those skilled in the art will appreciate that the silicidation process begins by depositing a thin layer of transition metal (e.g., nickel, cobalt, or titanium) over a fully formed and patterned semiconductor device (e.g., doped or ion-implanted source and drain regions 16a, 16b and corresponding staggered body contacts 20a-20c). After the material is deposited, the structure is heated to cause the transition metal to react with exposed silicon (or other semiconductor materials described herein) in the active regions of the semiconductor device (e.g., source regions 16a, drain regions 16b, and staggered body contacts 20a-20c) to form a low resistance transition metal silicide. After the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts 24 in the active regions of the device.

[0049] Figure 6 An asymmetric multi-finger device with body-source shorting, among other features, is shown. More specifically, Figure 6 The asymmetric multi-finger device 10d includes a plurality of gate structures 14, each having a body contact 20c, 20d electrically connected along its source side. Although two body contacts are shown in this embodiment and in other embodiments, it should be understood that more than two body contacts may also be conceived based on the parameters described herein. Moreover, as in each multi-finger embodiment, adjacent gate structures 14 may share a drain region 16b and a source region 16a. In this embodiment, a wiring structure 26 is formed on both the body contact 20c, 20d and the source region 16a of each gate structure 14. The wiring structure 26 includes a contact 28, which electrically connects each source region 16a to the body contact 20c, 20d, for example, via a contact. In this way, the body contacts 20c, 20d are shorted to the source region 16a of each gate structure 14.

[0050] Figure 7 An asymmetric multi-finger device with separated body terminals is shown, among other features. More specifically, Figure 7 The asymmetric multi-finger device 10e includes a plurality of gate structures 14, each of which has a body contact 20c, 20d electrically connected along its source side. In addition, an annular body contact 18 surrounds the asymmetric multi-finger device 10e (e.g., the plurality of gate structures 14). In this embodiment, a wiring structure 26 formed over both the body contact 20c, 20d and the source region 16a of each gate structure 14 includes a contact 28, which electrically connects the body contact 20c, 20d to the annular body contact 18, for example, via a contact. In this way, the body contact 20c, 20d of each gate structure 14 will be electrically connected to a separate body terminal and can therefore be independently biased.

[0051] Figure 8 An asymmetric multi-finger device having separate body and end terminals is shown, among other features. Figure 7 In addition to the features shown, Figure 8 The asymmetric multi-finger device 10 f also includes contact bridges 18 a , 18 b ( 18 a , 18 b having the same polarity doping as the body contact 20 ) that electrically connect each end of the corresponding gate structure 14 to the annular body contact 18 .

[0052] Fig. 9 A symmetrical multi-finger device with separate body terminals and optional end terminals is shown, among other features. Figure 8 In addition to the features shown, Fig. 9 The symmetric multi-finger device 10g also includes body contacts 20a, 20b along the drain side. In this embodiment, in addition to the wiring structure 26 that electrically connects the annular body contact 18 to the body contacts 20c, 20d on the source side, the annular body contact 18 is also electrically connected to each end of each gate structure 14 through contact bridges 18a, 18b. More specifically, the body 18 will connect all body contacts on the source / drain regions 16a, 16b through the wiring structure (i.e., metal) 26. In this embodiment and other embodiments, the use of contact bridges 18a, 18b is optional. The annular body contact 18 is also electrically connected to the gate structure 14 on the drain side through the body contacts 20a, 20b.

[0053] Fig.10 A symmetric multi-finger device having, among other features, a common contact from a ring body contact is shown. More specifically, Fig.10 The device 10i shown shows three symmetrical multi-finger devices combined in parallel, for example to form a total of nine fingers (nf total =9). In this embodiment, each symmetric multi-finger device 100, 200, 300 is connected together by a common leg 18' of each annular contact structure 18a, 18b, 18c. In addition, each common leg 18' is connected to the body contact 20c, 20d on the source side and 20a, 20b on the drain side of the adjacent gate structure 14 of the adjacent symmetric multi-finger device 100, 200, 300. It should be recognized that any number of symmetric multi-finger devices in parallel combination can be conceived herein, and the use of three symmetric multi-finger devices is provided as a non-limiting illustrative example. In this example, no metal wire 26 is required to electrically connect all body contacts to the annular body contact 18.

[0054] Fig.11 The maximum number of gate structures 14 that can be used inside the annular body contact 18 without using metal lines 26 to connect the body contacts is shown graphically. To determine the maximum number of fingers per cell (nf unit ), should satisfy the following formula:

[0055] Max(dist_X)≤dist_Y,

[0056] In this formula, dist_X and dist_Y are the distances of the annular contact 18 from the midpoint of the entire element. After this calculation, multiple elements can be placed in parallel to create a total Device, where nf total =nf unit ×Number of units.

[0057] FIG. 12A to FIG. 12C Several graphs are shown for determining the optimal spacing (eg, distance "x") for body contacts. Fig. 12A Vgs (gate-source voltage) is shown on the "x" axis and the body current in amperes is shown on the y-axis. Fig. 12B The distance from the body contact edge in μm on the x-axis and the internal body potential (Vbi) in V on the y-axis are shown. Fig. 12C Vds on the x-axis and body contact spacing in μm on the y-axis are shown. Fig. 12C The optimum value of bc_pitch at a given Vds is provided (eg, distance "x").

[0058] refer to FIG. 12A to FIG. 12C The following process can be used to find the optimal distance "x":

[0059] 1. Measure Vds = Maximum Vds (at Fig. 12B The relationship between the body current (Ibody) and Vgs at Vdmax (denoted by Vdmax in the figure).

[0060] 2. Determine Vgs = Vgmax, where Ibody is maximum ( Fig. 12A ). Note that Fig. 12A Vgs along the x-axis is normalized relative to Vdmax.

[0061] 3. At Vgs=Vgmax, for different Vds values ​​(e.g., Fig. 12B Vds1...Vdmax) in the device, measuring the internal body potential (Vbi) distribution along the width of the device (ie, at a variable distance from the body contact end of the device).

[0062] 4. Assume that the reference Vbi (Vbi_ref) is equal to the maximum Vbi at Vdmax ( Fig. 12B half of Vbimax).

[0063] 5. Draw a horizontal line with constant Vbi=Vbi_ref and collect all the intersections of this Vbi=Vbi_ref line with different constant Vds lines ( Fig. 12B a, b, c...)..).

[0064] 6. Draw a graph of the intersection points (collected in step 5), such as Fig. 12C As shown, the x-axis is Fig. 12B The Vds in the y-axis is Fig. 12B The X coordinate of the intersection point (a, b, c...) in . For example, Fig. 12B The coordinates of the intersection point (X1, Vds1) in is transformed into Fig. 12C The coordinates of the same point in (Vds1,X1).

[0065] 7. OK Fig. 12C The optimal value of bc_pitch (e.g., distance “x”) at a given Vds in .

[0066] 8. Once from Fig. 12C Once the bc_pitch value is determined in , continuous body contacts can be placed at a distance of 2×bc_pitch (eg, distance “x”). Fig. 12C Vds along the x-axis is normalized relative to Vdmax.

[0067] Fig.13 and Fig.14 are comparative graphs showing Ids linearity and Gds linearity of devices including body contacts according to some aspects of the present disclosure. Fig.13 and Fig.14 In , the x-axis is normalized Vds in volts (V) (eg, normalized to a maximum Vds (Vdmax)); and Fig.13 In the figure, the y-axis is Ids in amperes (A). Fig.14 In the figure, the y-axis is in Siemens Gds. In addition, Fig.13 and Fig.14 A floating body device, an H-body device, and a device containing the body contact described in this article are compared. In these measurements, the source, body, and gate are held at fixed voltages and the drain bias is swept linearly. Fig.13 and Fig.14 In FIG. 5 , the device including body contact shows the most linear Ids and Gds, respectively.

[0068] Fig.15 is a comparative graph showing the maximum self-gain (i.e., s-parameter data) of devices including body contacts according to some aspects of the present disclosure. Fig.15 In the graph of , the x-axis is frequency (GHz) and the y-axis is Gm / Gds. The device including the body contact is shown to have the largest self-gain compared to the floating body device and the H-body device.

[0069] Fig.16is a comparative graph showing the minimum noise of devices including body contacts according to some aspects of the present disclosure. Fig.16 In the graph of , the x-axis is frequency (GHz) and the y-axis is minimum noise (Nfmin (in dB10)). The device including the body contact is shown to have the lowest noise figure compared to the floating body device and the H-body device.

[0070] Fig.17 is a comparative graph showing the maximum breakdown voltage of devices containing body contacts in the off state (ie, when Vgs < 0) according to some aspects of the present disclosure. Fig.17 In the graph of , the x-axis is Vd (V) (e.g., normalized to the maximum Vds) and the y-axis is Ids (A). In addition, in this graph, the drain and source terminals are swept synchronously with opposite polarities, and the breakdown voltage (BV) is defined as the Vds voltage at which the drain current suddenly jumps. Devices with body contact have the maximum off-state breakdown voltage compared to floating body devices and H-body devices.

[0071] These devices can be utilized in system-on-chip (SoC) technology. It will be understood by those skilled in the art that an SoC is an integrated circuit (also referred to as a "chip") that integrates all components of an electronic system on a single chip or substrate. Because the components are integrated on a single substrate, an SoC consumes much less power and occupies much less area than a multi-chip design with equivalent functionality. As a result, SoCs are becoming a dominant force in the mobile computing (e.g., smartphones) and edge computing markets. SoCs are also commonly used in embedded systems and the Internet of Things.

[0072] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in the form of a single chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnects and / or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0073] The description of various embodiments of the present disclosure has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the various embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure comprising: a gate structure located on a semiconductor substrate material, the gate structure comprising a gate body having a width and a length; a plurality of body contacts electrically contacting a channel region below the gate body on at least one side of the gate body along a width of the gate body and configured to be independently biased; as well as An isolation structure extends to an underlying insulator material beneath the semiconductor substrate material to isolate the plurality of body contacts from associated source and drain regions of the gate structure.

2. The semiconductor structure according to claim 1, wherein: The plurality of body contacts overlap under the gate body along a width of the gate body.

3. The semiconductor structure according to claim 1, wherein: The gate body includes at least one tooth or tongue portion extending laterally outward from the at least one side of the gate body along a width of the gate body, and each of the tooth or tongue portions is electrically connected to a corresponding body contact of the plurality of body contacts. 4 . The semiconductor structure of claim 1 , further comprising an annular body contact surrounding the gate structure and in electrical contact with each of the plurality of body contacts. 5 . The semiconductor structure according to claim 4 , further comprising a contact bridge, wherein the contact bridge is in electrical contact with the ring body and is in electrical contact with the channel region below the gate body along two ends of the gate body.

6. The semiconductor structure according to claim 1, wherein: The semiconductor substrate material is semiconductor-on-insulator SOI technology.

7. The semiconductor structure according to claim 6, wherein: The plurality of body contacts are staggered about the gate body along two sides along a width of the gate body.

8. The semiconductor structure according to claim 7, wherein: The plurality of body contacts are placed symmetrically about the gate body along two sides along a width of the gate body.

9. The semiconductor structure according to claim 7, wherein: The plurality of body contacts are asymmetrically placed about the gate body along both sides along a width of the gate body.

10. The semiconductor structure according to claim 6, wherein: The source region and the drain region extend to the underlying insulator material of the SOI technology directly beneath the semiconductor substrate material.

11. The semiconductor structure according to claim 6, wherein: The plurality of body contacts are in electrical contact with the gate body on the same side as the source region, and the plurality of body contacts are electrically shorted to the source region.

12. The semiconductor structure according to claim 6, wherein: The multiple body contacts are electrically contacted with the gate body on the same side as the source region and on the same side as the drain region, and the body contact located on the same side as the source region is electrically contacted with the annular body contact through a wiring structure, and the body contact located on the same side as the drain region is directly electrically contacted with the annular body contact.

13. The semiconductor structure according to claim 6, wherein: The plurality of body contacts are offset from each other by a minimum distance of 2*body contact (bc) spacing.

14. A semiconductor structure comprising: Semiconductor-on-insulator substrates; an insulator layer located below the semiconductor-on-insulator substrate; at least one gate structure located on the semiconductor-on-insulator substrate; a source region and a drain region located on opposite sides of the at least one gate structure, the source region and the drain region extending to the insulator layer; a plurality of body contacts in electrical contact with the at least one gate structure on at least one side along a width of the at least one gate structure; as well as An isolation structure extends to the insulator layer to isolate the plurality of body contacts from the source region and the drain region.

15. The semiconductor structure according to claim 14, wherein: The plurality of body contacts are offset from each other by a minimum distance of 2*body contact (bc) spacing.

16. The semiconductor structure according to claim 14, wherein: The at least one gate structure is three or more gate structures having a shared source region, and the plurality of body contacts in electrical contact with the gate structures are shared along the shared source region.

17. The semiconductor structure according to claim 16, wherein: The plurality of body contacts in electrical contact with the at least one gate structure are also shared along a shared drain region.

18. The semiconductor structure according to claim 16, wherein: The plurality of body contacts are staggered with respect to the at least one gate structure along two sides along a width of the at least one gate structure.

19. A semiconductor structure comprising: at least one gate structure located on the semiconductor substrate material; an insulator layer directly beneath the semiconductor substrate material; a source region located on a first side of the at least one gate structure; a drain region located on a second side of the at least one gate structure; a plurality of staggered body contacts offset from one another and disposed along a width of the at least one gate structure at the first side and the second side, respectively; as well as An isolation structure extends to the insulator layer to isolate the staggered body contacts from the source region and the drain region and to isolate each of the plurality of staggered body contacts.

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