Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same, the device comprising: a plurality of lower electrodes on a semiconductor substrate; a supporting pattern connecting the lower electrodes at the sides of the lower electrodes; and a dielectric layer covering the lower electrodes and the supporting pattern, wherein: each lower electrode comprises: a pillar portion extending in a vertical direction perpendicular to the top surface of the semiconductor substrate; and a protrusion protruding from a side wall of the pillar portion to contact the supporting pattern, the pillar portion comprising a conductive material, the protrusion comprising the same conductive material as the pillar portion, and further doped with impurities.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Korean Patent Application No. 10-2020-0094799, titled “Semiconductor Device and Method for Manufacturing the Same,” filed on July 29, 2020, in the Korean Intellectual Property Office is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments relate to a semiconductor device and a method of manufacturing the same. Background Art

[0004] Semiconductor devices may be used in the electronics industry due to their small size, multifunctional characteristics, and / or low manufacturing cost. With the development of the electronics industry, semiconductor devices have become highly integrated. The width of patterns included in semiconductor devices has been reduced to increase the integration density of semiconductor devices. Summary of the invention

[0005] An embodiment can be implemented by providing a semiconductor device, which includes: a lower electrode on a semiconductor substrate; a supporting pattern connecting the lower electrode at a side of the lower electrode; and a dielectric layer covering the lower electrode and the supporting pattern, wherein each lower electrode includes: a pillar portion extending in a vertical direction perpendicular to a top surface of the semiconductor substrate; and a protrusion protruding from a side wall of the pillar portion to contact the supporting pattern, the pillar portion includes a conductive material, and the protrusion includes the same conductive material as the pillar portion and is further doped with impurities.

[0006] An embodiment can be implemented by providing a method for manufacturing a semiconductor device, the method comprising: stacking a molding layer and a supporting layer in order on a substrate; forming a lower electrode passing through the supporting layer and the molding layer, so that the lower electrode includes a conductive material and has a pillar shape; etching the supporting layer to form a supporting pattern that partially contacts the side wall of the lower electrode, the supporting pattern including a supporting hole exposing the molding layer; removing the molding layer through the supporting hole to expose the surface of the lower electrode; injecting impurities into the lower electrode to form a doping layer covering each lower electrode; removing impurities from a first portion of the doping layer exposed by the supporting pattern and leaving impurities in a second portion of the doping layer located between the supporting pattern and each lower electrode; and removing the first portion.

[0007] An embodiment can be implemented by providing a semiconductor device, which includes: a device isolation pattern that defines an active area in a substrate; a word line that is in the substrate and intersects the active area; a first doped region that is respectively located in the active area on one side of the word line; a second doped region that is respectively located in the active area on the other side of the word line; a bit line that is respectively connected to the first doped region and intersects the word line; a lower electrode contact that is respectively connected to the second doped region; a lower electrode that is respectively on the lower electrode contact; a supporting pattern that is on the side wall of the lower electrode to connect the lower electrode; a connecting pattern that is between the supporting pattern and the lower electrode; and a dielectric layer that covers the lower electrode and the supporting pattern, wherein: measured at the interface between the connecting pattern and the supporting pattern, the height of the connecting pattern in the vertical direction perpendicular to the top surface of the substrate is substantially equal to the height of the supporting pattern in the vertical direction, and the lower electrode and the connecting pattern that are connected to each other constitute a whole formed of the same material. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 is a plan view of a semiconductor device according to some example embodiments.

[0010] Figure 2 is a cross-sectional view of a semiconductor device according to some example embodiments.

[0011] Figure 3 and Figure 4 According to some example embodiments Figure 2 Magnified view of area 'A'.

[0012] Figures 5 to 14 are diagrams of stages in a method of manufacturing a semiconductor device according to some example embodiments.

[0013] Fig.15 is a cross-sectional view of a semiconductor device according to some example embodiments.

[0014] Figures 16 to 21 are diagrams of stages in a method of fabricating a semiconductor device according to some examples.

[0015] Fig. 22 is a plan view of a semiconductor device according to some example embodiments.

[0016] Fig.23 It is along Fig. 22 A cross-sectional view taken along lines CC' and D-D'. DETAILED DESCRIPTION

[0017] Figure 1is a plan view of a semiconductor device according to some example embodiments. Figure 2 It is along Figure 1 sectional views taken along lines AA′ and BB′ of FIG. 1 to illustrate semiconductor devices according to some example embodiments. Figure 3 and Figure 4 According to some example embodiments Figure 2 Magnified view of area 'A'.

[0018] Reference Figures 1 to 3 , a semiconductor substrate 100 may be provided. In one implementation, the semiconductor substrate 100 may be a single crystal silicon (Si) substrate. In one implementation, the semiconductor substrate 100 may include a substrate formed of a semiconductor material such as silicon-germanium (SiGe).

[0019] The interlayer insulating layer 102 may be located on the semiconductor substrate 100. The interlayer insulating layer 102 may include an insulating material. In one embodiment, when the semiconductor substrate 100 is a silicon (Si) substrate, the interlayer insulating layer 102 may include silicon dioxide (SiO 2 ), silicon nitride (SiN) or silicon oxynitride (SiON). As used herein, the term "or" is not an exclusive term, for example, "A or B" will include A, B, or A and B.

[0020] The lower electrode contact 104 may be located in the interlayer insulating layer 102. The lower electrode contact 104 may pass through the interlayer insulating layer 102 to be electrically connected to the semiconductor substrate 100. The lower electrode contact 104 may include a conductive material. In one implementation, for example, the lower electrode contact 104 may include polysilicon doped with a dopant, titanium nitride (TiN), or tungsten (W). In one implementation, as Figure 2 As shown, each lower electrode contact 104 has a single-layer structure. In one implementation, each lower electrode contact 104 may have a multi-layer structure.

[0021] In one implementation, the semiconductor component may be disposed on a semiconductor substrate 100. In one implementation, a device isolation layer may be in the semiconductor substrate 100. The device isolation layer may define an active area in the semiconductor substrate 100. The word line may be buried in the semiconductor substrate 100. Each word line may be insulated from the semiconductor substrate 100 by a gate insulating layer and a capping pattern. Dopant implantation regions may be located on both sides of each word line in the semiconductor substrate 100 (e.g., active area) to form source / drain regions. The bit lines may be electrically connected to the dopant implantation regions at one side of each word line, respectively. The lower electrode contacts 104 may be electrically connected to the dopant implantation regions that are not connected to the bit lines, respectively.

[0022] The etch stop layer 106 may be located on the interlayer insulating layer 102. In one implementation, for example, the etch stop layer 106 may include a silicon nitride (SiN) layer, a silicon boronitride (SiBN) layer, a silicon carbonitride (SiCN) layer, or a combination thereof.

[0023] The lower electrode 210 may be located on the etch stop layer 106. The lower electrode 210 may pass through the etch stop layer 106 to contact the lower electrode contact 104 respectively. Each lower electrode 210 may have a pillar shape. In one implementation, each lower electrode 210 may have a plug shape with a circular cross section. When viewed in a plan view, the lower electrode 210 may be arranged in a honeycomb form. In one implementation, when viewed in a plan view, six lower electrodes 210 may be arranged in a hexagon around one (e.g., center) lower electrode 210. The distance between the lower electrodes 210 adjacent to each other may be in the range of 1nm to 10nm. The lower electrode 210 may include a metal nitride. In one implementation, the lower electrode 210 may include, for example, titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN) or tantalum nitride (TaN). In one implementation, the lower electrode 210 may include a metal, a metal oxide or doped polysilicon.

[0024] The sidewall of the lower electrode 210 may contact the first support pattern 310 and the second support pattern 320. The first support pattern 310 and the second support pattern 320 may be spaced apart from each other. The second support pattern 320 may be located above the first support pattern 310 (e.g., farther away from the substrate 100 than the first support pattern 310 in the vertical direction). The top surface of the second support pattern 320 may be located at a higher level than the top surface of the lower electrode 210 (e.g., farther away from the substrate 100 in the vertical direction). In one implementation, the top surface of the second support pattern 320 may be coplanar with the top surface of the lower electrode 210. In one implementation, for example, each of the first support pattern 310 and the second support pattern 320 may include a silicon nitride (SiN) layer, a silicon boron nitride (SiBN) layer, a silicon carbon nitride (SiCN) layer, or a combination thereof.

[0025] The first support pattern 310 and the second support pattern 320 (e.g., when measured in the vertical direction) may have different thicknesses from each other. In one implementation, the second height h2 of the second support pattern 320 may be greater than the first height h1 of the first support pattern 310. Each of the first height h1 of the first support pattern 310 and the second height h2 of the second support pattern 320 may be greater than the first height h1 of the first support pattern 310. to Each of the first support pattern 310 and the second support pattern 320 may have a support hole. The first support pattern 310 may have a first support hole 312. The second support pattern 320 may have a second support hole 322. The first support hole 312 may vertically overlap with the second support hole 322. Each of the support holes 312 and 322 may expose the sidewalls of three lower electrodes 210 adjacent to each other.

[0026] The connection pattern 214 may be located between the first support pattern 310 and the lower electrode 210, and between the second support pattern 320 and the lower electrode 210. The connection pattern 214 may be a protrusion 214 extending outwardly toward the first support pattern 310 and the second support pattern 320 from the sidewall of the pillar portion 212 having a pillar shape of the lower electrode 210. In one implementation, each connection pattern 214 may be a part of the lower electrode 210 and may protrude from the sidewall of the pillar portion 212. In one implementation, the protrusion 214 and the pillar portion 212 of the lower electrode 210 may constitute a continuous component (e.g., a monolithic, integral structure), and the interface IF between the pillar portion 212 and the protrusion 214 may be invisible or non-existent. In one implementation, the pillar portion 212 and the protrusion 214 may be formed of the same material, and the interface IF between the pillar portion 212 and the protrusion 214 may not exist. In one implementation, the pillar portion 212 and the protrusion 214 may constitute a single component. Hereinafter, the protrusion 214 may be referred to as a connection pattern 214. The connection pattern 214 may include a first connection pattern 216 between the first support pattern 310 and the pillar portion 212 and a second connection pattern 218 between the second support pattern 320 and the pillar portion 212. The first connection pattern 216 may contact the first support pattern 310. The second connection pattern 218 may contact the second support pattern 320. At or near the interface between the first connection pattern 216 and the first support pattern 310, the first width w1 (e.g., height) of the first connection pattern 216 in a direction perpendicular to the top surface of the semiconductor substrate 100 (e.g., vertical direction) may be substantially equal to or greater than the first height h1 of the first support pattern 310. The first connection pattern 216 connecting the pillar portion 212 of the lower electrode 210 and the first support pattern 310 may be connected to or contact the entire sidewall of the first support pattern 310, so that the pillar portion 212 and the first support pattern 310 may be firmly connected to each other. The first connection pattern 216 may have a first width w1 from the pillar portion 212 toward the first support pattern 310 that is substantially uniform. The second connection pattern 218 may have a second width w2 (eg, height) in a vertical direction or a vertical direction from the pillar portion 212 toward the second support pattern 320 that is substantially uniform. Figure 4As shown, the first connection pattern 216 may have a tapered shape, for example, the first width w1 of the first connection pattern 216 may decrease from the pillar portion 212 toward the first support pattern 310 (for example, the height of the first connection pattern 216 near the pillar portion 212 may be greater than the height of the first connection pattern 216 near the first support pattern 310). In one implementation, the second connection pattern 218 may have a tapered shape, for example, the second width w2 of the second connection pattern 218 may decrease from the pillar portion 212 toward the second support pattern 320.

[0027] The connection pattern 214 may include the same material as the pillar portion 212. In one implementation, the connection pattern 214 may include a metal nitride. In one implementation, for example, the connection pattern 214 may include titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), or tantalum nitride (TaN). The connection pattern 214 may also include a first impurity. In one implementation, for example, the first impurity may include carbon (C) or boron (B). In one implementation, the content (e.g., atomic percentage) of the first impurity in the connection pattern 214 may be in the range of 3at% to 50at%.

[0028] The connection pattern 214 may further include a connection pattern 219 between the pillar portion 212 and the etch stop layer 106. In one implementation, the connection pattern 219 may not be disposed between the pillar portion 212 and the etch stop layer 106.

[0029] The content of the first impurity may vary or change according to the relative position in each connection pattern 214 (for example, the first impurity may have a concentration gradient in the connection pattern 214). The content of the first impurity in each connection pattern 214 may be reduced as it approaches or is close to the pillar portion 212, and may increase as it approaches or is close to the interface between each connection pattern 214 and each of the support patterns 310 and 320 (for example, there is a concentration gradient therein). In one implementation, the content of the first impurity may be substantially uniform in each connection pattern 214. The connection pattern 214 may include the first impurity, and the density of the connection pattern 214 may be increased. In one implementation, the connection pattern 214 may firmly connect the lower electrode 210 and the support patterns 310 and 320, and the structural stability of the semiconductor device may be improved.

[0030] In one implementation, Figures 2 to 4As shown, the connection pattern 214 of the lower electrode 210 may include the first impurity, and the pillar portion 212 of the lower electrode 210 may not include the first impurity. In one implementation, the pillar portion 212 of the lower electrode 210 may include the first impurity. In one implementation, the pillar portion 212 and the connection pattern 214 of the lower electrode 210 may be formed of the same material. In one implementation, the content of the first impurity in the pillar portion 212 may be substantially equal to or lower than the content of the first impurity in each of the connection patterns 214.

[0031] The dielectric layer 220 may be located on the lower electrode 210 and the first and second supporting patterns 310 and 320. The dielectric layer 220 may have a substantially uniform thickness and may cover the surface of the lower electrode 210 and the surfaces of the first and second supporting patterns 310 and 320. The dielectric layer 220 may contact (e.g., directly contact) the rest of the surface of the pillar portion 212 except for some portions of the sidewalls of the pillar portion 212 that have been covered by the first and second supporting patterns 310 and 320. The dielectric layer 220 may include an insulating material. The dielectric constant of the dielectric layer 220 may be higher than that of silicon dioxide (SiO 2 ) or silicon nitride (SiN). In one implementation, for example, the dielectric layer 220 may include a dielectric such as aluminum oxide (Al 2 O 3 ) layer or a metal oxide layer of a hafnium dioxide (HfO2) layer.

[0032] The upper electrode 230 may be located on the dielectric layer 220. The upper electrode 230 may include metal (eg, titanium nitride (TiN) or tungsten (W)), doped polysilicon, or a combination thereof. The lower electrode 210, the dielectric layer 220, and the upper electrode 230 may constitute a capacitor CA.

[0033] Figures 5 to 14 Diagrams illustrating stages in a method of manufacturing a semiconductor device according to some example embodiments. Figure 7 is a plan view of some processes of a method of manufacturing a semiconductor device according to some example embodiments. Figures 1 to 4 Components that are identical to the components described will be referred to by the same reference numerals.

[0034] Reference Figure 5 , an interlayer insulating layer 102 may be formed on the semiconductor substrate 100 . A lower electrode contact 104 may be formed in the interlayer insulating layer 102 . An etch stop layer 106 may be formed on the interlayer insulating layer 102 and the lower electrode contact 104 .

[0035] Then, the first mold layer 410, the first support layer 330, the second mold layer 420, and the second support layer 340 may be sequentially stacked on the etch stop layer 106. The first support layer 330 and the second support layer 340 may be formed of the same material. The first mold layer 410 and the second mold layer 420 may be formed of the same material. The first mold layer 410 and the second mold layer 420 may include a material having an etching selectivity relative to the first support layer 330 and the second support layer 340. In one implementation, each of the first mold layer 410 and the second mold layer 420 may be made of silicon dioxide (SiO 2 ) layer. Each of the first supporting layer 330 and the second supporting layer 340 may be formed of a single layer or a multilayer of a silicon nitride (SiN) layer, a silicon boron nitride (SiBN) layer, or a carbon silicon nitride (SiCN) layer. The first mold layer 410 may be formed thicker (e.g., in a vertical direction) than the second mold layer 420. The second supporting layer 340 may be formed thicker than the first supporting layer 330.

[0036] The lower electrode 210 may be formed to penetrate the first and second mold layers 410 and 420 and the first and second supporting layers 330 and 340 .

[0037] Reference Figure 6 , the second supporting layer 340, the second mold layer 420, the first supporting layer 330, and the first mold layer 410 may be sequentially etched to form lower electrode holes H respectively exposing the lower electrode contacts 104. In one implementation, a mask pattern may be formed on the second supporting layer 340, and then, an etching process may be performed using the mask pattern as an etching mask.

[0038] Reference Figure 7 and Figure 8 , the lower electrodes 210 may be respectively formed in the lower electrode holes H. In one implementation, a conductive layer may be formed on the entire top surface of the semiconductor substrate 100 to fill the lower electrode holes H, and then an etch-back process may be performed on the conductive layer to respectively form the lower electrodes 210 in the lower electrode holes H. In the etch-back process, the conductive layer on the top surface of the second supporting layer 340 may be removed to expose the top surface of the second supporting layer 340.

[0039] A mask pattern MP may be formed on the second supporting layer 340. The mask pattern MP may have openings OP partially exposing top surfaces of the lower electrodes 210. In one implementation, each opening OP may expose portions of top surfaces of three lower electrodes 210 adjacent to each other and a top surface of the second supporting layer 340 between the three lower electrodes 210.

[0040] Reference Fig. 9, the second supporting layer 340 and the first supporting layer 330 may be patterned to form supporting patterns 310 and 320 having supporting holes 312 and 322. In one implementation, an anisotropic etching process may be performed using the mask pattern MP as an etching mask to sequentially pattern the second supporting layer 340 exposed by the opening OP, the second mold layer 420 thereunder, and the first supporting layer 330 thereunder. At this time, supporting holes 312 and 322 exposing the top surface of the first mold layer 410 may be formed. The second supporting pattern 320 having the second supporting hole 322 may be formed by patterning the second supporting layer 340. The first supporting pattern 310 having the first supporting hole 312 may be formed by patterning the first supporting layer 330. The first supporting hole 312 may vertically overlap with the second supporting hole 322, respectively, and may have the same / similar shape and size as the second supporting hole 322. In addition, at this time, the sidewall of the second mold layer 420 may also be exposed.

[0041] Reference Fig.10 , the first mold layer 410 and the second mold layer 420 may be removed through the first support hole 312 and the second support hole 322. In one implementation, an isotropic etching process may be performed to remove the first mold layer 410 and the second mold layer 420 exposed through the first support hole 312 and the second support hole 322. Thus, the surface of the lower electrode 210 may be exposed. At this time, the top surface of the etch stop layer 106 and the top surface, sidewalls, and bottom surfaces of the first support pattern 310 and the second support pattern 320 may be exposed.

[0042] In one implementation, the second supporting layer 340 may be etched by an anisotropic etching process to form a second supporting pattern 320 having a second supporting hole 322, and then the second mold layer 420 may be removed by an isotropic etching process through the second supporting hole 322. Then, the first supporting layer 330 may be etched by an anisotropic etching process to form a first supporting pattern 310 having a first supporting hole 312, and then the first mold layer 410 may be removed by an isotropic etching process through the first supporting hole 312.

[0043] Reference Fig.11 , can be obtained from Fig.10 The resulting structure removes the mask pattern MP.

[0044] A doping layer 210a may be formed on the surface of each lower electrode 210. In one implementation, a surface portion of each lower electrode 210 may be doped with a first impurity to form the doping layer 210a. The first impurity may penetrate into a grain boundary of the lower electrode 210. At this time, a portion of each lower electrode 210 not doped with the first impurity may correspond to the reference Figure 2The pillar portion 212 is described. The doping layer 210a may be formed to cover the sidewalls and top surface of the pillar portion 212. The first impurity may include carbon (C) or boron (B). The content (eg, atomic percentage) of the first impurity in the doping layer 210a may be in the range of 3 at % to 50 at %.

[0045] Reference Fig.12 , the first impurity may be removed from a portion of the doped layer 210a. In one implementation, the first impurity may be removed from a first portion 210b of the doped layer 210a exposed (e.g., not covered by) through the first support pattern 310 and the second support pattern 320 and the etch stop layer 106. In one implementation, an ashing process may be performed on the exposed surface of the lower electrode 210 (e.g., the surface of the first portion 210b of the doped layer 210a exposed by the first support pattern 310 and the second support pattern 320 and the etch stop layer 106). The ashing process may include a plasma surface treatment process, a heat treatment process, or an oxidation process. At this time, the ashing process may not be performed on the second portion 210c of the doped layer 210a covered by the first support pattern 310 and the second support pattern 320 and the etch stop layer 106, and the first impurity may remain in the second portion 210c. An ashing process may be performed on the surface of the first portion 210b, and the height of the remaining second portion 210c may be substantially equal to the thickness (or height) of the first supporting pattern 310 adjacent thereto or the thickness (or height) of the second supporting pattern 320 adjacent thereto.

[0046] As described above, the first impurity can be removed from the first portion 210b of the doping layer 210a, and the first portion 210b can include the same material as the pillar portion 212. At this time, the crystal defects of the first portion 210b can be more than the crystal defects of the second portion 210c and the crystal defects of the pillar portion 212 (for example, the first portion 210b can include a larger number of crystal defects than the second portion 210c and the pillar portion 212). In one implementation, the first impurity infiltrated in the crystal structure of the first portion 210b can be removed, and a vacancy can be formed in the crystal structure of the first portion 210b. The vacancy can correspond to a crystal defect. In one implementation, the strength of the first portion 210b can be weaker than the strength of the pillar portion 212 and the strength of the second portion 210c, and in a subsequent etching process, the first portion 210b can have an etching selectivity relative to the second portion 210c.

[0047] Reference Fig.13, the first portion 210b of the lower electrode 210 may be removed. In one implementation, an isotropic etching process may be performed to etch the exposed first portion 210b. In the etching process, the first portion 210b having many crystal defects may be easily etched, but the pillar portion 212 and the second portion 210c may not be etched. At this time, the second portion 210c contacting the first support pattern 310 and the second support pattern 320 may not be etched. Therefore, undercutting caused by etching some portions of the lower electrode 210 located between the pillar portion 212 and the first support pattern 310 and the second support pattern 320 may not occur, and the first support pattern 310 and the second support pattern 320 may be prevented from being separated from the pillar portion 212. As a result, the structural stability of the semiconductor device may be improved. In addition, the first portion 210b of the lower electrode 210 may be removed, and the width of the lower electrode 210 may be reduced. Therefore, the integration density of the semiconductor device may be improved.

[0048] The second portion 210c remaining after the etching process may be a reference Figure 2 In one implementation, the second portion 210 c between the pillar portion 212 and the first support pattern 310 may be the first connection pattern 216 , and the second portion 210 c between the pillar portion 212 and the second support pattern 320 may be the second connection pattern 218 .

[0049] Reference Fig.14 , a dielectric layer 220 may be formed on the entire top surface of the semiconductor substrate 100. The dielectric layer 220 may be formed to a substantially uniform thickness on the top surface of the etch stop layer 106, the top surfaces, sidewalls, and bottom surfaces of the first and second support patterns 310 and 320, and the exposed surface of the lower electrode 210. Due to the presence of the connection pattern 214, the dielectric layer 220 may not be disposed between the pillar portion 212 and the first support pattern 310 and between the pillar portion 212 and the second support pattern 320.

[0050] Refer to Figure 2 , an upper electrode 230 may be formed on the dielectric layer 220. In one implementation, the upper electrode 230 may be formed by depositing or coating a conductive material on the semiconductor substrate 100.

[0051] A reference can be made as described above Figure 2 A semiconductor device is described.

[0052] Fig.15 is a cross-sectional view of a semiconductor device according to some example embodiments. In this embodiment, for the purpose of ease and convenience of explanation, the Figures 1 to 4 In other words, the following will mainly describe in detail the technical features of this embodiment and the technical features of the embodiment of Figures 1 to 4 Hereinafter, the same components as those in the aforementioned embodiment will be denoted by the same reference numerals.

[0053] Reference Fig.15 , each lower electrode 210 ′ may have a hollow cup shape or a hollow cylindrical shape.

[0054] The connection pattern 214 may be located between the first support pattern 310 and the outer sidewall of the lower electrode 210' and between the second support pattern 320 and the outer sidewall of the lower electrode 210'. The connection pattern 214 may be a protrusion 214 extending from the outer sidewall of the lower electrode 210' toward the first support pattern 310 and the second support pattern 320. In one implementation, the connection pattern 214 may be some portion of the lower electrode 210'.

[0055] The dielectric layer 220 may cover the inner sidewall of the lower electrode 210' and the outer sidewall of the lower electrode 210'. The upper electrode 230 may extend into the interior of the lower electrode 210'. Other components may be the same as those described in reference Figures 1 to 4 Same / similar as described.

[0056] Figures 16 to 21 are diagrams of stages in a method of manufacturing a semiconductor device according to some example embodiments.

[0057] Reference Fig.16 , the conductive layer can be Figure 6 The bottom surface and the inner sidewall of the lower electrode hole H of the resulting structure and the top surface of the second supporting layer 340 are formed to have a substantially uniform thickness. At this time, the thickness of the conductive layer may be relatively thin, and the conductive layer may not completely fill the lower electrode hole H. A sacrificial layer 430 may be formed on the conductive layer to fill the lower electrode hole H. Then, an etch-back process or a chemical mechanical polishing (CMP) process may be performed on the sacrificial layer 430 and the conductive layer to expose the top surface of the second supporting layer 340. At this time, the lower electrode 210' and the sacrificial layer 430 may remain in the lower electrode hole H.

[0058] A mask pattern MP may be formed on the second supporting layer 340. The mask pattern MP may have an opening OP partially exposing the top surface of the lower electrode 210'. In one implementation, each opening OP may expose a portion of the top surface of three lower electrodes 210' adjacent to each other and the top surface of the second supporting layer 340 between the three lower electrodes 210'. At this time, the opening OP may also expose a portion of the top surface of the sacrificial layer 430 in the lower electrode hole H.

[0059] Reference Fig.17, the second supporting layer 340 and the first supporting layer 330 may be patterned to form supporting patterns 310 and 320 having supporting holes 312 and 322. In one implementation, an anisotropic etching process may be performed using the mask pattern MP as an etching mask to sequentially pattern the second supporting layer 340 exposed through the opening OP, the second mold layer 420 thereunder, and the first supporting layer 330 thereunder. At this time, supporting holes 312 and 322 exposing the top surface of the first mold layer 410 may be formed. The second supporting pattern 320 having the second supporting hole 322 may be formed by patterning the second supporting layer 340. The first supporting pattern 310 having the first supporting hole 312 may be formed by patterning the first supporting layer 330. When etching the second mold layer 420, the sacrificial layer 430 may also be removed.

[0060] The first mold layer 410 and the second mold layer 420 may be removed through the first support hole 312 and the second support hole 322. In one implementation, an isotropic etching process may be performed to remove the first mold layer 410 and the second mold layer 420 exposed through the first support hole 312 and the second support hole 322. Thus, the surface of the lower electrode 210' may be exposed. At this time, the top surface of the etch stop layer 106 and the top surface, sidewalls, and bottom surfaces of the first support pattern 310 and the second support pattern 320 may be exposed. When the sacrificial layer 430 remains in the lower electrode hole H in the process of forming the first support hole 312 and the second support hole 322, the retained sacrificial layer 430 may also be removed in the removal process of the first mold layer 410 and the second mold layer 420.

[0061] Reference Fig.18 , can be obtained from Fig.17 The resulting structure removes the mask pattern MP.

[0062] A doping layer 210a may be formed on the surface of each lower electrode 210'. In one implementation, a surface portion of each lower electrode 210' may be doped with a first impurity to form the doping layer 210a. The doping layer 210a may be formed to cover the outer sidewall and the inner sidewall of the lower electrode 210'. The first impurity may include carbon (C) or boron (B). The content (e.g., atomic percentage) of the first impurity in the doping layer 210a may be in the range of 3at% to 50at%.

[0063] Reference Fig.19, the first impurity can be removed from a portion of the doped layer 210a. In one implementation, the first impurity can be removed from the first portion 210b of the doped layer 210a exposed (e.g., not covered by) through the first support pattern 310 and the second support pattern 320 and the etch stop layer 106. In one implementation, an ashing process can be performed on the exposed surface of the lower electrode 210' (e.g., the surface of the first portion 210b of the doped layer 210a exposed by the first support pattern 310 and the second support pattern 320 and the etch stop layer 106). The ashing process may include a plasma surface treatment process, a heat treatment process, or an oxidation process. At this time, the ashing process may not be performed on the second portion 210c of the doped layer 210a covered by the first support pattern 310 and the second support pattern 320 and the etch stop layer 106, and the first impurity may be retained in the second portion 210c.

[0064] Reference Fig. 20 , the first portion 210b of the lower electrode 210' may be removed. In one implementation, an isotropic etching process may be performed to etch the exposed first portion 210b. In the etching process, the first portion 210b having many crystal defects may be easily etched, and the pillar portion 212 and the second portion 210c may not be etched. Therefore, undercutting caused by etching some portions of the lower electrode 210' located between the pillar portion 212 and the first and second support patterns 310 and 320 may not occur, and the first and second support patterns 310 and 320 may be prevented from being separated from the lower electrode 210'. The second portion 210c retained after the etching process may be a connecting pattern 214.

[0065] Reference Fig.21 , a dielectric layer 220 may be formed on the entire top surface of the semiconductor substrate 100. The dielectric layer 220 may be formed to a substantially uniform thickness on the top surface of the etch stop layer 106, the top surface, sidewalls, and bottom surface of the first and second support patterns 310 and 320, and the exposed surface of the lower electrode 210'. The dielectric layer 220 may cover the outer sidewall and the inner sidewall of the lower electrode 210'. Due to the presence of the connection pattern 214, the dielectric layer 220 may not be provided between the lower electrode 210' and the first support pattern 310 and between the lower electrode 210' and the second support pattern 320.

[0066] Refer to Fig.15 , an upper electrode 230 may be formed on the dielectric layer 220 . In one implementation, the upper electrode 230 may be formed by depositing or coating a conductive material on the semiconductor substrate 100 .

[0067] A reference can be made as described above Fig.15 A semiconductor device is described.

[0068] Fig. 22 is a plan view of a semiconductor device according to some example embodiments. Fig.23 It is along Fig. 22 A cross-sectional view taken along lines CC' and D-D'.

[0069] Reference Fig. 22 and Fig.23 , a device isolation pattern 502 may be formed in the substrate 501 to define an active portion (or active area) ACT. When viewed in a plan view, each active portion ACT may have an isolated shape. When viewed in a plan view, each active portion ACT may have a bar shape extending in a first direction X1. When viewed in a plan view, each active portion ACT may correspond to a portion of the substrate 501 surrounded by the device isolation pattern 502. The substrate 501 may include a semiconductor material. The active portions ACT may be arranged parallel to each other in the first direction X1, and an end portion of one active portion ACT may be arranged adjacent to the center of another active portion ACT adjacent to the one active portion ACT.

[0070] The word line WL may intersect the active portion ACT. The word line WL may be disposed in a groove formed in the device isolation pattern 502 and the active portion ACT. The word line WL may be parallel to a second direction X2 intersecting the first direction X1. The word line WL may be formed of a conductive material. A gate dielectric layer 507 may be disposed between each word line WL and the inner surface of each groove. In one implementation, the bottom of the groove may be relatively deep in the device isolation pattern 502 and may be relatively shallow in the active portion ACT. The gate dielectric layer 507 may include at least one of thermal oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material. The bottom surface of the word line WL may be round.

[0071] The first doped region 512a may be in each active portion ACT between a pair of word lines WL, and a pair of second doped regions 512b may be respectively in two edge regions of each active portion ACT. For example, the first doped region 512a and the second doped region 512b may be doped with N-type dopants. The first doped region 512a may correspond to a common drain region, and the second doped region 512b may correspond to a source region. Each word line WL and the first doped region 512a and the second doped region 512b adjacent thereto may constitute a transistor. The word line WL may be in a groove, and the channel length of the channel region below the word line WL may be increased within a limited plane area. Therefore, the short channel effect may be minimized.

[0072] The top surface of the word line WL may be lower than the top surface of the active portion ACT. A word line capping pattern 510 may be located on each word line WL. The word line capping pattern 510 may have a line shape extending in the longitudinal direction of the word line WL and may completely cover the top surface of the word line WL. The word line capping pattern 510 may fill the groove on the word line WL. The word line capping pattern 510 may be formed of, for example, silicon nitride.

[0073] The interlayer insulating pattern 505 may be located on the substrate 501. In one implementation, the interlayer insulating pattern 505 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. The interlayer insulating pattern 505 may have an island shape separated from each other in a plan view. The interlayer insulating pattern 505 may cover ends of two active portions ACT adjacent to each other.

[0074] Upper portions of the substrate 501 , the device isolation pattern 502 , and the word line capping pattern 510 may be partially recessed to form a recess region R. The recess region R may have a mesh shape when viewed in a plan view. Sidewalls of the recess region R may be aligned with sidewalls of the interlayer insulating pattern 505 .

[0075] The bit line BL may be on the interlayer insulating pattern 505. The bit line BL may cross the word line capping pattern 510 and the word line WL. Fig. 22 As shown, the bit line BL may be parallel to a third direction X3 intersecting the first direction X1 and the second direction X2. Each bit line BL may include a bit line polysilicon pattern 530, a bit line ohmic pattern 531, and a bit line metal-containing pattern 532 stacked in sequence. The bit line polysilicon pattern 530 may include undoped polysilicon or polysilicon doped with a dopant. The bit line ohmic pattern 531 may include a metal silicide layer. The bit line metal-containing pattern 532 may include at least one of a metal (e.g., tungsten, titanium, or tantalum) and a conductive metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride). A bit line capping pattern 537 may be disposed on each bit line BL. The bit line capping pattern 537 may be formed of an insulating material such as silicon nitride.

[0076] The bit line contact DC may be disposed in a recess region R intersecting the bit line BL. The bit line contact DC may include undoped polysilicon or polysilicon doped with a dopant. Fig.23 In the cross section DD' of FIG. 5 , the sidewall of the bit line contact DC may contact the sidewall of the interlayer insulating pattern 505. Fig. 22 In a plan view of FIG. 5 , a sidewall of the bit line contact DC contacting the interlayer insulating pattern 505 may be recessed. The bit line contact DC may electrically connect the first doped region 512 a to the bit line BL.

[0077] The lower filling insulating pattern 541 may be in the recess region R where the bit line contact DC is not disposed. The lower filling insulating pattern 541 may be formed of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof.

[0078] The storage node contact BC may be between a pair of bit lines BL adjacent to each other. The storage node contacts BC may be spaced apart from each other. The storage node contact BC may include undoped polysilicon or polysilicon doped with impurities. The top surface of the storage node contact BC may be recessed. The insulating pattern may be located between the storage node contacts BC between the bit lines BL.

[0079] The bit line spacer SP may be located between the bit line BL and the storage node contact BC. The bit line spacer SP may include a first sub-spacer 521 and a second sub-spacer 525 spaced apart from each other by a spacer region GP. The spacer region GP may be referred to as an air gap region. The first sub-spacer 521 may cover the sidewalls of the bit line BL and the sidewalls of the bit line capping pattern 537. The second sub-spacer 525 may be adjacent to the storage node contact BC. The first sub-spacer 521 and the second sub-spacer 525 may include the same material. In one implementation, the first sub-spacer 521 and the second sub-spacer 525 may include silicon nitride.

[0080] The bottom surface of the second sub-spacer 525 may be lower than the bottom surface of the first sub-spacer 521. The height of the top end of the second sub-spacer 525 may be lower than the height of the top end of the first sub-spacer 521. Therefore, the margin of the subsequent process of forming the landing pad LP can be increased. As a result, the discontinuity between the landing pad LP and the storage node contact BC can be prevented. The first sub-spacer 521 may extend to cover the sidewalls of the bit line contact DC and the sidewalls and bottom of the recessed region R. In one implementation, the first sub-spacer 521 may be between the bit line contact DC and the lower filling insulation pattern 541, between the word line capping pattern 510 and the lower filling insulation pattern 541, between the substrate 501 and the lower filling insulation pattern 541, and between the device isolation pattern 502 and the lower filling insulation pattern 541.

[0081] The storage node ohmic layer 509 may be located on the storage node contact BC. The storage node ohmic layer 509 may include a metal silicide. A diffusion barrier pattern 511a having a substantially uniform thickness may cover the storage node ohmic layer 509, the first subspacer 521 and the second subspacer 525, and the bit line capping pattern 537. The diffusion barrier pattern 511a may include a metal nitride such as titanium nitride or tantalum nitride. A landing pad LP may be located on the diffusion barrier pattern 511a. The landing pad LP may correspond to Figure 2The lower electrode contact 104. The landing pad LP may be formed of a metal-containing material such as tungsten. The upper portion of the landing pad LP may cover the top surface of the bit line capping pattern 537 and may have a width greater than the width of the storage node contact BC. The center of the landing pad LP may be shifted from the center of the storage node contact BC in the second direction X2. A portion of the bit line BL may vertically overlap with the landing pad LP. An upper sidewall of the bit line capping pattern 537 may overlap with the landing pad LP and may be covered by the third sub-spacer 527. The pad separation pattern 557 may be located between the landing pads LP. The pad separation pattern 557 may correspond to Figure 2 The pad separation pattern 557 may include a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, or a porous layer. The pad separation pattern 557 may define a top end of the spacer region GP.

[0082] The lower electrodes 210 may be respectively located on the landing pads LP. The lower electrodes 210 may correspond to the reference Figures 1 to 4 The lower electrode 210 described. In one implementation, the lower electrode 210 may include a pillar portion and a connection pattern 214 protruding from a sidewall of the pillar portion. Some portions of the sidewall of the lower electrode 210 may be connected to the first support pattern 310 and the second support pattern 320. The first support pattern 310 may be connected to the lower electrode 210 through the first connection pattern 216, and the second support pattern 320 may be connected to the lower electrode 210 through the second connection pattern 218. The first support pattern 310 and the second support pattern 320 may have support holes.

[0083] The top surface of the pad separation pattern 557 between the lower electrodes 210 may be covered by the etch stop layer 106. In one implementation, for example, the etch stop layer 106 may include an insulating material such as a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer. The dielectric layer 220 may cover the surface of the lower electrode 210 and the surfaces of the support patterns 310 and 320. The upper electrode 230 may cover the dielectric layer 220.

[0084] In the semiconductor device according to the present embodiment, the spacer region GP may be between the first sub-spacer 521 and the second sub-spacer 525, and the dielectric constant of air / gas / vacuum may be smaller than the dielectric constant of silicon oxide. Therefore, the parasitic capacitance between the bit line BL and the storage node contact BC may be reduced. In addition, the connection pattern 214 connecting the support patterns 310 and 320 to the lower electrode 210 may be located on the sidewall of the lower electrode 210, and therefore, the lower electrode 210 may be firmly supported by the support patterns 310 and 320.

[0085] In a semiconductor device according to some example embodiments, a connection pattern connecting a pillar portion of a lower electrode to a support pattern may be connected to an entire portion of a sidewall of the support pattern, and thus, the pillar portion and the support pattern may be firmly connected to each other.

[0086] In addition, the density of the connection pattern can be increased by the impurities included in the connection pattern, and thus the connection pattern can firmly connect the lower electrode to the support pattern. As a result, the structural stability of the semiconductor device can be improved.

[0087] The method of manufacturing a semiconductor device according to some example embodiments may help prevent undercutting caused by etching of a portion of the lower electrode between the pillar portion and the support pattern and may help prevent the pillar portion from being separated from the support pattern. Thus, a semiconductor device having improved structural stability may be manufactured.

[0088] In addition, the peripheral portion of the lower electrode can be partially removed, and the width of the lower electrode can be reduced. Therefore, the integration density of the semiconductor device can be improved.

[0089] By way of summary and review, fine patterns may be formed using new exposure techniques and / or expensive exposure techniques, thereby causing problems with highly integrated semiconductor devices. Therefore, other integration techniques may be considered.

[0090] One or more embodiments may provide a semiconductor device including a capacitor.

[0091] One or more embodiments may provide a semiconductor device capable of improving integration density and structural stability.

[0092] Exemplary embodiments are disclosed herein, and although specific terms are used, they are used and interpreted only in a general and descriptive sense, and not for the purpose of limitation. In some cases, as this application is submitted, unless otherwise specifically stated, it will be apparent to one of ordinary skill in the art that the features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with the features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes may be made in form and detail without departing from the spirit and scope of the invention as described in the appended claims.

Claims

1. A semiconductor device comprising: a lower electrode on a semiconductor substrate; a supporting pattern connected to the lower electrode at a side of the lower electrode; as well as a dielectric layer covering the lower electrode and the support pattern, in: Each of the lower electrodes comprises: a pillar portion extending in a vertical direction perpendicular to a top surface of the semiconductor substrate; and a protrusion protruding from a side wall of the pillar portion to contact the support pattern, The pillar portion includes a conductive material, and The protrusion includes the same conductive material as the pillar portion and is further doped with impurities.

2. The semiconductor device according to claim 1, wherein: The conductive material includes titanium or tantalum nitride, and The impurities include carbon.

3. The semiconductor device according to claim 1, wherein A height of the protrusion in the vertical direction, measured at an interface between the protrusion and the support pattern, is equal to a height of the support pattern in the vertical direction.

4. The semiconductor device according to claim 1, wherein The protrusion has a tapered shape such that the height of the protrusion in the vertical direction becomes smaller from the side wall of the pillar portion toward the support pattern.

5. The semiconductor device according to claim 1, wherein The protrusion has an impurity with a concentration gradient such that the concentration of the impurity is maximum at an interface between the protrusion and the support pattern and becomes smaller in a direction toward the pillar portion.

6. The semiconductor device according to claim 1, wherein The content of impurities in the protrusions is in the range of 3 at % to 50 at %.

7. The semiconductor device according to claim 1, wherein The conductive material of the pillar portion is doped with impurities.

8. The semiconductor device according to claim 1, wherein The dielectric layer contacts a remaining portion of the surface of the pillar portion that is not covered by the support pattern.

9. The semiconductor device according to claim 1, wherein: A distance between adjacent ones of the lower electrodes is in a range of 1 nm to 10 nm.

10. The semiconductor device according to claim 1, wherein The support pattern has to Thickness.

11. The semiconductor device according to claim 1, wherein: The pillar portion of each of the lower electrodes has a hollow cup shape, and The dielectric layer contacts an inner sidewall of the pillar portion.

12. A method for manufacturing a semiconductor device, the method comprising: stacking a molding layer and a supporting layer in order on a substrate; forming a lower electrode passing through the support layer and the mold layer so that the lower electrode includes a conductive material and has a pillar shape; etching the support layer to form a support pattern partially contacting a sidewall of the lower electrode, the support pattern including a support hole exposing the mold layer; removing the molding layer through the supporting hole to expose the surface of the lower electrode; implanting impurities into the lower electrodes to form a doping layer covering each of the lower electrodes; removing the impurities from a first portion of the doping layer exposed by the support pattern and leaving the impurities in a second portion of the doping layer between the support pattern and each of the lower electrodes; as well as The first portion is removed.

13. The method according to claim 12, wherein: During the removal of the first portion, the second portion of the doped layer has an etch selectivity relative to the first portion of the doped layer.

14. The method of claim 12, wherein: The conductive material of the lower electrode includes titanium or tantalum nitride, and The impurities include carbon.

15. The method according to claim 12, wherein: After the impurities are removed from the first portion of the doping layer, an amount of crystal defects in the first portion of the doping layer is greater than an amount of crystal defects in the second portion and a amount of crystal defects in the lower electrode.

16. The method according to claim 12, wherein: A height of a second portion remaining after the first portion is removed in a vertical direction perpendicular to a top surface of the substrate is equal to or greater than a height of the support pattern in the vertical direction.

17. The method according to claim 12, wherein: The content of impurities in the doping layer is in the range of 3 at % to 50 at %.

18. A semiconductor device comprising: a device isolation pattern defining an active region in the substrate; a word line in the substrate and crossing the active area; A first doped region, which is located in the active region on one side of the word line; A second doped region, which is located in the active region on the other side of the word line; Bit lines are connected to the first doping regions respectively, and the bit lines cross the word lines; lower electrode contacts, connected to the second doped regions respectively; lower electrodes, which are respectively on the lower electrode contact members; A supporting pattern, which is on the side wall of the lower electrode to connect the lower electrode; a connecting pattern between the supporting pattern and the lower electrode; as well as a dielectric layer covering the lower electrode and the support pattern, in: Measured at an interface between the connection pattern and the support pattern, a height of the connection pattern in a vertical direction perpendicular to the top surface of the substrate is equal to a height of the support pattern in the vertical direction, and The lower electrode and the connection pattern connected to each other constitute an integral body formed of the same material.

19. The semiconductor device according to claim 18, wherein: The lower electrode includes a conductive material, and The connection pattern includes the same conductive material as the lower electrode and is further doped with impurities.

20. The semiconductor device according to claim 19, wherein: The conductive material includes titanium or tantalum nitride, and The impurities include carbon.

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