Circuit device

Abstract

The circuit device includes an output terminal, an output transistor, and a gate voltage control circuit. The output transistor is disposed between the first power supply node and the output terminal. After the input signal (TX) transitions from a first logic level to a second logic level, the gate voltage control circuit causes the gate voltage of the output transistor to change at a first time-voltage change rate. After the gate voltage reaches a first determination voltage, the circuit causes the gate voltage to change at a second time-voltage change rate that is smaller than the first time-voltage change rate. After the gate voltage reaches a second determination voltage, the circuit causes the gate voltage to change at a third time-voltage change rate that is larger than the second time-voltage change rate.

Description

TECHNICAL FIELD

[0001] The present application relates to a circuit device or the like. BACKGROUND

[0002] A pulse shaping configuration unit that forms a rectangular pulse is disclosed in Patent Literature 1. The pulse shaping configuration unit includes a signal edge generator to which a rectangular pulse is supplied, and an operational amplifier and an output amplification stage to which an output signal of the signal edge generator is input. An output signal of the output amplification stage is output to an output terminal, and the output signal is fed back to the operational amplifier. The signal edge generator generates a pulse having a rising, a falling that are slowed down, and a state transition portion having a rounded corner, from the rectangular pulse. The signal edge generator charges an internal capacitor with a fixed current, discharges it in order to obtain a falling edge, and rounds the signal waveform by limiting the efficiency of the current source and sink.

[0003] Patent Literature 1: Japanese Patent Application Laid-Open No. 6-97784

[0004] As described above, in Patent Literature 1, only the structure of the signal edge generator that rounds the signal waveform is simply described, and no specific structure of changing the waveform according to what conditions or the like is disclosed. SUMMARY

[0005] One embodiment of the present disclosure relates to a circuit device including an output terminal, an output transistor provided between a first power supply node to which a first power supply voltage is supplied and the output terminal, and a gate voltage control circuit that inputs an input signal and controls a gate voltage of the output transistor, the gate voltage control circuit changing the gate voltage at a first temporal voltage change rate after the input signal is changed from a first logic level to a second logic level, changing the gate voltage at a second temporal voltage change rate smaller than the first temporal voltage change rate after the gate voltage reaches a first determination voltage, and changing the gate voltage at a third temporal voltage change rate larger than the second temporal voltage change rate after the gate voltage reaches a second determination voltage higher than the first determination voltage. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a configuration example of a circuit device.

[0007] Figure 2 is a waveform diagram for explaining the operation of the circuit device.

[0008] Figure 3 is a detailed configuration example of a gate voltage control circuit.

[0009] Figure 4 is a waveform chart illustrating the operation of the gate voltage control circuit.

[0010] Figure 5 is a detailed configuration example of the voltage generation circuit.

[0011] Figure 6 is a detailed configuration example of the switch control circuit.

[0012] Figure 7 is a detailed configuration example of the output circuit.

[0013] Explanation of Reference Signs

[0014] 100: circuit device; 110: output transistor; 115: output resistor; 120: gate voltage control circuit; 130: voltage generation circuit; 131: first voltage dividing circuit; 132: second voltage dividing circuit; 133: N-type transistor; 134: current source circuit; 140: switch control circuit; 141 to 143: comparator; 144: output circuit; CA: capacitor; NVSS: first power supply node; NVsup: second power supply node; RA1 to RA7: first to seventh resistors; RA8: first power supply resistor; SQ: output signal; SW1 to SW7: first to seventh switches; SW8: first power supply switch; TQ: output terminal; TX: input signal; V1 to V7: first to seventh gate drive voltages; VSS: first power supply voltage; Va: first determination voltage; Vb: second determination voltage; Vc: third determination voltage; Vgate: gate voltage; Vsup: second power supply voltage. DETAILED DESCRIPTION

[0015] Hereinafter, a preferred embodiment of the present disclosure will be described in detail. In addition, the present embodiment described below is not intended to unduly limit the content recited in the claims, and all the structures described in the present embodiment are not necessarily essential structural elements.

[0016] 1. Circuit device

[0017] Figure 1 is a configuration example of the circuit device 100. The circuit device 100 includes an output transistor 110, an output resistor 115, a gate voltage control circuit 120, diodes DD1, DD2, and an output terminal TQ. The circuit device 100 is constituted by, for example, a semiconductor device. The semiconductor device is an integrated circuit device in which circuit elements are integrated on a semiconductor substrate. At this time, the output terminal TQ is a terminal formed on a land of the semiconductor substrate or provided at a package of the semiconductor device.

[0018] The gate voltage control circuit 120 generates the gate voltage Vgate by wave-shaping the input signal TX which is a digital signal of a rectangular wave. At this time, the wave-shaping is controlled by monitoring the gate voltage Vgate. The output transistor 110 and the output resistor 115 constitute an output circuit which outputs the output signal SQ to the output terminal TQ in accordance with the gate voltage Vgate. The diodes DD1, DD2 are provided as protection elements, specifically, to prevent reverse current. The output circuit is, for example, an output circuit of the LIN standard which is a standard of an in-vehicle network, but the use of the output circuit is not limited to LIN. LIN is an abbreviation of Local Interconnect Network.

[0019] The output transistor 110 is provided between a first power supply node NVSS to which a first power supply voltage VSS is supplied and the output terminal TQ. Specifically, the output transistor 110 is an N-type transistor. The source of the output transistor 110 is connected to the first power supply node NVSS, and the drain is connected to the cathode of the diode DD2. The anode of the diode DD2 is connected to the output terminal TQ. The first power supply voltage VSS is a voltage lower than a second power supply voltage Vsup supplied to a second power supply node NVsup. The first power supply voltage VSS is, for example, a ground voltage. The first power supply voltage VSS and the second power supply voltage Vsup are supplied to the circuit device 100 from the outside of the circuit device 100, for example, but can be supplied from a power supply circuit built in the circuit device 100.

[0020] The output resistor 115 is provided between the second power supply node NVsup and the output terminal TQ. Specifically, one end of the output resistor 115 is connected to the second power supply node NVsup, and the other end is connected to the anode of the diode DD1. The cathode of the diode DD1 is connected to the output terminal TQ.

[0021] Figure 2is a waveform chart illustrating the operation of the circuit device 100. The gate voltage control circuit 120 is input with the input signal TX, and controls the gate voltage Vgate of the output transistor 110. Specifically, the gate voltage control circuit 120 compares the gate voltage Vgate with a determination voltage, controls the gate voltage Vgate on the basis of the comparison result and the input signal TX, and thereby outputs an output signal SQ corresponding to the input signal TX to the output terminal TQ. More specifically, the gate voltage control circuit 120 causes the gate voltage Vgate to change at a first temporal voltage change rate after the input signal TX transitions from a high level to a low level. The gate voltage control circuit 120 causes the gate voltage Vgate to change at a second temporal voltage change rate smaller than the first temporal voltage change rate after the gate voltage Vgate reaches a first determination voltage Va. The gate voltage control circuit 120 causes the gate voltage Vgate to change at a third temporal voltage change rate larger than the second temporal voltage change rate after the gate voltage Vgate reaches a second determination voltage Vb higher than the first determination voltage Va.

[0022] Let the timing at which the input signal TX transitions from the high level to the low level be tl, and the timing at which the gate voltage Vgate reaches the first determination voltage Va be t2. The gate voltage control circuit 120 causes the gate voltage Vgate to change at the first temporal voltage change rate during a period from the timing tl to the timing t2. Let the timing at which the gate voltage Vgate reaches the second determination voltage Vb be t3, and the gate voltage control circuit 120 causes the gate voltage Vgate to change at the second temporal voltage change rate during a period from the timing t2 to the timing t3. The gate voltage control circuit 120 causes the gate voltage Vgate to change at the third temporal voltage change rate during a period from the timing t3 to a timing t4 to be described later.

[0023] In addition, the temporal voltage change rate is a change in voltage with respect to time. That is, the temporal voltage change rate corresponds to a slope of a waveform of the gate voltage Vgate in Figure 2 , or a time differential of the gate voltage Vgate. The first to third temporal voltage change rates are positive rates of change. In addition, in the input signal TX in Figure 2 , a logic level before the timing tl is set to a first logic level, and a logic level from the timing tl to the timing t5 is set to a second logic level. In Figure 2 , the first logic level is a high level, and the second logic level is a low level, but the first logic level can be a low level, and the second logic level can be a high level.

[0024] According to the present embodiment, during the period from the timing t2 at which the gate voltage Vgate reaches the first determination voltage Va to the timing t3 at which the gate voltage reaches the second determination voltage Vb, the gate voltage control circuit 120 causes the gate voltage Vgate to change at a second temporal voltage change rate smaller than the first and third temporal voltage change rates. Thereby, it is possible to make the angle at which the output signal SQ starts to drop smooth.

[0025] Specifically, the first determination voltage Va and the second determination voltage Vb are set near the threshold voltage of the output transistor 110 as described later in Figure 5 and the like. When the gate voltage Vgate is near the threshold voltage, the output signal SQ starts to drop, but at this time, the gate voltage Vgate changes at the second temporal voltage change rate which is gentle. Thereby, at the start of the drop of the output signal SQ, the temporal voltage change rate of the output signal SQ becomes small, and the angle at which the drop starts becomes smooth.

[0026] Thus, in the present embodiment, by the gate voltage control circuit 120 monitoring the gate voltage Vgate, it is possible to control the waveform of the gate voltage Vgate near the threshold voltage of the output transistor 110, and thereby to perform effective waveform shaping. By making the angle of the output signal SQ smooth, noise radiated from a signal line through which the output signal SQ is transmitted, for example, is reduced.

[0027] Next, a method of making the angle at which the drop of the output signal SQ ends smooth will be described. The gate voltage control circuit 120 causes the gate voltage Vgate to change at a fourth temporal voltage change rate smaller than the third temporal voltage change rate after the gate voltage Vgate reaches a third determination voltage Vc higher than the second determination voltage Vb. The fourth temporal voltage change rate is a positive change rate.

[0028] If the timing at which the gate voltage Vgate reaches the third determination voltage Vc is set as t4, the gate voltage control circuit 120 causes the gate voltage Vgate to change at the fourth temporal voltage change rate after the timing t4. After the gate voltage Vgate reaches a prescribed voltage, until the timing t5 at which the input signal TX changes from the low level to the high level, the gate voltage Vgate is maintained at the prescribed voltage. As described later in Figure 5 and the like, the prescribed voltage is a fourth gate drive voltage V4 higher than the third determination voltage Vc.

[0029] According to the present embodiment, after the timing t4 at which the gate voltage Vgate reaches the third determination voltage Vc, the gate voltage control circuit 120 causes the gate voltage Vgate to change at a fourth temporal voltage change rate which is smaller than the third temporal voltage change rate. The falling of the output signal SQ ends when the output signal SQ reaches the first power supply voltage VSS, but according to the present embodiment, at the timing t4 at which the output signal SQ approaches the first power supply voltage VSS, the temporal voltage change rate of the gate voltage Vgate becomes the gentle fourth temporal voltage change rate. Thus, at the time when the output signal SQ approaches the first power supply voltage VSS, the temporal voltage change rate of the output signal SQ becomes small, and the angle at which the falling ends becomes rounded.

[0030] As for the angle at which the rising of the output signal SQ starts and ends, the gate voltage control circuit 120 also rounds the angle by the same method as described above.

[0031] Specifically, the gate voltage control circuit 120 causes the gate voltage Vgate to change at a fifth temporal voltage change rate after the input signal TX transitions from the low level to the high level. The gate voltage control circuit 120 causes the gate voltage Vgate to change at a sixth temporal voltage change rate after the gate voltage Vgate reaches the third determination voltage Vc. The gate voltage control circuit 120 causes the gate voltage Vgate to change at a seventh temporal voltage change rate after the gate voltage Vgate reaches the second determination voltage Vb. The gate voltage control circuit 120 causes the gate voltage Vgate to change at an eighth temporal voltage change rate after the gate voltage Vgate reaches the first determination voltage Va. The seventh temporal voltage change rate is smaller than the eighth temporal voltage change rate. The sixth temporal voltage change rate is larger than the seventh temporal voltage change rate. The fifth temporal voltage change rate is smaller than the sixth temporal voltage change rate. In addition, the fifth to eighth temporal voltage change rates are negative change rates, and the above-described size relationship refers to the size relationship in absolute value.

[0032] According to the present embodiment, the output signal SQ starts to rise at the timing t5, but the temporal voltage change rate of the gate voltage Vgate becomes the gentle fifth temporal voltage change rate. Thus, the temporal voltage change rate of the output signal SQ becomes small, and the angle at which the rising starts becomes rounded. In addition, the rising of the output signal SQ ends when the gate voltage Vgate is near the threshold voltage, but at this time, the gate voltage Vgate changes at the gentle seventh temporal voltage change rate. Thus, at the time when the rising of the output signal SQ ends, the temporal voltage change rate of the output signal SQ becomes small, and the angle at which the rising ends becomes rounded.

[0033] 2. Detailed configuration example

[0034] Figure 3A detailed configuration example of the gate voltage control circuit 120 is shown in FIG. 1. The gate voltage control circuit 120 includes a voltage generation circuit 130, a switch control circuit 140, first to seventh switches SW1 to SW7, a first power supply switch SW8, first to seventh resistors RA1 to RA7, a first power supply resistor RA8, and a capacitor CA. Hereinafter, the switches SW1 to SW8 and the resistors RA1 to RA8 are omitted.

[0035] The voltage generation circuit 130 generates the first to third determination voltages Va, Vb, and Vc, and outputs them to the switch control circuit 140. In addition, the voltage generation circuit 130 generates the first to seventh gate drive voltages V1 to V7, and outputs them to the first to seventh nodes N1 to N7.

[0036] The switch SW1 and the resistor RA1 are connected in series between the first node N1 and the gate of the output transistor 110. Specifically, one end of the switch SW1 is connected to the first node N1, and the other end is connected to one end of the resistor RA1. The other end of the resistor RA1 is connected to the gate of the output transistor 110. Similarly, the switches SW2 to SW7 and the resistors RA2 to RA7 are connected in series between the second to seventh nodes N2 to N7 and the gate of the output transistor 110. The switch SW8 and the resistor RA8 are connected between the first power supply node NVSS and the gate of the output transistor 110. The switches SW1 to SW8 are constituted by transistors. The switches SW1 to SW8 can be, for example, P-type transistors or N-type transistors, or can be transfer gates in which P-type transistors and N-type transistors are connected in parallel.

[0037] One end of the capacitor CA is connected to the gate of the output transistor 110, and the other end is connected to the first power supply node NVSS.

[0038] The switch control circuit 140 controls the switches SW1 to SW8 to be turned on or off, based on the input signal TX, the gate voltage Vgate of the output transistor 110, the first to third determination voltages Va, Vb, and Vc. Specifically, the switch control circuit 140 determines whether the gate voltage Vgate reaches the first to third determination voltages Va, Vb, and Vc, by comparing the gate voltage Vgate with the first to third determination voltages Va, Vb, and Vc. Then, the switch control circuit 140 outputs the control signals CSW1 to CSW8 based on the determination result and the logic level of the input signal TX, thereby switching the switches SW1 to SW8 to be turned on or off. The switch control circuit 140 turns on any one of the switches SW1 to SW8, and turns off the switches other than the one.

[0039] For example, when the switch control circuit 140 turns on switch SW1, the first gate drive voltage V1 is output to the gate of the output transistor 110 via resistor RA1, and capacitor CA is charged. At this time, the charging rate of capacitor CA, i.e., the time-voltage change rate of the gate voltage Vgate, is determined according to the first gate drive voltage V1 and the resistance value of resistor RA1. By controlling which of the switches SW1 to SW8 is turned on by the switch control circuit 140, the time-voltage change rate of the gate voltage Vgate can be controlled, enabling [further control / performance]. Figure 2 That kind of waveform is formed.

[0040] Figure 4 This is a waveform diagram illustrating the operation of the gate voltage control circuit 120. Here, it is assumed that switches SW1 to SW8 are turned on when control signals CSW1 to CSW8 are high. VACP is the decision signal for comparator 141, which compares the first decision voltage Va and the gate voltage Vgate; VBCP is the decision signal for comparator 142, which compares the second decision voltage Vb and the gate voltage Vgate; and VCCP is the decision signal for comparator 143, which compares the third decision voltage Vc and the gate voltage Vgate. Regarding comparators 141 to 143, further explanation will follow... Figure 6 As will be discussed later. Comparators 141 to 143 output a high level when the gate voltage Vgate is higher than Va to Vc.

[0041] During the period from the time t1 when the input signal TX changes from high level to low level to the time t2 when the decision signal VCP changes from low level to high level, the switch control circuit 140 sets the control signal CSW1 to high level, thus turning on the switch SW1. At this time, the gate voltage Vgate changes at a first time voltage change rate determined by the first gate drive voltage V1 and the resistance value of the resistor RA1.

[0042] Next, during the period from time t2 until time t3 when the determination signal VBCP changes from low to high, the switch control circuit 140 sets the control signal CSW2 to high, thus turning on the switch SW2. At this time, the gate voltage Vgate changes at a second time-voltage change rate determined by the second gate drive voltage V2 and the resistance value of the resistor RA2.

[0043] Next, during the period from time t3 until time t4 when the determination signal VCCP changes from low to high, the switch control circuit 140 sets the control signal CSW3 to high, thus turning on the switch SW3. At this time, the gate voltage Vgate changes at a third time voltage change rate determined by the third gate drive voltage V3 and the resistance value of the resistor RA3.

[0044] Next, during the period from timing t4 to timing t5 when the input signal TX changes from low to high, the switch control circuit 140 sets the control signal CSW4 to high, thus turning on the switch SW4. At this time, the gate voltage Vgate changes at a fourth time voltage change rate determined by the fourth gate drive voltage V4 and the resistance value of the resistor RA4.

[0045] The resistance values ​​of resistors RA1 to RA4 are related as follows: the resistance of resistor RA2 is greater than that of resistor RA1, the resistance of resistor RA3 is less than that of resistor RA2, and the resistance of resistor RA4 is greater than that of resistor RA3. Therefore, the voltage change rate at the second time becomes smaller than that at the first time, the voltage change rate at the third time becomes larger than that at the second time, and the voltage change rate at the fourth time becomes smaller than that at the third time. For example, in... Figure 2 As explained, because the voltage change rates at the second and fourth time intervals are relatively small, the starting and ending angles of the decline in the output signal SQ become more rounded. Furthermore, because the voltage change rate at the third time interval is relatively large, the decline in the output signal SQ becomes more abrupt.

[0046] Next, during the period from the moment the input signal TX transitions from low to high (t5) until the moment the decision signal VCCP transitions from high to low (t6), the switch control circuit 140 sets the control signal CSW5 to high, thus turning on the switch SW5. At this time, the gate voltage Vgate changes at a fifth time-varying rate determined by the fifth gate drive voltage V5 and the resistance value of the resistor RA5.

[0047] Next, during the period from timing t6 until timing t7 when the determination signal VBCP changes from high to low, the switch control circuit 140 sets the control signal CSW6 to high, thus turning on the switch SW6. At this time, the gate voltage Vgate changes at a sixth time-varying rate determined by the sixth gate drive voltage V6 and the resistance value of resistor RA6.

[0048] Next, during the period from time t7 to time t8 when the decision signal VCP changes from high to low, the switch control circuit 140 sets the control signal CSW7 to high, thus turning on the switch SW7. At this time, the gate voltage Vgate changes at a seventh time voltage change rate determined by the seventh gate drive voltage V7 and the resistance value of the resistor RA7.

[0049] Next, during the period from timing t8 until the input signal TX transitions from high to low, the switch control circuit 140 sets the control signal CSW8 to high, thus turning on the switch SW8. At this time, the gate voltage Vgate changes at an eighth-time voltage change rate determined by the first power supply voltage VSS and the resistance value of resistor RA8.

[0050] The resistance values ​​of resistors RA5 to RA8 are related as follows: the resistance of resistor RA7 is greater than that of resistor RA8, the resistance of resistor RA6 is less than that of resistor RA7, and the resistance of resistor RA5 is greater than that of resistor RA6. Therefore, the voltage change rate at the seventh time becomes smaller than that at the eighth time, the voltage change rate at the sixth time becomes larger than that at the seventh time, and the voltage change rate at the fifth time becomes smaller than that at the sixth time. For example, in... Figure 2 As explained, because the voltage change rates at the fifth and seventh time points are relatively small, the starting and ending angles of the rise in the output signal SQ become more rounded. Furthermore, because the voltage change rate at the sixth time point is relatively large, the rise in the output signal SQ becomes more rapid.

[0051] Figure 5 This is a detailed structural example of the voltage generation circuit 130. The voltage generation circuit 130 includes a first voltage divider circuit 131, a second voltage divider circuit 132, an N-type transistor 133, and a current source circuit 134. Furthermore, the output transistor 110 is assumed to be a first N-type transistor, and the N-type transistor 133 is assumed to be a second N-type transistor.

[0052] The N-type transistor 133 is connected in a diode configuration. That is, the gate and drain of the N-type transistor 133 are connected, and the source is connected to the first power supply node NVSS. Therefore, the drain of the N-type transistor 133 is near its threshold voltage. The N-type transistor 133 is formed using the same process as the output transistor 110, thus its drain is near the threshold voltage of the output transistor 110.

[0053] A first voltage divider circuit 131 is disposed between the drain of the N-type transistor 133 and the first power supply node NVSS. By dividing the drain voltage of the N-type transistor 133 with the first power supply voltage VSS, it generates a first determination voltage Va, a second determination voltage Vb, a first gate drive voltage V1, a sixth gate drive voltage V6, and a seventh gate drive voltage V7. Specifically, the first voltage divider circuit 131 includes resistors RC1 to RC5 connected in series. One end of the series-connected resistors RC1 to RC5 is connected to the drain of the N-type transistor 133, and the other end is connected to the first power supply node NVSS. The second determination voltage Vb is output from the node between resistors RC1 and RC2; the first gate drive voltage V1 is output from the node between resistors RC2 and RC3; the first determination voltage Va is output from the node between resistors RC3 and RC4; and the sixth gate drive voltage V6 is output from the node between resistors RC4 and RC5. The seventh gate drive voltage V7 is output from the other end of the series-connected resistors RC1 to RC5. That is, the seventh gate drive voltage V7 is the first power supply voltage VSS. The voltage magnitudes are in the order Vb > V1 > Va > V6 > V7.

[0054] The drain of the N-type transistor 133 is near the threshold voltage of the output transistor 110, therefore a first determination voltage Va and a second determination voltage Vb are generated based on this threshold voltage. Thus, the first determination voltage Va and the second determination voltage Vb can be set near the threshold voltage of the output transistor 110, as in... Figure 2 As explained, by using these determination voltages, the rate of change of the gate voltage Vgate near the threshold voltage can be controlled. Various relationships can be considered between the first determination voltage Va and the second determination voltage Vb and the threshold voltage of the output transistor 110. As an example, the second determination voltage Vb is set to be the same as the threshold voltage of the output transistor 110. Furthermore, it is sufficient that the second determination voltage Vb is approximately the same as the threshold voltage of the output transistor 110. However, this is not a limitation; for example, the second determination voltage Vb and the first determination voltage Va can be set such that the threshold voltage of the output transistor 110 is between the second determination voltage Vb and the first determination voltage Va.

[0055] The N-type transistor 133 and the output transistor 110 are formed using the same process. Therefore, with respect to process variations, the threshold voltage of the output transistor 110 and the threshold voltage of the N-type transistor 133 tend to deviate in the same way. As a result, the relationship between the first determination voltage Va and the second determination voltage Vb and the threshold voltage of the output transistor 110 is not easily affected by process variations, and waveform shaping that is not easily affected by process variations is possible.

[0056] The second voltage divider circuit 132 is disposed between the drain of the N-type transistor 133 and the second power supply node NVsup. It generates a third determination voltage Vc, a second gate drive voltage V2, a third gate drive voltage V3, a fourth gate drive voltage V4, and a fifth gate drive voltage V5 by dividing the drain voltage of the N-type transistor 133 with the second power supply voltage Vsup. Specifically, the second voltage divider circuit 132 includes resistors RB1 to RB5 connected in series. One end of the current source circuit 134 is connected to the second power supply node NVsup, and the other end is connected to one end of the series-connected resistors RB1 to RB5. The other end of the series-connected resistors RB1 to RB5 is connected to the drain of the N-type transistor 133. The second gate drive voltage V2 is output from one end of the series-connected resistors RB1 to RB5. The third gate drive voltage V3 is output from the node between resistors RB1 and RB2, the fourth gate drive voltage V4 is output from the node between resistors RB2 and RB3, the third decision voltage Vc is output from the node between resistors RB3 and RB4, and the fifth gate drive voltage V5 is output from the node between resistors RB4 and RB5. The magnitudes of the voltages are in the order V2 > V3 > V4 > Vc > V5 > Vb.

[0057] The third determination voltage Vc is also generated based on the threshold voltage. Therefore, the relationship between the third determination voltage Vc and the threshold voltage of the output transistor 110 is not easily affected by process variations, and waveform shaping that is not easily affected by process variations can be performed.

[0058] Regarding the voltages related to the drop in output signal SQ, the order is: V2 > V3 > V4 > Vc > Vb > V1 > Va. Since V1 > Va, V1 is selected by turning on switch SW1, and the gate voltage Vgate reaches Va. Furthermore, since V2 > Vb, V2 is selected by turning on switch SW2, and the gate voltage Vgate reaches Vb. Additionally, since V3 > Vc, V3 is selected by turning on switch SW3, and the gate voltage Vgate reaches Vc. Finally, V4 is selected by turning on switch SW4, and the gate voltage Vgate rises from Vc to V4, then remains at V4.

[0059] Regarding the voltages related to the rise of the output signal SQ, Vc > V5 > Vb > Va > V6 > V7 = VSS. Since Vc > V5, V5 is selected by turning on switch SW5, and the gate voltage Vgate reaches Vc. Furthermore, since Vb > V6, V6 is selected by turning on switch SW6, and the gate voltage Vgate reaches Vb. Additionally, since Va > V7, V7 is selected by turning on switch SW7, and the gate voltage Vgate reaches Va. Finally, VSS is selected by turning on switch SW8, and the gate voltage Vgate drops from Va to VSS, then remains at VSS.

[0060] Figure 6 This is a detailed structural example of the switch control circuit 140. The switch control circuit 140 includes comparators 141 to 143, an output circuit 144, and inverters IVC1 to IVC5.

[0061] Comparator 141 determines whether the gate voltage Vgate is higher than the first determination voltage Va, and outputs a determination signal VACP as the result. Comparator 142 determines whether the gate voltage Vgate is higher than the second determination voltage Vb, and outputs a determination signal VBCP as the result. Comparator 143 determines whether the gate voltage Vgate is higher than the third determination voltage Vc, and outputs a determination signal VCCP as the result.

[0062] Inverter IVC1 logically inverts the input signal TX, outputting the result signal XTX. Inverter IVC2 logically inverts the signal XTX, outputting the result signal TXI. Inverter IVC3 logically inverts the decision signal VCP, outputting the result signal XVACP. Inverter IVC4 logically inverts the decision signal VBCP, outputting the result signal XVBCP. Inverter IVC5 logically inverts the decision signal VCCP, outputting the result signal XVCCP.

[0063] The output circuit 144 outputs control signals CSW1 to CSW8 based on signals XTX, XTI, XVACP, VCP, XVBCP, VBCP, XVCCP, and VCCP.

[0064] Figure 7 This is a detailed structural example of output circuit 144. Output circuit 144 includes AND circuits ANE1 to ANE8, inverter IVE1, OR circuits ORE2 and ORE3, inverters IVE4 and IVE5, OR circuits ORE6 and ORE7, and inverter IVE8.

[0065] When signals XTX and XVACP are high, inverter IVE1 outputs a high-level control signal CSW1. That is, when input signal TX and decision signal VCP are low, switch SW1 is on. When signals VCP and XVBCP are high and signal TXI is low, or circuit ORE2 outputs a high-level control signal CSW2. That is, when input signal TX is low, decision signal VCP is high, and decision signal VBCP is low, switch SW2 is on. When signals VBCP and XVCCP are high and signal TXI is low, or circuit ORE3 outputs a high-level control signal CSW3. That is, when input signal TX is low, decision signal VBCP is high, and decision signal VCCP is low, switch SW3 is on. When signals XTX and VCCP are high, inverter IVE4 outputs a high-level control signal CSW4. That is, when input signal TX is low and decision signal VCCP is high, switch SW4 is on.

[0066] Similarly, when the input signal TX and the decision signal VCCP are high, switch SW5 is turned on. When the input signal TX is high, the decision signal VCCP is low, and the decision signal VBCP is high, switch SW6 is turned on. When the input signal TX is high, the decision signal VBCP is low, and the decision signal VCP is high, switch SW7 is turned on. When the input signal TX is high and the decision signal VCP is low, switch SW8 is turned on. As described above, output circuit 144 outputs... Figure 4 The signal waveform.

[0067] The circuit arrangement of this embodiment described above includes an output terminal, an output transistor, and a gate voltage control circuit. The output transistor is disposed between the output terminal and a first power supply node supplied with a first power supply voltage. The gate voltage control circuit receives an input signal and controls the gate voltage of the output transistor. After the input signal transitions from a first logic level to a second logic level, the gate voltage control circuit causes the gate voltage to change at a first time-voltage change rate. After the gate voltage reaches a first determination voltage, the gate voltage control circuit causes the gate voltage to change at a second time-voltage change rate that is smaller than the first time-voltage change rate. After the gate voltage reaches a second determination voltage that is higher than the first determination voltage, the gate voltage control circuit causes the gate voltage to change at a third time-voltage change rate that is larger than the second time-voltage change rate.

[0068] According to this embodiment, after the gate voltage reaches the first determination voltage, until the second determination voltage is reached, the gate voltage control circuit causes the gate voltage to change at a second time voltage change rate that is smaller than both the first and third time voltage change rates. As a result, the change in the output signal output by the output transistor to the output terminal becomes smoother. Specifically, the angle at which the drop in the output signal begins can be rounded.

[0069] Furthermore, in this embodiment, the gate voltage control circuit may also cause the gate voltage to change at a fourth time voltage change rate that is smaller than the third time voltage change rate after the gate voltage reaches a third time voltage that is higher than the second time voltage change rate.

[0070] When the output signal reaches the first power supply voltage, the decline of the output signal ends. According to this embodiment, after the gate voltage reaches the third determination voltage, the time-voltage change rate of the gate voltage becomes a gentler fourth time-voltage change rate. Therefore, as the output signal approaches the first power supply voltage, the time-voltage change rate of the output signal decreases, and the angle at which the decline ends becomes more rounded.

[0071] Furthermore, in this embodiment, the gate voltage control circuit may also include a voltage generation circuit, a first switch, a first resistor, a second switch, a second resistor, a third switch, a third resistor, a first power supply switch, a first power supply resistor, a capacitor, and a switch control circuit. The voltage generation circuit may also generate a first determination voltage, a second determination voltage, a first gate drive voltage between the first and second determination voltages, a second gate drive voltage higher than the second determination voltage, and a third gate drive voltage. The first switch and the first resistor may also be connected in series between the first node outputting the first gate drive voltage and the gate of the output transistor. The second switch and the second resistor may also be connected in series between the second node outputting the second gate drive voltage and the gate. The third switch and the third resistor may also be connected in series between the third node outputting the third gate drive voltage and the gate. The first power supply switch and the first power supply resistor may also be connected in series between the first power supply node and the gate. One end of the capacitor may also be connected to the gate. The switch control circuit may also control the first to third switches and the first power supply switch to be on or off based on the input signal, the gate voltage, the first determination voltage, and the second determination voltage.

[0072] According to this embodiment, when the switch control circuit turns on the first switch, the first gate drive voltage is output to the gate of the output transistor via the first resistor, and the capacitor is charged. At this time, the charging rate of the capacitor is determined by the first gate drive voltage and the resistance value of the first resistor. That is, the gate voltage changes at a first time-voltage change rate. Similarly, when the switch control circuit turns on the second switch, the gate voltage changes at a second time-voltage change rate, and when the switch control circuit turns on the third switch, the gate voltage changes at a third time-voltage change rate. In this way, the time-voltage change rate of the gate voltage is controlled by which switch is turned on.

[0073] In addition, in this embodiment, the resistance value of the second resistor may be greater than the resistance value of the first resistor. The resistance value of the third resistor may be less than the resistance value of the second resistor.

[0074] According to this embodiment, the voltage change rate at the second time is smaller than the voltage change rate at the first time, and the voltage change rate at the third time is larger than the voltage change rate at the second time.

[0075] Furthermore, in this embodiment, the switch control circuit may also change the first power supply switch from on to off, and the first switch from off to on, when the input signal changes from a first logic level to a second logic level. Alternatively, the switch control circuit may change the first switch from on to off, and the second switch from off to on, when the gate voltage reaches a first determination voltage. Conversely, the switch control circuit may change the second switch from on to off, and the third switch from off to on, when the gate voltage reaches a second determination voltage.

[0076] According to this embodiment, since the first switch is turned on when the input signal changes from a first logic level to a second logic level, the first gate drive voltage is output to the gate of the output transistor via the first resistor, and the gate voltage changes with a first time-voltage change rate. Since the second switch is turned on when the gate voltage reaches a first determination voltage, the second gate drive voltage is output to the gate of the output transistor via the second resistor, and the gate voltage changes with a second time-voltage change rate. Since the third switch is turned on when the gate voltage reaches a second determination voltage, the third gate drive voltage is output to the gate of the output transistor via the third resistor, and the gate voltage changes with a third time-voltage change rate.

[0077] Alternatively, in this embodiment, the voltage generation circuit may also generate a fourth gate drive voltage that is higher than the third determination voltage, which is higher than the second determination voltage. The gate voltage control circuit may also include a fourth switch and a fourth resistor connected in series between the fourth node that outputs the fourth gate drive voltage and the gate.

[0078] According to this embodiment, when the switch control circuit turns on the fourth switch, the fourth gate drive voltage is output to the gate of the output transistor via the fourth resistor, and the gate voltage changes with the fourth time voltage change rate.

[0079] In addition, in this embodiment, the resistance value of the fourth resistor may also be greater than the resistance value of the third resistor.

[0080] According to this embodiment, the fourth time voltage change rate is less than the third time voltage change rate. Therefore, at the end of the output signal's decline, the gate voltage of the output transistor changes at a gradual time voltage change rate, thus rounding the angle at which the output signal's decline ends.

[0081] In addition, the switch control circuit can also change the third switch from on to off and the fourth switch from off to on when the gate voltage reaches the third determination voltage.

[0082] According to this embodiment, since the fourth switch is turned on when the gate voltage reaches the third determination voltage, the fourth gate drive voltage is output to the gate of the output transistor via the fourth resistor, and the gate voltage changes with the fourth time voltage change rate.

[0083] Alternatively, the circuit arrangement of this embodiment may also include an output resistor disposed between an output terminal and a second power supply node that is supplied with a second power supply voltage higher than the first power supply voltage.

[0084] According to this embodiment, an output circuit is formed by an output resistor disposed between the second power node and the output terminal and an output transistor disposed between the output terminal and the first power node, and an output signal corresponding to the gate voltage of the output transistor is output to the output terminal.

[0085] Furthermore, in this embodiment, the output transistor may also be a first N-type transistor. The first determination voltage and the second determination voltage may also be set based on the threshold voltage of the second N-type transistor.

[0086] According to this embodiment, the threshold voltages of the output transistor and the second N-type transistor tend to deviate in approximately the same manner relative to process variations. Furthermore, since the first and second determination voltages are set based on the threshold voltage of the second N-type transistor, the relationship between the threshold voltage of the output transistor and the first and second determination voltages is less susceptible to process variations. Therefore, waveform shaping that is less affected by process variations is possible.

[0087] Furthermore, in this embodiment, the first determination voltage and the second determination voltage can also be set according to the drain voltage of the second N-type transistor connected in a diode manner.

[0088] The drain voltage of the second N-type transistor, which is connected in a diode configuration, is near the threshold voltage of the second N-type transistor. Therefore, the first determination voltage and the second determination voltage are set based on the threshold voltage of the second N-type transistor.

[0089] Furthermore, in this embodiment, the output transistor may also be a first N-type transistor. The voltage generation circuit may also include a second N-type transistor connected in a diode configuration, a first voltage divider circuit, and a second voltage divider circuit. The first voltage divider circuit may also be disposed between the drain of the second N-type transistor and the first power supply node, generating a first determination voltage, a second determination voltage, and a first gate drive voltage by dividing the drain voltage of the second N-type transistor and the first power supply voltage. The second voltage divider circuit may also be disposed between the drain of the second N-type transistor and a second power supply node supplied with a second power supply voltage higher than the first power supply voltage, generating a second gate drive voltage and a third gate drive voltage by dividing the second power supply voltage and the drain voltage of the second N-type transistor.

[0090] According to this embodiment, a first determination voltage, a second determination voltage, a first gate drive voltage, a second gate drive voltage, and a third gate drive voltage can be generated based on the drain voltage of the second N-type transistor near the threshold voltage.

[0091] Furthermore, while this embodiment has been described in detail above, those skilled in the art will readily understand that various modifications can be made without substantially departing from the novel aspects and effects of this disclosure. Therefore, all such modifications are included within the scope of this disclosure. For example, in the specification or drawings, a term described at least once with a broader or synonymous term can be replaced with that different term anywhere in the specification or drawings. Additionally, all combinations of this embodiment and its modifications are also included within the scope of this disclosure. Furthermore, the structure and operation of circuit devices, etc., are not limited to the structures and operations described in this embodiment, and various modifications can be implemented.

Claims

1. A circuit arrangement, characterized by The circuit device includes: an output terminal; an output transistor provided between a first power supply node to which a first power supply voltage is supplied and the output terminal; and a gate voltage control circuit that controls a gate voltage of the output transistor, the gate voltage control circuit causes the gate voltage to change at a first temporal voltage change rate after the input signal transitions from a first logic level to a second logic level, causes the gate voltage to change at a second temporal voltage change rate smaller than the first temporal voltage change rate after the gate voltage reaches a first determination voltage, causes the gate voltage to change at a third temporal voltage change rate larger than the second temporal voltage change rate after the gate voltage reaches a second determination voltage higher than the first determination voltage, the gate voltage control circuit includes: a voltage generation circuit that generates the first determination voltage, the second determination voltage, a first gate drive voltage between the first determination voltage and the second determination voltage, and a second gate drive voltage and a third gate drive voltage higher than the second determination voltage; a first switch and a first resistor connected in series between a gate of the output transistor and a first node that outputs the first gate drive voltage; a second switch and a second resistor connected in series between the gate and a second node that outputs the second gate drive voltage; a third switch and a third resistor connected in series between the gate and a third node that outputs the third gate drive voltage; a first power supply switch and a first power supply resistor connected in series between the first power supply node and the gate; and a switch control circuit that controls the first switch to the third switch and the first power supply switch to be turned on or off in accordance with the input signal, the gate voltage, the first determination voltage, and the second determination voltage.

2. The circuit device according to claim 1, wherein the gate voltage control circuit causes the gate voltage to change at a fourth temporal voltage change rate smaller than the third temporal voltage change rate after the gate voltage reaches a third determination voltage higher than the second determination voltage.

3. The circuit device according to claim 1, wherein the gate voltage control circuit includes a capacitor having one end connected to the gate.

4. The circuit device according to claim 1, wherein a resistance value of the second resistor is larger than a resistance value of the first resistor, a resistance value of the third resistor is smaller than the resistance value of the second resistor.

5. The circuit device according to claim 1, wherein the switch control circuit causes the first power supply switch to be turned off and the first switch to be turned on when the input signal transitions from the first logic level to the second logic level, causes the first switch to be turned off and the second switch to be turned on when the gate voltage reaches the first determination voltage, and causes the second switch to be turned off and the third switch to be turned on when the gate voltage reaches the second determination voltage. ​ The second switch is changed from on to off and the third switch is changed from off to on when the gate voltage reaches the second determination voltage.

6. The circuit device according to claim 1, wherein the voltage generation circuit generates a fourth gate drive voltage that is higher than a third determination voltage that is higher than the second determination voltage, the gate voltage control circuit includes a fourth resistance and a fourth switch connected in series between the gate and a fourth node that outputs the fourth gate drive voltage.

7. The circuit device according to claim 6, wherein the fourth resistance has a resistance value that is greater than the resistance value of the third resistance.

8. The circuit device according to claim 6, wherein the switch control circuit changes the third switch from on to off and changes the fourth switch from off to on when the gate voltage reaches the third determination voltage.

9. The circuit device according to any one of claims 1 to 8, wherein the circuit device includes an output resistance provided between a second power supply node that is supplied with a second power supply voltage that is higher than the first power supply voltage and the output terminal.

10. The circuit device according to any one of claims 3 to 8, wherein the output transistor is a first N-type transistor, the voltage generation circuit includes: a second N-type transistor connected in diode form; a first voltage dividing circuit provided between a drain of the second N-type transistor and the first power supply node, which generates the first determination voltage, the second determination voltage, and the first gate drive voltage by voltage dividing between a voltage of the drain of the second N-type transistor and the first power supply voltage; and a second voltage dividing circuit provided between the drain of the second N-type transistor and a second power supply node that is supplied with a second power supply voltage that is higher than the first power supply voltage, which generates the second gate drive voltage and the third gate drive voltage by voltage dividing between the second power supply voltage and the voltage of the drain of the second N-type transistor.

11. The circuit device according to claim 10, wherein the first determination voltage and the second determination voltage are set in accordance with a threshold voltage of the second N-type transistor.

12. The circuit device according to claim 11, wherein the first determination voltage and the second determination voltage are set in accordance with a voltage of the drain of the second N-type transistor. ​

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