DC detector for transmit data path

Abstract

The present disclosure relates to a DC detector for a transmission data path. A transmitter with a DC detection circuit can control when the transmitter's operator is activated. When transmitting data, the tone introduced by the mixer in the transmission path is hidden by the data signal and has minimal impact on the transmission path. However, when there is no data, the tone causes unwanted noise. The modulator can emit a tone or noise that exceeds the bandwidth of the transmitter. Since the data can hide the tone, the DSM is only required when a DC signal is present. By activating the DSM only when a DC signal is detected, the additional power introduced by the modulator can be reduced while eliminating in-band noise.

Description

[0001] Incorporation of any priority application

[0002] This application claims priority to U.S. Provisional Application No. 63 / 062,942, filed on August 7, 2020, entitled “DC DETECTOR FOR TRANSMITTING DATA,” the disclosure of which is incorporated herein by reference in its entirety for all purposes. Any and all applications for which a foreign or domestic priority claim is identified in the Application Data Sheet filed with this application are hereby incorporated by reference pursuant to 37 CFR 1.57. Technical Field

[0003] Embodiments of the present disclosure relate to a transmit data path, and more particularly, to a DC detector for a transmit data path including a delta-sigma modulator. Summary of the invention

[0004] The systems, methods, and devices of the present disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein. The details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below.

[0005] Certain aspects of the present disclosure relate to a transmitter including a transmission data path capable of reducing a signal-to-noise ratio while maintaining or reducing power consumption compared to existing transmitter designs. The transmitter may include: a filter chain configured to process a transmit signal; a modulator configured to convert the transmit signal into a digital transmit signal when enabled; a digital-to-analog converter configured to convert the digital transmit signal into an analog signal; and a DC detector configured to determine a percentage of a DC component within the transmit signal and enable the modulator when the percentage of the DC component meets a DC threshold.

[0006] The transmitter of the preceding paragraph may include any combination and / or sub-combination of the following features: wherein the modulator is a delta-sigma modulator; wherein the DC detector is configured to determine a percentage of a DC component within a sampling window of the transmit signal; wherein the DC detector includes a sample comparator configured to compare a first sample obtained from the transmit signal and a second sample obtained from the transmit signal; wherein the first sample and the second sample include consecutive samples in a series of samples obtained from the transmit signal; wherein the DC detector also includes an accumulator configured to accumulate samples of the transmit signal corresponding to the sample window; wherein the accumulator includes an infinite impulse response (IIR) aggregator; wherein the accumulator is also configured to determine a DC count, the DC count including a count of consecutive samples within an equal sampling window determined by the DC detector; wherein the accumulator is also configured to determine a percentage of DC within the sample window based at least in part on the DC count; wherein the DC detector also includes a threshold comparator configured to: determine whether the DC count satisfies the DC threshold; and when the DC count satisfies the DC threshold, output an enable signal to enable the modulator; and wherein the transmitter also includes a register configured to store a DC threshold.

[0007] Additional aspects of the present disclosure relate to wireless devices, such as smartphones, tablets, laptops, or other computing devices that may include a transceiver or transmitter. A wireless device may include: an antenna configured to transmit a radio frequency signal; and a transmitter configured to generate the radio frequency signal for transmission by the antenna. The transmitter may include: a filter chain configured to process a transmit signal; a modulator configured to convert the transmit signal to a digital transmit signal when enabled; a digital-to-analog converter configured to convert the digital transmit signal to an analog signal; and a DC detector configured to determine a percentage of a DC component within the transmit signal and enable the modulator when the percentage of the DC component meets a DC threshold.

[0008] The wireless device described in the preceding paragraph may include any combination and / or sub-combination of the following features: wherein the modulator is a delta-sigma modulator; wherein the DC detector is configured to determine the percentage of a DC component within a sampling window of the transmitted signal; wherein the DC detector includes a sample comparator configured to compare a first sample obtained from the transmitted signal and a second sample obtained from the transmitted signal; wherein the first sample and the second sample include consecutive samples in a series of samples obtained from the transmitted signal; wherein the DC detector also includes an accumulator configured to accumulate samples of the transmitted signal corresponding to the sample window; wherein the accumulator includes an infinite impulse response (IIR) aggregator; wherein the accumulator is also configured to determine a DC count, the DC count including a count of consecutive samples within an equal sampling window determined by the DC detector; wherein the accumulator is also configured to determine the percentage of DC within the sample window based at least in part on the DC count; wherein the DC detector also includes a threshold comparator configured to: determine whether the DC count satisfies the DC threshold; and when the DC count satisfies the DC threshold, output an enable signal to enable the modulator; and wherein the wireless device also includes a register configured to store a DC threshold.

[0009]

[0013] Additional aspects of the present disclosure relate to a method of reducing power consumption in a transmitter. The method is implemented at least in part by a hardware-implemented DC detector. The method may include: receiving a first sample of a transmit signal within a sample window; receiving a second sample of the transmit signal within the sampling window; determining whether the first sample and the second sample are the same; in response to determining that the first sample and the second sample are the same, increasing a DC count; determining whether the DC count satisfies a DC threshold; and in response to determining that the DC count satisfies the DC threshold, enabling a modulator within a transmit path of the transmitter.

[0010] The method of the preceding paragraph may include any combination and / or sub-combination of the following features: wherein, in response to determining that the DC count does not meet the DC threshold, the method may also include enabling a modulator; wherein determining whether the first sample and the second sample are the same includes determining that the difference between the first sample and the second sample does not exceed a threshold difference; wherein the first sample and the second sample are consecutive samples; wherein the method may also include receiving one or more additional samples within the sample window, wherein determining whether the first sample and the second sample are the same includes determining whether the first sample, the second sample, and the one or more additional samples are the same, and wherein in response to determining that the first sample, the second sample, and the one or more additional samples are the same, the DC count increases; and wherein the method may also include: receiving a third sample within the sample window; determining whether the second sample and the third sample are the same; and in response to determining that the second sample and the third sample are the same, increasing the DC count, wherein the second sample and the third sample are consecutive samples. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Throughout the drawings, reference numerals are re-used to indicate corresponding relationships between reference elements.The drawings are provided to illustrate embodiments of the subject matter described herein and not to limit the scope thereof.

[0012] Figure 1 An example portion of a transmit data path that uses added bits to improve signal-to-noise ratio (SNR) and / or digital-to-analog converter (DAC) resolution is described.

[0013] Figure 2 An example portion of a transmit data path including a delta-sigma modulator (DSM) to reduce in-band noise is illustrated in accordance with certain embodiments.

[0014] Figure 3 An example portion of a transmit data path including a delta-sigma modulator (DSM) and a DC detection circuit is illustrated in accordance with certain embodiments.

[0015] Figure 4 An example implementation of a DC detection circuit in accordance with certain embodiments is illustrated.

[0016] Figure 5 The diagram shows that according to some embodiments, Figure 4 The DC detector circuit performs the DC detection process.

[0017] Figure 6 A simulation of the operation of a DC detector according to certain embodiments is illustrated. DETAILED DESCRIPTION

[0018] The following detailed description of the embodiments presents various descriptions of specific embodiments of the present invention. However, the present invention can be implemented in a variety of different ways. In this description, reference is made to the accompanying drawings, in which the same reference numerals may indicate the same or functionally similar elements. It should be understood that the elements shown in the figures are not necessarily drawn to scale. In addition, it should be understood that some embodiments may include more elements than a subset of the elements shown in the accompanying drawings and / or the accompanying drawings. In addition, some embodiments may combine any suitable combination of features from two or more accompanying drawings.

[0019] Wireless devices such as smart phones, tablet devices, or medical devices can communicate with base stations or other wireless devices using radio frequency (RF) signals. A wireless device may include a transceiver responsible for communicating with a base station or other device. A transceiver may include a transmission chain or transmission data path that processes data signals for transmission.

[0020] Figure 1 An example portion of a transmission data path 100 is illustrated. The transmission data path may receive and process a signal from a baseband integrated circuit (not shown). Among other elements, the transmit path may include a filter chain 102 with interpolation that filters the signal and provides the filtered signal to a truncation circuit 104 element. The truncation circuit 104 may truncate signal bits. Truncation of signal bits may include discarding bits that are less significant than the least significant bit desired. The truncated signal may then be provided to a digital-to-analog converter (DAC) 106.

[0021] In some use cases, it is desirable to improve Figure 1 The signal-to-noise ratio (SNR) achieved by the transmit data path 100 is shown. One way to improve the SNR and / or DAC resolution is to use additional bits. Another way is to increase the sampling rate of the DAC. While both of these methods can improve the SNR, the additional resolution and / or sampling can also increase the power required by the transmit path. This increased power can be significant. For example, for each additional bit, the power used or required by the transmit data path may double. Typically, at least 3-4 additional bits may be required to obtain sufficient SNR improvement for a particular application, resulting in up to an 8x increase in power used or required.

[0022] Furthermore, the truncation performed by the truncation circuitry often does not allow the circuit to accurately obtain the desired value. Instead, the signal is often truncated to the resolution of the DAC.

[0023] also, Figure 1The transmit path 100 of FIG. 100 typically does not meet the desired local oscillator (LO) leakage specification. The DAC is typically followed by a mixer (not shown). The LO leakage causes a tone to appear at the mixer frequency following the DAC. For example, the specification may be approximately -82dBFS (decibels relative to full scale or decibels below full scale) for a tone at the mixer frequency. In other words, in some cases, the specification may require the allowed noise power to be -82dBFS or less. However, for a 14-bit DAC (using 1-bit sign and 13-bit data), Figure 1 The transmission path may only be -78dBFS (6*13). Since the digital is signed, the full scale may be half the range. During communication with no data traffic, 0 is usually communicated through the transmission path and we get -78dBFS at the output, which does not meet the specification of -82dBFS.

[0024] The mixer after the DAC up-converts the data signal by the local oscillator (LO) frequency. An accurate input with an accurate signal level is required to the mixer so that the signal is 0. Therefore, the DAC has an offset adjustment to make the signal 0 when there is no data transmission. However, when the step size of the adjustment is too large, which is usually the case, it is difficult to set the signal to exactly 0. Instead, there will be some small offset. This offset is up-converted by the mixer, resulting in undesirable tones.

[0025] One solution to problems associated with bad tonality is to use an analog compensation DAC, which is added to the Figure 1 The output of the two DACs can be summed to help compensate for the tone. However, having two DACs introduces significant complexity and adds significant area and power requirements.

[0026] Another solution is to modulate the input of the DAC. Embodiments of the present disclosure include a transmit path capable of modulating a signal before it is provided to the DAC.

[0027] Figure 2 FIG. 2 illustrates an example portion of a transmission data path 200 including a delta-sigma modulator (DSM) 204 for reducing in-band quantization noise in accordance with some embodiments. The DSM 204 may replace Figure 1104 elements of the truncation circuit. Thus, the filter chain 102 can provide the filtered transmit signal to the DSM 204, which can perform delta-sigma modulation on the signal before providing the digital signal to the DAC 106. The output of the DAC 106 can then be provided to the mixer 206 to up-convert the signal using a local oscillator (LO) signal. When the transmission data path 200 sends a DC signal, the DSM 204 can modulate the signal to generate an output including a varying amplitude signal instead of a constant DC signal. The output average of many samples may have the same amount of DC as the input DC level. The DSM modulation can be performed at a relatively high rate so that noise or tones are pushed outside the bandwidth of the DAC. For example, the DSM 204 can run at the same rate as the DAC rate. The DAC rate can be 4 GHz. However, the DAC rate is not limited thereto and other rates (e.g., 2 GHz, 6 GHz, etc.) can be used.

[0028] Although using a DSM 204 can solve many of the above problems, the DSM 204 typically uses additional power proportional to the DAC sampling rate. If the DAC is running at a high rate, the additional power can be significant. For a high-speed DAC, the power required by the DSM and DAC together can approach the amount of power required by a high-precision DAC. For example, on average, some DACs may use or require 300 milliwatts (mW) to operate. In addition, some DSMs may use 10-12mW to operate. Therefore, the combination of the DAC and DSM may use 310mW or more of power. A high-precision DAC may use 2-300mW more power than the combined DAC and DSM.

[0029] Therefore, certain embodiments of the present disclosure include a DC detection circuit that can control when the DSM is activated. When transmitting data, the tones introduced by the offset are hidden by the data signal and have minimal impact on the transmission path. Therefore, the DSM may only be needed when a DC signal is present. By activating the DSM only when a DC signal is detected, additional power can be reduced while eliminating in-band noise. The amount of power reduced can vary depending on the ratio of data to DC signals over a period of time or during transmission. In some cases, the use of a DC detection circuit can reduce power by up to 10% or more.

[0030] Figure 3 An example portion of a transmission data path 300 including a delta-sigma modulator 204 (DSM) and a DC detection circuit 308 is illustrated in accordance with certain embodiments. Figure 3The transmit path 300 may be configured to turn on or enable the DSM 204 when a DC signal above a threshold amount is detected within a window of bits or samples. The DSM 204 circuit may be deactivated when a DC signal less than a threshold amount is detected within the sample window. The digital chain or filter chain 102 may also use less power when receiving a DC signal because there are fewer signal transitions when the transmit path 300 is processing the same value. Thus, when the DSM 204 is activated, additional power may be used to power the DSM 204 without significantly increasing the overall system power or the power required to operate the transmit data path 300. When real data or non-DC signals are being transmitted, as determined by the DC detection circuit 308, the DSM 204 may be automatically deactivated, helping to reduce power consumption of the transmit data path 300.

[0031] Thus, the present disclosure provides a way to build a hybrid DAC with relatively low system power that can operate at higher resolution when needed, such as when a DC signal is detected. In addition, since the transmitted data typically introduces sufficient randomness and momentum in the code processed by the DAC 106, on average, the correct value is provided to the DAC 106 at the expected frequency.

[0032] DSM 204 can be used as a high-speed sampling system. DSM 204 can be used due to Figure 1 The DSM 204 can be placed before the DAC 106 to reduce the DAC in-band noise. In addition, the use of the DSM 204 can be equivalent to increasing the DAC resolution, but has the advantage of not increasing the DAC power or the power consumed by the transmission data path 300. In addition, the DSM 204 can be configured to maintain the same signal delay whether it is enabled or disabled. In some embodiments, the DSM 204 can include an internal bypass path. The bypass path can include multiple delay elements, such as registers or flip-flops, which delay the signal by an amount equal to the delay introduced by the functional path of the DSM 204. Therefore, in some embodiments, whether the DSM 204 is active and the signal is processed by the functional path, or whether the DSM 204 is inactive and the signal is passed through the bypass path, the signal delay can be the same.

[0033] Figure 4An example implementation of a DC detection circuit 308 according to certain embodiments is illustrated. The DC detection circuit 308 or DC detector 308 may be located at the output of a digital up converter (DUC) band adder 404 and may be used to detect DC in TX data. The DUC adder 404 may sum the outputs of a pair of digital up converters (DUCs) 406 and 408. This pair of DUCs 406, 408 may be used to support carrier aggregation. Although two DUCs are illustrated, the transmission data path may include more or fewer DUCs. For example, the transmission data path may include 3 or 4 DUCs to support carrier aggregation of 3 or 4 transmit frequency bands. In some cases, such as when only a single-band signal is supported, there may be only one DUC. In some such cases, the band adder 404 may be omitted. In some cases, there may be multiple DUCs to support carrier aggregation, but when non-carrier aggregation transmission is used, one or more DUCs may be inactive. In some such cases, the input to the band adder 404 from the deactivated or inactive DUC may be 0 and the output of the band adder 404 may be equal to an active DUC. The DC detector 308 may include a sample comparator 410 that compares two consecutive samples. When the samples are the same value, the sample comparator 410 may assert its output, or provide an output signal indicating that the consecutive samples are the same to an IIR aggregator 412 (which may be an accumulator). In some embodiments, the accumulator may be an IIR (infinite impulse response) aggregation circuit.

[0034] The DC detector 308 can check a specific number or a programmable number of samples (e.g., 1024, 2048, etc.) to determine whether to activate or enable the DSM 204. The DC detector 308 counts the number of times that consecutive samples are equal. The number of samples can be referred to as a sample window. The size of the sample window can be provided to the IIR aggregator 412 as an input 414 by a control system (not shown) and / or can be read from a control register. The DC detector 308 checks or checks a programmable number of data samples (1024) and counts the number of times that consecutive samples are equal. The IIR aggregator 412 can accumulate the number of samples equal to the sample window. The IIR aggregator 412 can aggregate the number of occurrences within the window in which the sample comparator 410 detects the same consecutive samples in a series of samples obtained from the transmitted signal or the signal to be transmitted. In some cases, samples with a difference less than a threshold amplitude can be considered to be the same. In other words, the sample comparator 410 can have a tolerance equal to the threshold amplitude difference.

[0035] The IIR aggregator 412 can look at the current value (or current window) and the older value (or older window, such as a previous window). Thus, the system can take into account some historical quantities in the signal. Although the sample window for each observation generally remains the same, the leakage factor (described below) can contribute to the calculation of past windows in the current calculation. Thus, in effect, it is as if the DC detector 308 is observing a much larger window. When the signal changes rapidly, looking at only one window may not be enough to detect the DC level in the signal. In some such cases, the leakage factor enables the DC detector 308 to widen the observation window.

[0036] IIR aggregator 412 may be a 32-bit accumulator with a variable forgetting factor (which may be referred to as a "leakage factor") specified by register IIR_LEAK[3:0]. The leakage factor may indicate the amount of history to be considered when determining the DC value in the signal. The function of IIR may be expressed in Equation 1 as:

[0037] Equation 1

[0038] NEXT_IIR[31:0]=IIR[31:0]+(Accumulator[10:0]<<(21-IIR_LEAK[3:

[0039] 0]))–IIR[31:(IIR_LEAK[3:0])]

[0040] IIR[31:0] is a 1.31 unsigned fractional number representing the percentage of DC samples in the TX stream. These values ​​may include 0x8000_0000 = 100%, 0x4000_0000 = 50%, etc. Typically, overflow detection is not required because sufficient leakage can be configured from the IIR aggregator 412 (which may be an accumulator) so that it does not overflow.

[0041] From a sampling window (eg, a window of 1024 samples), the IIR aggregator 412 can output the percentage of adjacent samples that are identical. The percentage of adjacent samples that are identical can be used to detect DC or the likelihood that the signal is DC with respect to adjacent samples.

[0042] The DC detector 308 may also include a threshold comparator 416 that compares the percentage or number of adjacent samples that are identical to the output of the IIR aggregator 412 to a threshold. The threshold may be a user programmable threshold that may be provided by a controller (not shown) and / or accessed from a control register of a transmitter or a wireless device including the transmitter. Thus, in some cases, a user may program the DC level or amount in a signal that causes the DC detector 308 to enable the DSM 204.

[0043] In some embodiments, some or all of the DC detectors 308 may be duplicated to have one for each of the I and Q paths of the transmitter. Additionally, for each of the I and Q signal components, there may be Figure 3 1 and 2. The transmit path shown in FIG. 1 may include an I transmit path including elements such as a DSM, a DAC, and a DC detector, and a separate Q transmit path including elements such as a DSM, a DAC, and a DC detector. When a programmed threshold is detected, a threshold exceedance signal or an enable signal may be asserted to enable the DSM 204 within the transmit path 300. The enable signal may be updated during each measurement duration or window. In addition, the exceedance threshold signal may be used to automatically enable or disable the DSM 204 (which may also be referred to as a sigma-delta modulator or SDM).

[0044] The transmission data path 300 may include one or more additional filter elements. Figure 4 As shown, transmit data path 300 may include a less coarse NCO, a complex multiplier, or any other element that may be included in a filter chain with interpolation.

[0045] In addition, the transmitter may have multiple channels. For example, the transmitter may have 8 channels. Since each channel can be separated into I and Q components, the transmitter may have 16 data paths 300, including 16 DC detectors 308, 16 DSMs 204, and 16 DACs 106. Therefore, power consumption can be reduced by an average of about 10% for the following data paths 300 can be multiplied across 16 data paths.

[0046] The transmitter may be included in the wireless device as part of a transceiver or as a separate element of the wireless device. The wireless device may include an antenna capable of transmitting a radio frequency signal received from the transmitter. The radio frequency signal may be received from a transmission data path 300, which generates a radio frequency signal for transmission by the antenna.

[0047] Figure 5 Description can be Figure 4 5. The DC detection process 500 performed by the DC detector 308 circuit or one or more elements of the DC detector 308 circuit may begin at block 502, where the DC detector 308 circuit receives a first sample in a sample window. The sample may be received from a DUC circuit or from an adder that sums the outputs of multiple DUC circuits associated with different frequency bands.

[0048] At block 504, the DC detector 308 circuit receives a second sample within the sampling window. The second sample is typically a sample adjacent to or consecutive to the first sample. Although only two samples are described as being obtained, in some cases, the DC detector 308 circuit may obtain more than two samples. In other words, the operations associated with block 504 may be repeated to obtain a third consecutive sample, or a third and fourth consecutive sample, and so on.

[0049] At decision block 506, the DC detector 308 determines whether the first and second samples are identical or substantially identical (e.g., within a threshold difference of each other). If it is determined at decision block 506 that the first and second samples are not identical, the process 500 proceeds directly to decision block 510. If it is determined at decision block 506 that the first and second samples are identical, the DC detector 308 increases the DC count of the sample window at block 508 and proceeds to decision block 510. The DC count may be an integer value that counts the number of consecutive samples that have the same value.

[0050] At decision block 510, the DC detector 308 determines whether it is at the end of the sampling window. In some cases, the sample window can be a rolling window or a sliding window. For example, the first window can be the first 1024 bits, and the second window can replace the oldest bit with a new bit so that the second window includes 1023 bits of the first window and a new bit. In some cases, the window can slide more than one bit at a time. In other words, the subsequent window can replace the oldest multiple bits with a new multiple bits to define a new window. In some such cases, decision block 510 can be optional or omitted because each bit or each bit after bit 1024 can indicate the end of the new sample window. In the case where the sampling window is a rolling window, the DC count can be modified based on each discarded bit. For example, if the discarded bit causes the DC count to increase in the previous window, then when the bit is discarded in the subsequent window, the DC count can be decremented.

[0051] If it is determined at block 510 that the sample window is not complete, process 500 proceeds to block 512, where the second sample is set as the first sample, and the process returns to block 504, where a new second sample (or third sample) is obtained. Typically, this new second sample (or third sample) is subsequent to the previous second sample.

[0052] If it is determined at decision block 510 that the end of the sampling window has been reached, the DC detector determines at decision block 514 whether the DC count meets or exceeds a threshold. The threshold can be a count threshold, or a DC percentage that specifies a DC percentage within a sampling window that triggers an enable signal or enables a modulator (e.g., DSM 204). If the DC count does not exceed or meet the threshold, process 500 can end, or can be repeated in a subsequent sampling window. If the DC count does meet or exceed the threshold, the DC detector 308 enables the modulator (e.g., DSM 204) at block 516. Process 500 can end after the operations associated with block 516. Alternatively, process 500 can continue or repeat for the next sample window, which can be a new set of 1024 bits, or a sliding window.

[0053] In some cases, the count threshold (or DC threshold) may be preconfigured using laboratory testing. The user may be provided with the option to modify the preconfigured threshold. Initially, the DC threshold may be set to a value that does not change the power envelope of the transmit path and maintains the target waveform.

[0054] Figure 6 A simulation of the operation of a DC detector according to some embodiments is illustrated. More specifically, graph 600 illustrates the output of the IIR aggregator 412 of the DC detector 308. The y-axis represents the fraction of samples that are identical to the immediately preceding sample within the input signal (which can be considered DC). The y-axis ranges between 0 and 1, with 0 representing no DC and 1 representing the entire sample window being DC. Each bar on the x-axis represents a window containing 1024 samples.

[0055] Check Figure 6 In the first bar 602 of the graph 600, the height of bar 602 reaches 0.25, meaning that 25% of adjacent samples are the same. Each line can represent a different amount of leakage, where leakage indicates how much history or previous sampling windows are considered when determining whether the input signal includes DC. Leakage = 0 row 604 means that the history is not considered. Therefore, line 604 is equal to the immediately preceding sample window. The leakage factor allows old or previous windows to influence the current calculation based on the equation displayed above the graph. A leakage of 1 means that a small amount of previous values ​​are allowed to leak (or influence) the current calculation. As the leakage factor increases, the historical values ​​have a greater impact on the current result. Therefore, there is a "smoothing" effect on the graph - the calculated DC percentage does not change rapidly with changes in the input DC.

[0056] Terminology and Conclusion

[0057] The foregoing description may refer to elements or features as being "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connected" means that one element / feature is directly or indirectly connected to another element / feature, and is not necessarily mechanically connected. Similarly, unless otherwise expressly stated, "coupled" means that one element / feature is directly or indirectly coupled to another element / feature, and is not necessarily mechanically coupled. Therefore, although the various schematic diagrams shown in the figures depict example arrangements of elements and components, in actual embodiments there may be additional intermediate elements, devices, features, or components (assuming that the functionality of the depicted circuits is not adversely affected).

[0058] Although certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. In fact, the novel devices, methods, and systems described herein may be embodied in a variety of other forms; in addition, various omissions, substitutions, and changes may be made to the forms of the methods and systems described herein without departing from the spirit of the present disclosure. For example, although the disclosed embodiments are presented in a given arrangement, alternative embodiments may perform similar functions with different components and / or circuit topologies, and some elements may be deleted, moved, added, subdivided, combined, and / or modified. Each of these elements may be implemented in a variety of different ways. Any suitable combination of the elements and actions of the various embodiments described above may be combined to provide further embodiments.

[0059] Unless otherwise specifically stated, conditional language such as "may," "might," and the like are otherwise understood in context as generally used to convey that some embodiments include, while other embodiments do not include, certain features, elements, and / or steps. Thus, such conditional language is generally not intended to imply that one or more embodiments require features, elements, and / or steps in any way, or that one or more embodiments must include a method for deciding (with or without user input or prompting) whether such features, elements, and / or steps are included or will be performed in any particular embodiment.

[0060] Unless specifically stated otherwise, disjunctive language, such as the phrase "at least one of X, Y, or Z," should be understood along with the context as generally used to indicate that an item, term, etc. can be X, Y, or Z, or any combination thereof (e.g., X, Y, and / or Z). Thus, such disjunctive language is generally not intended to, and should not, imply that certain embodiments require that at least one of X, at least one of Y, or at least one of Z each be present.

[0061] Any process description, element or block in the flowcharts described herein and / or depicted in the accompanying drawings should be understood to potentially represent a module, segment or portion of code, which includes one or more executable instructions for implementing specific logical functions or elements in the process. Alternative implementations are included within the scope of the embodiments described herein, in which elements or functions may be deleted, executed out of order from the order shown or discussed, including substantially simultaneously or in reverse order, as understood by those skilled in the art, depending on the functions involved.

[0062] Unless expressly stated otherwise, articles such as "a" or "an" should generally be interpreted as including one or more of the described items. Thus, phrases such as "a device configured to" are intended to include one or more of the enumerated devices. Such one or more recited devices may also be configured together to perform the recited statements. For example, "a processor configured to perform statements A, B, and C" may include a first processor configured to perform statement A working in conjunction with a second processor configured to perform statements B and C.

[0063] It should be emphasized that many changes and modifications may be made to the above-described embodiments, and the elements therein should be understood as other acceptable examples. All such modifications and changes are intended to be included within the scope of this disclosure and protected by the following claims.

Claims

1. A transmitter, comprising: a filter chain configured to process a transmit signal; a modulator configured to convert the transmit signal into a digital transmit signal when enabled; a digital-to-analog converter configured to convert the digital transmission signal into an analog signal; and A DC detector is configured to determine a percentage of a DC component within the transmit signal and enable the modulator when the percentage of the DC component meets a DC threshold.

2. The transmitter of claim 1, wherein the modulator is a delta-sigma modulator. 3 . The transmitter of claim 1 , wherein the DC detector is configured to determine a percentage of a DC component within a sample window of the transmit signal. 4 . The transmitter of claim 1 , wherein the DC detector comprises a sample comparator configured to compare a first sample obtained from the transmit signal with a second sample obtained from the transmit signal.

5. The transmitter of claim 4, wherein the first sample and the second sample comprise consecutive samples in a series of samples obtained from the transmit signal.

6. The transmitter of claim 4, wherein the DC detector further comprises an accumulator configured to accumulate samples of the transmit signal corresponding to a sample window.

7. The transmitter of claim 6, wherein the accumulator comprises an infinite impulse response (IIR) aggregator.

8. The transmitter of claim 6, wherein the accumulator is further configured to determine a DC count comprising a count of consecutive samples within a sample window that the DC detector determines to be equal.

9. The transmitter of claim 8, wherein the accumulator is further configured to determine a percentage of direct current within the sample window based at least in part on the direct current count.

10. The transmitter of claim 8, wherein the DC detector further comprises a threshold comparator configured to: determining whether the DC count satisfies the DC threshold; and When the DC count meets the DC threshold, an enable signal is output to enable the modulator.

11. A wireless device comprising: an antenna configured to transmit a radio frequency signal; and A transmitter, configured to generate the radio frequency signal for transmission by the antenna, the transmitter comprising: a filter chain configured to process a transmit signal; a modulator configured to convert the transmit signal into a digital transmit signal when enabled; a digital-to-analog converter configured to convert the digital transmit signal into an analog signal; and A DC detector is configured to determine a percentage of a DC component within the transmit signal and enable the modulator when the percentage of the DC component meets a DC threshold.

12. The wireless device of claim 11 , wherein the DC detector comprises a sample comparator configured to compare a first sample obtained from the transmit signal and a second sample obtained from the transmit signal, and wherein the first sample and the second sample comprise consecutive samples in a series of samples obtained from the transmit signal.

13. The wireless device of claim 11 , wherein the DC detector comprises an accumulator configured to: Accumulating samples of the transmit signal corresponding to the sample window; and A DC count is determined, wherein the DC count comprises a count of consecutive samples within a sample window where the DC detector determines that they are equal.

14. The wireless device of claim 13, wherein the accumulator is further configured to determine a percentage of direct current within the sample window based at least in part on the direct current count.

15. The wireless device of claim 13, wherein the DC detector further comprises a threshold comparator configured to: determining whether the DC count satisfies the DC threshold; and When the DC count meets the DC threshold, an enable signal is output to enable the modulator.

16. A method for reducing power consumption in a transmitter, the method comprising: By implementing a DC detector in hardware, receiving a first sample of a transmit signal within a sample window; receiving a second sample of the transmit signal within the sample window; determining whether the first sample and the second sample are the same; In response to determining that the first sample and the second sample are the same, incrementing a DC count; determining whether the DC count satisfies a DC threshold; and In response to determining that the DC count satisfies a DC threshold, a modulator within a transmit path of the transmitter is enabled.

17. The method of claim 16, wherein in response to determining that the DC count does not satisfy a DC threshold, disabling the modulator.

18. The method of claim 16, wherein determining whether the first sample and the second sample are the same comprises determining that a difference between the first sample and the second sample does not exceed a threshold difference.

19. The method of claim 16, further comprising receiving one or more additional samples within the sample window, wherein determining whether the first sample and the second sample are the same comprises determining whether the first sample, the second sample, and the one or more additional samples are the same, and wherein in response to determining that the first sample, the second sample, and the one or more additional samples are the same, the DC count is increased.

20. The method of claim 16, further comprising: receiving a third sample within the sample window; determining whether the second sample and the third sample are the same; and In response to determining that the second sample and the third sample are the same, the DC count is incremented, wherein the second sample and the third sample are consecutive samples.

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