Fabrication method using inclined deposition and shadow wall

Abstract

A method of manufacturing an apparatus (12), the method comprising: forming a portion of an electronic circuit device and a shadow wall structure (13) above a substrate, and then depositing a conductive layer (5) on the substrate by depositing conductive material in at least a first deposition direction at an acute angle relative to the plane of the substrate. The shadow wall structure is arranged to cast a shadow during deposition to leave areas where conductive material is not deposited. The shadow wall structure includes one or more gaps (15), each gap being shorter than the shadow length of the corresponding portion of the shadow wall structure casting a shadow into the gap to prevent conductive material from forming in the gap and thereby forming electrically isolated areas of the upper conductive layer from each other. These are arranged to form conductive elements for applying signals to the electronic circuit device and / or receiving signals from the electronic circuit.

Description

Technical Field

[0001] The present disclosure relates to forming a conductive layer by oblique deposition, using shadow walls to leave shadow regions where conductive material is not deposited. The disclosed technology has exemplary applications in the fabrication of quantum computing devices comprising semiconductor-superconductor nanowires, or indeed other nanofabrication applications. Background Art

[0002] Topological quantum computing is based on the phenomenon that non-Abelian anyons in the form of "Majorana zero modes" (MZMs) can form in regions where semiconductors are coupled to superconductors. Non-Abelian anyons are a type of quasiparticle, which means that the non-Abelian anyon is not a particle itself, but an excitation in an electron liquid that behaves at least partially like a particle. MZMs are special bound states of this type of quasiparticle. Under certain conditions, these states can form near the semiconductor-superconductor interface in a nanowire, which is formed by a section of semiconductor coated with a superconductor. When an MZM is induced in a nanowire, it is said to be in a "topological state." To achieve this, a magnetic field needs to be applied to the nanowire and the nanowire is cooled to a temperature that can induce superconducting behavior in the superconducting material. It can also involve gating a portion of the nanowire by applying a change in electrostatic potential.

[0003] By forming a network of such nanowires, and inducing MZMs in portions of the network, it is possible to create quantum bits (qubits) that can be manipulated for quantum computing purposes. A quantum bit, or qubit, is an element on which a measurement with two possible outcomes can be performed, but at any given time (when not being measured), it can actually be in a quantum superposition of two states corresponding to different outcomes. Summary of the invention

[0004] Typically, the manufacturing process includes one or more "post-fabrication" steps after the nanowires are formed in order to form associated conductive elements (e.g., gates, leads, and bond pads). This post-processing typically includes etching or photolithography. However, the performance of semiconductor nanowire devices is susceptible to adverse effects associated with adsorbates and surface potential fluctuations. Standard photolithography and other post-fabrication steps that are typically performed to create complex nanoelectronic devices can be detrimental to device performance. After the semiconductor nanowires are introduced on the target device wafer, it is desirable to create a process flow that involves as few steps as possible, ideally bypassing the electron beam resist and physical or wet chemical etching steps entirely.

[0005] Similar considerations may also apply to the fabrication of other types of semiconductor, quantum, or electronic devices, where it is also desirable to reduce or even eliminate potentially disruptive post-fabrication steps that would otherwise be performed after the active structures of the device itself have been formed, in order to form electrical contacts, etc. Other such example applications may include: other types of quantum devices (e.g., SIS junctions, SIN junctions, and SQUIDS); spin electronic devices (e.g., spin transistors, spin-based storage elements, or spin-based sensing elements); or conventional semiconductor electronic devices.

[0006] According to a first aspect of the present invention, there is provided a method for manufacturing an apparatus, comprising: forming a portion of a circuit device and a shadow wall structure on a substrate, and then depositing an upper conductive layer on the substrate by obliquely depositing a conductor such as a metal. For example, this can be achieved using vapor deposition. Oblique deposition is performed in at least one deposition direction at an acute elevation angle relative to the plane of the substrate, wherein the shadow wall structure is arranged to cast a shadow during the deposition process to leave an area where the conductor is not deposited. The shadow wall structure includes one or more gaps, each of which is shorter than the shadow length of the corresponding part of the shadow wall structure that casts the shadow into the gap, so as to prevent the formation of a conductor in the gap during deposition, and thereby create areas of the upper conductive layer that are electrically isolated from each other. These electrically isolated areas are arranged to form conductive elements, such as terminals and / or leads for applying signals to one or more components of the electronic circuit device and / or receiving signals from one or more components of the electronic circuit. For example, these components may include one or more semiconductor-superconductor nanowires, for example, arranged to form quantum bits. Conductive elements can be used, for example, to create gates for gating the nanowires, or bonding pads for connecting leads for reading out qubits, or internal wires for connecting between components in the semiconductor layer, etc.

[0007] The shadow length refers to the extent of the shadow in the direction of the deposition beam in the plane of the substrate, given its height and deposition direction, that would be cast by the corresponding portion of the wall if the shadow were not interrupted by the portion of the wall structure on the other side of the gap. The fact that the gap is shorter than the shadow length means that metal is not deposited on the underlying layer or substrate (the "floor" of the gap) in the area between the walls surrounding the gap, thereby ensuring electrical isolation. The technology can be used to form conductor circuit elements, such as bonding pads, wires and / or gates, and can therefore reduce or even eliminate the need for destructive post-manufacturing steps such as etching and lithography for this purpose. In some embodiments, no etching or lithography steps are used to form any upper conductive layer after the semiconductor layer is formed. In the case of semiconductor-superconductor nanowires, conductive elements such as contacts and gates can be formed in the same deposition step (or one or more of the same deposition steps) as the superconductor coating of the nanowire.

[0008] According to a second aspect of the invention, a method for oblique deposition can be provided, the method comprising forming a vertical template perpendicular to the substrate. The vertical template comprises one or more holes corresponding to one or more regions in the plane of the substrate on which deposition is to be performed, given a deposition direction at an acute angle relative to the plane of the substrate. The method then comprises depositing material (e.g., a conductor, such as a metal) through one or more holes in the direction at the angle, thereby depositing material on one or more regions. The template can be placed around one or more sides of the substrate to allow deposition from one or more directions. The template can be left in place or removed when the device is capped.

[0009] The first aspect and the second aspect may be used together or independently. Any feature disclosed or claimed in connection with the first aspect may optionally be used in combination with the second aspect, and vice versa.

[0010] According to another aspect disclosed herein, there is provided a device manufactured by the method of any embodiment of the first aspect or the second aspect.

[0011] This summary is provided to introduce a selection of concepts in a simplified form that are further described in the detailed description below. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. The claimed subject matter is also not limited to implementations that solve any or all of the disadvantages mentioned herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] To assist in understanding the embodiments of the present disclosure and to show how these embodiments may be implemented, reference is made to the accompanying drawings, by way of example only, in which:

[0013] Figure 1A is a schematic side view of an example wafer,

[0014] Figure 1B is a schematic cross-section of an example nanowire,

[0015] Figure 1C is a schematic perspective view showing the use of an example vertical formwork,

[0016] Figure 2 is a high-angle view of an example wall structure,

[0017] Figure 3 is a schematic high-angle view of an example wall structure tilted arrangement,

[0018] Figure 4 is a schematic high-angle view of another wall structure tilted arrangement,

[0019] Figure 5 is a top view of an example of a double-angle deposition process.

[0020] Figure 6 is a schematic perspective view of an example wall structure,

[0021] Figure 7 is a schematic perspective view of another example wall structure, and

[0022] Figure 8 is a SEM image of a wafer containing an example wall structure. DETAILED DESCRIPTION

[0023] Embodiments disclosed herein provide device designs and manufacturing processes for producing, for example, Majorana devices including semiconductor-superconductor nanowires or other hybrid superconductor-semiconductor devices. The process reduces or even eliminates the need to perform any manufacturing steps after depositing or growing nanowires and tilting evaporation of metals on nanowires. Semiconductors (e.g., nanowire cores) can be grown, for example, by selective area growth (SAG) or vapor-liquid-solid (VLS) growth. However, conventional etching or photolithography, which is traditionally used to define structured electrical contacts and other such conductive elements after semiconductor growth and subsequent metal deposition, may damage the underlying structure. Therefore, reducing or eliminating such steps will improve the performance of such devices. The disclosed manufacturing process produces devices including elements such as gates, leads, high-quality dielectrics, and / or pads for bonding. After the growth or deposition of the nanowire core, metal is deposited to produce the semiconductor-superconductor hybrid required for the quantum bit (this step is always required). This metal only needs to be selectively deposited in certain areas of the nanowire. In order to produce this selective deposition, a blanket metal deposition can be performed, and then the metal is locally etched where it is not needed, but this is an example of a manufacturing step that will damage the device. The embodiments disclosed herein solve the problem of etching, fabricating gates and contacts, thereby eliminating every fabrication step after metal deposition.

[0024] In a first aspect, the solution utilizes a unique design of shadow walls, and specially formed gaps between the shadow walls, which allow electrical isolation from the contacts of the wires and prevent the occurrence of short circuits that would otherwise be created by the oblique overlying deposition of metal. Preferably, the walls form a "recess" or enclosure in the plane of the substrate, with one or more gaps in the walls of each recess. Thus, each recess encloses its own isolation area. In a second aspect, which can be used with the first aspect or independently, the process uses metal to be deposited through a vertical hard mask template with a hole pattern to prevent large areas of the chip from being shorted by the metal film.

[0025] As previously discussed, the performance of semiconductor nanowires is susceptible to deleterious effects related to adsorbates and surface potential fluctuations, for example, due to the inherently large surface-to-volume ratio. Standard lithography and other post-fabrication steps typically performed to create complex nanoelectronic devices (e.g., hybrid semiconductor-superconducting devices used as topological qubits) can be detrimental to device performance (e.g., due to low thermal budgets). In this article, post-fabrication is defined as any step after tilted metal deposition (or more generally, tilted conductive material deposition). This can include a series of clean room manufacturing steps that typically occur after wire growth in the case of SAG wires, or after wire deposition on a substrate in the case of VLS. After the semiconductor nanowires have been introduced onto the target / device chip, it is desirable to create a process flow involving as few steps as possible, ideally bypassing the electron beam resist and physical or wet chemical etching steps entirely.

[0026] This problem is particularly relevant (but not limited to) in hybrid semiconductor-superconductor structures where the semiconductor includes InSb and the superconductor includes Al. Since InSb / Al is a very delicate material combination, heating, aging, etching or other traditional preparation processes can affect the material quality and the InSb / Al interface, create interdiffusion or defects, and hinder Majorana signatures. The embodiments disclosed herein provide a device design and manufacturing flow that moves all device manufacturing steps to before the growth or deposition of the InSb structure and subsequent metallization.

[0027] A stencil mask would be an alternative solution to obtain devices that do not require fabrication after metal deposition. However, a stencil mask requires very precise mechanical positioning of the mask, which requires the introduction of complex additional machinery in the deposition chamber. Moreover, for each new deposition, a new stencil mask is required (often several depositions are required for a single device). On the other hand, currently disclosed solutions use selective deposition of shadow walls, for example by photolithographic positioning of the walls and then obliquely depositing the metal or other such conductor. This is both more accurate and easier.

[0028] Embodiments provide a shadow wall design that includes grooves and gaps that allow multiple isolation structures (e.g., contact leads, gates, dielectrics, and / or mesoscopic metal structures) to be created using directional deposition. One benefit of this design for metal deposition or other conductor deposition is that these structures do not short to each other or to the external environment, as would be the case when directional deposition of an inclined capping layer is used without these designs.

[0029] Embodiments also provide a technique for directional metal deposition through a selectively patterned vertical hard mask template with holes to prevent large areas of the chip from being shorted by the metal film. In addition, this enables the device to be covered from the top via blanket deposition of dielectric.

[0030] A manufacturing process is described below that produces a device including a gate, leads, high-quality dielectrics, and pads for wire bonding. A process is described related to the manufacture of a quantum computing device that includes a network of semiconductor-superconductor nanowires used to form MZM-based qubits. However, more generally, the design and manufacturing processes presented herein can be used to create a variety of different types of devices without any post-manufacturing steps. Such devices can include quantum devices such as semiconductor-insulator-semiconductor (SIS) junctions, semiconductor-insulator-normal (SIN) junctions, islands, superconducting quantum interference devices (SQUIDs), and / or superconducting flux / phase / charge qubits.

[0031] Figure 1A An example device (or portion thereof) formed according to an embodiment disclosed herein is shown. The device includes a wafer 1, which includes a substrate 2 and a multilayer formed on the substrate 2. The multilayer includes at least a first layer 4, and an upper conductive layer 5, the first layer 4 including a patterned portion of an electronic circuit device, and the upper conductive layer 5 including a patterned portion of a conductor. The first layer 4 may also be referred to as an active layer because the first layer 4 is where the functional portions of the electronic components (whether they are quantum components, spin electronic devices, or traditional electronic components) are formed. In an embodiment, the first layer 4 includes a semiconductor layer, which includes a patterned portion of a semiconductor. For example, the semiconductor may be InSb or InAs. The examples herein may be described in terms of a semiconductor layer 4, but the layer 4 may alternatively or additionally include one or more types of materials, such as a dielectric.

[0032] Please note that, unless otherwise stated, the term "circuit device" as used herein does not necessarily mean any specific type of device, logic, or electronic phenomenon. For example, it may refer to a quantum device based on any quantum phenomenon (such as MZM, superconducting quantum interference, etc.); or a spin electronic circuit (such as a spin transistor, a spin-based sensing or storage element, etc.); or a traditional electronic component (such as a transistor, a diode, a capacitor, etc.). A "portion" of a circuit device may refer to a single continuous element or multiple elements of a material. A given portion may form a complete electronic component by itself, or may be combined with one or more elements in one or more upper layers and / or lower layers (e.g., upper conductor 5 and / or lower conductor 6) to form a constituent part of a component.

[0033] The upper conductor 5 may be a superconducting metal such as Al. The semiconductor layer 4 is formed on the substrate 2, for example, by selective area growth (SAG) or vapor-liquid-solid (VLS) and subsequent deposition on the substrate 2. Various manufacturing techniques for forming semiconductor structures are known in the art per se. Subsequently, an upper conductive layer 5 is formed on the semiconductor layer 4. This is formed by an oblique deposition technique performed according to the teachings of the present disclosure. In an embodiment, the medium used for configuration is vapor deposition.

[0034] Optionally, in an embodiment, the wafer 1 may further include a bottom structure or lower structure 3. The lower structure 3 may include a lower conductive layer 6 and / or a lower dielectric layer 7. In an embodiment, the lower conductive layer 6 is formed on the substrate 2, and the lower dielectric layer 7 is subsequently formed on the lower conductive layer. In other embodiments, these lower layers 6, 7 may be applied in the opposite order, and / or there may be one of these lower layers 6, 7, and / or one or more other layers (not shown) may be included in the bottom structure. In an embodiment, the lower conductive layer 6 may include, for example, gold, tungsten or silver. The lower dielectric layer 7 may be formed of any suitable dielectric, such as SiO2 or SiOx. Any suitable manufacturing technique (e.g., vapor deposition or photolithography) may be used to form these layers 6, 7. Various materials and manufacturing techniques for forming the conductive layer 6 and the dielectric layer 7 are known in the art per se.

[0035] The semiconductor layer 4 may include various functional electronic circuit parts. In an embodiment, these may include one or more quantum computing components for forming a qubit or the like. For example, the semiconductor layer 4 may include a semiconductor core of a network of semiconductor-superconductor nanowires arranged to form a MZM-based qubit.

[0036] Figure 1B An example structure that can be formed in the semiconductor layer 4 and the upper conductive layer 5 is schematically shown. Here, the structure includes semiconductor-superconductor nanowires 9, Figure 1B 4 is shown in a cross section perpendicular to its axis (and the length of the nanowire 9 extends perpendicular to the page). The nanowire 9 includes a section of a semiconductor 4n forming the core of the nanowire 9, and a superconductor coating 5n formed around at least a portion of the semiconductor core 4n. The superconducting coating 5n may be formed directly on the semiconductor core 4n or indirectly on the semiconductor core 4n (for example, a ferromagnetic insulator may be placed between the superconducting coating 5n and at least a portion of the semiconductor core 4n, not shown).

[0037] The structure also includes one or more associated conductive elements formed in the conductive layer 5 , such as electrical contacts, leads and / or signal terminals, such as a gate 5 g for applying an electrostatic potential to the nanowire 9 .

[0038] As is familiar to those skilled in the art, Majorana zero modes (MZMs) can be induced in semiconductor-superconductor nanowires 9 by cooling the device 1 to a temperature at which the superconductor 5n exhibits superconducting behavior and applying a magnetic field to the nanowire 9. The magnetic field can be applied from a source external to the device 1 (e.g., an external electromagnet); and / or can be applied by a magnetic element integrated into the device 1 itself (e.g., a ferromagnetic insulator (not shown) formed on at least a portion of the nanowire core 4n). Inducing an MZM also typically involves gating, i.e., applying an electrostatic field to the nanowire 5n by an appropriate gating element 5g. However, it is also possible to induce an MZM without gating using a full-shell nanowire (with a layer of superconducting coating around the nanowire). The techniques for inducing an MZM in a nanowire are known per se in the art. In the example shown, the gate is a side gate 5g, but a top gate or a bottom gate can also be formed in the lower conductive layer 6.

[0039] Figure 1B One nanowire 9 is shown for illustrative purposes, but it will be understood that there may be more nanowires (and associated conductive elements in the upper conductive layer 5, and any associated structures in the lower conductive layer 6 and / or dielectric layer 7) depending on the device being manufactured. A network of such nanowires 9 formed in the plane of the substrate 2 may be arranged to form a qubit or a quantum computing device comprising a plurality of such qubits. Arrangements for forming qubits and quantum computing devices from a network of nanowires are known per se in the art.

[0040] The upper conductive layer 5 includes various conductive elements that can be used to make contact with one of the electronic components formed in the semiconductor layer 4 and / or to apply an electric potential to these components. For example. These may include internal wires (wires) connected between different components in the semiconductor layer 4, and / or terminals such as gates 5g for gating components such as nanowires 9. Some terminals may include bonding pads for connecting external leads to the device 1 so that signals can be applied to the device 1 or signals from external devices such as an external computer system (not shown) can be read from the device. For example. Signals from room temperature electronic devices can be applied to the leads and gates through bonding pads.

[0041] Preferably, as will be discussed in more detail later, according to embodiments disclosed herein, the superconductor coating 5n may be formed in the same deposition step (or at least one same step) as other conductive elements (eg, gate 5g, bonding pad 5b and / or wire, etc.).

[0042] Optionally, one or more other layers may be included. For example, part or all of the semiconductor layer 4 may be separated from the conductive layer 5 by an intermediate dielectric layer (not shown) to produce one or more gates. And / or, one or more further upper layers (e.g., an oxide layer and / or a packaging dielectric layer for preventing oxidation) (not shown) of the wafer 1 may be formed on the upper conductive layer 5. And / or, one or more further or alternative lower layers (not shown) may be included in the lower structure 3.

[0043] Note that the described process does not exclude the possibility of additional prefabricated bonding pads. For example, it may be advantageous to already have relatively thick metal pads in place to facilitate wire bonding, see Figure 6 cf. 5b in. For example. This can be formed in the lower layer 6.

[0044] Also note again, Figure 1A 1 b are schematic, wherein the shapes and sizes shown are not limiting. For example, in an embodiment, the cross section of the nanowire 9 may actually be a hexagon.

[0045] As far as terminology is concerned, "substrate" 2 refers herein to the final base of wafer 1, while "wafer" refers to the base plus any additional layers formed on or above the base 2 at any point in the manufacturing or in the final completed wafer. "Above" herein can refer to any one or more intermediate layers formed directly or indirectly in the middle. So "above" the substrate herein can refer to being formed directly on the substrate 2 or having one or more intermediate layers, such as a dielectric layer between the substrate 2 and the semiconductor 4. "On..." refers herein to being directly on (i.e., directly on the basis without any intermediate layers). Neither of these two terms necessarily refers to a layer being formed across the entire bottom layer. Please also note that the terms "on..." or "above", "upper" and "lower", "horizontal" and "vertical" or generic terms such as these used herein do not necessarily mean a specific orientation relative to gravity. Instead, they refer to a position relative to the surface of the substrate 2 being processed (the surface where the layer is starting to form). Please also note that "upper" and "lower" are merely relative terms and do not necessarily mean that any layer referred to by these terms is the absolute uppermost or lowermost layer of its type. Furthermore, reference to an "upper" conductive layer 5 does not necessarily imply the presence of a lower conductive layer, and reference to a lower dielectric layer 7 does not necessarily imply the presence of an upper dielectric layer. Furthermore, the term "layer" does not necessarily imply a continuous or unbroken layer, but may also refer to a patterned or structured layer. Furthermore, any given pair of different layers 2-7 need not necessarily be the same. Figure 1A As schematically shown in FIG. Figure 1BAs shown in the example in , portions of the metal layer 5 may "wrap around" or drop down in the semiconductor layer 4 or similarly over structures in any adjacent layer pair.

[0046] Once fabricated, the wafer 1 is packaged into an integrated circuit (IC) package using known IC packaging techniques. The package may include leads inserted between external connectors (e.g., pins or ball pads) of the package and internal bonding pads 5b (shown later) formed in the upper conductive layer 5, so that an external device can control or read out the semiconductor components in the semiconductor layer 4. The package may include covering the wafer and leads with a suitable encapsulant (usually a dielectric), examples of which will be known in the art.

[0047] Now refer to FIGS. 1 to Figure 7 Example manufacturing process flows according to embodiments of the present disclosure are discussed. As an illustration, these will be described in conjunction with an example where the deposited metal 5 is a conductor, such as a superconductor (e.g., Al) used to form the coating 5n of the nanowire 9, and the lower conductive layer 6 is also formed of a metal (e.g., gold or tungsten). However, it should be understood that this is not limiting.

[0048] FIG. 1 shows a stage where a lower structure 3 has been formed above a substrate 2. In an embodiment, the semiconductor 4 and the upper conductive layer 5 are formed only on one or more selected active circuit regions 12, and not on other regions above the substrate 2. One such region 12 is shown in FIG. 1, but there may be more regions. The dielectric 6 may also be formed only in this layer. Other regions outside the selected regions may be used for other purposes. For example. The metal layer 6 in these other regions may be patterned to provide a coplanar waveguide resonator to read out the quantum bits formed in the selected regions 12. Alternatively, other areas may simply be left as non-functional areas.

[0049] The deposition of the conductor 5 (e.g., metal) is performed by an inclined vapor process, whereby a vapor beam 5' comprising the conductive material being deposited is directed toward the substrate, for example by electron beam physical vapor deposition, chemical vapor deposition, or plasma enhanced chemical vapor deposition. The arrow marked 5' indicates the deposition of the conductor (e.g., metal) at a steep angle. The deposition angle is at least an acute angle relative to the plane of the substrate 2 (i.e., a non-perpendicular angle between the normal to the plane of the substrate 2 and the plane of the substrate 2). Preferably, the angle is less than 45 degrees relative to the plane of the substrate (greater than 45 degrees relative to the normal), and in embodiments may be much less than 45 degrees, for example less than 22.5 degrees, or less than 12.25 degrees. The specific desired angle may depend on the geometry of the SAG or VLS wire. A related condition may be that the deposition must be able to make electrical connections through the substrate (or a metal ring connecting several semiconductor segments through the substrate). The actual angle depends on the face of the nanowire. For a nanowire with a hexagonal cross section, the maximum deposition angle with the substrate plane is 60°. In reality, it may be beneficial to use an angle steeper than it to ensure proper coverage of the lowest hexagonal face. For example, an embodiment uses 30 degrees.

[0050] In an embodiment, the substrate 2 is provided with a vertical hard mask template 10 placed on at least one side of the substrate 2. The template includes one or more holes 11, each hole 11 corresponding to a corresponding one of the selected deposition areas 12. The evaporated material 5' is deposited through the holes 11 so as to be formed only on the corresponding area 12 above the substrate 2. The template 12 can be manufactured on the chip 1 by 3D printing, for example, made of a special resin, or it can be a thin patterned Cu mask placed on top of the chip (it can be included in the sample fixture to ensure accurate alignment between the sample and the template). The position, size and shape of these areas 12 are a function of the size and position of the holes 11 and the deposition direction including the deposition angle. The purpose of the template structure 10 is to prevent the metal film 5 from covering a large area of ​​the chip 1 during metal deposition. The vertical template 10 can make the deposited metal film 5 coarsely structured. However, in alternative embodiments, other appropriately focused beam-based vapor deposition techniques not involving template 10 may be used; however, if region 12 (or any of regions 12) is less than 100×100 μm2 (or less than 100 μm in any dimension in the plane of the substrate), then a template may be preferred to achieve the desired accuracy.

[0051] In the example shown, the coplanar waveguide resonators shown have been manufactured in the lower metal layer 6 before the nanowire deposition. In the deposition process, only the area 12 on the chip 1 is selectively covered with metal.

[0052] If deposition from multiple angles is required, multiple vertical hard mask templates 11 may be placed on different sides of the substrate. In an embodiment, the vertical template may contain holes 11 of approximately 100 μm wide and may have a slope equal to the evaporation angle.

[0053] The holes 11 in the vertical template 10 are positioned so that metal is selectively deposited only near the nanowire device. In an embodiment, this allows, for example, the nanowire device to be incorporated into a coplanar waveguide resonator for quantum bit readout and two-qubit entanglement. In an embodiment, the vertical template structure 10 can be left in place when the entire device is finally capped and packaged into an IC package. Because the hard mask template 10 is vertically oriented, the final device can be protected by covering it in situ with a dielectric layer after depositing the metal leads. Therefore, the device is protected from degradation when exposed to air, maintaining high quality. However, this is not necessary, and in alternative embodiments, the template structure 10 can be removed prior to packaging.

[0054] Within a given deposition area 12, the metal 5 can be patterned by means of a structure of shadow walls 13, also called "smart walls". Figure 2-Figure 7 As shown, it will be discussed in more detail later. In an embodiment, the shadow walls 13 are formed of a dielectric material. Preferably, these walls 13 are formed before the semiconductor layer 4 is grown to avoid possible damage caused by the processing involved in forming the shadow walls 13. However, it is not excluded that they can be formed after the semiconductor 4.

[0055] The basic overall concept of shading is known. However, the original idea of ​​a shading wall was simply to eliminate the need for local patterning near the device area. The inventors have found that when using smart walls without the additional features proposed herein, a lot of etching is still required to create a device with multiple metal parts that must be completely electrically isolated from each other (such as required when connecting leads to the device). This means that a smart wall by itself is not enough to create a device without post-fabrication. Problems such as Figure 2-Figure 3 The disclosed solution uses gaps 15 to inherently pattern electrically isolated metal grooves, such as Figure 4 shown and described below.

[0056] Figure 2 An example of a "groove" structure 14 defined by shadow walls 13 is shown. Figure 2 A simplified version of a potential groove structure made of walls 13 and manufactured on the dielectric layer 7 or the substrate 2 is shown. In this example, the groove 14 comprises an area enclosed by the wall structure 13 on all sides. Figure 2 1 shows a specific structure that can be formed in a portion of a selected deposition area 12 in FIG. 1 (hence the ratio of FIG. 1 to Figure 2is much larger than Figure 3-Figure 7 ). Compared with the ideas disclosed in this article, Figure 2 The walls 13 of the groove structure do not include any gaps.

[0057] Figure 3 shows that after metal deposition using tilted evaporation technology, Figure 2 The gapless groove structure. The arrow marked 5' indicates the direction of metal evaporation, i.e. the deposition direction. The groove is short-circuited to the external film by the path depicted around the wall and therefore has no electrical isolation.

[0058] In detail, when the metal vapor 5' Figure 3 When depositing at an angle (e.g., <45° relative to the sample horizontal) as indicated by the large arrow, the wall 13 will cast a shadow (visible as black) above the substrate. This disconnects most of the area where the outer film 5 can contact the inner groove area 14. However, there are still some areas in which the metal 5' climbs up the wall 13 vertically from the deposition direction and continues horizontally on the top of the wall 13, where the metal 5' will eventually find its way down to the groove. In other words, the metal vapor 5' will "climb" over the wall 13. When the resulting metal film 5 is then deposited on the top of the wall 13 and the inside of the wall 13 within the groove 14, and further deposited on the floor of the groove 14, this means that electrical contact is formed between the metal 5 inside and outside the groove (i.e., they are short-circuited). Figure 3 (and Figure 4 ) depicts an example electron path of charge carriers in the film 5 (not the direction of the metal vapor 5'). Figure 3 In the case of the above, there is a path connecting the outer film to the inside of the groove 14. Therefore, the deposited film 5 in the groove 14 cannot be used as an isolated electrical contact, such as a bonding pad for connecting the lower conductive layer 6 to the lead. Therefore, if there is no modification, the groove structure 13 is not suitable for forming such a contact.

[0059] To prevent this problem, interruptions can be added to the groove wall structure in the form of gaps 15, such as Figure 4 shown. Figure 4 The groove structure 14 after metal evaporation is shown, similar to Figure 3 , but with a gap 15 in the wall 13. The gap 15 is incorporated in the structure to prevent electrical connection around the wall 13. The interior of the groove 14 is electrically isolated from the outer film.

[0060] Due to these gaps 15, the film is discontinuous at the top of the wall 13. By design, the size of such gaps 15 is small enough to not allow any metal inside the gap for the desired evaporation angle, thereby achieving complete electrical isolation of the groove 14 relative to the outer film. The shadow length of a given part of the wall structure 13 is the extent of the shadow projected onto the plane of the substrate 2 by the projection of the part of the wall structure, extending from the part of the wall structure, if it is not interrupted by the wall on the other side of the gap 15. It is not only a function of the height and shape of the relevant part of the wall structure 13 itself, but also a function of the deposition direction (including the polar angle of the arrangement direction). In other words, the gap 15 is short enough so that the metal (or other conductive material) being deposited does not hit the bottom of the gap 15.

[0061] The inventors have found that as long as the gap 15 remains shorter than the shadow length of the portion of the wall structure 13 that forms the shadow, the metal vapor 5' will not fall to the floor of the gap 15. The effect is geometric: the angle of deposition is not steep enough so that the deposition beam 5' projected onto the plane of the substrate 2 can reach the bottom of the gap 15 before hitting the side of the opposite wall 13 on the far side of the gap. If the gap 15 is larger than the shadow, the metal 5' will fall inside the gap 15, onto the bottom of the gap 15 (the substrate 2 or the bottom layer 6 / 7). In this case, Figure 4 The resulting metal film 5 outside the groove 14 will be connected to the inside of the groove through the floor in the gap 15 (in this case not through the wall, but still connecting the outer metal film to the metal inside the groove 14).

[0062] Therefore, Figure 3 different, Figure 4 The metal film 5 deposited in the groove 14 is electrically isolated from the metal film 5 deposited outside the groove 14. This means that the deposited film 5 in the groove 14 can be arranged as an isolated electrical contact for controlling a component of the device, or reading from it.

[0063] For example. The metal film 5 deposited in the groove 14 can be arranged as a bonding pad for connecting a lead to the lower conductive layer 6, which bonding pad can alternatively be connected to other active components (e.g. one of the semiconductor components in the semiconductor layer, such as a nanowire). In an embodiment, in order to connect to the nanowire 9, an opening extending from the bottom to the top of the wall can be formed in the farthest wall 13, assuming that the nanowire is located outside the groove 14 (see also Figure 5 and Figure 6 , which will be discussed in more detail later). Alternatively, the connection to the nanowires 9 may be formed via the lower conductive layer 6.

[0064] As another example, the metal film 5 deposited in the groove 14 can be arranged as a gate for gating the nanowire 9. In this case, the gate can be separated from the nanowire by a dielectric, but an electrostatic potential is applied to the nanowire 9 propagating through the dielectric. The gate can be controlled by the connection between the metal film 5 in the groove 4 and the lower conductive layer 6. In an embodiment, this can be done by bonding through the intermediate dielectric layer 7. In one possibility, the gate can be formed by the metal film 15 in the groove 14, and the dielectric can be formed by the wall 13 itself. However, considering the fact that the wall 13 is much larger than 100nm in the embodiment, this will only allow very weak coupling with the gate electrode. For the gate, a more preferred implementation will be through a patterned layer 6 covered with a thin dielectric layer 7. These "bottom gates" can be effectively coupled to the semiconductor (allowing more obvious changes in electrostatic potential) because the gate is very close to the semiconductor channel. The gate can be connected to the thin film 5 in the groove 4 to achieve electrical connection with another component or external source.

[0065] Please note, Figure 2-Figure 4 The shape of the wall 13 is a trapezoid, such as Figure 3 and 4 . The trapezoid has two parallel walls 13 (the base of the trapezoid) and two non-parallel walls (the sides or legs of the trapezoid). The longest base of the trapezoid is arranged as a front wall that is substantially facing the deposition direction (the first wall 13 of the groove 14 is to be encountered when moving along the deposition direction), while the shortest base of the trapezoid is arranged as a rear wall behind the front wall (the last wall of the groove 14 is to be encountered when moving along the deposition direction). The base is preferably substantially perpendicular to the deposition direction. The side wall 13 tapers inwardly from the front wall to the rear wall in the plane of the substrate 2 at an angle that is steeper than parallel to the deposition beam direction. Therefore, the area behind the side wall is shaded.

[0066] The trapezoidal shape is advantageous because it allows tolerance in the evaporation azimuth angle. In the case of a rectangular wall, if the evaporation comes slightly from the side, the metal 575 will cover the outside of the wall. However, this is not necessarily detrimental because the gap can be adjusted accordingly. The rectangular shape is only a problem if the deposition is not perfectly directional. If the wall 13 is completely straight and parallel to the deposition direction, which is also perfectly directional (or close enough), the metal vapor will not be deposited on the side of the wall because the impingement flux on this wall is equal to zero. However, with the trapezoidal shape, it is possible to determine which of the two side walls the metal evaporates even in the presence of an imperfectly directional beam.

[0067] Similar effects can be achieved with other groove shapes having a front wall that is wider than the rear wall and one or more side walls that taper rearwardly along at least part of their length. Figure 6 The groove shape shown will be discussed in detail later.

[0068] Figure 5 Another example of a trapezoidal groove shape is illustrated. Here, the groove is used to form contacts for the nanowire 9 (the nanowire 9 may require contacts for the gate and superconducting coating 5n in order to operate as part of a quantum bit). Panel a) shows the layout of the shadow wall 13 of the nanowire and the semiconductor core 4n, both of which are formed above the substrate 2 and any intermediate layers 6, 7 of the lower structure 3. The longest base of one groove 14i is arranged as a front wall facing the first deposition direction, which is the deposition direction of the first beam 5' of the metal vapor. The shortest base (the back wall in the first direction) has an opening 16 that opens onto a portion of the nanowire core 4n. When the first metal beam 5' is deposited, as shown in panel b), it not only forms a contact (contact) in the groove 14, such as a bonding pad 5b, but also passes through the opening 16 and covers the corresponding portion of the nanowire core 4n to form a superconducting coating 5n (assuming that the deposited metal is a suitable superconductor, such as Al). This also enables electrical contact between the membrane 5 in the recesses 14 and the nanowire coating 5n by the material deposited in the openings 16. Thus, the superconducting coating 5n of the semiconductor-superconducting nanowire 9 can be formed from the same deposition step as the rest of the inclined metal deposition.

[0069] Note that the superconductor (e.g. Al) coating 5n is formed only over a relatively small length of the semiconductor core of the nanowire, where Figure 5 (and Figure 6 , or Figure 7 Where the unshaded "cuts" in the walls of the ) connect to the nanowires 9 (discussed in more detail later) the small openings in the grooves connect to the semiconductor.

[0070] Referring also to panel c), Figure 5 Also shown is a double corner deposition using a smart wall (shadow wall) 13 with a gap 15 on both sides of the nanowire 9. The double wall 13 is used to avoid partial electrical shorting of the device.

[0071] The longest base of the second groove 14ii is arranged as a front wall facing the second deposition direction, which is the deposition direction 5" of the second beam of metal vapor. Typically, this can be the same or a different kind of metal as that deposited in the first beam. The shortest base of the second groove 14ii (the back wall in the second direction) has an opening 16 that opens to another part of the nanowire core 4n. When the second metal beam 5" is deposited, as shown in panel c, it not only forms a contact such as a bonding pad 5b in the second groove 14ii, but also passes through the opening 16 and covers a corresponding part of the nanowire core 4n to form a superconducting coating 5n (similar to the situation described with respect to the first groove 14i, but in the opposite direction and covering another part of the length of the semiconductor 4).

[0072] While the approach described above with a gap 15 is suitable for a single evaporation step, shorting may still occur when multiple depositions are made at different angles, even when a gap is used. Therefore, the design can be modified to allow for multiple angles. In an embodiment, the modification made is to use a double wall structure with the distance between the two walls being small enough to prevent metal deposition between them (again shorter than the shadow length). Figure 5 An example is described.

[0073] More generally, the deposition of the metal or conductor 5 can be performed from any two or more different directions. Note that a given direction referred to herein includes both polar angles and azimuth angles. The polar angle is the elevation angle relative to the plane of the substrate 2, or equivalently the angle formed with the normal of the substrate. The azimuth angle is the angle within the plane of the substrate 2. Different deposition directions may include different polar angles, azimuth angles, or both.

[0074] Using methods like Figure 5 As shown, complex isolation patterns can be made on chip 1 that contact the wires but not anything else, or even produce superconducting and normal contacts on semiconductor wires that are electrically isolated from each other. Figure 5 In the embodiment shown, this can be achieved by using two in-situ evaporation steps, where two different metals (e.g., aluminum and gold) are present in the deposited clusters at two different evaporation angles ( Figure 5 b and Figure 5 c, from the top and bottom of the picture respectively). Figure 5 In FIG. 5 , they are represented by two different gray colors. The deposition of two different first and second metals in their vapor form is labeled 5′ and 5″, respectively. The corresponding first deposited film and second deposited film are labeled 5i (dark gray) and 5ii (light gray), respectively. If two evaporation angles are used, the designed wall structure can contain similar Figure 5 double wall to achieve complete isolation between metal 5i and 5ii.

[0075] Figure 6 A schematic diagram of a smart wall 13 surrounding two bonding grooves is given. Gaps 15 are joined to electrically isolate the metal films 5 within the two grooves from each other and from the outside of the wall 13. The metal film 5 formed inside each groove 5 includes a bonding pad 5b. The raised portion shown within the groove 14 (in this case a square) can be patterned prior to nanowire deposition and then the metal film 5 is coated with the rest of the metal layer. This is because wire bonding applies force to the chip, so in order to avoid damage to the layer, a relatively thick metal layer can be pre-fabricated in the bonding groove area. However, this is optional, and instead the floor of the groove 14 forming the bonding pad 5b can simply be flat. Note also that Figure 6 Shows Figure 4 and Figure 5 A variation of the idea behind the trapezoid shown. Figure 6 In the embodiment of the embodiment of the present invention, the shape is not trapezoidal, but the function is similar. The longer front wall of the groove faces the oncoming deposition beam 5'. The side walls taper rearwardly along at least a portion of their length. Also in this case, two adjacent grooves share a central wall.

[0076] The grooves are isolated similarly to the previous examples. The deposited metal 5 also covers at least some of the sides and top of the walls (although Figure 6 14). However, this layout (which is only an illustrative schematic) avoids short circuits between two grooves 14. The central wall tapers gradually inwards. Therefore, no metal 5 is deposited on the left or right side of the central wall. Having some straight walls (as is the case here) can be a problem in some cases (for example, if the deposition is not completely directional) so that the metal can cover the inside and outside of the wall. However, this is not necessarily a problem because the evaporation 5' can be done very directional.

[0077] Figure 6 The example of also shows the idea of ​​an opening 16 on the shorter back wall, which opens to the nanowire for coating the nanowire core 4n and at the same time forms a contact between the nanowire coating 5n and the bonding pad 5b in the recess. Figure 6 In the case of Figure 5 The dual configuration angle method. Figure 5 Except for the case of dual angle or multi-angle deposition shown, in embodiments, the process requires only a single metal deposition step. The nanowires are semiconducting and hybrid semi / superconducting segments on the nanowires are produced in this evaporation. One advantage of this approach is that not only superconducting contacts, but also effective normal conductor contacts can be made in this way in a single deposition (electrical superconducting contacts made of Al, placed several microns away from the critical device, effectively act as normal conducting leads).

[0078] In an embodiment, following the post-fab paradigm, the device 1 does not include a top gate for electrostatically tuning the device. Instead, it employs a bottom and / or side gate structure that is fabricated prior to the smart wall 13 (and nanowire deposition or growth), and the electrochemical potential of the nanowires is controlled locally from below. To connect these gates to the outside world, the methods described above (e.g. Figure 5 or Figure 6) creates grooves for wire bonding 14. Since the bottom gate is fabricated prior to nanowire deposition or selective nanowire growth, this process allows for a higher thermal budget and higher quality dielectrics. If desired, additional gate or metal wires can be directed from the device to these bonding grooves through the shaded areas and the gaps described previously to provide electrical connection to the bonding area.

[0079] Figure 7 An exemplary implementation of a hybrid semiconductor-superconducting structure separated by normal conductor segments is shown. The left panel shows wafer 1 before metal deposition, and the right panel shows wafer 1 after metal deposition. Note that in the left panel, the lower dielectric layer 7 is not shown to illustrate the bottom gate 6g formed in the lower metal layer 6, but it will be understood that the lower dielectric layer 7 exists on top of the lower metal layer 6. In an embodiment, the lower dielectric layer 7 is a uniform coating, but it can alternatively be patterned, such as a patterned structure on top of the gate 6g. Figure 7 The grooves 14 are not shown in the figure, but one or more such grooves may be formed in the large white area marked as "metal film 5", for example for connecting to the nanowires 9 (e.g. in a manner similar to Figure 4-Figure 6 discussed). Figure 7 The incorporation of bottom gate in the process flow (following a post-fab approach) is emphasized.

[0080] exist Figure 7 In the example of , the wall structure 13 shields most of the length of the semiconductor 4n forming the core of one or more nanowires, except for one or more trenches 17 and / or cutout regions 18 left in the wall structure 13. These trenches 17 and / or cutouts 18 prevent the corresponding parts of the semiconductor 4n from being shown, so the deposited layer 5' covers each of these parts with a metal coating 5n to form a corresponding semiconductor-superconducting nanowire 9. In addition, the shadow is long enough to expose some parts of the lower dielectric layer 7 without being covered by the metal film 5.

[0081] The gates 5g / 6g are conductive and by applying appropriate voltages to the gates, a topological phase can be induced in the nanowire 9. However, these gates are electrically isolated from the nanowires because the gates and wires are physically separated by a gate dielectric (e.g., Al2O3, HfO2, or Si3N4 or similar). They apply an electrostatic potential to the gates via an electric field propagating in the dielectric. This is how most types of gates are implemented in research / industry. The electric field generated by the potential on the gates locally changes the energy levels of the nanowire 9, which is necessary for the realization of the phase change. The normally conductive segment is the very narrow shaded area in the center of the nanowire.

[0082] In summary, the present disclosure presents a method that reduces the need for fabrication steps following deposition or growth of semiconductor layers and subsequent metal deposition (e.g., including semiconductor nanowires), and in embodiments eliminates the need for any such steps entirely. By designing a shadow wall structure, preferably using a small evaporation angle relative to the plane of the substrate and in combination with a vertical hard mask template, electrical contacts can then be patterned onto the semiconductor structure 4 in a manner that keeps the contacts isolated from the global film 5 that is located on the substrate after evaporation. This will prevent or at least reduce the need for any fabrication on the chip after metal deposition. In embodiments, bottom gates or side gates can also be fabricated prior to deposition or growth of the semiconductor.

[0083] If an in-situ dielectric capping method can be employed in a deposition cluster, clean, protected, and resistant to degradation and aging devices can be obtained that are not possible with any conventional manufacturing design and process currently available. The disclosed process involves smart walls and, in embodiments, hard mask templates. This technique enables complex hybrid nanowire devices to be fabricated without relying on additional nanofabrication steps. Figure 8 A scanning electron microscope (SEM) image of a device is shown, which contains a network of smart walls with gaps and pads after the manufacturing process as described in this article. It allows to achieve electrically isolated contacts with the wires after metal deposition, avoiding metal etching. If a bottom gate is introduced, it is not necessary to make ports on this device. This last development is currently underway.

[0084] It should be understood that the above embodiments are described as examples only.

[0085] For example, similar techniques can be applied to form any structure where it is desirable to avoid or reduce potential damage by post-fabrication steps such as etching or lithography, which are typically used to form upper conductor structures. The disclosed techniques can be used to form other types of qubits or quantum devices, not just MZM-based qubits based on semiconductor-superconducting nanowires. For example. Semiconductor layer 4 can include components of other types of qubits or other quantum devices, such as SIS junctions, SIN junctions, and SQUIDS; or spin electronic devices, such as spin transistors, spin-based storage elements, or spin-based sensing elements; or even conventional semiconductor elements, such as transistors.

[0086] The conductive material 5 used in the upper and / or lower conductive layer 6, 5 need not be a metal. More generally, it may comprise a superconductor or other conductor. It may comprise a metal, or another conductor, such as a conductive polymer. In some embodiments, the conductive material 5 deposited in the oblique deposition may even comprise a semiconductor. In an embodiment, multiple sub-layers of different types of conductive materials may be applied in different steps at different deposition angles.

[0087] In embodiments, any of the disclosed methods may even be generally used for oblique deposition of any type of material. For example, in embodiments, the oblique deposition process may be used to form one or other type of layer, such as a dielectric, in addition to the conductive material 5. For example, the method may be used to evaporate a dielectric material such as Al2O3 as a gate dielectric and then a metal layer. Alternatively, the deposited material 5 may comprise only another type of material, such as only a dielectric. This may be particularly relevant in the case of a vertical template 10. For example, it may be desirable to deposit a dielectric only in the middle of the chip and have some bonding pads around the area without dielectric, where the bonding pads may be bonded.

[0088] The semiconductor 4 may comprise any semiconductor material, such as InAs, GaSb or InSb, including any kind of combination of these materials (e.g. GaxIn1-xAsySb1-y), with or without any kind of impurities (e.g. Bi, Te), single component or multicomponent (e.g. multilayer) in the form of nanoparticles, nanowires, thin films or bulk crystals. Or more generally, the first layer or active layer 4 forming the circuit part before the oblique deposition of the conductive material 5 does not have to include or not only include semiconductor material. In principle, the fourth layer can also be some previously patterned material (e.g. dielectric or metal), and even shadow wall deposition can be used in the previous deposition step. For example, in the case of forming a layer of SIS quantum components, each component can include two metal leads deposited on top of a dielectric sheet (forming the "I" part of the component) located on or above the substrate 2.

[0089] Where a dielectric is used for any part of the device 1, this may be any of a variety of dielectric materials known to those skilled in the art. Furthermore, the shadow wall 13 is not limited to being formed from a dielectric. For example. the wall 13 may be made of a metal or a semiconductor. This in effect enables some of the walls to be used as gates, for example. Dielectrics may be preferred in order to avoid the risk of accidental short circuits, and because thick dielectric layers are easy to construct. However, this is not a fundamental problem. If designed properly, the risk of short circuits is not much higher in the case of metal smart walls. Furthermore, there are also feasible fabrication techniques for metal etching.

[0090] It is not excluded that other layers than the ones shown in the figures may be present.

[0091] More generally, according to a first aspect of the present disclosure, there is provided a method for manufacturing an apparatus, comprising: providing a substrate defining a plane; forming a portion of an electronic circuit device on the substrate; forming a shadow wall structure on the substrate; and after forming the portion and the shadow wall, depositing an upper conductive layer on the substrate by depositing a conductive material in at least a first deposition direction at an acute angle to the plane of the substrate, wherein the shadow wall structure is arranged to cast a shadow during deposition to leave an area where no conductive material is deposited; wherein the shadow wall structure comprises one or more gaps, each of which is shorter than a shadow length of a corresponding portion of the shadow wall structure that casts a shadow into the gap to prevent conductive material from being formed in the gap and thereby create electrically isolated regions of the upper conductive layer from each other; and wherein the electrically isolated regions are arranged to form conductive elements for applying signals to and / or receiving signals from the electronic circuit device.

[0092] In an embodiment, the conductive element may include one or more of: one or more bonding pads for connecting external leads to one or more active components, one or more internal conductive lines connected between two or more active components, and / or one or more gates for gating one or more portions of the circuit.

[0093] In an embodiment, a method may include forming a lower structure over the substrate before forming the portion and the shadow wall, the lower structure including a lower conductive layer and / or a lower dielectric layer.

[0094] In an embodiment, the conductive element may include one or more bonding pads connected to the lower conductive layer, and / or one or more internal lines connected between the lower conductive layer and the one or more portions.

[0095] In an embodiment, the conductive material is a conductor. In an embodiment, the conductor may include a metal. Alternatively, the conductor may include a conductive polymer. In an embodiment, the conductor may include a superconductor (e.g., Al). Alternatively, the conductor may include a semiconductor.

[0096] In an embodiment, the portion of the circuit comprises a portion of a semiconductor.Alternatively or additionally, the portion of the circuit arrangement may comprise one or more portions of a dielectric.

[0097] In an embodiment, the device being manufactured may include a topological quantum computing device comprising a network of semiconductor-superconductor nanowires, each nanowire comprising a segment of a semiconductor and a superconductor coating formed on at least a portion of the semiconductor. The portion of the semiconductor may include the segment of the semiconductor. One or more electrical contacts may be arranged for applying a signal to and / or reading a signal from one or more nanowires.

[0098] In an embodiment, the conductive material may comprise a superconductor and the coating may comprise some superconductor deposited as part of the upper conductive layer, whereby the conductive elements are formed as part of the same oblique deposition as the superconducting coating.

[0099] In an embodiment, the shadow wall structure may include one or more partially enclosed grooves formed in the plane of the substrate, each groove including a wall surrounding an area in which a corresponding one of the conductive elements is formed within the groove wall. The wall of each groove may have one or more gaps for creating electrical isolation, and optionally an opening for forming a connection to at least one of the parts of the circuit device. In an embodiment, preferably, there are no other discontinuities in the wall of the groove.

[0100] In an embodiment, at least one of the recesses does not comprise an opening for forming a connection to any of the semiconductor components, but rather the respective conductive component is connected to one or more parts of the circuit arrangement via the underlying conductive layer.

[0101] In an embodiment, at least one groove may have a front wall facing the first deposition direction, a rear wall behind the front wall from the perspective of the first deposition direction, and a side wall connecting the front wall and the rear wall. The rear wall may be shorter than the front wall, and at least one side wall may be at least partially tapered backwards between the front wall and the rear wall, so that a shadow of the at least one side wall prevents the conductive material from being deposited outside the at least one side wall.

[0102] In an embodiment, the rear wall may comprise said opening.

[0103] In an embodiment, the groove may take the shape of a trapezoid, the front wall and the rear wall being parallel bases of the trapezoid, and the side walls being the sides of the trapezoid.

[0104] In an embodiment, the front wall may be arranged substantially perpendicular to the deposition direction (or at least one of the deposition directions).

[0105] In an embodiment, after forming portions of the circuit device, any conductive layer may be formed without using etching or photolithography steps.

[0106] In an embodiment, the deposition of the upper conductive layer over the substrate may be achieved by obliquely depositing the conductive material in each direction of a plurality of deposition directions at an acute angle to the plane of the substrate, the shadow wall structure thus casting a plurality of corresponding shadows in the deposition. The gap may be shorter than the shadow length of the corresponding portion of the wall structure casting all the plurality of shadows to prevent the conductive material from being deposited in the gap from any direction in the deposition direction.

[0107] Different directions may include different polar angles (vertical) and / or different azimuth angles (in the plane of the substrate). In an embodiment, the directions may include at least a first direction and a second direction, or only a first direction and a second direction. The first direction and the second direction may have opposite parallel azimuth angles (the directions are opposite and parallel in the projection on the plane of the substrate).

[0108] In an embodiment, the oblique deposition may include: forming a vertical template perpendicular to the substrate on one or more sides of the substrate, the vertical template including one or more holes, the one or more holes corresponding to one or more regions in the plane of the substrate, the deposition will be performed on the one or more regions given the angle of the deposition direction relative to the one or more directions of the substrate; and depositing the conductive material through the one or more holes at an angle of each deposition direction in the deposition direction or multiple deposition directions, thereby depositing the conductive material on the one or more regions. When the device is subsequently capped, the vertical template can be left in place or removed.

[0109] According to a more general variation of the first aspect, there is provided a method of manufacturing an apparatus, comprising: providing a substrate defining a plane; forming a portion of an electronic circuit device above the substrate; forming a shadow wall structure on the substrate; and after forming the portion and the shadow wall, depositing an upper layer on the substrate by oblique deposition of any material in at least a first deposition direction at an acute angle to the plane of the substrate, wherein the shadow wall structure is arranged to cast a shadow during deposition, leaving areas where no conductive material is deposited; wherein the shadow wall structure comprises one or more gaps, each of which is shorter than a shadow length of a corresponding portion of the shadow wall structure that casts a shadow into the gap, thereby producing a discontinuous area of ​​the material. In an embodiment, any of the features disclosed above may be applied additionally in conjunction with this definition of the first aspect.

[0110] According to the second aspect disclosed in this article, a method for manufacturing a device by inclined deposition can be provided, including: setting a substrate that defines a plane; forming a vertical template perpendicular to the substrate, the vertical template including one or more holes, the one or more holes corresponding to one or more areas in the plane of the substrate, and the deposition will be performed on the one or more areas at an acute angle relative to the plane of the substrate in a given deposition direction; and depositing material through the one or more holes in the direction at the angle, thereby depositing material on one or more of the areas.

[0111] The first aspect and the second aspect can be used together independently of each other. In an embodiment, any feature described with respect to the first aspect may or may not be used in combination with the second aspect, and vice versa.

[0112] According to another aspect disclosed herein, there is provided a device formed by any of the methods disclosed herein.

[0113] According to another aspect of the present disclosure, a method of operating a device is provided. The method may include applying an internal magnetic field or an external magnetic field to one or more nanowires and cooling the device to a temperature that induces superconductivity in the superconductor so as to induce Majorana zero modes (MZMs) in the one or more nanowires.

[0114] In an embodiment, the induction of the MZM may further include gating the nanowire with an electrostatic potential applied via one of the conductive elements.

[0115] Other variations or use cases of the disclosed technology will become apparent to those skilled in the art once given the disclosure herein.The scope of the present disclosure is not limited by the described embodiments but only by the appended claims.

Claims

1. A method for manufacturing a device, comprising: providing a substrate defining a plane; forming a portion of an electronic circuit device above the substrate; forming a shadow wall structure above the substrate; as well as after forming said portions and said shadow walls, depositing an upper conductive layer over said substrate by obliquely depositing a conductive material in at least a first deposition direction at an acute angle to said plane of said substrate, wherein said shadow wall structure is arranged to cast a shadow during said deposition to leave areas where said conductive material is not deposited; wherein the shadow wall structure includes one or more gaps, each gap being shorter than a shadow length of a corresponding portion of the shadow wall structure casting the shadow into the gap, to prevent the conductive material from forming in the gaps and thereby create electrically isolated regions of the upper conductive layer from one another; as well as The electrically isolated region is arranged to form an electrically conductive element for applying a signal to the electronic circuit arrangement and / or receiving a signal from the electronic circuit arrangement.

2. The method of claim 1 , wherein the conductive element comprises one or more of the following: one or more bonding pads for connecting external leads to one or more of the active components; one or more internal wires connected between two or more of the active components; and / or one or more gates for switching on one or more of the parts of the circuit device. 3 . The method of claim 1 , comprising forming a lower structure over the substrate before forming the portion and the shadow wall, the lower structure comprising a lower conductive layer and / or a lower dielectric layer.

4. The method according to claim 3, wherein the conductive element comprises: one or more bonding pads connected to the lower conductive layer; and / or one or more internal lines connected between the lower conductive layer and one or more portions of the portion. The method of claim 1 , wherein the conductive material is a metal. The method of claim 1 , wherein the conductive material is a superconductor. The method of claim 1 , wherein the portion comprises a portion of a semiconductor.

8. The method according to claim 1, wherein: The devices being fabricated include a topological quantum computing device comprising a network of semiconductor-superconductor nanowires, each nanowire comprising a semiconductor segment and a superconductor coating formed on at least a portion of the semiconductor segment; said portion of said semiconductor comprising said segment of said semiconductor; as well as One or more of the electrical contacts are arranged for applying a signal to one or more of the nanowires and / or reading the signal from one or more of the nanowires.

9. The method of claim 8, wherein the conductive material comprises a superconductor and the coating comprises some of the superconductor deposited as part of the upper conductive layer, whereby the conductive elements are formed as part of the same oblique deposition as the superconductor coating.

10. The method of claim 1, wherein the shadow wall structure comprises: one or more partially enclosed recesses formed in the plane of the substrate, each recess comprising walls enclosing a region within the walls of the recess in which a respective one of the conductive elements is formed; The walls of each recess have: one or more gaps for creating said electrical isolation, and optionally openings for forming a connection to at least one of said parts of said circuit arrangement, but no other discontinuities in said walls of said recess.

11. The method according to claim 10, comprising forming a lower structure above the substrate before forming the portion and the shadow wall, the lower structure comprising a lower conductive layer and / or a lower dielectric layer, wherein: At least one of the recesses does not comprise an opening for making a connection to any of the semiconductor components, but rather the respective conductive element is connected to one or more of the portions of the circuit arrangement via the lower conductive layer.

12. The method of claim 10 , wherein at least one of the grooves comprises: a front wall facing the first deposition direction; a rear wall behind the front wall from the perspective of the first deposition direction; and side walls joining the front wall and the rear wall, wherein the rear wall is shorter than the front wall, and at least one of the side walls at least partially tapers backwards between the front wall and the rear wall, such that a shadow of the at least one side wall prevents the conductive material from being deposited on the outside of the at least one side wall.

13. The method of claim 12, wherein the rear wall includes the opening.

14. The method of claim 1, wherein after forming the portion of the circuit arrangement, no etching or photolithography steps are used to form any conductive layers.

15. The method of claim 1, wherein: Depositing the upper conductive layer over the substrate is by obliquely depositing a conductive material in each of a plurality of deposition directions, each of the deposition directions being at an acute angle to the plane of the substrate, the shadow wall structure thereby casting a plurality of corresponding shadows in the deposition; as well as The gap is shorter than the shadow length of the corresponding portion of the wall structure casting all of the plurality of the shadows to prevent the conductive material from being deposited in the gap from any of the deposition directions.

16. The method according to claim 1, wherein the oblique deposition comprises: On one or more sides of the substrate, a vertical template is formed perpendicular to the substrate, the vertical template comprising one or more holes, the one or more holes corresponding to one or more regions in the plane of the substrate, given the angle of the deposition direction or multiple deposition directions relative to the substrate, the deposition will be performed above the one or more regions; and depositing the conductive material through the one or more holes in a deposition direction or in a plurality of deposition directions at an angle in each of the deposition directions, thereby depositing the conductive material over one or more of the regions; Wherein when the apparatus is subsequently capped, the vertical formwork is either left in place or removed.

17. A device formed by the method of claim 1.

18. A method of operating an apparatus formed by the method according to claim 8, the method of operating the apparatus comprising, An internal magnetic field or an external magnetic field is applied to one or more of the nanowires, and the device is cooled to a temperature that induces superconductivity in the superconductor so as to induce Majorana zero modes, MZMs, in the one or more nanowires.

19. The method of claim 18, wherein the inducing of the MZM further comprises gating the nanowire using an electrostatic potential applied through one of the conductive elements.

20. A method of manufacturing a device by oblique deposition, comprising: providing a substrate defining a plane; forming a vertical template perpendicular to the substrate, the vertical template comprising one or more holes, the one or more holes corresponding to one or more regions in the plane of the substrate, the deposition to be performed above the one or more regions given a deposition direction at an acute angle to the plane of the substrate; as well as Material is deposited through the one or more holes along the direction at the angle, thereby depositing the material over the one or more regions.

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