Array substrate and touch display device

Abstract

An array substrate and a touch display device. The array substrate includes a touch signal line, a common electrode and a first pixel electrode located on a substrate. The first pixel electrode includes a first edge and a second edge arranged in a first direction and extending in a second direction, and the touch signal line extends in the second direction and its orthographic projection on the substrate is located between the orthographic projections of the first edge and the second edge on the substrate. The via connection portion of the touch signal line is electrically connected to the common electrode through the touch line via hole, and the size of the via connection portion in the first direction is larger than the size of the portion of the touch signal line adjacent to the via connection portion in the first direction; the first pixel electrode also includes a third edge extending in the first direction, and the orthographic projection of the first recess of the third edge on the substrate accommodates at least part of the orthographic projection of the via connection portion on the substrate. When the array substrate is applied to a liquid crystal display device, color deviation can be avoided and the consistency of pixel capacitance can be improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an array substrate and a touch display device. Background Art

[0002] Touch screens are everywhere around us. Touch screens save space, are easy to carry, and have better human-computer interaction. Among all types of touch screens, capacitive touch screens are widely used because of their strong sensitivity and multi-touch capabilities.

[0003] The working principle of a capacitive touch screen is: a conductive material is set on the surface of a substrate as a touch electrode; when a touch object (such as a user's finger) touches the touch screen, the capacitance of the touch electrode at the touch point changes, and the position of the touch point on the touch screen can be detected based on the change.

[0004] Capacitive touch technology can be divided into touch technology using the mutual capacitance principle and touch technology using the self-capacitance principle. Compared with the touch technology using the mutual capacitance principle, the touch sensing accuracy and signal-to-noise ratio of the touch technology using the self-capacitance principle are higher.

[0005] The embedded touch screen is a touch screen in which the touch electrodes are arranged inside the display panel. The embedded touch screen has a high degree of integration and is thinner and lighter, so it has a wide range of application prospects. Summary of the invention

[0006] Embodiments of the present disclosure provide an array substrate and a touch display device, wherein the array substrate can avoid color deviation.

[0007] At least one embodiment of the present disclosure provides an array substrate, comprising: a substrate; a plurality of first display signal lines and a plurality of second display signal lines located on the substrate, wherein the plurality of first display signal lines extend along a first direction and are arranged in sequence along a second direction different from the first direction, the plurality of second display signal lines extend along the second direction and are arranged in sequence along the first direction, and the plurality of second display signal lines cross the first display signal lines to define a plurality of sub-pixel regions; a touch signal line located on the substrate, wherein the touch signal line extends along the second direction; a first insulating layer and a common electrode located on the substrate, wherein the first insulating layer is located between the touch signal line and the common electrode in a direction perpendicular to the substrate, and the touch signal line is electrically connected to the common electrode through a touch line via hole penetrating the first insulating layer; and a plurality of pixel electrodes located on the substrate, wherein the plurality of pixel electrodes are respectively located in the plurality of sub-pixel regions. The multiple sub-pixel regions include a first sub-pixel region, the multiple pixel electrodes include a first pixel electrode, the first pixel electrode is located in the first sub-pixel region, the first pixel electrode includes a first edge and a second edge arranged along the first direction and extending along the second direction, the orthographic projection of the touch signal line on the substrate is located between the orthographic projections of the first edge and the second edge on the substrate; the orthographic projection of the touch line via on the substrate is at least partially located between the orthographic projections of adjacent pixel electrodes on the substrate, the touch signal line includes a via connection portion electrically connected to the common electrode at the touch line via, the size of the via connection portion in the first direction is larger than the size of a portion of the touch signal line adjacent to the via connection portion in the first direction; the first pixel electrode is the pixel electrode closest to the via connection portion among the multiple pixel electrodes, the first pixel electrode also includes a third edge located between the first edge and the second edge, the third edge extends along the first direction, the third edge has a first recess, and the orthographic projection of the first recess on the substrate accommodates at least part of the orthographic projection of the via connection portion on the substrate.

[0008] In the array substrate provided in at least one embodiment, the first sub-pixel area includes a first area and a second area surrounding the first area; in the first direction, the distances between the orthographic projection of the touch signal line in the first area and two second display signal lines adjacent to the touch signal line are not equal.

[0009] In at least one embodiment, the array substrate includes a plurality of touch signal lines, and a first pixel electrode in a first sub-pixel area in each column of sub-pixel areas includes a first edge and a second edge, between which there is an orthographic projection of one of the plurality of touch signal lines on the substrate.

[0010] In the array substrate provided in at least one embodiment, an orthographic projection of the via connection portion on the substrate does not overlap with an orthographic projection of the first pixel electrode on the substrate.

[0011] In the array substrate provided in at least one embodiment, the edge of the first recess is parallel to the edge of the via connecting portion adjacent thereto.

[0012] In the array substrate provided in at least one embodiment, the array substrate includes a plurality of touch signal lines located on the substrate; the plurality of pixel electrodes include adjacent first-row pixel electrodes and second-row pixel electrodes, the first-row pixel electrodes and the second-row pixel electrodes both extend along the first direction and are arranged in sequence along the second direction; the first-row pixel electrodes and the second-row pixel electrodes both intersect with at least two touch signal lines, at least one of the at least two touch signal lines has the via connection portion between the first-row pixel electrode and the second-row pixel electrode, and at least another of the at least two touch signal lines does not have the via connection portion between the first-row pixel electrode and the second-row pixel electrode.

[0013] In the array substrate provided in at least one embodiment, the first row of pixel electrodes is closer to the via-hole connecting portion than the second row of pixel electrodes, and the pixel electrode in the first row of pixel electrodes closest to the via-hole connecting portion has the first recess.

[0014] In the array substrate provided by at least one embodiment, the pixel electrode in the first row of pixel electrodes adjacent to the pixel electrode closest to the via-hole connecting portion has a second recess facing the pixel electrode in the second row.

[0015] In the array substrate provided in at least one embodiment, the array substrate includes a first electrode, the first electrode is the common electrode or the first pixel electrode, the first electrode includes a plurality of strip electrodes, and the plurality of strip electrodes extend along the second direction; within the first sub-pixel area, the orthographic projection of the touch signal line is at least partially located between the orthographic projections of adjacent strip electrodes in the first direction on the substrate.

[0016] At least one embodiment of the present disclosure provides an array substrate, comprising: a substrate; a plurality of first display signal lines and a plurality of second display signal lines located on the substrate, wherein the plurality of first display signal lines extend along a first direction and are arranged in sequence along a second direction different from the first direction, the plurality of second display signal lines extend along the second direction and are arranged in sequence along the first direction, and the plurality of second display signal lines cross the first display signal lines to define a plurality of sub-pixel regions; a touch signal line located on the substrate, wherein the touch signal line extends along the second direction; a common electrode located on the substrate, which is electrically connected to the touch signal line; and a plurality of pixel electrodes located on the substrate, wherein the plurality of pixel electrodes are respectively located in the plurality of sub-pixel regions. The plurality of sub-pixel regions include a first sub-pixel region, the plurality of pixel electrodes include a first pixel electrode, the first pixel electrode is located in the first sub-pixel region, the first pixel electrode includes a first edge and a second edge arranged along the first direction and extending along the second direction, and the orthographic projection of the touch signal line on the substrate is located between the orthographic projections of the first edge and the second edge on the substrate; the array substrate includes a first electrode, the first electrode is the common electrode or the first pixel electrode, the first electrode includes a plurality of strip electrodes, and the plurality of strip electrodes extend along the second direction; in the first sub-pixel region, the orthographic projection of the touch signal line is at least partially located in the strip electrodes adjacent to each other in the first direction. The electrode is between the orthographic projections on the substrate; the first sub-pixel area includes a first area and a second area surrounding the first area; the multiple strip electrodes include a first strip electrode adjacent to the touch signal line, the first strip electrode has a first strip electrode bending portion in the first area, the touch signal line has a first touch line bending portion in the first area, the first touch line bending portion and the first strip electrode bending portion are bent in the same direction in the first area, the orthographic projection of the first touch line bending portion on the substrate and the orthographic projection of the first strip electrode bending portion on the substrate are arranged sequentially in the first direction, and the bending angle of the first touch line bending portion is greater than the bending angle of the first strip electrode bending portion.

[0017] In the array substrate provided by at least one embodiment, the first strip electrode bending portion is located on a first side of the first touch line bending portion, and the first touch line bending portion is bent in a direction away from the first strip electrode bending portion; along the direction from one end to the other end of the first strip electrode, the distance between the orthographic projection of the first touch line bending portion and the orthographic projection of the first strip electrode bending portion first decreases and then increases.

[0018] In the array substrate provided by at least one embodiment, the first strip-shaped electrode bent portion has a tip extending toward the first touch wire bent portion, and the first touch wire bent portion has an arc-shaped end extending in a direction away from the tip.

[0019] In the array substrate provided by at least one embodiment, the orthographic projection of the first strip-shaped electrode bent portion does not overlap with the orthographic projection of the first touch line bent portion.

[0020] In the array substrate provided in at least one embodiment, the plurality of strip electrodes also include a second strip electrode adjacent to the touch signal line, the second strip electrode having a second strip electrode bending portion in the first area, the first strip electrode bending portion, the second strip electrode bending portion and the first touch line bending portion located therebetween are bent toward the same direction within the first area, the orthographic projection of the second strip electrode bending portion on the substrate and the orthographic projection of the first touch line bending portion are arranged sequentially in the first direction, and the bending angle of the second strip electrode bending portion is smaller than the bending angle of the first touch line bending portion.

[0021] In at least one embodiment, the array substrate further includes a plurality of switching elements located on the substrate, wherein the plurality of switching elements are respectively located in the plurality of sub-pixel regions, the plurality of switching elements include a first switching element, and the first switching element is located in the first sub-pixel region, the touch signal line has a second touch line bend portion, the second touch line bend portion is located between the first touch line bend portion and the first switch element in the second direction, and the second touch line bend portion is located between adjacent switch elements in the first direction.

[0022] In the array substrate provided in at least one embodiment, a bending angle of the second touch wire bending portion is greater than a bending angle of the first touch wire bending portion.

[0023] In the array substrate provided in at least one embodiment, the first strip electrode has a third strip electrode bending portion, the third strip electrode bending portion is located between the second touch line bending portion and the first switch element in the first direction, and the bending direction of the third strip electrode bending portion is opposite to that of the second touch line bending portion.

[0024] In the array substrate provided in at least one embodiment, each switch element includes a gate, a source, and a drain, and an orthographic projection of the source on the substrate includes a U-shaped structure.

[0025] At least one embodiment of the present disclosure provides an array substrate, comprising: a substrate; a plurality of first display signal lines and a plurality of second display signal lines located on the substrate, wherein the plurality of first display signal lines extend along a first direction and are arranged in sequence along a second direction different from the first direction, the plurality of second display signal lines extend along the second direction and are arranged in sequence along the first direction, and the plurality of second display signal lines cross the first display signal lines to define a plurality of sub-pixel regions; a touch signal line located on the substrate, wherein the touch signal line extends along the second direction; a first insulating layer and a common electrode located on the substrate, wherein the first insulating layer is located between the touch signal line and the common electrode in a direction perpendicular to the substrate, and the touch signal line is electrically connected to the common electrode through a touch line via hole penetrating the first insulating layer; and a plurality of pixel electrodes located on the substrate, wherein the plurality of pixel electrodes are respectively located in the plurality of sub-pixel regions. The multiple sub-pixel areas include a first sub-pixel area, the multiple pixel electrodes include a first pixel electrode, the first pixel electrode is located in the first sub-pixel area, the first pixel electrode includes a first edge and a second edge arranged along the first direction and extending along the second direction, and the orthographic projection of the touch signal line on the substrate is located between the orthographic projections of the first edge and the second edge on the substrate; the array substrate includes a pixel electrode layer located on the substrate, the pixel electrode layer includes the multiple pixel electrodes and includes an etching blocking portion insulated from the multiple pixel electrodes, the etching blocking portion is located in the touch line via hole, and the common electrode is electrically connected to the touch signal line through the etching blocking portion.

[0026] In the array substrate provided in at least one embodiment, the first insulating layer includes a first sub-insulating layer, an organic insulating layer, and a second sub-insulating layer sequentially located on the substrate, and the first sub-insulating layer is located between the organic insulating layer and the substrate in a direction perpendicular to the substrate; the touch line via includes a first sub-insulating layer via located in the first sub-insulating layer, an organic insulating layer via located in the organic insulating layer, and a second sub-insulating layer via located in the second sub-insulating layer, the first sub-insulating layer via, the organic insulating layer via, and the second sub-insulating layer via are interconnected, and the etching blocking portion at least covers the side wall of the first sub-insulating layer via.

[0027] In the array substrate provided in at least one embodiment, adjacent edges of the first sub-insulating layer via hole and the organic insulating layer via hole are aligned.

[0028] In the array substrate provided in at least one embodiment, the orthographic projection of the organic insulating layer on the substrate includes a portion extending into the orthographic projection of the via hole of the second sub-insulating layer on the substrate.

[0029] In the array substrate provided in at least one embodiment, the array substrate also includes a connector and a second insulating layer located on the substrate, wherein the second insulating layer is located on the side of the touch signal line facing the substrate, and the first insulating layer is located on the side of the touch signal line facing away from the substrate; the connector is located on the side of the second insulating layer facing the substrate, and the connector is electrically connected to the common electrode through a connector via that penetrates the second insulating layer and the first insulating layer.

[0030] In the array substrate provided in at least one embodiment, the connecting member via includes a first sub-via located in the second insulating layer, a second sub-via located in the first sub-insulating layer, a third sub-via located in the organic insulating layer, and a fourth sub-via located in the second sub-insulating layer, and the first sub-via, the second sub-via, the third sub-via and the fourth sub-via are interconnected.

[0031] An embodiment of the present disclosure further provides a touch display device, which includes the array substrate provided by any of the above embodiments.

[0032] In the touch display device provided in at least one embodiment, the touch display device further includes a black matrix layer, a portion of the first sub-pixel area surrounded by the black matrix layer is an opening area, and the orthographic projection of the touch signal line in the first sub-pixel area passes through the opening area. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0034] Figure 1A A schematic diagram of an embedded touch screen.

[0035] Figure 1B for Figure 1A A schematic diagram of the positional relationship between touch signal lines and sub-pixel areas in an embedded touch screen is shown.

[0036] Figure 2 A schematic diagram of the positional relationship between touch signal lines and sub-pixel areas in an array substrate provided in an embodiment of the present disclosure.

[0037] Figure 3 A schematic top view of an array substrate provided in an embodiment of the present disclosure is shown first.

[0038] Figure 4A A schematic top view of an array substrate provided in an embodiment of the present disclosure Figure 2 .

[0039] FIG. 4B to FIG. 4D for Figure 4A A schematic top view of part of the structure in the array substrate is shown.

[0040] Figure 5A A schematic top view of an array substrate provided in an embodiment of the present disclosure Figure 3 .

[0041] Figure 5B for Figure 5A A schematic top view of some structures in the array substrate is shown.

[0042] Fig. 6A A schematic diagram of the positional relationship between the second display signal lines and the strip electrodes in the array substrate provided by an embodiment of the present disclosure.

[0043] Figure 6B A schematic diagram of the positional relationship between touch signal lines and strip electrodes in an array substrate provided in an embodiment of the present disclosure.

[0044] Fig. 7A A schematic diagram of the connection relationship between the touch electrodes TE and the touch signal lines TX in the array substrate provided by the embodiment of the present disclosure.

[0045] Figure 7B A schematic diagram of the positional relationship between the touch line via holes and the sub-pixel areas in the array substrate provided in an embodiment of the present disclosure.

[0046] Fig. 8A and Figure 8B A schematic diagram of the positional relationship between touch signal lines and pixel electrodes in an array substrate provided in an embodiment of the present disclosure.

[0047] Fig. 9A A first schematic cross-sectional structural diagram of an array substrate provided in an embodiment of the present disclosure.

[0048] Fig. 9B For Fig. 9A Schematic diagram of the manufacturing steps of the array substrate shown.

[0049] Fig.10 For Fig. 9A The schematic diagram of the array substrate when over-engraving occurs is shown.

[0050] Fig.11A A cross-sectional view of an array substrate provided in an embodiment of the present disclosure Figure 2 .

[0051] Fig. 11B for Fig.11A Schematic diagram of the manufacturing steps of the array substrate shown.

[0052] Fig. 12AA schematic top view of a touch display device provided in an embodiment of the present disclosure.

[0053] Fig. 12B The touch display device provided by the embodiment of the present disclosure is Fig. 12A A simplified cross-sectional view of the dotted line A in FIG.

[0054] Fig.13 A flow chart of a method for manufacturing an array substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0056] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0057] Figure 1A is a schematic diagram of an embedded touch screen. Figure 1B for Figure 1A Schematic diagram of the positional relationship between the touch signal line and the sub-pixel area in the embedded touch screen. Figure 1A As shown, the embedded touch screen includes a plurality of touch electrodes TE and a plurality of touch signal lines Tx arranged in an array, and each touch electrode TE is electrically connected to a corresponding touch signal line Tx through a via VH, thereby being electrically connected to a touch control circuit IC through the touch signal line Tx. Figure 1B As shown, the embedded touch screen includes a plurality of pixel areas P ( Figure 1BFour pixel regions P1, P2, P3 and P4 are shown in the figure for illustration), each pixel region P includes three sub-pixel regions (see SP1, SP2, SP3), each sub-pixel region is composed of adjacent gate lines G ( Figure 1B Two gate lines G1 and G2 are shown for illustration) and the adjacent data line S ( Figure 1B Each touch signal line Tx is located between two adjacent columns of pixel regions P in the extending direction of the gate line G.

[0058] The inventors of the present application have noticed in their research that Figure 1A When the embedded touch screen shown is applied to a liquid crystal display device, the touch signal line Tx may easily cause color deviation in the liquid crystal display device.

[0059] Figure 2 Schematic diagram of the positional relationship between the touch signal line and the sub-pixel area in the array substrate provided by the embodiment of the present disclosure. Figure 2 As shown, the embodiment of the present disclosure provides an array substrate, which includes a substrate BS and includes a plurality of first display signal lines PX1 and a plurality of second display signal lines PX2 located on the substrate BS. The plurality of first display signal lines PX1 extend along a first direction and are arranged in sequence along a second direction different from the first direction; the plurality of second display signal lines PX2 extend along the second direction and are arranged in sequence along the first direction. One of the first display signal line PX1 and the second display signal line PX2 is a gate line and the other is a data line; the second display signal line PX2 crosses the first display signal line PX1 to define a plurality of sub-pixel regions SP, and the plurality of sub-pixel regions SP respectively belong to a plurality of pixel regions P( Figure 2 Four pixel regions P1, P2, P3 and P4 are shown for illustration purposes only), that is, each pixel region P includes a plurality of sub-pixel regions SP. For example, each pixel region P includes three sub-pixel regions SP1, SP2 and SP3. Each sub-pixel region SP includes a first region and a second region ( Figure 2 The first area and the second area are not shown); when the array substrate is used for a display device, the first area of ​​the sub-pixel area is an opening area not blocked by the black matrix layer in the display device, and the second area of ​​the sub-pixel area is a non-opening area blocked by the black matrix layer.

[0060] like Figure 2As shown in FIG. 1 , the array substrate further includes a plurality of touch signal lines TX located on the substrate BS, the plurality of touch signal lines TX extending along the second direction and arranged in sequence along the first direction; and each touch signal line TX passes through the first area of ​​the sub-pixel area SP. In the embodiment of the present disclosure, by making the touch signal line TX pass through the first area of ​​the sub-pixel area, for example, making the same touch signal line TX pass through the first area of ​​the sub-pixel area in the same column, it is possible to avoid Figure 1A and Figure 1B The in-cell touch screen shown in the figure has color shift when applied to a liquid crystal display device.

[0061] The array substrate also includes a plurality of pixel electrodes ( Figure 2 (not shown), the plurality of pixel electrodes are respectively located in the plurality of sub-pixel regions SP, for example, each pixel electrode is located in one sub-pixel region; each pixel electrode includes a first edge and a second edge arranged along a first direction and extending along a second direction, the first edge and the second edge are the edges of the pixel electrode that are farthest apart in the first direction, and the first edge and the second edge are located in the first region of the sub-pixel region where the pixel electrode is located. In view of this, the touch signal line TX passing through the first region of the sub-pixel region means that the portion of the orthogonal projection of the touch signal line TX on the substrate BS in the sub-pixel region is located between the orthogonal projections of the first edge and the second edge of the pixel electrode in the sub-pixel region on the substrate.

[0062] The inventors of the present application also noticed that Figure 1A and Figure 1B When the embedded touch screen shown is applied to medium and large-sized touch products, the number of touch electrodes TE is large, and the touch electrodes TE with a relatively fixed area cannot be arranged with many touch signal lines TX, so the number of touch signal lines TX and touch electrodes TE cannot be matched. For example, for common MobileHD products, the area of ​​the pixel area is about 100*100μm, and the area of ​​the touch electrode is about 4*4mm, then each touch electrode corresponds to a 40*40 pixel area, that is, according to the following Figure 1A and 1B The wiring method shown can arrange 40 touch signal lines in each touch electrode; however, when the size of the touch product is larger, the number of touch electrodes in a column is greater than 40, and the number of touch signal lines that can be arranged in each touch electrode cannot meet the number of touch signal lines required by the touch electrodes in the column.

[0063] In order to match the number of touch signal lines with the number of touch electrodes, in at least one embodiment, Figure 2 As shown in FIG. 1 , the first area of ​​each column of sub-pixel areas SP passes through a touch signal line TX. Figure 1BIn the wiring method shown, each touch signal line TX is located between two adjacent columns of pixel areas P. In the embodiment of the present disclosure, the first area of ​​each column of sub-pixel areas SP included in each column of pixel areas P passes through a touch signal line TX. This can greatly increase the number of touch signal lines TX and avoid the situation where the number of touch signal lines TX cannot meet the number of touch electrodes when the touch product is large in size and has a large number of touch electrodes.

[0064] On the other hand, since the number of touch signal lines TX is increased in the embodiment of the present disclosure, each touch electrode can use more touch signal lines TX to supply signals, thereby enhancing the supply of touch signals and avoiding touch horizontal stripes.

[0065] On the other hand, since each of the multiple sub-pixel areas (for example, three sub-pixel areas) included in the same pixel area corresponds to a touch signal line TX, the parasitic capacitance / storage capacitance ratio Cpd / Cst of these sub-pixel areas is more uniform, thereby avoiding the phenomenon of uneven picture color.

[0066] On the other hand, the inventor of the present application noticed that when the touch product is large in size and adopts Figure 1A and Figure 1B In the case of the embedded touch screen shown in the figure, the touch signal will experience RC delay when it is transported from the output end of the touch control circuit IC to the far end of the touch product screen, which causes the touch signal to attenuate, that is, the signal of the touch electrode at the far end of the screen is weaker than the signal of the touch electrode at the near end of the screen (the near end of the screen is closer to the IC than the far end of the screen), resulting in a display difference between the far end of the screen and the near end of the screen (for example, bad horizontal stripes); in the embodiment of the present disclosure, the number of touch signal lines TX is relatively large. For example, a single touch electrode can use multiple touch signal lines TX to supply signals at the same time, which is equivalent to reducing the overall resistance R of the touch signal line electrically connected to the touch electrode, so that the signal attenuation of the touch electrode becomes smaller, so as to reduce the display difference between the far end of the screen and the near end of the screen.

[0067] In at least another embodiment, the first areas of a portion of the plurality of sub-pixel areas included in the array substrate may be respectively passed by the touch signal lines, and the first areas of another portion of the plurality of sub-pixel areas may not be passed by the touch signal lines.

[0068] For ease of description, the sub-pixel region of the first region where the touch signal line passes is referred to as the first sub-pixel region, the pixel electrode located in the first sub-pixel region is referred to as the first pixel electrode, the sub-pixel region of the first region where the touch signal line does not pass is referred to as the second sub-pixel region, and the pixel electrode in the second sub-pixel region is referred to as the second pixel electrode. Therefore, the first region of each column of sub-pixel regions SP passes through a touch signal line TX, which means that there is a positive projection of the touch signal line TX on the substrate between the positive projections of the first edge and the second edge of the first pixel electrode in the first sub-pixel region of each column of sub-pixel regions on the substrate.

[0069] In at least one embodiment, the array substrate includes a first electrode located on a substrate BS, the first electrode includes a plurality of strip electrodes extending along a second direction; in a first sub-pixel region, an orthographic projection of a touch signal line on the substrate BS is at least partially located between orthographic projections of adjacent strip electrodes on the substrate BS in the first direction. By locating the touch signal line between adjacent strip electrodes, the touch signal line can be prevented from overlapping with the adjacent strip electrodes as much as possible, so as to reduce the capacitance between the touch signal line and the first electrode. The first electrode may be a common electrode or a pixel electrode.

[0070] In at least one embodiment, the array substrate further includes a second electrode located on the substrate, and the second electrode is located between the first electrode and the substrate in a direction perpendicular to the substrate (a direction perpendicular to the main surface of the substrate). When the first electrode is a common electrode, the second electrode is a pixel electrode; when the first electrode is a pixel electrode, the second electrode is a common electrode. When the array substrate is applied to a liquid crystal display device for display, a pixel voltage is applied to the pixel electrode, and a common voltage is applied to the common electrode, so that an electric field for controlling the deflection of the liquid crystal in the liquid crystal display device is generated between the pixel electrode and the common electrode to realize the display function.

[0071] In at least one embodiment, the first electrode is a common electrode and is electrically connected to the touch signal line, that is, the common electrode is reused as a touch electrode. At this time, when the array substrate is applied to a liquid crystal display device, for example, a time-sharing drive method can be adopted, that is: in the display stage, a common voltage is applied to the common electrode to realize the display function; in the touch stage, a touch signal is applied to the common electrode to realize the touch function.

[0072] For example, the array substrate provided by the embodiment of the present disclosure may adopt the principle of self-capacitance. Taking the common electrode being reused as a touch electrode as an example, the common electrode layer includes a plurality of common electrodes electrically insulated from each other, the plurality of common electrodes are arranged in a plurality of rows and a plurality of columns, each common electrode is used as a self-capacitance touch electrode, and the area where each common electrode is located has a plurality of rows and columns of sub-pixel areas.

[0073] In at least one embodiment, the array substrate further comprises a plurality of switch elements on the substrate, the plurality of switch elements being respectively located in a plurality of sub-pixel regions included in the array substrate and being respectively electrically connected to the pixel electrodes in the sub-pixel regions, and the switch elements being located at the position where the first display signal line and the second display signal line intersect. The switch element located in the first sub-pixel region is hereinafter referred to as the first switch element. In order to avoid the touch signal line from overlapping with the first switch element to reduce the parasitic capacitance, in at least one embodiment, the touch signal line has a bend at a position adjacent to the first switch element to bypass the switch element, and the bend is located between adjacent switch elements in the first direction. In order to avoid the touch signal line from overlapping with the first switch element, in at least one embodiment, in the first region of the first sub-pixel region, the distances between the touch signal line and the two second display signal lines adjacent thereto may not be equal, and the first switch element in the first sub-pixel region is located between the touch signal line and the second display signal line having a larger distance to the touch signal line and adjacent to the touch signal line.

[0074] Hereinafter, the array substrate provided by the embodiment of the present disclosure is described in detail by taking the case where the first electrode is a common electrode including a plurality of strip electrodes and the second electrode is a pixel electrode as an example.

[0075] Figure 3 A schematic top view of an array substrate provided in an embodiment of the present disclosure; Figure 4A A schematic top view of an array substrate provided in an embodiment of the present disclosure Figure 2 ; FIG. 4B to FIG. 4D for Figure 4A A schematic top view of a portion of the structure in the array substrate shown; Figure 5A A schematic top view of an array substrate provided in an embodiment of the present disclosure Figure 3 ; Figure 5B A schematic top view of part of the structure in the array substrate is shown.

[0076] like Figure 3-4C and Figure 5A-5B As shown, the array substrate provided by the embodiment of the present disclosure includes a substrate BS, and includes a plurality of first display signal lines PX1, a plurality of second display signal lines PX2, and a plurality of touch signal lines TX located on the substrate BS. The first display signal line PX1 extends along the first direction, the second display signal line PX2 extends along the second direction, and the area defined by the intersection of adjacent first display signal lines PX1 and adjacent second display signal lines PX2 is a sub-pixel area. The sub-pixel area includes a first area (as shown by the area surrounded by each dotted box) and a second area surrounding the first area. The first display signal line PX1 and the second display signal line PX2 are both located in the second area. The touch signal line TX extends along the second direction, and the touch signal line TX passes through the first area of ​​the sub-pixel area where it is located.

[0077] In at least one embodiment, Figure 3-4C and Figure 5A-5B As shown, at the position where the touch signal line TX crosses the first display signal line PX1 , the first display signal line PX1 has a recess to reduce the overlapping area between the first display signal line PX1 and the touch signal line TX, thereby reducing the parasitic capacitance.

[0078] In at least one embodiment, Figure 3 As shown, the array substrate includes a plurality of sub-pixel regions including a first sub-pixel region P11 and a second sub-pixel region P12, the first region of the first sub-pixel region P11 passes through the touch signal line TX, and the first region of the second sub-pixel region P12 does not pass through the touch signal line TX. In other embodiments, such as Figure 4A and Figure 5A As shown, a touch signal line TX passes through the first area of ​​each sub-pixel area, that is, the multiple sub-pixel areas included in the array substrate only include the first sub-pixel area P11 but not the second sub-pixel area P12. In this case, there is only one touch signal line TX between each two adjacent second display signal lines PX2, and there is only one second display signal line PX2 between each two adjacent touch signal lines TX. As described above, by making the first area of ​​each sub-pixel area pass through only one touch signal line TX, it is possible to avoid the situation where the number of touch signal lines TX cannot meet the number of touch electrodes when the number of touch electrodes is large, to avoid poor touch horizontal stripes, to avoid the phenomenon of uneven screen color, and to reduce the display difference between the far end of the screen and the near end of the screen.

[0079] like Figures 3 to 5B As shown, the array substrate further includes a plurality of pixel electrodes PE located on the substrate BS, each pixel electrode PE is located in a sub-pixel region, and each pixel electrode PE includes a first edge PE1 and a second edge PE2 arranged along the first direction and extending along the second direction, and the first edge PE1 and the second edge PE2 are the two edges of the pixel electrode PE that are farthest apart in the first direction. For example, the first edge PE1 and the second edge PE2 both include two ends arranged along the second direction and a main body located between the two ends, the two ends are both located in the second region of the sub-pixel region, and the main body is located in the first region.

[0080] In some embodiments, Figure 3-4A , Figure 4C and Figure 5A-5BAs shown, the edges PE1 and PE2 that are farthest apart and opposite to each other in the first direction included in each pixel electrode PE are both located in the first area. In view of this, the touch signal line TX passes through the first area of ​​the first sub-pixel area P11 means that, in the first sub-pixel area P11, the positive projection of the touch signal line TX on the substrate BS is located between the positive projections of the first edge PE1 and the second edge PE2 included in the first pixel electrode PEA on the substrate BS. Since the size of the first area in the second direction is larger than the size of the second area in the second direction, in the second direction, the size of the portion of the touch signal line located in the first area is larger than the size of the portion of the touch signal line located in the second area.

[0081] In at least one embodiment, Figure 3 As shown, the first pixel electrode PEA in the first sub-pixel region P11 has an opening SL extending along the second direction between the first edge PE1 and the second edge PE2, and the positive projection of the touch signal line TX on the substrate BS is located between the positive projections of the edges opposite in the first direction included in the opening SL on the substrate BS, so that the touch signal line TX and the first pixel electrode PEA do not overlap with the first pixel electrode PEA at the position of the opening SL, thereby reducing the capacitance between the touch signal line TX and the first pixel electrode PEA. Figure 3 As shown, since the touch signal line TX does not pass through the first area of ​​the second sub-pixel area P12, that is, the second pixel electrode PEB in the second sub-pixel area P12 does not overlap with the touch signal line TX. In this case, the second pixel electrode PEB in the second sub-pixel area is a continuous structure without an opening between its two edges (that is, the first edge PE1 and the second edge PE2) that are farthest apart in the first direction, that is, the second pixel electrode PEB is a plate-like structure.

[0082] In at least one embodiment, Figure 3 As shown, when the first pixel electrode PEA in the first sub-pixel area P11 has an opening SL corresponding to the touch signal line TX and the second pixel electrode PEB in the second sub-pixel area P12 does not have an opening, in order to reduce the difference between the pixel capacitances of the first sub-pixel area P11 and the second sub-pixel area P12, the size of the first pixel electrode PEA in the first direction is larger than the size of the second pixel electrode PEB in the second direction, that is, the distance between the first edge PE1 and the second edge PE2 of the first pixel electrode PEA is larger than the distance between the first edge PE1 and the second edge PE2 of the second pixel electrode PEB.

[0083] In at least another embodiment, Figure 4A , Figure 4C and Figure 5A-5BAs shown, since the first area of ​​each sub-pixel area is passed by the touch signal line TX, the pixel electrode PE in each sub-pixel area is a continuous structure without openings between the first edge PE1 and the second edge PE2 (ie, each pixel electrode PE is a plate-shaped structure).

[0084] In at least another embodiment, when the first area of ​​each sub-pixel area is passed by the touch signal line TX, the pixel electrode PE in each sub-pixel area has an opening extending along the second direction between the first edge PE1 and the second edge PE2, and the orthographic projection of the touch signal line TX in the sub-pixel area on the substrate BS is located between the orthographic projections of the opposite edges in the first direction included in the opening on the substrate BS, so as to reduce the capacitance between the touch signal line TX and the pixel electrode PE.

[0085] like Figure 3-4C and Figure 5A-5B As shown, the array substrate further includes a plurality of switch elements T located on the substrate BS, and the plurality of switch elements T are respectively located in a plurality of sub-pixel regions included in the array substrate. For example, the plurality of switch elements T correspond to the plurality of sub-pixel regions one by one. Each touch signal line TX is a curved structure having a curved portion in the first sub-pixel region P11, so as to bypass the first switch element T1 in the first sub-pixel region P11 through the curved portion.

[0086] In order to prevent the touch signal line TX from overlapping with the first switch element T1 , in at least one embodiment, the touch signal line TX is located between two adjacent switch elements T in the first direction.

[0087] In order to avoid the touch signal line TX from overlapping with the first switching element T1, in at least one embodiment, in the first area of ​​the first sub-pixel area P11, the distances between the orthographic projection of the touch signal line TX on the substrate BS to two second display signal lines PX2 adjacent to the touch signal line TX are not equal, and the first switching element T1 included in the first sub-pixel area P11 is located between the touch signal line TX and the second display signal line PX2 that is farther from the touch signal line TX.

[0088] like Figure 3-4B and Figure 5AAs shown, the array substrate further includes a plurality of strip electrodes ST located on the substrate BS, and the plurality of strip electrodes ST extend along the second direction; in the first sub-pixel region P11, the orthographic projection of the touch signal line TX on the substrate BS is at least partially located between the orthographic projections of the adjacent strip electrodes ST on the substrate BS in the first direction. For example, in the first region of the first sub-pixel region P11, the touch signal line TX and the adjacent strip electrodes ST do not overlap; in the second region of the first sub-pixel region P11, the touch signal line TX and the adjacent strip electrodes ST do not overlap or only partially overlap. For example, the plurality of strip electrodes ST included in the array substrate belong to the common electrode CE. In other embodiments, the pixel electrode PE may also include the plurality of strip electrodes ST.

[0089] Fig. 6A A schematic diagram of the positional relationship between the second display signal line and the strip electrodes in the array substrate provided by an embodiment of the present disclosure; Figure 6B A schematic diagram of the positional relationship between touch signal lines and strip electrodes in an array substrate provided in an embodiment of the present disclosure.

[0090] like Fig. 6A and Figure 6B As shown, the common electrode CE includes a plurality of strip electrodes ST, and the pixel electrode PE is located between the substrate BS and the common electrode CE in a direction perpendicular to the substrate BS.

[0091] In at least one embodiment, Figures 4A-4B , Figure 5A and Fig. 6A As shown, the orthographic projection of each second display signal line PX2 on the substrate BS overlaps with the orthographic projection of a strip electrode ST on the substrate BS, which is helpful to prevent light leakage.

[0092] In at least one embodiment, Figures 4A-4B , Figure 5A and Fig. 6A As shown, the strip electrode ST overlapping the second display signal line PX2 has a larger size in the first direction than the strip electrode ST adjacent to and not overlapping the second display signal line PX2. By making the strip electrode ST overlapping the second display signal line PX2 have a larger width, crosstalk can be prevented.

[0093] In at least one embodiment, Figures 4A-4B , Figure 5A and Fig. 6AAs shown, the edges of the strip electrode ST overlapping with the second display signal line PX2 arranged in the first direction are all located in the first area of ​​the sub-pixel area, so that when the array substrate is applied to a display device, the strip electrode ST overlapping with the second display signal line PX2 exceeds the shielding area of ​​the black matrix layer, which is beneficial to improving the transmittance.

[0094] In at least one embodiment, Figures 4A-4B and Figure 5A As shown, the portion of the second display signal line PX2 overlapping the strip electrode ST includes an edge whose orthographic projection on the substrate is substantially parallel to the orthographic projection of the edge of the strip electrode ST on the substrate.

[0095] In at least one embodiment, Figure 6B As shown, the touch signal line TX includes a portion that does not overlap with the strip electrode ST; in the first direction, the spacing between the adjacent strip electrodes ST located on the same side of the portion of the touch signal line TX is Ss and the width is Ws, and the spacing between the portion of the touch signal line TX and the adjacent strip electrode ST is Sst. In at least one embodiment, the range of Ws / Ss is 45% to 80%. If it exceeds this range, the transmittance fluctuates greatly and is prone to defects. In at least one embodiment, the distance Sst from the strip electrode ST adjacent to the touch signal line TX to the touch signal line TX is in the range of 1.7 to 3.0 μm. If Sst is too large, the transmittance loss is large, and if Sst is too small, the touch signal line TX is easy to overlap with the strip electrode ST. In at least one embodiment, the width Wt of the touch signal line TX in the first direction is in the range of 2 to 3.5 μm, such as 3.1 μm or 3.5 μm. If the width of the touch signal line TX is too small, the touch signal line TX is prone to disconnection, and the greater the width of the touch signal line TX, the greater the transmittance loss. For example, the width Wt of the touch signal line TX is about 3.5 μm, the width Ws of the strip electrode ST is about 2.6 μm, the spacing Ss between the strip electrodes ST is about 4.5 μm, and the distance Sst from the strip electrode ST adjacent to the touch signal line TX to the touch signal line TX is about 1.85 μm.

[0096] In at least one embodiment, a plurality of strip electrodes ST in the same sub-pixel region may have a multi-domain structure (eg, Figure 3-4B and Figure 4D ) or a single domain structure (as shown Figure 5A shown).

[0097] like Figure 3-4B and Figure 4DAs shown, each strip electrode ST has two ends arranged along the second direction and includes a main body located between the two ends, the main body of the strip electrode ST is located in the first area of ​​the sub-pixel area, and the main body of the strip electrode ST includes a first linear portion STX1 and a second linear portion STX2 arranged in sequence along the second direction, and the extension directions of the first linear portion STX1 and the second linear portion STX2 intersect. For example, the first linear portions ST1 included in the main body of the strip electrode ST in the same sub-pixel area are substantially parallel to each other, and the second linear portions ST1 included in the main body of the strip electrode ST in the sub-pixel area are substantially parallel to each other, so that the strip electrode ST in the sub-pixel area has a dual-domain structure.

[0098] like Figure 5A As shown, the main body of the strip electrodes ST in the same sub-pixel region is substantially linear, and the strip electrodes ST in the same sub-pixel region P11 are parallel to each other, so that the strip electrodes in the sub-pixel region have a single-domain structure.

[0099] The embodiments of the present disclosure are described by taking a single-domain structure and a dual-domain structure as examples; in other embodiments, the strip electrodes ST in the same sub-pixel region may also have a domain structure with three domains or more than three domains.

[0100] In at least one embodiment, the domain structures of the strip electrodes in the adjacent sub-pixel regions in the second direction may be the same. For example, for the first row of sub-pixel regions and the second row of sub-pixel regions adjacent in the second direction (the row direction is along the first direction), the portion of the strip electrodes in the first row of sub-pixel regions close to the second row of sub-pixel regions and the portion of the strip electrodes in the second row of sub-pixel regions close to the first row of sub-pixel regions have different extension directions. In other embodiments, the domain structures of the strip electrodes in the adjacent sub-pixel regions in the second direction may also be different.

[0101] like Figure 3 and Figure 4A As shown, since the first strip electrode linear portion ST1 and the second strip electrode linear portion ST2 of the strip electrode ST intersect, the strip electrode ST has a first strip electrode bent portion STB1 at a position where the first strip electrode linear portion ST1 and the second strip electrode linear portion ST2 intersect.

[0102] In at least one embodiment, Figure 3 and Figure 4AAs shown, the plurality of strip electrodes ST in the array substrate include a first strip electrode ST1 adjacent to the touch signal line TX, and the touch signal line TX also has a bending portion (hereinafter referred to as the touch line bending portion TB) at a position adjacent to the first strip electrode bending portion STB1 included in the first strip electrode ST1, so as to avoid the touch signal line TX from overlapping with the strip electrode ST in the first region of the first sub-pixel region P11 as much as possible. For example, the touch signal line TX includes a first touch line linear portion TX1 and a second touch line linear portion TX2 arranged in sequence along the second direction and connected (for example, directly connected) to the touch line bending portion TB in the first region, the touch line bending portion TB is located between the first touch line linear portion TX1 and the second touch line linear portion TX2 in the second direction, the first touch line linear portion TX1 is substantially parallel to the first strip electrode linear portion STX1, and the second touch line linear portion TX2 is substantially parallel to the second strip electrode linear portion STX2.

[0103] In at least one embodiment, Figure 3 and Figure 4A As shown, the second display signal line PX2 also has a bending portion (hereinafter referred to as the display line bending portion) at a position adjacent to the first strip electrode bending portion STB1. The second display signal line PX2 includes a first display line linear portion PXA and a second display line linear portion PXC arranged in sequence along the second direction, and the display line bending portion PXB is located between the first display line linear portion PXA and the second display line linear portion PXC in the second direction. The first display line linear portion PXA is substantially parallel to the first strip electrode linear portion STX1, and the second display line linear portion PXC is substantially parallel to the second strip electrode linear portion STX2.

[0104] The inventors of the present application have discovered that Figure 3 In the embodiment shown, the touch line bend TB of the touch signal line TX has a sharp tip, which causes abnormal liquid crystal orientation at the touch line bend TB when the array substrate is used in a liquid crystal display device, thereby causing dark state light leakage. Based on this discovery, the embodiment of the present disclosure proposes an improvement scheme for the touch line bend TB, such as Figure 4AAs shown, for the touch signal line TX located in the first sub-pixel region P11 and the first strip electrode ST1 adjacent to the touch signal line TX, the first strip electrode ST1 has a first strip electrode bending portion STB1 in the first region, the touch signal line TX has a first touch line bending portion TB1 in the first region, the first touch line bending portion TB1 and the first strip electrode bending portion STB1 are bent in the same direction in the first region, the orthographic projection of the first touch line bending portion TB1 on the substrate BS and the orthographic projection of the first strip electrode bending portion STB1 on the substrate BS are sequentially arranged in the first direction, and the bending angle of the first touch line bending portion TB1 is greater than the bending angle of the first strip electrode bending portion STB1. By making the bending angle of the first touch line bending portion TB1 greater than the bending angle of the first strip electrode bending portion STB1, the first touch line bending portion TB1 is smoother than the first strip electrode bending portion STB1, thereby avoiding the disorder of the liquid crystal orientation at the first touch line bending portion TB1, and further avoiding the dark state light leakage there.

[0105] It should be noted that the bending angle of the first touch line bend TB1 is greater than the bending angle of the first strip electrode bend STB1, which means that the first strip electrode bend TB1 is located on the first side of the first touch line bend STB1 (see the right side in the figure), and the first touch line bend STB1 bends in the direction away from the first side (in the figure); the distance between the orthographic projection of the first touch line bend TB1 and the orthographic projection of the first strip electrode bend STB1 first decreases and then increases, that is, the distance between the orthographic projections of the mutually approaching edges of the two bends on the substrate BS first decreases and then increases, thereby having a minimum value at the top of the first strip electrode bend STB1.

[0106] In at least one embodiment, the first strip electrode bend STB1 has a tip extending toward the first touch wire bend TB1, and the first touch wire bend TB1 has an arc-shaped end extending away from the tip. The first touch wire bend TB1 has an arc-shaped end, which can effectively avoid dark state light leakage at the first touch wire bend TB1.

[0107] In at least one embodiment, the angle of the first touch line bend TB1 ranges from 100° to 160°. If the angle of the first touch line bend TB1 is too large, the touch signal line TX and the strip electrode ST may overlap, thereby affecting the display effect; if the angle of the first touch line bend TB1 is too small, the transmittance loss may be large.

[0108] In at least one embodiment, Figure 3 and Figure 4A As shown, the orthographic projection of the first strip electrode bending portion STB1 included in the first strip electrode ST1 on the substrate BS does not overlap with the orthographic projection of the first touch wire bending portion TB1 .

[0109] For example, Figure 3 and Figure 4A As shown, the multiple strip electrodes ST located in the first sub-pixel area P11 also include a second strip electrode ST2 adjacent to the touch signal line TX, the second strip electrode ST2 has a second strip electrode bending portion STB2 in the first area, the first strip electrode bending portion STB1, the second strip electrode bending portion STB2 and the first touch line bending portion TB1 located therebetween are bent in the same direction in the first area, the orthographic projection of the second strip electrode bending portion STB2 on the substrate BS and the orthographic projection of the first touch line bending portion TB1 are arranged sequentially in the first direction, and the bending angle of the second strip electrode bending portion STB2 is smaller than the bending angle of the first touch line bending portion TB1.

[0110] It should be noted that the bending angle of the second strip electrode bending portion STB2 is smaller than the bending angle of the first touch line bending portion TB1, which means that the second strip electrode bending portion TB2 is located on the second side of the first touch line bending portion STB1 opposite to the first side (see the left side in the figure), and the first touch line bending portion STB1 is bent toward the second side; the distance between the orthographic projection of the second strip electrode bending portion STB2 and the orthographic projection of the first touch line bending portion TB1 first increases and then decreases, that is, the distance between the orthographic projections of the mutually adjacent edges of the two bending portions on the substrate BS first increases and then decreases, thereby having a maximum value at the top of the first touch line bending portion TB1.

[0111] In at least one embodiment, the second strip electrode bend STB2 has a tip extending in the same direction, and the first touch wire bend TB1 has an arc-shaped end bent in the same direction. The first touch wire bend TB1 has an arc-shaped end, which can effectively alleviate dark state light leakage at the first touch wire bend TB1.

[0112] like Figure 3 and Figure 4A As shown, in order to avoid the first switching element T1 in the first sub-pixel area P11, the touch signal line TX has a bending portion (hereinafter referred to as the switch side bending portion) TB' at a position adjacent to the first switching element T1, and the switch side bending portion TB' is located between the touch line bending portion TB and the first switching element T1 included in the first sub-pixel area P11 in the second direction, and the switch side bending portion TB' is located between the first switching element T1 and the switching element T adjacent to the first switching element T1 in the first direction.

[0113] exist Figure 3 In the embodiment shown, the switch-side bent portion TB' included in the touch signal line TX has a sharp tip and is located in the first area of ​​the first sub-pixel area P11. The inventors of the present application have found in their research that Figure 3 In the embodiment shown, the liquid crystal orientation is disordered at the switch-side bent portion TB' included in the touch signal line TX, resulting in dark state light leakage. Based on this finding, the embodiment of the present disclosure proposes an improvement scheme for the switch-side bent portion TB'. Figure 4A As shown, the touch signal line TX has a second touch line bending portion TB2 in the first sub-pixel region P11, the second touch line bending portion TB2 is located between the first touch line bending portion TB1 and the first switch element T1 included in the first sub-pixel region P11 in the second direction, the second touch line bending portion TB2 is located between the first switch element T1 and the switch element T adjacent to the first switch in the first direction, and the bending angle of the second touch line bending portion TB2 is greater than the bending angle of the first touch line bending portion TB1. In other words, the angle between the two linear portions directly connected to the first touch line bending portion TB1 included in the touch signal line TX is smaller than the angle between the two linear portions directly connected to the second touch line bending portion TB2 included in the touch signal line TX, so that the touch signal line TX is smoother at the second touch line bending portion TB2 than at the first touch line bending portion TB1.

[0114] In at least one embodiment, Figure 4A As shown, the first strip electrode ST1 adjacent to the touch signal line TX in the first sub-pixel area P11 has a third strip electrode bending portion STB3, and the third strip electrode bending portion STB3 is located between the first switch element T1 and the second touch line bending portion TB2 (i.e., the switch side bending portion TB') of the touch signal line TX in the first direction, and the bending directions of the second touch line bending portion TB2 and the third strip electrode bending portion STB3 are opposite.

[0115] In at least one embodiment, the angle of the second touch line bending portion TB2 is 165° to 175°. If the angle of the second touch line bending portion TB2 is too small, the distance between the touch signal line TX and the switch element is too close, which may cause a defect.

[0116] In at least one embodiment, the angle between the extension directions of the two linear portions of the touch signal line TX directly connected to the second touch line bending portion TB2 is 165° to 175°.

[0117] For example, Figure 4A As shown, the second touch line bend TB2 is located in the second area of ​​the first sub-pixel area P11, so that when the array substrate is applied to a display device, the second touch line bend TB2 is blocked by the black matrix layer in the display device, which can further avoid dark state light leakage at the second touch line bend TB2 and reduce the width of the black matrix layer at the second touch line bend TB2, which is beneficial to improving the transmittance.

[0118] In some embodiments of the present disclosure, Figures 3 to 5B As shown, the switch element T may be a transistor, which includes a gate GE, a source SE and a drain DE, wherein the drain DE is electrically connected to the pixel electrode PE. For example, the drain DE is connected to the pixel electrode via hole VHP (eg, Figure 5A-5B When the switching element T is a transistor, it also includes an active layer AL (as shown) electrically connected to the source electrode SE and the drain electrode DE. Figure 5B shown).

[0119] In at least one embodiment, Figure 3 and Figures 4A-4C As shown, the switch element T may be a U-shaped structure, that is, the orthographic projection of the source electrode SE of the switch element T on the substrate BS includes a U-shaped structure, and the orthographic projection of the drain electrode DE on the substrate BS extends into the U-shaped structure.

[0120] In other embodiments, to meet the requirements of high resolution, such as Figure 5A-5B As shown, the switch element T may also be a linear structure. Figure 5B As shown, when the switch element T is a linear structure, the source SE and the drain DE are arranged in sequence along the first direction, the active layer AL and the gate GE have a roughly isosceles trapezoidal structure, the two waists of the isosceles trapezoid are arranged along the second direction, and the two bases of the isosceles trapezoid are arranged along the first direction.

[0121] The switch element T may be a top-gate transistor (the gate GE is located on the side of the active layer away from the substrate BS) or a bottom-gate transistor (the gate GE is located on the side of the active layer facing the substrate BS) or a back-channel protection transistor (the transistor includes an etching barrier layer to protect the active layer when the source and drain electrode layers are etched). The switch element T may be a thin film transistor such as an amorphous silicon thin film transistor, a polycrystalline silicon thin film transistor or an oxide thin film transistor. In other embodiments, the switch element T may also be of other types.

[0122] like Figure 3-4C and Figure 5A-5B As shown, the switch element T is located at the intersection of the first display signal line PX1 and the second display signal line PX2, that is, the switch element T is located in the second area of ​​the sub-pixel area to avoid affecting the display.

[0123] In some embodiments, Figure 3-4C and Figure 5A-5B As shown in FIG. 1 , a portion of the first display signal line PX1 connected to the switch element T serves as the gate GE. Figure 3-4C and Figure 5A-5BAs shown, the first display signal line PX1 has a larger width at the position where it intersects with the second display signal line PX2, and the portion of the first display signal line PX1 with the larger width serves as the gate GE. In this case, the first display signal line PX1 is a gate line, and correspondingly, the second display signal line PX2 is a data line.

[0124] In some embodiments, Figure 3-4C and Figure 5A-5B As shown, a portion of the second display signal line PX2 connected to the switch element T serves as the source electrode SE. In this case, the second display signal line PX2 is a data line, and correspondingly, the first display signal line PX1 is a gate line.

[0125] In at least one embodiment, the source electrode SE, the drain electrode DE, the second display signal line PX2 and the touch signal line TX are located in the same layer. That is, the source electrode SE, the drain electrode DE, the second display signal line PX2 and the touch signal line TX are formed by patterning the same film, which can simplify the manufacturing process.

[0126] Fig. 7A A schematic diagram of the connection relationship between the touch electrodes TE and the touch signal lines TX in the array substrate provided by the embodiment of the present disclosure; Figure 7B A schematic diagram of the positional relationship between the touch line via holes and the sub-pixel areas in the array substrate provided in an embodiment of the present disclosure.

[0127] In at least one embodiment, Fig. 7A As shown, each touch signal line TX passes through multiple ( Fig. 7A (two are used as examples for illustration) The touch line via holes VHT are electrically connected to the corresponding touch electrodes TE. The electrical connection between each touch signal line TX and the corresponding touch electrode TE is realized through multiple via holes, which is conducive to ensuring a good connection between the touch electrode TE and the touch signal line TX. Figure 7B As shown, each touch signal line TX may also be electrically connected to the corresponding touch electrode TE through a touch line via hole VHT.

[0128] In at least one embodiment, Fig. 7A As shown in FIG. 1 , each touch electrode TE is electrically connected to one touch signal line TX. In other embodiments, each touch electrode TE is electrically connected to a plurality of touch signal lines TX. Figure 7BAs shown, the touch signal line TX-1 is electrically connected to the touch electrode TEA through the touch line via hole VHT1, and the touch signal line TX-2 is electrically connected to the touch electrode TEA through the touch line via hole VHT2, so that the touch electrode TEA is supplied with signals through the two touch signal lines TX-1 and TX-2. As described above, by using multiple touch signal lines TX to supply signals to the same touch electrode TE, the supply of touch signals can be enhanced, the RC delay can be reduced, and touch horizontal stripes can be avoided.

[0129] In at least one embodiment, Figure 7B As shown, the region where each touch electrode TE is located has multiple rows and columns of sub-pixel regions SP; the touch line vias VHT in the region where the same touch electrode TE is located are located around sub-pixel regions SP in different rows and around sub-pixel regions SP in different columns, that is, the touch line vias in the region where the same touch electrode TE is located are staggered in the first direction and staggered in the second direction. In this way, the visibility of the touch line vias VHT can be reduced, thereby improving the uniformity of the display screen.

[0130] Fig. 8A and Figure 8B Schematic diagram of the positional relationship between the touch signal line and the pixel electrode in the array substrate provided by the embodiment of the present disclosure. In at least one embodiment, Fig. 8A and Figure 8B As shown, the touch signal line TX includes a via connection portion HC electrically connected to the touch electrode TE (e.g., the common electrode CE) at the touch line via hole VHT, and the size of the via connection portion HC in the first direction is larger than the size of the remaining portion of the touch signal line TX in the first direction. By providing a relatively large via connection portion HC, it is beneficial to ensure that the touch signal line TX has a good electrical connection with the touch electrode TE.

[0131] In order to avoid affecting the display effect, in at least one embodiment, the orthographic projection of the touch line via VHT on the substrate BS is at least partially located between the orthographic projections of adjacent pixel electrodes PE on the substrate BS, and accordingly, the orthographic projection of the via connection portion HC on the substrate BS is at least partially located between the orthographic projections of adjacent pixel electrodes PE on the substrate BS.

[0132] The inventors of the present application have discovered in their research that the size of the touch signal line TX at the touch line via VHT in the first direction is relatively large (i.e., the size of the via connection portion HC is relatively large), which easily leads to differences in capacitance between pixels. Taking the adjacent first touch signal line and the second touch signal line and two adjacent sub-pixel areas as an example, assuming that the first touch signal line overlaps with the pixel electrode PE in one of the two sub-pixel areas and has a via connection portion HC in the sub-pixel area, and the second touch signal line overlaps with the pixel electrode PE in the other sub-pixel area of ​​the two sub-pixel areas and does not have a via connection portion in the other sub-pixel area, the via connection portion causes the capacitance between the first touch signal line and the pixel electrode in the one sub-pixel area to be greater than the capacitance between the second touch signal line and the pixel electrode in the other sub-pixel area, thereby causing differences in the capacitances corresponding to the two sub-pixel areas. In view of this, in at least one embodiment, if Fig. 8A and Figure 8B As shown, the orthographic projection of the via hole connection portion HC on the substrate BS is outside the orthographic projection of the pixel electrode PE closest to the via hole connection portion HC on the substrate BS, that is, the orthographic projection of the via hole connection portion HC on the substrate BS does not overlap with the orthographic projection of the pixel electrode PE closest to the via hole connection portion HC on the substrate BS.

[0133] The embodiment of the present disclosure does not limit the shape of the via connection portion. Fig. 8A and Figure 8B As shown, the orthographic projection of the via connection portion HC on the substrate BS is an octagon, and the orthographic projection of the touch signal line TX on the substrate BS passes through the orthographic projection of the via connection portion HC. In other embodiments, the orthographic projection of the via connection portion HC on the substrate BS is a quadrilateral and is located on one side of the orthographic projection of the touch signal line TX. In other embodiments, the orthographic projection of the via connection portion HC may also be other polygons or non-polygons.

[0134] In at least one embodiment, Fig. 8A and Figure 8B As shown, the pixel electrode PE closest to the via hole connection portion HC includes a first edge PE1 and a second edge PE2 arranged along the first direction and includes a third edge PE3 located between the first edge PE1 and the second edge PE2, and the third edge PE3 has a first recess PEC1, and the orthographic projection of the first recess PEC1 on the substrate BS accommodates at least a part of the orthographic projection of the via hole connection portion HC on the substrate BS. By making the pixel electrode PE include the first recess to accommodate the via hole connection portion HC, it is helpful to avoid the orthographic projection of the pixel electrode PE on the substrate BS from overlapping with the orthographic projection of the via hole connection portion HC on the substrate BS.

[0135] In at least one embodiment, Fig. 8A and Figure 8B As shown, the third edge PEE3 of the pixel electrode PE is substantially parallel to the edge of the orthographic projection of the via-hole connecting portion HC at the first recess PEC1.

[0136] In at least one embodiment, Fig. 8A and Figure 8B As shown, the orthographic projection of the pixel electrode PE on the substrate BS is a continuous structure without an opening between the first edge PE1 and the second edge PE2 of the pixel electrode PE.

[0137] In at least one embodiment, Fig. 8A As shown, the array substrate includes a plurality of pixel electrodes PE including adjacent first-row pixel electrodes PEQ1 and second-row pixel electrodes PEQ2, the first-row pixel electrodes PEQ1 and the second-row pixel electrodes PEQ2 both extend along the first direction and are sequentially arranged along the second direction; the first-row pixel electrodes PEQ1 and the second-row pixel electrodes PEQ2 both intersect with at least two touch signal lines TX, at least one of the at least two touch signal lines TX has a via connection portion HC between the first-row pixel electrode PEQ1 and the second-row pixel electrode PEQ2, and at least another of the at least two touch signal lines TX does not have a via connection portion HC between the first-row pixel electrode PEQ1 and the second-row pixel electrode PEQ2.

[0138] For example, the first row of pixel electrodes PEQ1 is closer to the via hole connection portion HC than the second row of pixel electrodes PEQ2. The pixel electrode PE closest to the via hole connection portion HC in the first row of pixel electrodes PEQ1 (eg Fig. 8A The first pixel electrode PEA shown has a first recess PEC1, and the remaining pixel electrodes PE in the first row of pixel electrodes PEQ1 have a second recess PEC2 facing the second row of pixel electrodes PEQ2. The second recess PEC2 is helpful to further avoid the difference in capacitance between pixels caused by the via hole connection part HC.

[0139] For example, the second recess PEC2 has the same shape as the first recess PEC1, that is, the second recess PEC2 has the same shape profile and size as the first recess PEC1, so that the areas of the orthographic projections of the first row pixel electrode PEQ1 and the second row pixel electrode PEQ2 on the substrate BS are substantially the same, so as to further avoid differences in inter-pixel capacitance caused by the via connection portion HC. In other embodiments, the second recess PEC2 may have different shapes from the first recess PEC1.

[0140] In at least one embodiment, each pixel electrode PE in the first row of pixel electrodes PEQ1 and the second row of pixel electrodes PEQ2 is a continuous structure without an opening between the first edge PE1 and the second edge PE2 of the pixel electrode PE.

[0141] Fig. 9A A schematic diagram of a cross-sectional structure of an array substrate provided in an embodiment of the present disclosure; Fig. 9B For Fig. 9A A schematic diagram of the manufacturing steps of the array substrate shown; Fig.10 For Fig. 9A The schematic diagram of the array substrate when over-engraving occurs; Fig.11A A cross-sectional view of an array substrate provided in an embodiment of the present disclosure Figure 2 ; Fig. 11B for Fig.11A Schematic diagram of the manufacturing steps of the array substrate shown.

[0142] In at least one embodiment, Fig. 9A and Fig.11A As shown, the array substrate includes a first insulating layer ISL1 and a touch electrode (for example, a common electrode CE) located on a substrate BS. The first insulating layer ISL1 is located between the touch signal line TX and the touch electrode in a direction perpendicular to the substrate BS. The touch signal line TX is electrically connected to the touch electrode through a touch line via VHT penetrating the first insulating layer ISL1. The orthographic projection of the touch line via VHT on the substrate BS is at least partially located between the orthographic projections of adjacent pixel electrodes PE on the substrate BS in the second direction.

[0143] In at least one embodiment, the first insulating layer ISL1 may include an organic insulating layer RS, so that the first insulating layer ISL1 may have a greater thickness to reduce the capacitance between the touch signal line TX and the touch electrode (eg, the common electrode CE).

[0144] The first insulating layer ISL1 may be a single-layer film structure or a multi-layer film structure. In at least one embodiment, when the first insulating layer ISL1 is a multi-layer film structure, the first insulating layer ISL1 may include a first sub-insulating layer, an organic insulating layer, and a second sub-insulating layer sequentially located on the substrate BS, and the first sub-insulating layer is located between the organic insulating layer and the substrate BS in a direction perpendicular to the substrate BS. In at least one embodiment, the first sub-insulating layer and the second sub-insulating layer are both inorganic insulating layers. For example, the inorganic insulating layer may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer, and the first sub-insulating layer and the second sub-insulating layer may be layers of the same material or layers of different materials. For example, as Fig. 9A and Fig.11A As shown, in the case where the first insulating layer ISL1 is a multi-layer film structure, the first insulating layer ISL1 may include a buffer layer BF (an example of a first sub-insulating layer), an organic insulating layer RS ​​and a passivation layer PVX (an example of a second sub-insulating layer) sequentially located on a substrate BS, the buffer layer BF is located between the organic insulating layer and the substrate BS in a direction perpendicular to the substrate BS, and both the buffer layer BF and the passivation layer PVX are inorganic insulating layers.

[0145] In the case where the first insulating layer ISL1 is a multi-layer film structure, the touch line via hole VHT penetrating the first insulating layer ISL1 includes a plurality of via holes connected to each other. Fig. 9A and Fig.11A As shown, in the case where the first insulating layer ISL1 includes a first sub-insulating layer, an organic insulating layer, and a second sub-insulating layer sequentially located on the substrate BS, the touch line via VHT includes a first sub-insulating layer via V11 located in the first sub-insulating layer, an organic insulating layer via VRS located in the organic insulating layer, and a second sub-insulating layer via V12 located in the second sub-insulating layer, and the first sub-insulating layer via V11, the organic insulating layer via VRS, and the second sub-insulating layer via V12 are interconnected.

[0146] In at least one embodiment, the slope angles of the first sub-insulating layer via hole V11, the organic insulating layer via hole VRS, and the second sub-insulating layer via hole V12 may range from 30° to 80°. The smaller the slope angles of these via holes, the less likely the touch electrodes are to fall off the side walls of the via holes.

[0147] In at least one embodiment, the first sub-insulating layer via V11 can be made using the organic insulating layer RS ​​as a mask, so that the first sub-insulating layer via V1 and the organic insulating layer via VRS are made using the same mask plate. By making part of the vias included in the touch line via VTH using the same mask plate, the number of mask plates can be saved, thereby reducing costs. On the other hand, the method of making the first sub-insulating layer via V11 using the organic insulating layer RS ​​as a mask is conducive to avoiding over-engraving of the first sub-insulating layer via V11.

[0148] Since the first sub-insulating layer via hole V11 can be manufactured using the organic insulating layer RS ​​as a mask, in at least one embodiment, adjacent edges of the first sub-insulating layer via hole V11 and the organic insulating layer via hole VRS are substantially aligned.

[0149] In at least one embodiment, since the organic insulating layer via VRS and the second sub-insulating layer via V12 are made using different mask plates (i.e., the organic insulating layer RS ​​and the second sub-insulating layer are made using different mask plates). In at least one embodiment, since the organic insulating layer RS ​​and the second sub-insulating layer are made using different mask plates, the organic insulating layer via VRS and the second sub-insulating layer via V12 are not equal in size in a direction parallel to the substrate BS (i.e., in a direction parallel to the main surface of the substrate BS), so that the touch line via VHT has a step structure. In this case, Fig. 9A and Fig.11A As shown, the orthographic projection of the organic insulating layer RS ​​on the substrate BS includes a portion extending into the orthographic projection of the second sub-insulating layer via hole V12 on the substrate BS.

[0150] In at least one embodiment, Fig. 9A and Fig.11A As shown, the array substrate further includes a connector GC and a second insulating layer ISL2 located on the substrate BS, the second insulating layer ISL2 is located on the side of the touch signal line TX facing the substrate BS, and the first insulating layer ISL1 is located on the side of the touch signal line TX away from the substrate BS; the connector GC is located on the side of the second insulating layer ISL2 facing the substrate BS, and the connector GC is electrically connected to the common electrode CE through a connector via VHC penetrating the second insulating layer ISL2 and the first insulating layer ISL1 and a common electrode connecting portion CECP located in the connector via VHC. The connector GC and the common electrode connecting portion CECP are used to electrically connect the touch line Tx to other components, that is, the connector GC and the common electrode connecting portion CECP play a switching role. The connector GC and the connector via VHC are located in the frame area, that is, outside the multiple sub-pixel areas included in the array substrate.

[0151] For example, the connector GC and the first display signal line PX1 are located in the same layer, that is, the connector GC and the first display signal line PX1 are formed by patterning the same film to simplify the manufacturing process. For example, the common electrode connection portion CECP and the common electrode CE are located in the same layer, that is, the two are formed by patterning the same film to simplify the manufacturing process.

[0152] Since the second insulating layer ISL2 is located between the touch signal line TX and the substrate BS in a direction perpendicular to the substrate BS, the bottom end of the connector via VHC is closer to the substrate BS than the bottom end of the touch line via VHT. Therefore, in at least one embodiment, when the first insulating layer ISL1 is a multi-layer film structure, a portion of the insulating layer included in the first insulating layer ISL1 can be made with the second insulating layer ISL2 using the same mask plate to reduce the number of mask plates, thereby reducing costs.

[0153] For example, in the case where the first insulating layer ISL1 includes a first sub-insulating layer, an organic insulating layer, and a second sub-insulating layer sequentially located on the substrate BS, as shown in FIG. Fig. 9A and Fig.11A As shown, the connector via VHC includes a first sub-via V21 located in the second insulating layer ISL2, a second sub-via V22 located in the first sub-insulating layer, a third sub-via V23 located in the organic insulating layer RS, and a fourth sub-via V24 located in the second sub-insulating layer. The first sub-via V21, the second sub-via V22, the third sub-via V23 and the fourth sub-via V24 are interconnected.

[0154] In at least one embodiment, the second sub-via hole V22 may be manufactured using the organic insulating layer RS ​​as a mask, so that adjacent edges of the second sub-via hole V22 and the third sub-via hole V23 are substantially aligned.

[0155] Since the organic insulating layer RS ​​and the second sub-insulating layer are made using different masks, in at least one embodiment, the third sub-via hole V23 and the fourth sub-via hole V24 have different sizes in a direction parallel to the substrate BS (i.e., a direction parallel to the main surface of the substrate BS), so that the connector via hole VHC has a step structure. Fig. 9A and Fig.11A As shown, the orthographic projection of the organic insulating layer RS ​​on the substrate BS includes a portion extending into the orthographic projection of the fourth sub-via hole V24 on the substrate BS.

[0156] In at least one embodiment, the second insulating layer ISL2 and the second sub-insulating layer can be patterned using the same mask plate, that is, the first sub-via V21 and the fourth sub-via V24 can be made using the same mask plate to reduce the number of mask plates, thereby reducing the production cost.

[0157] For example, the second sub-insulating layer and the second insulating layer ISL2 are both inorganic insulating layers. For example, the inorganic insulating layer may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer, and the second sub-insulating layer and the second insulating layer ISL2 may be layers of the same material or layers of different materials.

[0158] like Fig. 9B As shown, Fig. 9A The manufacturing process of the array substrate shown includes the following steps S91 to S99.

[0159] Step S91: Using a gate conductive layer mask, a gate conductive layer is formed on the substrate BS, so that the gate electrode of the gate conductive layer ( Fig. 9A ), a first display signal line PX1 (eg, a gate line) and a connecting member GC.

[0160] Step S92: Using an active layer mask, an active layer ( Fig. 9A not shown).

[0161] Step S93: forming a gate insulating layer film on the substrate BS, and then patterning the gate insulating layer film using a gate insulating layer mask to form a gate insulating layer GI having a first sub-via hole V21. For example, the thickness of the gate insulating layer film is Or other values.

[0162] Step S94: using the source-drain conductive layer mask plate, forming a source-drain conductive layer on the gate insulating layer GI, so that the source-drain conductive layer includes the source electrode ( Fig. 9A not shown) and the drain ( Fig. 9A The display signal line PX2 is not shown in the figure and includes a second display signal line PX2 (eg, a data line) and a touch signal line TX.

[0163] Step S95 : forming a buffer layer thin film for forming a buffer layer BF on the substrate BS having the source-drain conductive layer formed thereon.

[0164] Step S96: An organic material layer for forming an organic insulating layer RS ​​is formed on the buffer layer film, and then the organic material layer is patterned using an organic insulating layer mask to form an organic insulating layer RS ​​having an organic insulating layer via VRS and a third sub-via V23. Thereafter, the buffer layer film is etched using the organic insulating layer RS ​​as a mask to form a buffer layer BF having a first sub-insulating layer via V11 and a second sub-via V22, so that the first sub-insulating layer via V11 is connected to the organic insulating layer via VRS, and the third sub-via V23 and the second sub-via V22 are connected to the first sub-via V21.

[0165] Step S97: forming a pixel electrode on the organic insulating layer RS ​​using a pixel electrode mask. Fig. 9A ), so that the pixel electrode passes through the pixel electrode via hole VHP (see Figure 5A ) is electrically connected to the drain of the switching element.

[0166] Step S98: forming a passivation layer film for forming a passivation layer PVX covering the pixel electrode on the substrate BS, and patterning the passivation layer film using a passivation layer mask to form a passivation layer PVX having a second sub-insulating layer via hole V12 and a fourth sub-via hole V24, connecting the second sub-insulating layer via hole V12 with the organic insulating layer via hole VRS to obtain a touch line via hole VHT, and connecting the fourth sub-via hole V24 with the third sub-via hole V23 to obtain a connector via hole VHC. For example, the thickness of the passivation layer film is Or other values.

[0167] Step S99: forming a common electrode CE on the passivation layer PVX by using a common electrode mask, so that the common electrode CE directly contacts the touch signal line TX at the touch line via hole VHT and directly contacts the connector GC at the connector via hole VHC.

[0168] It should be noted that, in the above steps S91 to S99, the production order of some steps can be changed. For example, the production order of step S91 and step S92 can be interchanged.

[0169] The inventors of the present application have noticed in their research that a total of 8 mask plates are required for the manufacturing process including the above-mentioned steps S91 to S99; the reason why the gate insulating layer GI and the passivation layer PVX are manufactured using different mask plates is to prevent the buffer layer BF under the organic insulating layer RS ​​from being over-etched when the passivation layer film is etched (i.e., to avoid over-etching at the first sub-insulating layer via V11); if the gate insulating layer GI and the passivation layer PVX are manufactured using the same mask plate (i.e., the passivation layer mask plate), then only one layer of the passivation layer film needs to be etched at the touch line via VHT, while the two films, the passivation layer film and the gate insulating layer film used to form the gate insulating layer GI, need to be etched at the connector via VHC, which can easily cause the buffer layer BF to be over-etched at the touch line via VHT. Fig.10 FIG. 1 is a schematic diagram of the structure when the buffer layer in the array substrate is overetched. Fig.10 As shown, the buffer layer BF is over-etched at the touch line via VHT. At the over-etching position (as shown by the dotted line), there is no buffer layer BF to support the common electrode CE in the touch line via VHT, so the common electrode CE is easily broken at the touch line via VTH.

[0170] In order to reduce the number of masks while avoiding over-etching of the first sub-insulating layer (eg, buffer layer BF), the present disclosure proposes a method as follows: Fig.11A The array substrate shown in FIG. Fig.11A As shown, the array substrate includes a pixel electrode layer PEL located on a substrate BS, the pixel electrode layer PEL includes a pixel electrode PE and includes an etching stopper ESL electrically insulated from the pixel electrode PE, as shown in FIG. Fig.11A and Figure 5A As shown, the etching stopper ESL is located in the touch line via hole VHT, and the common electrode CE is electrically connected to the touch signal line TX through the etching stopper ESL. For example, the etching stopper ESL directly contacts the touch signal line TX and the common electrode CE located on both sides thereof. By making the pixel electrode layer PEL include a pixel electrode and a conductive etching stopper ESL, and making the etching stopper ESL located in the touch line via hole VHT to electrically connect the common electrode CE and the touch signal line TX, the first sub-insulating layer (for example, the buffer layer BF) can be prevented from being over-etched at the touch line via hole VHT, and the number of mask plates produced can be reduced.

[0171] For example, the etch stopper ESL at least covers the sidewall of the first sub-insulating layer via hole V11 to further prevent the first sub-insulating layer from being over-etched at the touch line via hole VHT.

[0172] like Fig. 11B As shown, Fig.11A The manufacturing process of the array substrate shown includes the following steps S11 to S19.

[0173] Step S11: Using a gate conductive layer mask, a gate conductive layer is formed on the substrate BS, so that the gate electrode of the gate conductive layer ( Fig.11A ), a first display signal line PX1 (eg, a gate line) and a connecting member GC.

[0174] Step S12: Using an active layer mask, an active layer ( Fig.11A not shown).

[0175] Step S13: forming a gate insulating layer film on the substrate BS for forming the gate insulating layer GI. For example, the thickness of the gate insulating layer film is Or other values.

[0176] Step S14: Using the source-drain conductive layer mask plate, a source-drain conductive layer is formed on the gate insulating layer film, so that the source-drain conductive layer includes the source electrode ( Fig.11A not shown) and the drain ( Fig.11A The display signal line PX2 is not shown in the figure and includes a second display signal line PX2 (eg, a data line) and a touch signal line TX.

[0177] Step S15: forming a buffer layer thin film for forming a buffer layer BF on the substrate BS having the source-drain conductive layer formed thereon.

[0178] Step S16: An organic material layer for forming an organic insulating layer RS ​​is formed on the buffer layer film, and then the organic material layer is patterned using an organic insulating layer mask to form an organic insulating layer RS ​​having an organic insulating layer via VRS and a third sub-via V23. Thereafter, the buffer layer film is etched using the organic insulating layer RS ​​as a mask to form a buffer layer BF having a first sub-insulating layer via V11 and a second sub-via V22, so that the first sub-insulating layer via V11 is connected to the organic insulating layer via VRS, and the third sub-via V23 and the second sub-via V22 are connected.

[0179] Step S17: forming a pixel electrode layer ( Fig.11A (not shown in the figure), the pixel electrode layer includes a pixel electrode and an etch blocking portion ESL, the pixel electrode is electrically connected to the drain of the switching element through a via hole penetrating the organic insulating layer RS ​​and the buffer layer BF, and the etch blocking portion ESL is located in the organic insulating layer via hole VRS and is electrically connected to (e.g., directly contacts) the touch signal line TX.

[0180] Step S18: A passivation layer film for forming a passivation layer PVX covering the pixel electrode is formed on the substrate BS, and the passivation layer film and the gate insulating layer film are patterned using a passivation layer mask to form a passivation layer PVX having a second sub-insulating layer via hole V12 and a fourth sub-via hole V24 and a gate insulating layer GI having a first sub-via hole V21, so that the second sub-insulating layer via hole V12, the organic insulating layer via hole VRS and the first sub-insulating layer via hole V11 are connected to obtain a touch line via hole VHT, and the fourth sub-via hole V24, the third sub-via hole V23, the second sub-via hole V22 and the first sub-via hole V21 are connected to obtain a connector via hole VHC. For example, the thickness of the passivation layer film is Or other values.

[0181] Step S19: Use a common electrode mask to form a common electrode CE on the passivation layer PVX, so that the common electrode CE is electrically connected (e.g., directly in contact with) the etching stopper ESL at the touch line via hole VHT to electrically connect to the touch signal line TX, and the common electrode CE is electrically connected (e.g., directly in contact with) the connector GC at the connector via hole VHC.

[0182] It should be noted that, in the above steps S11 to S19, the production order of some steps can be changed. For example, the production order of step S11 and step S12 can be interchanged.

[0183] It can be seen from the above steps S11 to S19 that Fig.11A The array substrate shown in FIG. 1 can be manufactured by using 7 mask plates, as shown in FIG. Fig. 9A Compared with the array substrate shown in the figure, one mask plate is reduced.

[0184] An embodiment of the present disclosure further provides a touch display device, which includes the array substrate provided by any one of the above embodiments.

[0185] Fig. 12A A schematic top view of a touch display device provided in an embodiment of the present disclosure; Fig. 12B The touch display device provided by the embodiment of the present disclosure is Fig. 12A A simplified cross-sectional view of the dashed line A. Fig. 12A and Fig. 12B As shown, the touch display device also includes a black matrix layer BM, the portion of the sub-pixel area not blocked by the black matrix layer is an opening area, the portion of the sub-pixel area blocked by the black matrix layer is a non-opening area, and the positive projection of the touch signal line TX in the first sub-pixel area passes through the opening area.

[0186] In at least one embodiment, the touch display device is an embedded touch display device, that is, the touch electrodes and the touch signal lines are located in the display panel of the touch display device. Fig. 12BAs shown, the touch display device includes a display panel, and the display panel includes an array substrate AS and an opposing substrate OS arranged opposite to each other and a liquid crystal layer ( Fig. 12B In at least one embodiment, the counter substrate OS includes a black matrix layer BM. In other embodiments, the array substrate AS may include a black matrix layer BM.

[0187] The via connection portion HC, the touch signal line via hole VHT, the connector via hole VHC and the second touch line bending portion TB2 mentioned in the above embodiment are all located in the area blocked by the black matrix layer.

[0188] For example, the touch display device provided in the embodiments of the present disclosure may be: a liquid crystal panel, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with touch and display functions.

[0189] The disclosed embodiment also provides a method for manufacturing an array substrate, the method comprising: forming a second insulating layer film for forming a second insulating layer on a substrate; forming an organic insulating layer having an organic insulating layer via on the second insulating layer film; forming a second sub-insulating layer film for forming a second sub-insulating layer on the organic insulating layer, so that the second sub-insulating layer film includes a portion located in the organic insulating layer via and covering the second insulating layer film; and patterning the second insulating layer film and the second sub-insulating layer film using the same mask plate to form the second insulating layer and the second sub-insulating layer. By using the same mask plate to form the second insulating layer and the second sub-insulating layer, the number of mask plates can be reduced to reduce costs.

[0190] In at least one embodiment, the method for manufacturing the array substrate further includes: before forming the organic insulating layer, forming a first sub-insulating layer thin film on the second insulating layer thin film for forming the first sub-insulating layer; after forming the organic insulating layer and before forming the second sub-insulating layer thin film, etching the first sub-insulating layer thin film using the organic insulating layer as a mask to form the first sub-insulating layer. Etching the first sub-insulating layer thin film using the organic insulating layer as a mask is conducive to reducing the risk of over-etching the first sub-insulating layer when forming the second insulating layer and the second sub-insulating layer using the same mask plate.

[0191] Fig.13 The flowchart of a method for manufacturing an array substrate provided by an embodiment of the present disclosure is as follows. Fig.13 As shown, when the first sub-insulating layer thin film is etched using the organic insulating layer as a mask and the second insulating layer and the second sub-insulating layer are formed using the same mask plate, the method for manufacturing the array substrate includes the following steps S1 to S5.

[0192] Step S1: forming a second insulating layer thin film for forming a second insulating layer on a substrate.

[0193] Step S2: forming a first sub-insulating layer thin film for forming a first sub-insulating layer on the second insulating layer thin film.

[0194] Step S3: forming an organic insulating layer having an organic insulating layer via hole and a third sub-via hole on the first sub-insulating layer thin film.

[0195] Step S4: using the organic insulating layer as a mask to etch the first sub-insulating layer film to form a first sub-insulating layer having a first sub-insulating layer via hole and a second sub-via hole, so that the first sub-insulating layer via hole is connected to the organic insulating layer via hole, and the second sub-via hole is connected to the third sub-via hole.

[0196] Step S5: After forming the first sub-insulating layer, forming a second sub-insulating layer film for forming a second sub-insulating layer on the organic insulating layer, so that the second sub-insulating layer film includes a portion located in the organic insulating layer via and covering the second insulating layer film; and patterning the second insulating layer film and the second sub-insulating layer film using the same mask plate to form a second insulating layer having a first sub-via and a second sub-insulating layer having a second sub-insulating layer via and a fourth sub-via, so that the first sub-via is connected to the second sub-via, the second sub-insulating layer via is connected to the organic insulating layer via, and the fourth sub-via is connected to the third sub-via.

[0197] In at least one embodiment, Fig.11A As shown, the array substrate further includes an etching stopper ESL, so that the touch signal line TX is electrically connected to the common electrode CE through the etching stopper ESL, thereby reducing the number of mask plates under the premise of avoiding over-etching of the first sub-insulating layer. In this case, the method for manufacturing the array substrate further includes: after forming the organic insulating layer and before forming the second sub-insulating layer film, forming a pixel electrode layer on the substrate having the organic insulating layer, so that the pixel electrode layer includes a pixel electrode and an etching stopper electrically insulated from the pixel electrode.

[0198] For example, the second insulating layer, the first sub-insulating layer and the second sub-insulating layer may be respectively as follows: Fig. 9A and Fig.11A The gate insulating layer GI, the buffer layer BF and the passivation layer PVX in the illustrated embodiment. In other embodiments, the second insulating layer, the first sub-insulating layer and the second sub-insulating layer may also be other layers respectively.

[0199] For example, the second insulating layer, the first sub-insulating layer and the second sub-insulating layer are respectively as follows Fig. 9AIn the case of the gate insulating layer GI, the buffer layer BF and the passivation layer PVX in the embodiment shown, the manufacturing method provided by the embodiment of the present disclosure includes the above steps S91 to S99; the second insulating layer, the first sub-insulating layer and the second sub-insulating layer are respectively as follows Fig.11A In the case of the gate insulating layer GI, the buffer layer BF and the passivation layer PVX in the illustrated embodiment, the manufacturing method provided by the embodiment of the present disclosure includes the above steps S11 to S19. The repeated parts will not be repeated here.

[0200] In the array substrate and the manufacturing method thereof and the touch display device provided by the embodiments of the present disclosure, the same components can be arranged in the same manner.

[0201] In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other.

[0202] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. An array substrate, comprising: substrate; a plurality of first display signal lines and a plurality of second display signal lines located on the substrate, wherein the plurality of first display signal lines extend along a first direction and are sequentially arranged along a second direction different from the first direction, the plurality of second display signal lines extend along the second direction and are sequentially arranged along the first direction, and the plurality of second display signal lines cross the first display signal lines to define a plurality of sub-pixel regions; A touch signal line located on the substrate, wherein the touch signal line extends along the second direction; a first insulating layer and a common electrode located on the substrate, wherein the first insulating layer is located between the touch signal line and the common electrode in a direction perpendicular to the substrate, the touch signal line is electrically connected to the common electrode through a touch line via hole penetrating the first insulating layer, and an orthographic projection of the touch line via hole on the substrate overlaps with an orthographic projection of the first display signal line on the substrate; and A plurality of pixel electrodes are located on the substrate, wherein the plurality of pixel electrodes are respectively located in the plurality of sub-pixel regions, The plurality of sub-pixel regions include a first sub-pixel region, the plurality of pixel electrodes include a first pixel electrode, the first pixel electrode is located in the first sub-pixel region, the first pixel electrode includes a first edge and a second edge arranged along the first direction and extending along the second direction, and the orthographic projection of the touch signal line on the substrate is located between the orthographic projections of the first edge and the second edge on the substrate; The orthographic projection of the touch line via hole on the substrate is at least partially located between the orthographic projections of adjacent pixel electrodes on the substrate, the touch signal line includes a via connection portion electrically connected to the common electrode at the touch line via hole, and the size of the via connection portion in the first direction is greater than the size of a portion of the touch signal line adjacent to the via connection portion in the first direction; The first pixel electrode is the pixel electrode closest to the via connection portion among the multiple pixel electrodes, and the first pixel electrode also includes a third edge located between the first edge and the second edge, the third edge extends along the first direction, and the third edge has a first recess, and the orthographic projection of the first recess on the substrate accommodates at least part of the orthographic projection of the via connection portion on the substrate.

2. The array substrate according to claim 1, wherein: The first sub-pixel region includes a first region and a second region surrounding the first region; In the first direction, the distances between the orthographic projection of the touch signal line and two second display signal lines adjacent to the touch signal line in the first region are not equal.

3. The array substrate according to claim 1, wherein: The array substrate includes multiple touch signal lines, and a first pixel electrode in a first sub-pixel area in each column of sub-pixel areas includes a first edge and a second edge, between which there is an orthographic projection of one of the multiple touch signal lines on the substrate.

4. The array substrate according to claim 1, wherein: An orthographic projection of the via connection portion on the substrate does not overlap with an orthographic projection of the first pixel electrode on the substrate.

5. The array substrate according to claim 1, wherein: The edge of the first recess is parallel to the edge of the via connecting portion adjacent thereto.

6. The array substrate according to any one of claims 1 to 5, wherein: The array substrate comprises a plurality of touch signal lines located on the substrate; The plurality of pixel electrodes include adjacent first and second rows of pixel electrodes, the first and second rows of pixel electrodes both extending along the first direction and being sequentially arranged along the second direction; The first row of pixel electrodes and the second row of pixel electrodes both intersect with at least two touch signal lines, at least one of the at least two touch signal lines has the via connection portion between the first row of pixel electrodes and the second row of pixel electrodes, and at least another of the at least two touch signal lines does not have the via connection portion between the first row of pixel electrodes and the second row of pixel electrodes.

7. The array substrate according to claim 6, wherein: The pixel electrodes in the first row are closer to the via-hole connecting portion than the pixel electrodes in the second row, and the pixel electrodes in the first row of pixel electrodes that are closest to the via-hole connecting portion have the first recess.

8. The array substrate according to claim 7, wherein: The pixel electrode in the first row of pixel electrodes adjacent to the pixel electrode closest to the via-hole connecting portion has a second recess facing the pixel electrode in the second row.

9. The array substrate according to any one of claims 1 to 5, wherein: The array substrate includes a first electrode, the first electrode is the common electrode or the first pixel electrode, the first electrode includes a plurality of strip electrodes, and the plurality of strip electrodes extend along the second direction; In the first sub-pixel region, the orthographic projection of the touch signal line is at least partially located between orthographic projections of adjacent strip electrodes in the first direction on the substrate.

10. An array substrate, comprising: substrate; a plurality of first display signal lines and a plurality of second display signal lines located on the substrate, wherein the plurality of first display signal lines extend along a first direction and are sequentially arranged along a second direction different from the first direction, the plurality of second display signal lines extend along the second direction and are sequentially arranged along the first direction, and the plurality of second display signal lines cross the first display signal lines to define a plurality of sub-pixel regions; A touch signal line located on the substrate, wherein the touch signal line extends along the second direction; a first insulating layer and a common electrode located on the substrate, wherein the first insulating layer is located between the touch signal line and the common electrode in a direction perpendicular to the substrate, the touch signal line is electrically connected to the common electrode through a touch line via hole penetrating the first insulating layer, and an orthographic projection of the touch line via hole on the substrate overlaps with an orthographic projection of the first display signal line on the substrate; and A plurality of pixel electrodes are located on the substrate, wherein the plurality of pixel electrodes are respectively located in the plurality of sub-pixel regions, The plurality of sub-pixel regions include a first sub-pixel region, the plurality of pixel electrodes include a first pixel electrode, the first pixel electrode is located in the first sub-pixel region, the first pixel electrode includes a first edge and a second edge arranged along the first direction and extending along the second direction, and the orthographic projection of the touch signal line on the substrate is located between the orthographic projections of the first edge and the second edge on the substrate; The array substrate comprises a first electrode, the first electrode is the common electrode or the first pixel electrode, the first electrode comprises a plurality of strip electrodes, and the plurality of strip electrodes extend along the second direction; in the first sub-pixel region, the orthographic projection of the touch signal line is at least partially located between orthographic projections of adjacent strip electrodes on the substrate in the first direction; The first sub-pixel region includes a first region and a second region surrounding the first region; The multiple strip electrodes include a first strip electrode adjacent to the touch signal line, the first strip electrode having a first strip electrode bending portion in the first area, the touch signal line having a first touch line bending portion in the first area, the first touch line bending portion and the first strip electrode bending portion bending in the same direction in the first area, an orthographic projection of the first touch line bending portion on the substrate and an orthographic projection of the first strip electrode bending portion on the substrate are arranged sequentially in the first direction, and a bending angle of the first touch line bending portion is greater than a bending angle of the first strip electrode bending portion.

11. The array substrate according to claim 10, wherein: The first strip electrode bending portion is located on a first side of the first touch line bending portion, and the first touch line bending portion is bent in a direction away from the first strip electrode bending portion; along the direction from one end to the other end of the first strip electrode, the distance between the orthographic projection of the first touch line bending portion and the orthographic projection of the first strip electrode bending portion first decreases and then increases.

12. The array substrate according to claim 10, wherein: The first strip-shaped electrode bent portion has a tip extending toward the first touch wire bent portion, and the first touch wire bent portion has an arc-shaped end extending in a direction away from the tip.

13. The array substrate according to claim 10, wherein: The orthographic projection of the first strip electrode bent portion does not overlap with the orthographic projection of the first touch line bent portion.

14. The array substrate according to claim 10, wherein: The multiple strip electrodes also include a second strip electrode adjacent to the touch signal line, the second strip electrode having a second strip electrode bending portion in the first area, the first strip electrode bending portion, the second strip electrode bending portion and the first touch line bending portion located therebetween are bent toward the same direction within the first area, the orthographic projection of the second strip electrode bending portion on the substrate and the orthographic projection of the first touch line bending portion are arranged sequentially in the first direction, and the bending angle of the second strip electrode bending portion is smaller than the bending angle of the first touch line bending portion.

15. The array substrate according to any one of claims 10 to 14, further comprising a plurality of switch elements located on the substrate, wherein: The plurality of switch elements are respectively located in the plurality of sub-pixel regions, the plurality of switch elements include a first switch element, and the first switch element is located in the first sub-pixel region, The touch signal line has a second touch line bending portion, the second touch line bending portion is located between the first touch line bending portion and the first switch element in the second direction, and the second touch line bending portion is located between adjacent switch elements in the first direction.

16. The array substrate according to claim 15, wherein: A bending angle of the second touch wire bending portion is greater than a bending angle of the first touch wire bending portion.

17. The array substrate according to claim 15, wherein: The first strip electrode has a third strip electrode bending portion, the third strip electrode bending portion is located between the second touch line bending portion and the first switch element in the first direction, and the bending direction of the third strip electrode bending portion is opposite to that of the second touch line bending portion.

18. The array substrate according to claim 15, wherein: Each switching element includes a gate, a source and a drain, and an orthographic projection of the source on the substrate includes a U-shaped structure.

19. An array substrate, comprising: substrate; a plurality of first display signal lines and a plurality of second display signal lines located on the substrate, wherein the plurality of first display signal lines extend along a first direction and are sequentially arranged along a second direction different from the first direction, the plurality of second display signal lines extend along the second direction and are sequentially arranged along the first direction, and the plurality of second display signal lines cross the first display signal lines to define a plurality of sub-pixel regions; A touch signal line located on the substrate, wherein the touch signal line extends along the second direction; a first insulating layer and a common electrode located on the substrate, wherein the first insulating layer is located between the touch signal line and the common electrode in a direction perpendicular to the substrate, and the touch signal line is electrically connected to the common electrode through a touch line via hole penetrating the first insulating layer; and A plurality of pixel electrodes are located on the substrate, wherein the plurality of pixel electrodes are respectively located in the plurality of sub-pixel regions, The plurality of sub-pixel regions include a first sub-pixel region, the plurality of pixel electrodes include a first pixel electrode, the first pixel electrode is located in the first sub-pixel region, the first pixel electrode includes a first edge and a second edge arranged along the first direction and extending along the second direction, and the orthographic projection of the touch signal line on the substrate is located between the orthographic projections of the first edge and the second edge on the substrate; The array substrate comprises a pixel electrode layer located on the substrate, the pixel electrode layer comprises the plurality of pixel electrodes and comprises an etching stopper insulated from the plurality of pixel electrodes, the etching stopper is located in the touch line via hole, and the common electrode is electrically connected to the touch signal line through the etching stopper; The etching stopper covers the sidewall of the touch line via hole.

20. The array substrate according to claim 19, wherein: The first insulating layer comprises a first sub-insulating layer, an organic insulating layer and a second sub-insulating layer which are sequentially located on the substrate, and the first sub-insulating layer is located between the organic insulating layer and the substrate in a direction perpendicular to the substrate; The touch line via includes a first sub-insulating layer via located in the first sub-insulating layer, an organic insulating layer via located in the organic insulating layer, and a second sub-insulating layer via located in the second sub-insulating layer, the first sub-insulating layer via, the organic insulating layer via, and the second sub-insulating layer via are interconnected, and the etching blocking portion at least covers the side wall of the first sub-insulating layer via.

21. The array substrate according to claim 20, wherein: Adjacent edges of the first sub-insulating layer via hole and the organic insulating layer via hole are aligned.

22. The array substrate according to claim 20, wherein: The orthographic projection of the organic insulating layer on the substrate includes a portion extending into the orthographic projection of the second sub-insulating layer via hole on the substrate.

23. The array substrate according to any one of claims 20 to 22, further comprising a connecting member and a second insulating layer located on the substrate, wherein: The second insulating layer is located on a side of the touch signal line facing the substrate, and the first insulating layer is located on a side of the touch signal line facing away from the substrate; The connecting member is located on a side of the second insulating layer facing the substrate, and the connecting member is electrically connected to the common electrode through a connecting member via hole penetrating the second insulating layer and the first insulating layer.

24. The array substrate as claimed in claim 23, wherein: The connecting member via includes a first sub-via located in the second insulating layer, a second sub-via located in the first sub-insulating layer, a third sub-via located in the organic insulating layer, and a fourth sub-via located in the second sub-insulating layer, and the first sub-via, the second sub-via, the third sub-via and the fourth sub-via are interconnected.

25. A touch display device, comprising the array substrate according to any one of claims 1 to 9, the array substrate according to any one of claims 10 to 18, or the array substrate according to any one of claims 19 to 24.

26. The touch display device according to claim 25, further comprising a black matrix layer, wherein: A portion of the first sub-pixel region surrounded by the black matrix layer is an opening region, and the orthographic projection of the touch signal line in the first sub-pixel region passes through the opening region.

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