Reservoir devices and methods of operating reservoir devices

Abstract

A memory device is provided. The memory device includes a non-volatile memory device disposed on a printed circuit board (PCB), a connector, a memory controller, and at least one first passive filter. The connector is disposed in the PCB and includes connection terminals. The memory controller is disposed on the PCB, communicates with an external host through the connection terminals, and controls the non-volatile memory device. The at least one first passive filter is disposed in the PCB, connected between the connector and the memory controller, and performs equalization on signals provided to and from the memory controller.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0099602, filed on August 10, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The methods, apparatus, and systems consistent with the example embodiments generally relate to storage devices, and more specifically, to storage devices and methods of operating storage devices. Background Technology

[0004] Storage devices are devices used to store data under the control of a host device such as a computer, smartphone, and / or smart tablet. Storage devices include devices for storing data on disks (such as hard disk drives (HDDs)) and devices for storing data on semiconductor memory (such as solid-state drives (SSDs) and memory cards), that is, including non-volatile memory.

[0005] The use of storage devices, including non-volatile memory, is expanding from personal computers to commercial computers such as data servers. With the increasing use of storage devices, various functionalities and form factors are required in various fields. Storage devices connect to various hosts and transmit high-frequency signals to them, thus necessitating enhanced signal characteristics at the output of the storage device. Summary of the Invention

[0006] Some example embodiments provide a storage device capable of enhancing the signal integrity of signals output from the storage device.

[0007] Some example embodiments provide a method of operating a storage device that can enhance the signal integrity of signals output from the storage device.

[0008] According to an example embodiment, a memory device includes: a plurality of non-volatile memory devices disposed on a printed circuit board (PCB), a connector, a memory controller, and at least one first passive filter. The connector is disposed in the PCB and includes a plurality of connection terminals. The memory controller is disposed on the PCB and communicates with an external host via the connection terminals to control the plurality of non-volatile memory devices. The at least one first passive filter is disposed in the PCB, connected between the connector and the memory controller, and performs equalization on signals supplied to and from the memory controller.

[0009] According to an example embodiment, a method of operating a memory device includes: arranging a memory controller and a plurality of non-volatile memory devices on a printed circuit board (PCB); arranging a connector including a plurality of connection terminals in the PCB; arranging a data transmission line electrically connecting the memory controller and the plurality of non-volatile memory devices in the PCB; arranging at least one passive filter in the PCB between the connector and the memory controller; performing equalization on signals provided to or from the memory controller using the at least one passive filter; and communicating with an external host using the memory controller via the connector.

[0010] According to an example embodiment, a memory device includes: a plurality of non-volatile memory devices disposed on a printed circuit board (PCB), a connector, a memory controller, and at least one passive filter. The connector is disposed in the PCB and includes a plurality of connection terminals. The memory controller is disposed on the PCB, communicates with an external host via the connection terminals, and controls the plurality of non-volatile memory devices. The at least one passive filter is disposed in the PCB, connected between the connector and the memory controller, and performs equalization on signals supplied to or from the memory controller. The at least one passive filter includes a filter resistor and a filter capacitor connected in parallel between a first node and a second node. The filter resistor and filter capacitor are disposed in the PCB. The first node is coupled to the memory controller, and the second node is coupled to the connector.

[0011] Therefore, at least one passive filter is placed on the PCB between the connector and the memory controller, through which the memory controller communicates with an external host. The memory controller and the at least one passive filter perform equalization on the signals provided to or supplied to the memory controller. As a result, the signal integrity of the high-frequency signals output from the memory controller to the host is improved, and thus, the power consumption of the memory device can be reduced. Attached Figure Description

[0012] The above and other objects and features will become more apparent from the following description of exemplary embodiments with reference to the accompanying drawings, in which:

[0013] Figure 1 This is a block diagram illustrating a storage system according to an example embodiment.

[0014] Figure 2 This illustrates an example embodiment. Figure 1 A block diagram of the host in the system.

[0015] Figure 3 This illustrates an example embodiment. Figure 1 A block diagram of an example of a memory controller.

[0016] Figure 4 It is further shown that it is used for Figure 1 A block diagram illustrating an example of the interface of a storage system.

[0017] Figure 5A Showing according to an example embodiment Figure 1 The upper surface of the connector in the middle, Figure 5B Showing according to an example embodiment Figure 1 The lower surface of the connector in the middle.

[0018] Figure 6 Showing according to an example embodiment Figure 5A and Figure 5B The connector terminals in the middle.

[0019] Figure 7 Showing according to an example embodiment Figure 1 The relationship between the passive filter, memory controller and host in the system.

[0020] Figure 8 Showing according to an example embodiment Figure 7 An example of the first filter in the example.

[0021] Figure 9 and Figure 10 These are, respectively, a plan view and a cross-sectional view of a PCB on which a storage device is mounted, according to an example embodiment.

[0022] Figure 11 and Figure 12 These are plan and cross-sectional views of a storage device according to an example embodiment.

[0023] Figure 13 This illustrates an example embodiment. Figure 1 A block diagram of an example of a storage device.

[0024] Figure 14 This illustrates a configuration in a PCB according to an example embodiment. Figure 13 Examples of passive filters in [the text].

[0025] Figure 15 This illustrates a configuration in a PCB according to an example embodiment. Figure 13 Another example of a passive filter in [the context].

[0026] Figure 16 This illustrates an example embodiment. Figure 1 A block diagram of another example of a storage device in the image.

[0027] Figure 17 This illustrates an example embodiment. Figure 1A block diagram of one of the non-volatile memory devices in the memory device.

[0028] Figure 18 Showing according to an example embodiment Figure 17 A block diagram of a memory cell array in a non-volatile memory device.

[0029] Figure 19 Showing according to an example embodiment Figure 18 A circuit diagram of one of the memory blocks.

[0030] Figure 20 Show Figure 19 An example of the structure of a string of cells in a memory block.

[0031] Figure 21 and Figure 22 This is a diagram used to explain the operation of a storage device according to an example embodiment.

[0032] Figure 23 This is a flowchart illustrating a method of operating a storage device according to an example embodiment.

[0033] Figure 24 This is a block diagram illustrating a storage system according to an example embodiment. Detailed Implementation

[0034] In the following description, exemplary embodiments will be described more fully with reference to the accompanying drawings, in which some exemplary embodiments are illustrated.

[0035] Figure 1 This is a block diagram illustrating a storage system according to an example embodiment.

[0036] Reference Figure 1 The storage system may include a host 100 and a storage device 200. The host 100 may include a storage interface 140.

[0037] exist Figure 1 In this example, storage device 200 is shown as a solid-state drive (SSD) device. However, the example embodiment is not limited to this. According to some example embodiments, storage device 200 can be any kind of storage device.

[0038] The storage device 200 may include a storage controller 300, a plurality of non-volatile memory devices 400a to 400k (where k is an integer greater than 2), a power supply circuit 500, and a connector 240. The connector 240 may include a signal connector 241 and a power connector 243. The storage device 200 may also include a volatile memory device 250.

[0039] Multiple non-volatile memory devices 400a to 400k may be used as storage media for memory device 200. In some example embodiments, each of the multiple non-volatile memory devices 400a to 400k may include flash memory or vertical NAND memory devices. Memory controller 300 may be coupled to the multiple non-volatile memory devices 400a to 400k respectively via multiple channels CHG1 to CHGk.

[0040] The memory controller 300 can receive a receive signal RX from the host 100, send a transmit signal TX to the host 100, and exchange a clock signal CLK with the host 100 via a signal connector 241. The receive signal RX may include a command signal, an address signal, and data.

[0041] The memory controller 300 can write data to multiple non-volatile memory devices 400a to 400k based on command signals and address signals, or read data from multiple non-volatile memory devices 400a to 400k based on command signals and address signals. That is, the memory controller 300 can communicate with the host 100 through connector 240.

[0042] The memory controller 300 may use the volatile memory device 250 as an input / output buffer to communicate with the host 100. In some example embodiments, the volatile memory device 250 may include dynamic random access memory (DRAM).

[0043] Additionally, the storage device 200 may include at least one passive filter 260 and 280 connected between the storage controller 300 and the signal connector 241. The at least one passive filter 260 and 280 may perform equalization on signals provided to or supplied by the storage controller 300.

[0044] At least one passive filter 260 and 280 may be disposed in a printed circuit board (PCB) on which a memory controller 300 and a plurality of non-volatile memory devices 400a to 400k are disposed. At least one passive filter 260 and 280 may be provided (or formed) using at least a portion of the PCB.

[0045] Passive filter 260 can perform equalization on signals supplied from storage controller 300 to host 100, and passive filter 280 can perform equalization on signals supplied from host 100 to storage controller 300. That is, at least one passive filter 260 and 280 can enhance the signal integrity of signals exchanged between host 100 and storage device 200. Signals can indicate data.

[0046] The power supply circuit 500 can be configured to receive a power supply voltage (i.e., an external power supply voltage) VES from the host 100 via a power connector 243. The power supply circuit 500 can generate, based on the power supply voltage VES, at least one first operating voltage VOP1 used by a plurality of non-volatile memory devices 400a to 400k, at least one second operating voltage VOP2 used by the memory controller 300, and at least one third operating voltage VOP3 used by the volatile memory device 250.

[0047] The power supply circuit 500 can provide a first operating voltage VOP1 to a plurality of non-volatile memory devices 400a to 400k, a second operating voltage VOP2 to the memory controller 300, and a third operating voltage VOP3 to the volatile memory device 250.

[0048] Figure 2 This illustrates an example embodiment. Figure 1 A block diagram of the host in the system.

[0049] Reference Figure 2 The host 100 may include a central processing unit (CPU) 110, a read-only memory (ROM) 120, a main memory 130, a storage interface 140, a user interface 150, and a bus 160.

[0050] Bus 160 can refer to the channel via which data is sent and received between the CPU 110, ROM 120, main memory 130, storage interface 140, and user interface 150 of host 100. ROM 120 can store various applications. For example, it can store applications that support storage protocols such as Advanced Technology Attachment (ATA), Small Computer System Interface (SCSI), Embedded Multimedia Card (eMMC), and / or Unix File System (UFS).

[0051] Main memory 130 may temporarily store data or programs. User interface 150 may be a physical or virtual medium for exchanging information between a user and host 100, computer programs, etc., and includes physical hardware and logical software. For example, user interface 150 may include input devices for allowing the user to manipulate host 100, and output devices for outputting the processing results of the user's input.

[0052] CPU 110 can control the overall operation of host 100. CPU 110 can generate commands for storing data in storage device 200 or requests (or commands) for reading data from storage device 200 by using applications stored in ROM 120, and send the requests to storage device 200 via storage interface 140.

[0053] Figure 3This illustrates an example embodiment. Figure 1 A block diagram of an example of a memory controller.

[0054] Reference Figure 3 The memory controller 300 may include a processor 310, an error correction code (ECC) engine 320, a ROM 330, a random function generator 335, a host interface 340, a memory controller 360, and a non-volatile memory interface 350, which are connected via a bus 305.

[0055] The processor 310 controls the overall operation of the memory controller 360.

[0056] The threshold voltage distribution of the memory cells in the non-volatile memory devices 400a to 400k may vary due to factors such as program runtime, temperature, program interference, and read interference. For example, due to these factors, the data stored in the non-volatile memory devices 400a to 400k may become corrupted. The memory controller 300 utilizes various error correction techniques to correct such errors. For example, the memory controller 300 may include an ECC engine 320. The ECC engine 320 can correct errors in the data read from the non-volatile memory devices 400a to 400k.

[0057] ROM 330 can store firmware, and the firmware can be loaded into volatile memory device 250 and driven by processor 310.

[0058] Random function generator 335 randomizes data stored in non-volatile memory devices 400a to 400k. For example, random function generator 335 can randomize data stored in non-volatile memory devices 400a to 400k on a word-line basis.

[0059] Data randomization is used to process data so that the programming states of memory cells connected to a word line have the same ratio. For example, if the memory cells connected to a word line are multilevel cells (MLCs) that each store 2 bits of data, then each of the memory cells has one of the following states: erase state and first programming state through third programming state.

[0060] In this case, the random function generator 335 randomizes the data such that, in the memory cells connected to a word line, the number of memory cells in the erase state, the number of memory cells in the first programming state, the number of memory cells in the second programming state, and the number of memory cells in the third programming state are substantially the same. For example, the memory cells storing the randomized data have an equal number of programming states.

[0061] The random function generator 335 derandomizes the data read from the non-volatile memory devices 400a to 400k.

[0062] The memory controller 300 can communicate with the host 100 via the host interface 340, and can communicate with non-volatile memory devices 400a to 400k via the non-volatile memory interface 350. The memory controller 300 can control the volatile memory device 250 via the memory controller 360.

[0063] Figure 4 It is further shown that it is used for Figure 1 A block diagram illustrating various aspects of the interface of a storage system.

[0064] exist Figure 4 The example shown is a SATA interface. However, the example embodiment is not limited to this.

[0065] The storage interface 140 and connector 240 can be connected via a SATA cable that includes a data segment and a power segment.

[0066] The data segment (i.e., signal connector 241) is shown as comprising two unidirectional data line pairs, DIN and DOUT. DIN is used to provide data from host 100 to storage device 200. DOUT is used to provide data from storage device 200 to host 100. The data lines implementing DIN and DOUT can be connected between the corresponding transmit (TX) and receive (RX) terminals (e.g., TXP, TXN, RXP, and RXN terminals) of host 100 and storage device 200. The data segment may also be referred to as the signal segment.

[0067] The power section (i.e., power connector 243) includes 15 power lines (e.g., P1 to P15). The power section can be connected to various power terminals (PWR) of the host 100 and the storage device 200, and can be used to supply various voltages such as 3.3V, 5V and 12V from the host 100 to the storage device 200.

[0068] Passive filters 260 and 280 can be disposed between connector 240 and memory controller 300.

[0069] Figure 5A Showing according to an example embodiment Figure 1 The upper surface of the connector in the middle, Figure 5B Showing according to an example embodiment Figure 1 The lower surface of the connector in the middle.

[0070] like Figure 5A As shown, the odd-numbered pins from pin 1 to pin 75 can be arranged in parallel on the upper surface of connector 240. (As...) Figure 5BAs shown, the even-numbered pins from pin 2 to pin 74 can be arranged in parallel on the lower surface of connector 240.

[0071] Connector 240 may provide a key where no pins are provided. The key prevents connector 240 from being inverted when inserted into host 100. For example, the key may be off-center from the center of connector 240 and may be located at pins 59 to 66 (pins 59 to 66). The pins of connector 240 may be arranged to support communication interfaces such as PCIe. The pin arrangement may be changed to support other communication interfaces.

[0072] Figure 6 Showing according to an example embodiment Figure 5A and Figure 5B The connector terminals in the middle.

[0073] Reference Figure 5A and Figure 6 The diagram shows pins 1 through 75 of connector 240. For example, pins with odd numbers from pin 1 to pin 75 may be located on the upper surface of connector 240, and pins with even numbers from pin 2 to pin 74 may be located on the lower surface of connector 240.

[0074] Pins 1, 3, 9, 15, 21, 27, 33, 39, 45, 51, 57, 71, 73 and / or 75 (pin 1, pin 3, pin 9, pin 15, pin 21, pin 27, pin 33, pin 39, pin 45, pin 51, pin 57, pin 71, pin 73 and / or pin 75) may be configured to be connected to ground voltage GND, regardless of the communication type of the storage device 200.

[0075] Depending on the power mode, pins 2, 4, 14, 16, 18, 70, 72, and 74 (pins 2, 4, 14, 16, 18, 70, 72, and 74) may be unconnected (N / C) or receive 3.3V power. The power mode may be determined based on or without considering the communication type of the storage device 200. N / C may indicate that the pin is not physically connected to the storage controller 300. In some example embodiments, N / C may indicate that the pin is physically connected to the storage controller 300, but the storage controller 300 may not use the pin.

[0076] Pins 40 and 42 (pins 40 and 42) can form a sideband interface as part of the System Management Bus (SMBus). Pin 40 (pin 40) can input the System Management Bus clock SMB_CLK from host 100 to connector 240, or output the clock SMB_CLK from connector 240 to host 100. Pin 40 (pin 40) can be switched between 0V and 1.8V.

[0077] Pin 42 (pin 42) allows the system management bus data SMB_DATA to be input from host 100 to connector 240, or the data SMB_DATA to be output from connector 240 to host 100. Pin 42 (pin 42) can be switched between 0V and 1.8V.

[0078] Pins 56 and 58 (pins 56 and 58) may be used during the manufacturing process of the memory device 200. Pin 56 (pin 56) may be reserved during manufacturing for manufacturing data transmission (MFG_DATA).

[0079] Pin 58 (pin 58) may be reserved during manufacturing for manufacturing clock transmission (MFG_CLK). After the manufacture of memory device 200 is complete, i.e., during normal operation of memory device 200, pins 56 and 58 (pins 56 and 58) may not be used. Pin 68 (pin 68) can be used to receive the pause clock SUSCLK in low-power mode. For example, the pause clock SUSCLK may have a frequency of 32 kHz.

[0080] Pins 59 to 66 (pins 59 to 66) correspond to Figure 2 The key shown, and pins 59 to 66 (pins 59 to 66) may not actually be provided. However, pins 59 to 66 (pins 59 to 66) are in Figure 6 The pin numbers are shown in the diagram to clearly describe them.

[0081] Pin 5 can be used as the third negative transmit terminal PETn3 in the PCIe communication interface. Pin 7 can be used as the third positive transmit terminal PETp3 in the PCIe communication interface. Pin 11 can be used as the third negative receive terminal PERn3 in the PCIe communication interface.

[0082] Pin 13 (pin 13) can be used as the third positive receive terminal PERp3 in the PCIe communication interface.

[0083] Pin 17 (pin 17) can be used as the second negative transmit terminal PETn2 in the PCIe communication interface. Pin 19 (pin 19) can be used as the second positive transmit terminal PETp2 in the PCIe communication interface. Pin 23 (pin 23) can be used as the second negative receive terminal PERn2 in the PCIe communication interface.

[0084] Pin 25 (pin 25) can be used as the second positive receive terminal PERp2 in the PCIe communication interface.

[0085] Pin 29 can be used as the first negative transmit terminal PETn1 in the PCIe communication interface. Pin 31 can be used as the first positive transmit terminal PETp1 in the PCIe communication interface. Pin 35 can be used as the first negative receive terminal PERn1 in the PCIe communication interface. Pin 37 can be used as the first positive receive terminal PERp1 in the PCIe communication interface.

[0086] Pin 41 (pin 41) can be used as the zeroth negative transmit terminal PETn0 in the PCIe communication interface. Pin 43 (pin 43) can be used as the zeroth positive transmit terminal PETp0 in the PCIe communication interface.

[0087] Pin 47 can be used as the zero negative receive terminal PERn0 in the PCIe communication interface. Pin 49 can be used as the zero positive receive terminal PERp0 in the PCIe communication interface.

[0088] Pin 53 (pin 53) can be used to receive the negative reference clock REFCLKn from the PCIe communication interface. Pin 55 (pin 55) can be used to receive the positive reference clock REFCLKp from the PCIe communication interface.

[0089] Pin 10 (pin 10) can be used by storage device 200 to send a signal LED1# for controlling an external light-emitting diode (LED) to an external device (e.g., host 100).

[0090] Terminal 38 can be used to send or receive the device sleep signal DEVSLP or the power off signal PWDIS in SATA communication type, and can be an unconnected N / C in PCIe communication type. Terminal 44 can be an unconnected N / C in SATA communication type, and can be used to receive or send the alarm signal ALERT# in PCIe communication type. Terminal 44 can be included in the System Management Bus (SMBus) in PCIe communication type.

[0091] Terminal 50 can be unconnected (N / C) in SATA communication type and can be used to receive the reset signal PERST#0 in PCIe communication type. Terminal 52 can be unconnected (N / C) in SATA communication type and can be used to send or receive the clock request signal CLKREQ# in PCIe communication type. Terminal 54 can be unconnected (N / C) in SATA communication type and can be used to send or receive the wake-up signal PEVAKE# in PCIe communication type.

[0092] The 69th connection terminal can be used to notify an external host of the communication type of the storage device 200. In SATA communication type, the 69th connection terminal can be connected to the ground node of the storage device 200 and can provide ground voltage to the host as a notification signal PEDET. In PCIe communication type, the 69th connection terminal can be unconnected (N / C) or floating. That is, the 69th connection terminal can be used by the storage device 200 to support multiple communication protocols, specifically to determine whether any of the multiple communication protocols are used.

[0093] Terminals 6, 8, 20, 22, 24, 26, 28, 30, 32, 34, 36, 46, 48, and 67 (connection terminal 6, connection terminal 8, connection terminal 20, connection terminal 22, connection terminal 24, connection terminal 26, connection terminal 28, connection terminal 30, connection terminal 32, connection terminal 34, connection terminal 36, connection terminal 46, connection terminal 48, and connection terminal 67) can be used to support power mode.

[0094] The description of the connection terminals is merely an example, and the number of connection terminals and the function of each connection terminal may vary based on the communication protocol.

[0095] Figure 7 Showing according to an example embodiment Figure 1 The relationship between the passive filter, memory controller and host in the system.

[0096] exist Figure 7 It also shows Figure 2 The receiver 141 in the storage interface and the transmitter 341 in the host interface 340.

[0097] exist Figure 7 In the transmitter 341, there is a driver 342 for transmitting differential signals SIGP and SIGN to the receiver 141 via pads PD11 and PD12, passive filter 260, connection terminals 241a and 241b of signal connector 241, and main channels HCH1 and HCH2.

[0098] Reference Figure 7 The transmitter 341 includes a driver 342, a first resistor R11, a first capacitor C11, a second resistor R12, and a second capacitor C12.

[0099] The first resistor R11 can be coupled between node N11 and driver 342, the first capacitor C11 can be coupled between node N11 and ground voltage VSS, the second resistor R12 can be coupled between node N12 and driver 342, and the second capacitor C12 can be coupled between node N12 and ground voltage VSS.

[0100] The first resistor R11 and the second resistor R12 may have the same resistance value. The first capacitor C11 and the second capacitor C12 may have the same capacitance value. The transmitter 341 may provide a positive signal SIGP at node N11 and a negative signal SIGN at node N12.

[0101] The passive filter 260 may include a first filter (FIL1) 261 and a second filter (FIL2) 263.

[0102] The first filter 261 can be connected between pad PD11 and the first connection terminal 241a, and the second filter 263 can be connected between pad PD12 and the second connection terminal 241b. The first filter 261 can equalize (filter) the positive signal SIGP to provide an equalized signal to the main channel HCH1 through the first connection terminal 241a, and the second filter 263 can equalize (filter) the negative signal SIGN to provide an equalized signal to the main channel HCH2 through the second connection terminal 241b.

[0103] The first connection terminal 241a can be connected to the receiver 141 via the main channel HCH1, and the second connection terminal 241b can be connected to the receiver 141 via the main channel HCH2.

[0104] Receiver 141 may include resistor R2, first capacitor C21 and second capacitor C22.

[0105] Resistor R2 may be coupled between nodes N31 and N32, first capacitor C21 may be coupled between node N31 and ground voltage VSS, and second capacitor C22 may be coupled between node N32 and ground voltage VSS. First capacitor C21 and second capacitor C22 may have the same capacitance. A positive voltage signal VOUTP is provided at node N31 in response to the positive signal SIGP, and a negative voltage signal VOUTN is provided at node N32 in response to the negative signal SIGN.

[0106] Figure 8 Showing according to an example embodiment Figure 7 An example of the first filter in the example.

[0107] refer to Figure 8 The first filter 261 may include a filter resistor Rf and a filter capacitor Cf connected in parallel between the first node N21 and the second node N22.

[0108] The construction of the second filter 263 can be compared with... Figure 7 The first filter 261 is constructed identically. At least one of the filter resistor Rf and filter capacitor Cf can be provided using at least a portion of the PCB.

[0109] Figure 7 The resistor R2 and capacitors C21 and C22 in receiver 141 and Figure 8 The filter resistor Rf and filter capacitor Cf in the first filter 261 can form a passive continuous-time linear equalizer (CTLE). The passive CTLE can provide enhanced linearity and improve the signal integrity of voltage signals VOUTP and VOUTN.

[0110] Figure 9 and Figure 10 These are, respectively, a plan view and a cross-sectional view of a PCB on which a storage device is mounted, according to an example embodiment.

[0111] Reference Figure 9 and Figure 10 PCB 10 is shown as including first channel pattern CHP1 to fourth channel pattern CHP4.

[0112] PCB 10 may include a body layer 11, a top protective layer 13, and a bottom protective layer 15. PCB 10 may include wiring units, and the wiring units on PCB 10 may be electrically connected to a memory controller 300 and non-volatile memory devices 400a to 400k. Additionally, PCB 10 may include connectors 240. PCB 10 may be electrically connected to a module substrate, system board, motherboard, etc., via connectors 240.

[0113] In the main body layer 11, multi-layer or single-layer wiring units can be formed, and the PCB 10 can be electrically connected to the memory controller 300 and non-volatile memory devices 400a to 400k through the wiring units. The top protective layer 13 and the bottom protective layer 15 can perform protective functions and can be formed of solder resist.

[0114] In addition, the main body layer 11 can typically be achieved by the following steps: pressing a polymer material such as thermosetting resin, epoxy resin, and phenolic resin (such as flame retardant 4 (FR-4), bismaleimide triazine (BT) and Ajinomoto structure film (ABF)) to a certain thickness, forming a thin layer from the pressing result, coating copper foil on both sides of the formed thin layer, and forming wiring units as transmission paths for electrical signals by patterning.

[0115] Furthermore, PCB 10 can be divided into a single-layer PCB with wiring formed on one side and a double-layer PCB with wiring formed on both sides. In addition, the number of thin layers can be three or more, and the thin layers can be formed by using an insulating material such as a prepreg, and a PCB including multi-layer wiring can be realized by forming three or more wiring layers depending on the number of thin layers formed.

[0116] PCB 10 may be a substrate on which semiconductor packages are mounted, and includes an insulating layer and wiring units. The wiring units may include a first conductive trace CT1 and a second conductive trace CT2 formed in the insulating layer, and may include a first conductive via CV1 that passes through the insulating layer and is connected to the first conductive trace CT1, and a second conductive via CV2 that passes through the insulating layer and is connected to the second conductive trace CT2.

[0117] The first channel pattern CHP1 may be a first wiring unit and may include a first conductive trace CT1 extending in a first direction D1, a first conductive via CV1 extending in a third direction D3, and a first conductive pad CP1 formed on the top side of the first conductive via CV1.

[0118] The second channel pattern CHP2 may be a second wiring unit and may include a second conductive trace CT2 extending in the first direction D1, a second conductive via CV2 extending in the third direction D3, and a second conductive pad CP2 formed on the top side of the second conductive via CV2.

[0119] In some example embodiments, the second channel pattern CHP2 formed in a daisy chain manner / topology may have different wiring lengths in the first mounting area MR1 and the second mounting area MR2 to compensate for signal loss that occurs only in either the first mounting area MR1 or the second mounting area MR2.

[0120] In some example embodiments, the semiconductor package in the first mounting region MR1 may be electrically connected to the first channel pattern CHP1 to the fourth channel pattern CHP4, and the semiconductor package in the second mounting region MR2 may be electrically connected to the second channel pattern CHP2 and the third channel pattern CHP3.

[0121] Although for ease of description in Figure 10 Only the first channel pattern CHP1 and the second channel pattern CHP2 are shown, but the first channel pattern CHP1 and the third channel pattern CHP3 can be configured in a point-to-point manner / topologically identical to each other (or can be configured as a group of channel patterns), and the second channel pattern CHP2 and the fourth channel pattern CHP4 can be configured in a daisy chain manner / topologically identical to each other (or can be configured as another group of channel patterns). The second channel pattern CHP2 and the fourth channel pattern CHP4 can be formed facing each other and adjacent to each other; and the first channel pattern CHP1 and the third channel pattern CHP3 can be formed facing each other, with the second channel pattern CHP2 and the fourth channel pattern CHP4 located between the first channel pattern CHP1 and the third channel pattern CHP3. Because the second channel pattern CHP2 and the fourth channel pattern CHP4 are formed in a daisy chain manner / topologically and have a branch point in the middle, the branch point can be configured in the arrangement shape described above, such that the branch point does not overlap with the first channel pattern CHP1 and the third channel pattern CHP3, in other words, for the ease of circuit design.

[0122] exist Figure 10 In the example, the second conductive trace CT2 of the second channel pattern CHP2 is shown to be formed on a layer closer to the bottom protective layer 15 than the first conductive trace CT1 of the first channel pattern CHP1. However, the example embodiment is not limited to this, and the first conductive trace CT1 of the first channel pattern CHP1 may be formed on a layer closer to the bottom protective layer 15 than the second conductive trace CT2 of the second channel pattern CHP2, and the first conductive trace CT1 of the first channel pattern CHP1 and the second conductive trace CT2 of the second channel pattern CHP2 may also be formed on the same layer.

[0123] The memory controller region CR and the first mounting region MR1 may include all of the first conductive via CV1 and the second conductive via CV2, as well as the first conductive pad CP1 and the second conductive pad CP2 included in the first channel pattern CHP1 to the fourth channel pattern CHP4, and the second mounting region MR2 may include only a portion of the first conductive via CV1 and the second conductive via CV2, as well as the first conductive pad CP1 and the second conductive pad CP2 included in the second channel pattern CHP2 and the third channel pattern CHP3.

[0124] In addition, PCB 10 may include a power supply area PR next to the memory controller area CR.

[0125] Figure 11 and Figure 12 These are a plan view and a cross-sectional view of a storage device according to an example embodiment.

[0126] refer to Figure 11 and Figure 12 A storage device 200a is provided, wherein a first memory package 401 may be mounted only in a first mounting area MR1 of a PCB 10, a second memory package 402 may be mounted only in a second mounting area MR2 of a PCB 10, a first channel CH1 and a third channel CH3 are connected to the first memory package 401, and a second channel CH2 and a fourth channel CH4 are connected to the second memory package 402.

[0127] Can be stacked Figure 1 At least some of the non-volatile memory devices 400a to 400k are used to form each of the first memory package 401 and the second memory package 402. The first memory package 401 is connected to the first channel CH1 and the second channel CH2 via solder balls SB11 and SB12, the second memory package 402 is connected to the second channel CH2 via solder ball SB22, and the memory controller 300 is connected to the first channel CH1 and the second channel CH2 via solder balls SB31 and SB32.

[0128] Passive filters 260 and 280, which connect connector 240 and memory controller 300, are disposed on PCB 10. Passive filter 260 can be connected to memory controller 300 via solder ball SB33.

[0129] Figure 13 This illustrates an example embodiment. Figure 1 A block diagram of an example of a storage device.

[0130] Reference Figure 13 The memory device 200b may include a memory controller 300 and a package 400, the package 400 including a plurality of non-volatile memory devices 400a to 400k disposed on the PCB 10.

[0131] The memory controller 300 and the non-volatile memory devices 400a to 400k can be electrically coupled to each other via transmission line 50. The memory controller 300 can send command signals and address signals to the non-volatile memory devices 400a to 400k via transmission line 50, and can also exchange data with the non-volatile memory devices 400a to 400k via transmission line 50.

[0132] The storage device 200b may further include a connector 240 disposed as part of a PCB 10 and at least one passive filter 260 connected between the connector 240 and the storage controller 300. The at least one passive filter 260 is disposed in the PCB 10 and can be provided (or formed) by using at least a portion of the PCB 10. The passive filter 260 can be connected to the storage controller 300 via a first conductive pattern 45 and to the connector 240 via a second conductive pattern 40. Figure 1 Signal connector 241 in the middle.

[0133] For reference Figure 7 and Figure 8 The passive filter 260 can equalize the signal provided from the storage controller 300 to the host 100 through the connector 240 to increase the linearity of the signal.

[0134] although Figure 13 The storage device 200b shown includes a storage controller 300 and a package 400 having a plurality of non-volatile memory devices 400a to 400k, but the storage device 200b may also include other components such as power supply circuitry and volatile memory devices.

[0135] Storage device 200b may include flash memory-based data storage media, such as memory cards, smart cards, universal serial bus (USB) memory, and solid-state drives (SSDs).

[0136] Package 400 may include non-volatile memory devices 400a to 400k. If non-volatile memory devices 400a to 400k are housed in package 400 as multiple stacked chips, the stacked non-volatile memory devices 400a to 400k are connected to memory controller 300 via the same channel. When a command associated with a read or write operation is received from the host, and a non-volatile memory device 400a is selected to read data from or write data to, the capacitance of the channel may include parasitic capacitances of unselected non-volatile memory devices 400b to 400k that are not associated with read, write, or copy-back operations.

[0137] Regarding signal integrity, parasitic capacitance affects data transmission through the channel. Non-volatile memory devices 400a to 400k are connected to the same channel, and write data is sent to the non-volatile memory through this channel. When the reflection coefficient between the non-volatile memory devices 400a to 400k and the channel is "0", data to be transmitted to the non-volatile memory can be transmitted to the non-volatile memory without reflection. The reflection coefficient is expressed by the following equation:

[0138] [Equation 1]

[0139] Γ=(Zr-Z0) / (Zr+Z0)

[0140] In Equation 1, “Zr” represents the impedance of the non-volatile memory device 400a to 400k, and “Zo” represents the self-impedance of the channel.

[0141] Theoretically, no reflection will occur when the impedance of the non-volatile memory device (400A to 400K) equals the self-impedance of the channel. The parasitic capacitance of non-volatile memories connected to the same channel increases proportionally to the number of non-volatile memories connected to the same channel.

[0142] As the number of non-volatile memories connected to the same channel increases, the probability of signals sent from the memory controller 300 to the non-volatile memory devices 400a to 400k being reflected becomes higher. Because the signal is distorted due to reflection or impedance mismatch, it is desirable for the measured reactance value of the channel to have a predetermined value.

[0143] Because the probability of signals sent from the memory controller 300 to the host 100 being reflected in the connector 240 due to parasitic capacitance may become higher, the predetermined value of the measured reactance of the channel is similarly applied when read data is provided to the host 100 from the non-volatile memory device via the memory controller.

[0144] According to an example embodiment, the storage device 200 provides at least one passive filter 260 connected in a PCB 10 between a connector 240 and a storage controller 300, and can improve the signal integrity of signals exchanged between the storage controller 300 and the host 100. That is, the storage device 200 can provide an equalizer in the PCB 10 between the connector 240 and the storage controller 300.

[0145] Figure 14 This illustrates a configuration in a PCB according to an example embodiment. Figure 13 Examples of passive filters in [the text].

[0146] Reference Figure 14 The passive filter 260a may include a first pad 265, a second pad 267, and a vertical conductive pattern 268. The first pad 265 may be connected to the connector 240 in the PCB 10. The second pad 267 may be spaced apart from the first pad 265 in a vertical direction D3 from the upper surface UF of the PCB 10 to the lower surface BF of the PCB 10. The vertical conductive pattern 268 may connect the first pad 265 and the second pad 267 in the vertical direction D3.

[0147] The first pad 265 and the second pad 267 can provide Figure 8 The filter capacitor Cf in the middle, and the vertical conductive pattern 268 can provide Figure 8 The filter resistor Rf is located in the memory. The second pad 267 can be connected to the memory controller 300 via the first conductive pattern 45.

[0148] The first pad 265 is a component directly connected to the connector 240, and the second pad 267 is a component connected to the first pad 265. Both the first pad 265 and the second pad 267 may have high capacitance. The vertical conductive pattern 268 may be implemented using a metal with high resistance.

[0149] Figure 15 This illustrates a configuration in a PCB according to an example embodiment. Figure 13 Another example of a passive filter in [the context].

[0150] Reference Figure 15 The passive filter 260b may include a first pad 265, a second pad 267a, and a resistor element 269. The first pad 265 may be connected to the connector 240 in the PCB 10. The second pad 267a is spaced apart from the first pad 265 in a vertical direction D3 from the upper surface UF of the PCB 10 to the lower surface BF of the PCB 10. The resistor element 269 may be disposed on the lower surface BF of the PCB 10.

[0151] The first pad 265 and the second pad 267a can be connected to the resistor element 269 via a first via 266a and a second via 266b on the vertical direction D3, respectively. The second via 266b can penetrate at least a portion of the second pad 267a to connect to the resistor element 269.

[0152] The first pad 265 and the second pad 267a can provide Figure 8 The filter capacitor Cf, and the resistor element 269, the first via 266a and the second via 266b can provide Figure 8 The filter resistor Rf is located in the memory. The second pad 267a can be connected to the memory controller 300 via the first conductive pattern 45.

[0153] The first pad 265 is a component that is directly connected to the connector 240, and the first pad 265 and the second pad 267a may have high capacitance.

[0154] Figure 16 This illustrates an example embodiment. Figure 1 A block diagram of another example of a storage device in the image.

[0155] Reference Figure 16The memory device 200c may include a memory controller 300 disposed on a PCB 10, a package 400 including a plurality of non-volatile memory devices 400a to 400k, and a volatile memory device 250.

[0156] The memory controller 300 and the non-volatile memory devices 400a to 400k can be electrically coupled to each other via a first transmission line 50a and a second transmission line 50b. The memory controller 300 can send command signals and address signals to the non-volatile memory devices 400a to 400k via the first transmission line 50a and the second transmission line 50b, and can also exchange data with the non-volatile memory devices 400a to 400k via the first transmission line 50a and the second transmission line 50b.

[0157] Furthermore, the storage device 200c may also include a connector 240 provided as part of a PCB 10 and at least one passive filter 260 connecting the connector 240 and the storage controller 300. The at least one passive filter 260 is disposed in the PCB 10 and can be provided (or formed) using at least a portion of the PCB 10. The passive filter 260 can be connected to the storage controller 300 via a first conductive pattern 45 and to the connector 240 via a second conductive pattern 40. Figure 1 Signal connector 241 in the middle.

[0158] The memory device 200c may also include at least one passive filter (FIL) 80 disposed in the PCB 10 and connected between the memory controller 300 and the non-volatile memory devices 400a to 400k.

[0159] At least one passive filter 80 can be connected to the memory controller 300 via a first transmission line 50a and to the non-volatile memory devices 400a to 400k via a second transmission line 50b. The at least one passive filter 80 can perform equalization on signals exchanged between the memory controller 300 and the non-volatile memory devices 400a to 400k. The at least one passive filter 80 can improve the signal integrity of signals exchanged between the memory controller 300 and the non-volatile memory devices 400a to 400k.

[0160] The memory device 200c may also include at least one passive filter (FIL) 90 disposed in the PCB 10 and connected between the memory controller 300 and the volatile memory device (VM) 250.

[0161] At least one passive filter 90 can be connected to the memory controller 300 via a first transmission line 95a and to the volatile memory device 250 via a second transmission line 95b. The at least one passive filter 90 can perform equalization on the signals exchanged between the memory controller 300 and the volatile memory device 250. The at least one passive filter 90 can improve the signal integrity of the signals exchanged between the memory controller 300 and the volatile memory device 250.

[0162] At least one passive filter 260 may be referred to as at least one first passive filter, at least one passive filter 80 may be referred to as at least one second passive filter, and at least one passive filter 90 may be referred to as at least one third passive filter.

[0163] Each of passive filters 80 and 90 may include a filter resistor and a filter capacitor connected in parallel in a manner similar to that of passive filter 260. Each of passive filters 80 and 90 may include, as referenced... Figure 8 The filter resistor and filter capacitor are connected in parallel.

[0164] Figure 17 This illustrates an example embodiment. Figure 1 A block diagram of one of the non-volatile memory devices in the memory device.

[0165] Reference Figure 17 The non-volatile memory device 400a includes a memory cell array 430, an address decoder 460, a page buffer circuit 410, a data input / output circuit 420, a control circuit 450, and a voltage generator 470.

[0166] The memory cell array 430 is coupled to the address decoder 460 via a serial select line SSL, multiple word lines WL, and a ground select line GSL. Furthermore, the memory cell array 430 is coupled to the page buffer circuit 410 via multiple bit lines BL. The memory cell array 430 includes multiple memory cells coupled to the multiple word lines WL and the multiple bit lines BL. The memory cell array 430 may also include multiple memory cells coupled to multiple word lines WL stacked in a vertical direction perpendicular to the substrate.

[0167] Figure 18 Show Figure 17 A block diagram of a memory cell array in a non-volatile memory device.

[0168] Reference Figure 18The memory cell array 430 may include multiple memory blocks BLK1 to BLKz. Memory blocks BLK1 to BLKz extend along a first direction D1, a second direction D2, and a third direction D3. In an example embodiment, memory blocks BLK1 to BLKz are formed by... Figure 17 The address decoder 460 selects the memory block BLK corresponding to the block address from memory blocks BLK1 to BLKz.

[0169] Figure 19 Show Figure 18 A circuit diagram of one of the memory blocks.

[0170] Figure 19 The memory block BLKi can be formed on the substrate SUB in a three-dimensional (or vertical) structure. For example, multiple strings of memory cells included in the memory block BLKi can be formed on a direction PD perpendicular to the substrate SUB.

[0171] Reference Figure 19 The memory block BLKi may include memory cell strings NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32, and NS33 (hereinafter referred to as memory cell strings NS11 to NS33) coupled between bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the memory cell strings NS11 to NS33 may include a string select transistor SST, a plurality of memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8 (hereinafter referred to as memory cells MC1 to MC8), and a ground select transistor GST. Figure 19 In this example, each of the memory cell strings NS11 to NS33 includes eight memory cells MC1 to MC8. However, the example embodiment is not limited thereto. In some example embodiments, each of the memory cell strings NS11 to NS33 may include any number of memory cells.

[0172] The serial select transistor SST can be connected to the corresponding serial select lines SSL1, SSL2, and SSL3. Multiple memory cells MC1 to MC8 can be connected to the corresponding word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8 (hereinafter referred to as word lines WL1 to WL8). The ground select transistor GST can be connected to the corresponding ground select lines GSL1, GSL2, and GSL3. The serial select transistor SST can be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground select transistor GST can be connected to the common source line CSL.

[0173] Word lines of the same height (e.g., WL1) can be connected together, and ground select lines GSL1 to GSL3 and serial select lines SSL1 to SSL3 can be separated. Figure 16 In this example, the memory block BLKi is coupled to eight word lines WL1 to WL8 and three bit lines BL1 to BL3. However, the example embodiment is not limited to this. In some example embodiments, the memory cell array 430 may be coupled to any number of word lines and bit lines.

[0174] Figure 20 Show Figure 19 An example of the structure of a cell string CS (e.g., memory cell string NS11) in a memory block.

[0175] Reference Figure 19 and Figure 20 The pillar PL is disposed on the substrate SUB, such that the pillar PL extends in a direction perpendicular to the substrate SUB to contact the substrate SUB. Figure 19 Each of the ground select line GSL (e.g., ground select line GSL1), word lines WL1 to WL8, and string select line SSL (e.g., string select line SSL1) shown may be formed of a conductive material (e.g., a metallic material) parallel to the substrate SUB. The pillar PL may be in contact with the substrate SUB through the conductive material forming the string select line SSL, word lines WL1 to WL8, and ground select line GSL.

[0176] Figure 20 The diagram also shows a cross-sectional view taken along line A-A'. In an example embodiment, a cross-sectional view of the first memory cell MC1 corresponding to the first word line WL1 is shown. The pillar PL may include a cylindrical body BD. An air gap AG may be defined within the body BD.

[0177] The body BD may include P-type silicon and may be the region where the channel will be formed. The pillar PL may also include a cylindrical tunnel insulating layer TI surrounding the body BD and a cylindrical charge trapping layer CT surrounding the tunnel insulating layer TI. A barrier insulating layer BI may be disposed between the first word line WL and the pillar PL. The body BD, tunnel insulating layer TI, charge trapping layer CT, barrier insulating layer BI, and first word line WL may constitute a charge trapping transistor formed in a direction perpendicular to the substrate SUB or perpendicular to the upper surface of the substrate SUB. The string select transistor SST, ground select transistor GST, and other memory cells may have the same structure as the first memory cell MC1.

[0178] Return to reference Figure 17 The control circuit 450 can receive command signal CMD and address signal ADDR from the memory controller 300, and control the erase operation, programming operation and read operation of the non-volatile memory device 400a based on the command signal CMD and address signal ADDR.

[0179] For example, control circuit 450 can generate control signal CTL for controlling voltage generator 470 based on command signal CMD, and generate row address R_ADDR and column address C_ADDR based on address signal ADDR. Control circuit 450 can provide row address R_ADDR to address decoder 460, and provide column address C_ADDR to data input / output circuit 420.

[0180] In the example embodiment, the address decoder 460 is coupled to the memory cell array 430 via the serial select line SSL, multiple word lines WL, and ground select line GSL.

[0181] In the example embodiment, voltage generator 470 generates word line voltage VWL for operation of non-volatile memory device 400a using a first operating voltage VOP1 based on control signal CTL. Word line voltage VWL is applied to multiple word lines WL via address decoder 460.

[0182] In an example embodiment, page buffer circuitry 410 is coupled to memory cell array 430 via multiple bit lines BL. Page buffer circuitry 410 may include multiple page buffers. In some example embodiments, a page buffer may be connected to one bit line. In other example embodiments, a page buffer may be connected to two or more bit lines. Page buffer circuitry 410 may temporarily store data to be programmed into or read from a selected page. Page buffer circuitry 410 is controlled in response to a control signal PCLL received from control circuitry 450.

[0183] In the example embodiment, the data input / output circuit 420 is coupled to the page buffer circuit 410 via the data line DL. During programming operations, the data input / output circuit 420 may receive programming data DTA from the memory controller 300 and provide the programming data DTA to the page buffer circuit 410 based on the column address C_ADDR received from the control circuit 450. During read operations, the data input / output circuit 420 may provide read data DTA stored in the page buffer circuit 410 to the memory controller 300 based on the column address C_ADDR received from the control circuit 450.

[0184] Figure 21 and Figure 22 This is a diagram used to explain the operation of a storage device according to an example embodiment.

[0185] Figure 21 Is when Figure 1 The storage device 200 in the middle does not include at least one passive filter 260 and 280 when the eye diagram of the data signal output from connector 240 to host 100 is not included. Figure 22 Is when Figure 1 The storage device 200 includes at least one passive filter 260 and 280 for the eye diagram of the data signal output from connector 240 to host 100.

[0186] exist Figure 21 and Figure 22 In the diagram, the horizontal axis represents time, and the vertical axis represents the voltage level of the data signal.

[0187] refer to Figure 1 , Figure 21 and Figure 22 , noticed, Figure 1 The storage device 200 includes at least one passive filter 260 and 280 with an eye opening ratio EO2 greater than 1. Figure 1 The storage device 200 does not include at least one passive filter 260 and 280 with an eye opening ratio EO1. Furthermore, it is noted that the data signal in Figure 21 As shown in part F, the data signal is dispersed, and the data signal is... Figure 22 As shown in part F', the signal is not dispersed. Therefore, when the storage device 200 includes at least one passive filter 260 and 280, the signal integrity output from the storage device 200 can be improved.

[0188] According to an example embodiment, at least one passive filter is disposed on the PCB between the connector and the memory controller, and the at least one passive filter equalizes the signal provided from or supplied to the memory controller. Therefore, the signal integrity of the high-frequency signal output from the memory controller to the host can be improved, and thus, the power consumption of the memory device can be reduced.

[0189] Figure 23 This is a flowchart illustrating a method of operating a storage device according to an example embodiment.

[0190] Reference Figures 1 to 23 In the method of operating the memory device 200, a memory controller 300 and a plurality of non-volatile memory devices 400a to 400k are disposed on the PCB 10 (operation S110). The plurality of non-volatile memory devices 400a to 400k may be distributed on the PCB 10, or the plurality of non-volatile memory devices 400a to 400k may be disposed on the PCB in the form of a multi-stacked chip package.

[0191] A connector 240 with multiple connection terminals is provided in PCB 10 (operation S 120). The memory controller 300 can communicate with the external host 100 through the connector 240.

[0192] Multiple transmission lines 50 are provided on the PCB to electrically connect the memory controller 300 and the non-volatile memory devices 400a to 400k (operation S130).

[0193] At least one passive filter 260 and 280 are provided between the memory controller 300 and the connector 240 in PCB 10 (operation S140). At least one passive filter 260 and 280 can perform equalization on signals provided to or from the memory controller 300.

[0194] At least one passive filter 260 and 280 can be configured by connecting a filter resistor Rf and a filter capacitor Cf in parallel between a first node N21 coupled to the memory controller 300 and a second node N22 coupled to the connector 240 on PCB 10.

[0195] Therefore, at least one passive filter 260 and 280 can improve the signal integrity of the signals exchanged between the storage controller 300 and the host 100.

[0196] Figure 24 This is a block diagram illustrating a storage system according to an example embodiment.

[0197] Reference Figure 24 The storage system 1000 may include a host 1100 and a storage device 1200. The storage device 1200 can be connected to the host 1100 via a connector 1201 including multiple connection terminals and can communicate with the host 1100. The connector 1201 may include, as shown in reference... Figure 1 The aforementioned signal connector and power connector.

[0198] The host 1100 includes an application 1110, a device driver 1120, a host controller 1130, and a buffer RAM 1140. The host controller 1130 includes a command manager 1131, a host direct memory access (DMA) 1132, and a power manager 1133.

[0199] In operation, system-level commands (e.g., write commands) are generated by application 1110 and device driver 1120 of host 1100, and then provided to command manager 1131 of host controller 1130. Command manager 1131 can be used to generate corresponding storage device commands (i.e., corresponding commands or command sets consistent with the protocol implemented by storage system 1000) provided to storage device 1200 using device driver 1120. Commands generated by command manager 1131 can also be provided to host DMA 1132, which sends the commands to storage device 1200 via storage interface 1101.

[0200] Storage device 1200 includes flash memory device 1210, device controller 1230, and buffered random access memory (RAM) 1240. Device controller 1230 may include central processing unit (CPU) 1231, device DMA 1232, flash DMA 1233, command manager 1234, buffer manager 1235, flash translation layer (FTL) 1236, flash manager 1237, and power supply circuitry 1238. Power supply circuitry 1238 may generate an operating voltage based on the power supply voltage VES provided by host 1100.

[0201] Flash memory device 1210, device controller 1230, and buffer RAM 1240 may be disposed on a PCB. The memory device 1200 may also include at least one passive filter 1220 connected between the device controller 1230 and connector 1201. At least one passive filter 1220 may be disposed in the PCB.

[0202] At least one passive filter 1220 can perform equalization on the signals exchanged between the device controller 1230 and the connector 1201, and can improve the signal integrity of the signals. At least one passive filter 1220 may include, as referenced... Figure 8 The filter resistor and filter capacitor are connected in parallel.

[0203] Commands transmitted from host 1100 to storage device 1200 can be provided to device DMA1232 via connector 1201.

[0204] Then, the DMA device 1232 can transmit the received command to the command manager 1234. The command manager 1234 can be used to allocate memory space in the buffer RAM 1240 so as to receive the corresponding write data via the buffer manager 1235. Once the storage device 1200 is ready to receive write data, the command manager 1234 can send a "transfer ready" signal to the host 1100.

[0205] Upon receiving a transmission ready signal, host 1100 transmits write data to storage device 1200. The write data can be sent to storage device 1200 using host DMA 1132 and storage interface 1101. Storage device 1200 can then use device DMA 1232 and buffer manager 1235 to store the received write data in buffer RAM 1240. The write data stored in buffer RAM 1240 can then be provided to flash manager 1237 via flash DMA 1233. Flash manager 1237 can be used to program the write data according to the address of flash memory 1210, which is derived from an address mapping table by flash translation layer 1236.

[0206] Once the data transfer and programming are complete, the storage device 1200 can send a response to the host 1100, notifying the host 1100 that the write command has been successfully executed. Based on the received response signal, the host 1100 indicates to the device driver 1120 and the application 1110 that the command is complete, and thereafter terminates the execution of the operation corresponding to the command.

[0207] As described above, the host 1100 and the storage device 1200 can exchange data, corresponding commands and / or (one or more) control signals (e.g., ready signals and response signals) via data lines (e.g., data lines DIN and DOUT).

[0208] The storage device 1200 includes a passive filter 1220 connected in a PCB between the device controller 1230 and the connector 1201, which can improve the signal integrity of the signal output from the device controller 1230 to the host 1100.

[0209] Various package types or package configurations can be used to package the memory device or memory system according to the example embodiments.

[0210] This disclosure can be applied to various electronic devices, including storage devices.

[0211] The above is a description of exemplary embodiments and should not be construed as limiting them. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the exemplary embodiments without substantially departing from the novel teachings and advantages of this disclosure. Therefore, all such modifications are intended to be included within the scope of this disclosure as defined in the claims.

Claims

1. A storage device, comprising: Multiple non-volatile memory devices are disposed on a printed circuit board; A connector disposed in the printed circuit board, the connector including a plurality of connection terminals, the plurality of connection terminals including a first connection terminal and a second connection terminal; A memory controller, disposed on the printed circuit board, is configured to communicate with an external host and control the plurality of non-volatile memory devices via the plurality of connection terminals; as well as At least one first passive filter is disposed in the printed circuit board and connected between the connector and the memory controller, the at least one first passive filter being configured to perform equalization on any one or any combination of the signal provided to the memory controller and the signal provided from the memory controller. Wherein, the at least one first passive filter includes: A first filter is connected between the memory controller and the first connection terminal, and A second filter is connected between the memory controller and the second connection terminal.

2. The storage device as claimed in claim 1, wherein: The first filter includes a first filter resistor and a first filter capacitor connected in parallel between the memory controller and the first connection terminal; The first filter resistor and the first filter capacitor are connected in parallel between the first node and the second node; The first filter resistor and the first filter capacitor are disposed on the printed circuit board; and The first node is connected to the storage controller, and the second node is connected to the connector.

3. The reservoir device of claim 2, wherein, The first filter resistor and any one or any combination of the first filter capacitor are provided by using at least a portion of the printed circuit board.

4. The storage device as claimed in claim 2, wherein: The first filter capacitor includes a first pad and a second pad. The first pad is connected to the connector in the printed circuit board, and the second pad is spaced apart from the first pad in a vertical direction from the upper surface to the lower surface of the printed circuit board. The first filter resistor includes a vertical conductive pattern that connects the first pad and the second pad in the vertical direction.

5. The reservoir device of claim 4, wherein, The second pad is connected to the memory controller via a conductive pattern.

6. The storage device as claimed in claim 2, wherein: The first filter capacitor includes a first pad and a second pad, the first pad being connected to the connector in the printed circuit board, and the second pad being spaced apart from the first pad in a vertical direction from the upper surface of the printed circuit board to the lower surface of the printed circuit board. and The first filter resistor includes a resistive element connected to the first pad and the second pad via a via formed in the vertical direction, and the resistive element is disposed on the lower surface of the printed circuit board.

7. The reservoir device of claim 6, wherein, The second pad is connected to the memory controller via a conductive pattern.

8. The storage device of claim 6, wherein: The via includes a first via and a second via, the first via connecting the first pad and the resistor element, and the second via connecting the second pad and the resistor element. The first via penetrates the second pad.

9. The storage device as claimed in claim 2, wherein: The storage controller includes a host interface configured to connect to the external host interface; The host interface includes a transmitter configured to send differential signals based on requests from the external host. The first filter is connected between the first pad coupled to the transmitter and the first connection terminal, and The second filter is connected between the second pad coupled to the transmitter and the second connection terminal.

10. The storage device of claim 9, wherein: The second filter includes a second filter resistor and a second filter capacitor connected in parallel between the second pad and the second connection terminal.

11. The storage device of claim 10, wherein: The first connection terminal is connected via a host channel to a resistor and capacitor in the receiver of the external host's storage interface; and The first filter resistor, the first filter capacitor, the resistor in the receiver, and the capacitor constitute a continuous-time linear equalizer.

12. The storage device of claim 1, further comprising: A volatile memory device connected to the memory controller, configured to function as a buffer; A second passive filter is disposed in the printed circuit board and connected between the memory controller and at least one of the plurality of non-volatile memory devices; as well as A third passive filter is disposed in the printed circuit board and connected between the memory controller and the volatile memory device.

13. The reservoir device of claim 12, wherein, The second passive filter and any one or any combination of the third passive filter are provided by using at least a portion of the printed circuit board.

14. The storage device as claimed in claim 1, wherein, The plurality of non-volatile memory devices are disposed on the printed circuit board as multi-stacked chips.

15. The storage device of claim 14, wherein, Each of the plurality of non-volatile memory devices includes: A memory cell array comprising a plurality of memory blocks, each of the plurality of memory blocks comprising a plurality of nonvolatile memory cells coupled to word lines and bit lines; A data input / output circuit configured to receive data to be programmed into the memory cell array from the memory controller via a data transmission line, and to provide data read from the memory cell array to the memory controller via the data transmission line; and A control circuit configured to control the data input / output circuit.

16. The storage device of claim 15, wherein, Any one or any combination of the plurality of memory blocks includes a NAND string, each of the NAND strings comprising a plurality of non-volatile memory cells stacked sequentially on a substrate.

17. A method of operating a storage device, the method comprising: A memory controller and multiple non-volatile memory devices are mounted on a printed circuit board; A connector with multiple connection terminals is provided in the printed circuit board; Data transmission lines electrically connecting the memory controller and the plurality of non-volatile memory devices are provided in the printed circuit board; At least one passive filter is provided on the printed circuit board between the connector and the memory controller; The at least one passive filter is used to perform equalization on any one or any combination of the signals provided to the memory controller and the signals provided from the memory controller; as well as The storage controller communicates with an external host via the connector. The plurality of connection terminals include a first connection terminal and a second connection terminal. Wherein, the at least one passive filter includes: A first filter is connected between the memory controller and the first connection terminal, and A second filter is connected between the memory controller and the second connection terminal.

18. The method of claim 17, in, The first filter includes a first filter resistor and a first filter capacitor connected in parallel between the memory controller and the first connection terminal. The configuration of the at least one passive filter includes: connecting the first filter resistor and the first filter capacitor in parallel between the first node and the second node, and The first filter resistor and the first filter capacitor are disposed in the printed circuit board, the first node is connected to the memory controller, and the second node is connected to the first connection terminal.

19. The method of claim 18, wherein, The first filter resistor and any one or any combination of the first filter capacitor are provided by using at least a portion of the printed circuit board.

20. A storage device comprising: Printed circuit boards; Multiple non-volatile memory devices are disposed on the printed circuit board; A connector disposed in the printed circuit board, the connector comprising a plurality of connection terminals; A memory controller, disposed on the printed circuit board, is configured to communicate with an external host and control the plurality of non-volatile memory devices via the plurality of connection terminals; and At least one passive filter is disposed in the printed circuit board and connected between the connector and the memory controller, the at least one passive filter being configured to perform equalization on any one or any combination of the signal provided to the memory controller and the signal provided from the memory controller. The at least one passive filter includes a first filter resistor and a first filter capacitor connected in parallel between the first node and the second node, and a second filter resistor and a second filter capacitor connected in parallel between the third node and the fourth node. The first filter resistor and the first filter capacitor are disposed in the printed circuit board, and the first node and the third node are coupled to the memory controller, and the second node and the fourth node are coupled to the connector.

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