Impedance matching circuit, impedance matching method, and semiconductor memory

Abstract

The present disclosure provides an impedance matching circuit, an impedance matching method and a semiconductor memory, the circuit comprising a driving module, a calibration module, a digital logic module, a receiving module and a first resistor, the output end of the driving module being connected with the receiving module, and the output end of the calibration module being connected with the first resistor; wherein the calibration module is configured to perform calibration processing in cooperation with the driving module according to the impedance values of the first resistor and the receiving module, and determine a plurality of calibration parameters obtained at different output level values; the digital logic module is configured to receive the plurality of calibration parameters and determine target calibration parameters of each of at least one transistor group in the driving module; and the driving module is configured to receive the target calibration parameters, adjust the impedance of the at least one transistor group according to the target calibration parameters, so that the impedance values of the driving module and the receiving module have an impedance matching relationship at different output level values. In this way, the output linearity is ensured while the signal integrity is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to an impedance matching circuit, an impedance matching method, and a semiconductor memory. Background Technology

[0002] With the continuous development of semiconductor technology, people have placed increasingly higher demands on data transmission speed when manufacturing and using devices such as computers. To achieve faster data transmission speeds, a series of devices, such as memory capable of double data rate (DDR) transmission, have emerged. However, when using signal modulation based on non-return-to-zero (NRZ) mode, it is difficult to meet the requirements for high-capacity and high-speed data transmission.

[0003] In recent years, pulse amplitude modulation (PAM) methods have been actively researched in some transmitter circuits to explore alternatives suitable for high-capacity and high-speed data transmission. However, existing PAM methods still have shortcomings, especially due to the influence of factors such as process angle, temperature, and voltage, which leads to inconsistent transmitter output impedance and seriously affects signal integrity. Summary of the Invention

[0004] This disclosure provides an impedance matching circuit, an impedance matching method, and a semiconductor memory that can improve signal integrity while ensuring output linearity.

[0005] In a first aspect, embodiments of this disclosure provide an impedance matching circuit, which includes a driving module, a calibration module, a digital logic module, a receiving module, and a first resistor. The output terminal of the driving module is connected to the receiving module, and the output terminal of the calibration module is connected to the first resistor; wherein:

[0006] The calibration module is used to perform calibration processing in conjunction with the drive module based on the impedance values ​​of the first resistor and the receiving module, and to determine multiple calibration parameters obtained under different output level values.

[0007] A digital logic module is used to receive multiple calibration parameters and determine the target calibration parameters for each of at least one transistor group in the drive module.

[0008] The driving module is used to receive target calibration parameters and adjust the impedance of at least one transistor group according to the target calibration parameters, so that the impedance value of the driving module and the impedance value of the receiving module have an impedance matching relationship under different output level values.

[0009] In some embodiments, the driving module includes a first pull-up module, a second pull-up module, and a pull-down module, and the calibration module includes a third pull-up module and a fourth pull-up module, wherein: one end of the first pull-up module and one end of the third pull-up module are both connected to a first power supply; one end of the second pull-up module and one end of the fourth pull-up module are both connected to a second power supply; one end of the pull-down module is grounded; the other ends of the first pull-up module, the second pull-up module, and the pull-down module are all connected to the input terminal of the receiving module, and the output terminal of the receiving module is grounded; the other ends of the third pull-up module and the fourth pull-up module are both connected to one end of a first resistor, and the other end of the first resistor is grounded.

[0010] In some embodiments, the transistors in the first pull-up module and the third pull-up module are NMOS transistors; the transistors in the second pull-up module and the fourth pull-up module are PMOS transistors; and the transistors in the pull-down module are NMOS transistors.

[0011] In some embodiments, the value of the first power supply is lower than the value of the second power supply.

[0012] In some embodiments, the driving module is further configured to output a target data signal based on n-level pulse amplitude modulation (PAMn); where n is an integer greater than or equal to 2.

[0013] In some embodiments, the calibration module is further configured to, when the target data signal corresponds to the maximum level value, perform PMOS transistor calibration in the second pull-up module and the fourth pull-up module in cooperation with the driving module based on the impedance values ​​of the first resistor and the receiving module, and then perform NMOS transistor calibration in the first pull-up module and the third pull-up module in cooperation with the driving module based on the calibration parameters corresponding to the second pull-up module and the fourth pull-up module.

[0014] In some embodiments, when n equals 4, the target data signal includes at least a first level value, a second level value, and a third level value; wherein: the calibration module is used to, when the output level value is the first level value, perform a first calibration process in conjunction with the driving module based on the impedance values ​​of the first resistor and the receiving module, to determine the first calibration parameters corresponding to the first pull-up module and the third pull-up module; and, when the receiving module is turned off and the first calibration parameters corresponding to the first pull-up module and the third pull-up module are fixed, perform a second calibration process in conjunction with the driving module to determine the second calibration parameters corresponding to the pull-down module; or, the calibration module is used to, when the output level value is the second level value, perform a first calibration process in conjunction with the driving module based on the impedance values ​​of the first resistor and the receiving module, to determine the third calibration parameters corresponding to the second pull-up module and the fourth calibration parameters corresponding to the fourth pull-up module. The calibration module is configured to: determine the fifth calibration parameter corresponding to the first pull-up module; and determine the sixth calibration parameter corresponding to the first pull-up module and the seventh calibration parameter corresponding to the third pull-up module, based on the impedance values ​​of the first resistor and the receiving module, when the output level is a third level value; and determine the eighth calibration parameter corresponding to the pull-down module, based on the second preset value, when the first preset value is fixed to the second preset value, and determine the eighth calibration parameter corresponding to the pull-down module, when the first preset value is related to the third and fourth calibration parameters, and the second preset value is related to the sixth and seventh calibration parameters.

[0015] In some embodiments, the impedance matching circuit further includes a first processing module, a second processing module, and a third processing module; wherein, the first processing module includes a first comparator and a first counter, used to receive a reference voltage and a first output voltage through the first comparator, and output a first comparison result of the reference voltage and the first output voltage; and to receive the first comparison result and a calibration clock signal through the first counter, and control the first counter to perform a counting operation when the calibration clock signal indicates that it is in calibration mode and the first comparison result meets a preset condition, and determine the first counting result, wherein the first counting result is used to determine the calibration parameters corresponding to the first pull-up module or the second pull-up module at different output level values; the second processing module includes a second comparator and a second counter, used to receive a reference voltage and a first output voltage through the second comparator, and output a second comparison result of the reference voltage and the first output voltage; and to receive the second comparison result and a calibration clock signal through the second ... when the calibration clock signal indicates that it When the quasi-clock signal indicates that the system is in calibration mode and the second comparison result meets the preset conditions, the system controls the second counter to perform a counting operation and determines the second counting result. The second counting result is used to determine the calibration parameters corresponding to the pull-down module at different output level values. The third processing module includes a third comparator and a third counter. It receives a reference voltage and a second output voltage through the third comparator and outputs a third comparison result between the reference voltage and the second output voltage. It also receives the third comparison result and a calibration clock signal through the third counter. When the calibration clock signal indicates that the system is in calibration mode and the third comparison result meets the preset conditions, the system controls the third counter to perform a counting operation and determines the third counting result. The third counting result is used to determine the calibration parameters corresponding to the third pull-up module or the fourth pull-up module at different output level values. The first output voltage represents the voltage value at the output terminal of the drive module, and the second output voltage represents the voltage value at the output terminal of the calibration module.

[0016] In some embodiments, the plurality of calibration parameters are composed of a first calibration parameter, a second calibration parameter, a third calibration parameter, a fourth calibration parameter, a fifth calibration parameter, a sixth calibration parameter, a seventh calibration parameter, and an eighth calibration parameter; wherein: the digital logic module is further configured to acquire the master calibration parameters of at least one transistor group, and determine the target calibration parameters of at least one transistor group based on the first calibration parameter, the second calibration parameter, the third calibration parameter, the fourth calibration parameter, the fifth calibration parameter, the sixth calibration parameter, the seventh calibration parameter, the eighth calibration parameter, and the master calibration parameters of at least one transistor group.

[0017] In some embodiments, the first pull-up module includes at least one first type of transistor group, the second pull-up module includes at least one second type of transistor group, the third pull-up module includes at least one third type of transistor group, the fourth pull-up module includes at least one fourth type of transistor group, and the pull-down module includes at least one fifth type of transistor group; wherein: in the first pull-up module, the first type of transistor group includes multiple NMOS transistors; in the second pull-up module, the second type of transistor group includes multiple PMOS transistors; in the third pull-up module, the third type of transistor group includes multiple NMOS transistors; in the fourth pull-up module, the fourth type of transistor group includes multiple PMOS transistors; and in the pull-down module, the fifth type of transistor group includes multiple NMOS transistors.

[0018] In some embodiments, at least one first type of transistor group includes a first transistor group, a second transistor group, and a third transistor group; at least one second type of transistor group includes a fourth transistor group; and at least one fifth type of transistor group includes a fifth transistor group and a sixth transistor group. Specifically: in the first pull-up module, the first transistor group includes multiple NMOS transistors; the second transistor group includes multiple NMOS transistors; and the third transistor group includes multiple NMOS transistors. In the second pull-up module, the fourth transistor group includes multiple PMOS transistors. In the pull-down module, the fifth transistor group includes multiple NMOS transistors; and the sixth transistor group includes multiple NMOS transistors.

[0019] In some embodiments, the first transistor group includes a first main transistor and at least one first auxiliary transistor; the second transistor group includes a second main transistor and at least one second auxiliary transistor; the third transistor group includes a third main transistor and at least one third auxiliary transistor; the fourth transistor group includes a fourth main transistor and at least one fourth auxiliary transistor; the fifth transistor group includes a fifth main transistor and at least one fifth auxiliary transistor; and the sixth transistor group includes a sixth main transistor and at least one sixth auxiliary transistor; wherein: at least one first auxiliary transistor is impedance-adjusted based on a first target calibration parameter; at least one second auxiliary transistor is impedance-adjusted based on a second target calibration parameter; at least one third auxiliary transistor is impedance-adjusted based on a third target calibration parameter; at least one fourth auxiliary transistor is impedance-adjusted based on a fourth target calibration parameter; at least one fifth auxiliary transistor is impedance-adjusted based on a fifth target calibration parameter; and at least one sixth auxiliary transistor is impedance-adjusted based on a sixth target calibration parameter.

[0020] In some embodiments, the digital logic module is configured to: determine a first target calibration parameter based on a first calibration parameter, a sixth calibration parameter, a seventh calibration parameter, and a master calibration parameter corresponding to a first master transistor; determine a second target calibration parameter based on the first calibration parameter, a fifth calibration parameter, a sixth calibration parameter, a seventh calibration parameter, and a master calibration parameter corresponding to a second master transistor; determine a third target calibration parameter based on the first calibration parameter, the fifth calibration parameter, and a master calibration parameter corresponding to a third master transistor; determine a fourth target calibration parameter based on the third calibration parameter, a fourth calibration parameter, and a master calibration parameter corresponding to a fourth master transistor; determine a fifth target calibration parameter based on an eighth calibration parameter and a master calibration parameter corresponding to a fifth master transistor; and determine a sixth target calibration parameter based on the second calibration parameter, the eighth calibration parameter, and a master calibration parameter corresponding to a sixth master transistor.

[0021] In some embodiments, the drain terminals of the first, second, and third main transistors are all connected to a first power supply. The gate terminal of the first main transistor is used to receive a first driving signal, the gate terminal of the second main transistor is used to receive a second driving signal, and the gate terminal of the third main transistor is used to receive a third driving signal. The source terminals of the first, second, and third main transistors are all connected to an output node. The source terminal of the fourth main transistor is connected to a second power supply, the gate terminal of the fourth main transistor is used to receive a fourth driving signal, and the drain terminal of the fourth main transistor is connected to an output node. The source terminals of the fifth and sixth main transistors are both connected to ground. The gate terminal of the fifth main transistor is used to receive a fifth driving signal, the gate terminal of the sixth main transistor is used to receive a sixth driving signal, and the drain terminals of the fifth and sixth main transistors are both connected to an output node. The output node is used to output a target data signal based on PAMn, and the first, second, third, fourth, fifth, and sixth driving signals are determined by logical operations based on the most significant bit and least significant bit signals included in the input signal.

[0022] In some embodiments, the first driving signal is the least significant bit signal; the second driving signal is obtained by performing an OR logic operation based on the most significant bit signal and the least significant bit signal; the third driving signal is the most significant bit signal; the fourth driving signal is obtained by performing an OR logic operation based on the NOT signals of the most significant bit signal and the least significant bit signal; the fifth driving signal is obtained by performing a NOT logic operation based on the first driving signal; and the sixth driving signal is obtained by performing a NOT logic operation based on the second driving signal.

[0023] In some embodiments, when n equals 4, the target data signal includes a first level value, a second level value, a third level value, and a fourth level value; wherein: when the input signal is 11, the first main transistor, the second main transistor, and the third main transistor are in the on state, making the level of the target data signal the first level value; when the input signal is 01, the first main transistor, the second main transistor, and the fourth main transistor are in the on state, making the level of the target data signal the second level value; when the input signal is 10, the second main transistor, the third main transistor, and the fifth main transistor are in the on state, making the level of the target data signal the third level value; when the input signal is 00, the fifth main transistor and the sixth main transistor are in the on state, making the level of the target data signal the fourth level value.

[0024] In some embodiments, the first level value is less than the second level value, the third level value is less than the first level value, and the fourth level value is less than the third level value.

[0025] Secondly, embodiments of this disclosure provide an impedance matching method, the method comprising:

[0026] Determine the impedance values ​​of the first resistor connected to the calibration module and the receiver module connected to the drive module;

[0027] Based on the impedance values ​​of the first resistor and the receiving module, the calibration module and the driving module work together to perform calibration processing and determine multiple calibration parameters obtained at different output level values.

[0028] Based on multiple calibration parameters, the target calibration parameters for each of at least one transistor group in the drive module are determined by the digital logic module.

[0029] The impedance of at least one transistor group in the drive module is adjusted according to the target calibration parameters so that the impedance value of the drive module and the impedance value of the receiver module have an impedance matching relationship under different output level values.

[0030] Thirdly, embodiments of this disclosure provide a semiconductor memory that includes at least the impedance matching circuit described in the first aspect.

[0031] In some embodiments, the semiconductor memory includes a transmitter circuit and a receiver circuit; wherein: the transmitter circuit includes a driving module for outputting a target data signal based on PAMn; the receiver circuit includes a receiving module for receiving the target data signal transmitted from the transmitter circuit through a channel; wherein the impedance value of the receiver circuit and the impedance value of the transmitter circuit have an impedance matching relationship.

[0032] This disclosure provides an impedance matching circuit, an impedance matching method, and a semiconductor memory. The impedance matching circuit includes a driving module, a calibration module, a digital logic module, a receiving module, and a first resistor. The output terminal of the driving module is connected to the receiving module, and the output terminal of the calibration module is connected to the first resistor. The calibration module, based on the impedance values ​​of the first resistor and the receiving module, performs calibration processing in conjunction with the driving module to determine multiple calibration parameters obtained at different output level values. The digital logic module receives the multiple calibration parameters and determines target calibration parameters for each of at least one transistor group in the driving module. The driving module receives the target calibration parameters and adjusts the impedance of at least one transistor group according to the target calibration parameters, so that there is an impedance matching relationship between the impedance values ​​of the driving module and the receiving module at different output level values. In this way, because the transistors in the driver module are of different types, the driver module can be compatible with the advantages of both NMOS and PMOS transistors, avoiding the shortcomings of using only NMOS or PMOS transistors as pull-up transistors. Moreover, by adjusting the impedance of at least one group of transistors in the driver module through the calibration module and the digital logic module, an impedance matching relationship can be achieved between the impedance value of the driver module and the impedance value of the receiving module under different output level values. This not only saves the overall circuit area, but also improves signal integrity and reduces power consumption while ensuring output linearity, thereby effectively improving data transmission performance. Attached Figure Description

[0033] Figure 1 A schematic diagram illustrating the basic principle of defining output linearity;

[0034] Figure 2 This is a schematic diagram illustrating the basic principle of impedance matching.

[0035] Figure 3 A schematic diagram of the composition structure of an impedance matching circuit provided in an embodiment of this disclosure;

[0036] Figure 4 A schematic diagram of the composition structure of another impedance matching circuit provided in an embodiment of this disclosure;

[0037] Figure 5 A schematic diagram of the composition structure of a driver module provided in an embodiment of this disclosure;

[0038] Figure 6 This is a schematic diagram of the composition structure of a first transistor group provided in an embodiment of the present disclosure;

[0039] Figure 7 This is a schematic diagram of the composition structure of another first transistor group provided in an embodiment of the present disclosure;

[0040] Figure 8A schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of this disclosure;

[0041] Figure 9 A schematic diagram of the composition structure of another semiconductor memory provided in an embodiment of this disclosure;

[0042] Figure 10 This is a comparative schematic diagram of eye diagram structures under three process angles provided in an embodiment of the present disclosure;

[0043] Figure 11 A detailed structural schematic diagram of an impedance matching circuit provided in an embodiment of this disclosure;

[0044] Figure 12 This is a schematic flowchart of an impedance matching method provided in an embodiment of the present disclosure. Detailed Implementation

[0045] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining the relevant applications and are not intended to limit the applications. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0047] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0048] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0049] It should also be noted that the high and low levels used for signals in the embodiments of this disclosure refer to the logic levels of the signals. A signal having a high level is different from having a low level. For example, a high level may correspond to a signal having a first voltage, while a low level may correspond to a signal having a second voltage. In some embodiments, the first voltage is greater than the second voltage. Furthermore, the logic level of a signal may be different from or opposite to the described logic level. For example, a signal described as having a logic "high" level may alternatively have a logic "low" level, and a signal described as having a logic "low" level may alternatively have a logic "high" level.

[0050] Understandably, in Dynamic Random Access Memory (DRAM), transmitter circuits often use non-return-to-zero (NRZ) signals for transmission, and their signal integrity decreases significantly with increasing speed. The requirements for equalization techniques and high-speed clocks are becoming increasingly stringent. Therefore, this disclosure introduces four-level pulse amplitude modulation (PAM4) to improve the efficiency of the signal spectrum.

[0051] In related technologies, PAM4-based transmitter circuits are mostly used in serializer-deserializer (SERDe) circuits, which are often differential circuits. The main difference between SERDe circuits and low-power (LP) DDR interface circuits is that SERDe circuits do not transmit a separate clock signal and can operate at a very high speed. Therefore, the output signal of a PAM4-based transmitter circuit should have good linearity and signal integrity to ensure that the receiver can recognize the data. For example, Figure 1 A diagram illustrating how output linearity is defined is provided. For example... Figure 1 As shown, the four level values ​​of the output data signal can be mapped to two input signals respectively; for example, the highest level value (represented by V1) can be mapped to "11", the lowest level value (represented by V4) can be mapped to "00", and the two middle level values ​​(represented by V2 and V3) can be mapped to "10" and "01". The interval between two adjacent level values ​​is represented by a, b, and c respectively, and the linearity is defined as follows:

[0052]

[0053] Furthermore, due to factors such as process angle, temperature, and voltage, the output impedance of the transmitter circuit is not constant. Therefore, a zero-quantity (ZQ) calibration circuit is needed to perform impedance calibration to ensure signal integrity. For example, Figure 2 A schematic diagram illustrating the basic principle of impedance matching is provided. For example... Figure 2 As shown, the impedance value of region 1 can be Z1, and the impedance value of region 2 can be Z2. Impedance matching between region 1 and region 2 can be achieved through Z1 and Z2. The definitions of reflection coefficient and transmission coefficient are as follows:

[0054]

[0055]

[0056] Where Γ represents the reflection coefficient, T represents the transmission coefficient; V reflect Represents the reflected voltage, V trans This represents the voltage actually transferred to Z2, V. inc This represents the voltage originally emitted by Z1. Here, if there is an impedance mismatch between Z1 and Z2, then a reflected voltage V will occur. reflect .

[0057] In simple terms, the main difference between the PAM4-based ZQ calibration circuit and the traditional NRZ ZQ calibration circuit lies in the need to ensure impedance matching at different output levels. That is, achieving impedance matching while maintaining output linearity.

[0058] Based on this, this disclosure provides an impedance matching circuit, which includes a driving module, a calibration module, a digital logic module, a receiving module, and a first resistor. The output terminal of the driving module is connected to the receiving module, and the output terminal of the calibration module is connected to the first resistor. Specifically: the calibration module is used to perform calibration processing in conjunction with the driving module based on the impedance values ​​of the first resistor and the receiving module, determining multiple calibration parameters obtained at different output level values; the digital logic module is used to receive the multiple calibration parameters and determine the target calibration parameters for each of at least one transistor group in the driving module; the driving module is used to receive the target calibration parameters and adjust the impedance of at least one transistor group according to the target calibration parameters, so that there is an impedance matching relationship between the impedance values ​​of the driving module and the receiving module at different output level values. In this way, because the transistors in the driver module are of different types, the driver module can be compatible with the advantages of both NMOS and PMOS transistors, avoiding the shortcomings of using only NMOS or PMOS transistors as pull-up transistors. Moreover, by adjusting the impedance of at least one group of transistors in the driver module through the calibration module and the digital logic module, an impedance matching relationship can be achieved between the impedance value of the driver module and the impedance value of the receiving module under different output level values. This not only saves the overall circuit area, but also improves signal integrity and reduces power consumption while ensuring output linearity, thereby effectively improving data transmission performance.

[0059] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0060] In one embodiment of this disclosure, see Figure 3 This illustration shows a schematic diagram of the composition structure of an impedance matching circuit provided in an embodiment of this disclosure. Figure 3 As shown, the impedance matching circuit 30 may include a driving module 301, a calibration module 302, a digital logic module 303, a receiving module 304, and a first resistor R1. The output terminal of the driving module 301 is connected to the receiving module 304, and the output terminal of the calibration module 302 is connected to the first resistor R1; wherein:

[0061] The calibration module 302 is used to perform calibration processing in conjunction with the drive module based on the impedance values ​​of the first resistor and the receiving module, and to determine multiple calibration parameters obtained under different output level values.

[0062] Digital logic module 303 is used to receive multiple calibration parameters and determine the target calibration parameters for each of at least one transistor group in drive module 301.

[0063] The driving module 301 is used to receive target calibration parameters and adjust the impedance of at least one transistor group according to the target calibration parameters, so that the impedance value of the driving module 301 and the impedance value of the receiving module 304 have an impedance matching relationship under different output level values.

[0064] It should be noted that, in this embodiment, the impedance matching circuit 30 can be applied not only to PAM4-based circuits but also to PAM3-based circuits, and is even compatible with traditional transmitter circuits based on NRZ signals. In other words, the impedance matching circuit 30 described in this embodiment has good compatibility and can be applied to various circuit scenarios such as NRZ, PAM3, and PAM4.

[0065] Understandably, NRZ is a line code used to represent 0 and 1 bits. A positive voltage represents logic 1, and a negative voltage represents logic 0. Because NRZ signals only have two levels, they can also be called PAM2-based signals. PAM4 is a line code that uses pulse amplitude modulation (PAM). PAM4 signals have four levels, corresponding to logic bits 00, 01, 10, and 11. In other words, each symbol in a PAM4 code consists of two bits, corresponding to a voltage level, i.e., amplitude. Bits per second (bps) represents the total number of 0 or 1 bits transmitted per second. Baud rate represents the number of symbols transmitted per second. For NRZ signals, the symbol rate and bit rate are the same, as are the baud rate and bits per second; however, for PAM4 signals, they are different. Specifically, the number of symbols transmitted per second (baud rate) is half the number of bits transmitted per second. Thus, compared to traditional NRZ signals, PAM4 allows twice the information of NRZ signals to be transmitted per symbol period; therefore, at the same code rate, the baud rate (also known as the symbol rate) of PAM4 is only half that of NRZ signals, significantly reducing signal loss in PAM4-based transmission channels. Based on this, the following description focuses on PAM4 as the primary application scenario, but this disclosure is not limited to this specific application scenario.

[0066] It should also be noted that, in the embodiments disclosed herein, in Figure 3 Based on the impedance matching circuit 30 shown, see... Figure 4 The drive module 301 may include a first pull-up module 311, a second pull-up module 312, and a pull-down module 313, and the calibration module 302 may include a third pull-up module 321 and a fourth pull-up module 322, wherein:

[0067] One end of the first pull-up module 311 and one end of the third pull-up module 321 are both connected to the first power supply.

[0068] One end of the second pull-up module 312 and one end of the fourth pull-up module 322 are both connected to the second power supply.

[0069] One end of the pull-down module 313 is grounded, and the other ends of the first pull-up module 311, the second pull-up module 312, and the pull-down module 313 are all connected to the input end of the receiving module 304. The output end of the receiving module 304 is grounded.

[0070] The other end of the third pull-up module 321 and the other end of the fourth pull-up module 322 are both connected to one end of the first resistor R1, and the other end of the first resistor is grounded.

[0071] In this embodiment of the disclosure, for the driving module 301, the transistors included in the first pull-up module 311 and the second pull-up module 312 can be referred to as pull-up transistors, and the transistors included in the pull-down module 313 can be referred to as pull-down transistors. For the calibration module 302, the transistors included in the third pull-up module 321 and the fourth pull-up module 322 can also be referred to as pull-up transistors. The transistor types of the pull-up transistors can include PMOS transistors and NMOS transistors, and the transistor type of the pull-down transistors can be NMOS transistors.

[0072] In other words, the two pull-up modules (first pull-up module 311 and second pull-up module 312) in the driving module 301 have different transistor types, and the two pull-up modules (third pull-up module 321 and fourth pull-up module 322) in the calibration module 302 also have different transistor types. In some embodiments, the transistors in the first pull-up module 311 and the third pull-up module 321 are NMOS transistors, and the transistors in the second pull-up module 312 and the fourth pull-up module 322 are PMOS transistors; or, the transistors in the first pull-up module 311 and the third pull-up module 321 are PMOS transistors, and the transistors in the second pull-up module 312 and the fourth pull-up module 322 are NMOS transistors. This allows the driving module 301 to be compatible with the advantages of both PMOS and NMOS transistors in terms of pull-up, avoiding the shortcomings of using only NMOS or PMOS transistors as pull-up transistors.

[0073] Furthermore, the first power supply connected to the first pull-up module 311 and the third pull-up module 321 is different from the second power supply connected to the second pull-up module 312 and the fourth pull-up module 322. In some embodiments, when the transistors in the first pull-up module 311 and the third pull-up module 321 are NMOS transistors and the transistors in the second pull-up module 312 and the fourth pull-up module 322 are PMOS transistors, the value of the first power supply is lower than the value of the second power supply.

[0074] In this embodiment, the power supply voltage of the PMOS transistor is higher than that of the NMOS transistor. Therefore, if the transistors in the first pull-up module 311 and the third pull-up module 321 are NMOS transistors, and the transistors in the second pull-up module 312 and the fourth pull-up module 322 are PMOS transistors, then it can be determined that the value of the first power supply is lower than the value of the second power supply; otherwise, if the transistors in the first pull-up module 311 and the third pull-up module 321 are PMOS transistors, and the transistors in the second pull-up module 312 and the fourth pull-up module 322 are NMOS transistors, then it can be determined that the value of the first power supply is higher than the value of the second power supply.

[0075] Understandably, since the power supply voltage of a PMOS transistor is higher than that of an NMOS transistor, the relatively higher power supply voltage of a PMOS transistor allows for a larger signal swing, thus reducing the demands on the receiver. Conversely, the lower power supply voltage of an NMOS transistor results in a smaller output load capacitance, better linearity, and lower power consumption. Therefore, for the impedance matching circuit 30 of this embodiment, since the pull-up circuit of the impedance matching circuit 30 includes both an NMOS transistor and a PMOS transistor, on the one hand, compared with related technologies where the pull-up circuit only includes an NMOS transistor, it can increase the signal swing, thereby reducing the demands on the receiver; on the other hand, compared with related technologies where the pull-up circuit only includes a PMOS transistor, it has a smaller output load capacitance, thus offering advantages in signal integrity, linearity, and power consumption.

[0076] In this embodiment, assuming that the transistors in the first pull-up module 311 and the third pull-up module 321 are NMOS transistors, and the transistors in the second pull-up module 312 and the fourth pull-up module 322 are PMOS transistors, then the first power supply can be V DDQ This indicates that the second power source can be V. CC It should be noted that, unless otherwise specified, the transistors in the first pull-up module 311 and the third pull-up module 321 will be NMOS transistors, the transistors in the second pull-up module 312 and the fourth pull-up module 322 will be PMOS transistors, and the transistors in the pull-down module will be NMOS transistors for the following detailed explanation of the technical solution.

[0077] It is also understandable that the driving module 301 can output target data signals with multiple levels, and that there is an impedance matching relationship between the impedance value of the driving module and the impedance value of the receiving module at different output level values. In some embodiments, the driving module 301 is also used to output target data signals based on PAMn; where n is an integer greater than or equal to 2.

[0078] It should be noted that in this embodiment, if n equals 4, the target data signal may include four output level values, such as 0.45V, 0.3V, 0.15V, and 0V. Among these four output level values, there is definitely a maximum level value (such as 0.45V). The maximum level value based on the PAM4 output can be provided by using a combination of PMOS and NMOS transistors as pull-up transistors, while the other relatively lower level values ​​are provided by using NMOS transistors as pull-up transistors.

[0079] Thus, for the maximum voltage level, both the PMOS and NMOS transistors in the pull-up circuit need to be calibrated. To save overall circuit area, in some embodiments, the calibration module 302 is also used to, when the target data signal corresponds to the maximum voltage level, calibrate the PMOS transistors in the second and fourth pull-up modules in conjunction with the driving module based on the impedance values ​​of the first resistor and the receiving module, and then calibrate the NMOS transistors in the first and third pull-up modules in conjunction with the driving module based on the calibration parameters corresponding to the second and fourth pull-up modules.

[0080] In other words, in this embodiment, the PMOS transistor needs to be calibrated first at the highest voltage level, and then the NMOS transistor needs to be calibrated. The reason is that calibrating the NMOS transistor first requires a smaller impedance value, while calibrating the PMOS transistor first requires a larger impedance value; since the smaller the impedance value, the larger the required size, this embodiment calibrates the PMOS transistor first and then the NMOS transistor in order to save overall circuit area.

[0081] Furthermore, regarding the calculation of multiple calibration parameters obtained under different output level values, in some embodiments, when n equals 4, the target data signal includes at least a first level value, a second level value, and a third level value; wherein:

[0082] The calibration module 302 is used to perform a first calibration process in conjunction with the driving module, based on the impedance values ​​of the first resistor and the receiving module, when the output level is a first level value, to determine the first calibration parameters corresponding to the first pull-up module and the third pull-up module; and to perform a second calibration process in conjunction with the driving module, when the receiving module is turned off and the first calibration parameters corresponding to the first pull-up module and the third pull-up module are fixed, to determine the second calibration parameters corresponding to the pull-down module; or...

[0083] The calibration module 302 is used to perform a first calibration process in conjunction with the drive module, based on the impedance values ​​of the first resistor and the receiving module, when the output level is a second level value, to determine the third calibration parameter corresponding to the second pull-up module and the fourth calibration parameter corresponding to the fourth pull-up module; and to perform a second calibration process in conjunction with the drive module, when the calibration parameters corresponding to the second and fourth pull-up modules are fixed at a first preset value, to determine the fifth calibration parameter corresponding to the first pull-up module; or...

[0084] The calibration module 302 is used to perform a first calibration process in conjunction with the driving module when the output level value is the third level value, based on the impedance values ​​of the first resistor and the receiving module, to determine the sixth calibration parameter corresponding to the first pull-up module and the seventh calibration parameter corresponding to the third pull-up module; and to perform a second calibration process in conjunction with the driving module when the calibration parameters corresponding to the first pull-up module and the third pull-up module are fixed at the second preset value, to determine the eighth calibration parameter corresponding to the pull-down module.

[0085] Among them, the first preset value is related to the third and fourth calibration parameters, and the second preset value is related to the sixth and seventh calibration parameters.

[0086] It should be noted that, in this embodiment, the first calibration parameter can be represented by C0, the second calibration parameter by C1, the third calibration parameter by C2, the fourth calibration parameter by C3, the fifth calibration parameter by C4, the sixth calibration parameter by C5, the seventh calibration parameter by C6, and the eighth calibration parameter by C7. Furthermore, in this embodiment, the first preset value can be set to... The second preset value can be set to

[0087] It should also be noted that, in this embodiment of the disclosure, the first voltage level is equal to 1 / 2V. DDQ The second voltage level is equal to 3 / 4V. DDQ The first voltage level is equal to 1 / 4V. DDQ For example, suppose V DDQ If the voltage is 0.6V, then the first voltage level is 0.3V, the second voltage level is 0.45V, and the third voltage level is 0.15V.

[0088] Specifically, when the output level is 1 / 2V DDQ In this case, the impedance value Rx of the first resistor R1 and the receiver module 304 are equal, and both are equal to Z0. In this situation, firstly, the first calibration loop is processed in conjunction with the driver module 301 to determine the first calibration parameter C0 corresponding to the first pull-up module 311 and the third pull-up module 321; then, the receiver module 304 is turned off, and C0 is further used in conjunction with the driver module 301 to process the second calibration loop, which determines the second calibration parameter C1 corresponding to the pull-down module 313 (note that the receiver module 304 is in the off state at this time). The output level is 3 / 4V. DDQIn this case, the impedance value Rx of the first resistor R1 differs from that of the receiving module 304. In this situation, the first resistor R1 equals Z0, but Rx equals Z0 + Δ1. Firstly, the first calibration loop is processed in conjunction with the driving module 301. At this time, only the PMOS transistor in the pull-up transistor is turned on, allowing the determination of the third calibration parameter C2 corresponding to the second pull-up module 312 and the fourth calibration parameter C3 corresponding to the fourth pull-up module 322. Afterwards, the calibration parameter corresponding to the PMOS transistor is fixed as follows: By further processing the second calibration loop in conjunction with the driver module 301, the fifth calibration parameter C4 corresponding to the first pull-up module 311 can be determined. The output level is 1 / 4V. DDQ In this case, the impedance value Rx of the first resistor R1 and the receiver module 304 are also different. In this case, the first resistor R1 equals Z0, but Rx equals Z0-Δ2. Firstly, the first calibration loop is processed in conjunction with the driver module 301. At this time, only the NMOS transistor in the pull-up transistor is turned on, and the sixth calibration parameter C5 corresponding to the first pull-up module 311 and the seventh calibration parameter C6 corresponding to the third pull-up module 321 can be determined. Then, the calibration parameter corresponding to the NMOS transistor is fixed as follows: Further processing in conjunction with the driver module 301 is performed in the second calibration loop to determine the eighth calibration parameter C7 corresponding to the pull-down module 313. Here, Δ1 and Δ2 are the resistance changes of the MOSFET under different drain voltages, and their specific values ​​are set according to the actual situation, without any limitations.

[0089] Thus, based on the C0 to C7 obtained from the calibration, impedance matching can be maintained at different output level values ​​while ensuring good output linearity.

[0090] It is also understood that, in the embodiments of this disclosure, in Figure 3 Based on the impedance matching circuit 30 shown, see... Figure 4 The impedance matching circuit 30 may further include a first processing module 305, a second processing module 306, and a third processing module 307; wherein,

[0091] The first processing module 305 may include a first comparator a1 and a first counter b1, for receiving a reference voltage and a first output voltage through the first comparator a1, and outputting a first comparison result between the reference voltage and the first output voltage; and for receiving the first comparison result and a calibration clock signal through the first counter b1, controlling the first counter to perform a counting operation when the calibration clock signal indicates that it is in calibration mode and the first comparison result meets a preset condition, and determining a first counting result, wherein the first counting result is used to determine the calibration parameters corresponding to the first pull-up module 311 or the second pull-up module 312 under different output level values;

[0092] The second processing module 306 may include a second comparator a2 and a second counter b2, for receiving a reference voltage and a first output voltage through the second comparator a2, and outputting a second comparison result between the reference voltage and the first output voltage; and for receiving the second comparison result and a calibration clock signal through the second counter b2, controlling the second counter to perform a counting operation when the calibration clock signal indicates that it is in calibration mode and the second comparison result meets a preset condition, and determining the second counting result, wherein the second counting result is used to determine the calibration parameters corresponding to the pull-down module 313 under different output level values;

[0093] The third processing module 307 may include a third comparator a3 and a third counter b3, for receiving a reference voltage and a second output voltage through the third comparator a3, and outputting a third comparison result between the reference voltage and the second output voltage; and for receiving the third comparison result and a calibration clock signal through the third counter b3, controlling the third counter to perform a counting operation when the calibration clock signal indicates that it is in calibration mode and the third comparison result meets the preset conditions, and determining the third counting result, wherein the third counting result is used to determine the calibration parameters corresponding to the third pull-up module 321 or the fourth pull-up module 322 under different output level values;

[0094] Wherein, the first output voltage represents the voltage value at the output terminal of the drive module 301, and the second output voltage represents the voltage value at the output terminal of the calibration module 302.

[0095] It should be noted that, in the embodiments of this disclosure, the reference voltage is represented by V. ref This indicates that the calibration clock signal uses CLK. ZQ This means that for the counters (Count, CNT), whether it is the first counter b1, the second counter b2, or the third counter b3, each counter needs to receive CLK. ZQ Signals are used to control the start and end of ZQ calibration.

[0096] It should also be noted that in this embodiment, the counting operation of the first counter b1, the second counter b2, and the third counter b3 is the same. For example, taking the first counter b1 as an example, the completion of each calibration can be determined by comparing the reference voltage and the first output voltage, thereby controlling the first counter b1 to perform the counting operation. Here, the determination criterion could be that the reference voltage and the first output voltage are equal, but in reality, they may not be equal. In this case, the determination criterion could be that the first output voltage is greater than the reference voltage in the first comparison and less than the reference voltage in the second comparison. Then, the calibration parameter is between the count value in the first comparison and the count value in the second comparison (generally, to reduce error, this process usually needs to be repeated at least two to three times).

[0097] Additionally, it should be noted that the counting operation for each counter can be performed by adding or subtracting a preset step size after each comparison result. The preset step size can be 1, 2, 3, 4, etc., that is, it can be an operation of adding 1, subtracting 1, adding 2, subtracting 2, etc. This disclosure embodiment does not limit this in any way.

[0098] Thus, for the first comparator a1 and the first counter b1, calibration parameters C0, C2, C4, and C5 can be determined by comparing the first output voltage with the reference voltage and by counting the first counter b1 at different output level values. For the second comparator a2 and the second counter b2, calibration parameters C1 and C7 can be determined by comparing the first output voltage with the reference voltage and by counting the second counter b2 at different output level values. For the third comparator a3 and the third counter b3, calibration parameters C0, C3, and C6 can be determined by comparing the second output voltage with the reference voltage and by counting the third counter b3 at different output level values. After obtaining C0, C1, C2, C3, C4, C5, C6, and C7, these parameters can be used to determine the target calibration parameters for at least one transistor group in the drive module 301, so as to perform impedance adjustment on these at least one transistor group, ensuring an impedance matching relationship between the impedance value of the drive module 301 and the impedance value of the receiving module 304 at different output level values.

[0099] It is also understood that, in some embodiments of this disclosure, for the driving module 301 and the calibration module 302, the first pull-up module 311 may include at least one first type of transistor group, the second pull-up module 312 may include at least one second type of transistor group, the third pull-up module 321 may include at least one third type of transistor group, the fourth pull-up module 322 may include at least one fourth type of transistor group, and the pull-down module 313 may include at least one fifth type of transistor group; wherein:

[0100] In the first pull-up module 311, the first type of transistor group includes multiple NMOS transistors;

[0101] In the second pull-up module 312, the second type of transistor group includes multiple PMOS transistors;

[0102] In the third pull-up module 321, the third type of transistor group includes multiple NMOS transistors;

[0103] In the fourth pull-up module 322, the fourth type of transistor group includes multiple PMOS transistors;

[0104] In the pull-down module 313, the fifth type of transistor group includes multiple NMOS transistors.

[0105] It should be noted that in the driving module 301, the first pull-up module 311 may include one or more first-type transistor groups, which are connected in parallel to adjust the parallel resistance value of the first pull-up module 311; the second pull-up module 312 may include one or more second-type transistor groups, which are connected in parallel to adjust the parallel resistance value of the second pull-up module 312; the pull-down module 313 may include one or more fifth-type transistor groups, which are connected in parallel to adjust the parallel resistance value of the pull-down module 313. Thus, based on the parallel resistance value of the first pull-up module 311, the parallel resistance value of the second pull-up module 312, and the parallel resistance value of the pull-down module 313, the pull-up resistor and pull-down resistor corresponding to the driving module 301 can be adjusted to match the impedance value of the receiving module 304 connected to the output terminal of the driving module 301.

[0106] It should also be noted that in the calibration module 302, the third pull-up module 321 may include one or more first-type transistor groups, which are connected in parallel to adjust the parallel resistance value of the third pull-up module 321; the fourth pull-up module 322 may include one or more second-type transistor groups, which are connected in parallel to adjust the parallel resistance value of the fourth pull-up module 322; thus, based on the parallel resistance value of the third pull-up module 321 and the parallel resistance value of the fourth pull-up module 322, the pull-up resistor corresponding to the calibration module 302 can be adjusted to match the first resistor R1 (resistance value equal to Z0) connected to the output terminal of the calibration module 302.

[0107] Furthermore, in some embodiments, in Figure 4 Based on the impedance matching circuit 30 shown, see... Figure 5 For the drive module 301, at least one first type of transistor group may include a first transistor group N1, a second transistor group N2, and a third transistor group N3; at least one second type of transistor group may include a fourth transistor P1; and at least one fifth type of transistor group may include a fifth transistor group N4 and a sixth transistor group N5; wherein:

[0108] In the first pull-up module 311, the first transistor group N1 may include multiple NMOS transistors, the second transistor group N2 may include multiple NMOS transistors, and the third transistor group N3 may include multiple NMOS transistors;

[0109] In the second pull-up module 312, the fourth transistor group P1 may include multiple PMOS transistors;

[0110] In the pull-down module 313, the fifth transistor group N4 may include multiple NMOS transistors, and the sixth transistor group N5 may include multiple NMOS transistors.

[0111] It should be noted that, in this embodiment, the first pull-up module 311 may include three transistor groups (e.g., a first transistor group N1, a second transistor group N2, and a third transistor group N3); and the second pull-up module 312 may include one transistor group (e.g., a fourth transistor group P1). The number of transistor groups included in either the first pull-up module 311 or the second pull-up module 312 is specifically set according to the actual application scenario, and no limitation is made here.

[0112] so, Figure 5 As a specific example, for the first pull-up module 311, the parallel resistance value of the first pull-up module 311 can be adjusted through the first transistor group N1, the second transistor group N2, and the third transistor group N3; for the second pull-up module 312, the parallel resistance value of the second pull-up module 312 can be adjusted through the fourth transistor group P1; then, based on the parallel resistance value of the first pull-up module 311 and the parallel resistance value of the second pull-up module 312, the resistance value of the pull-up resistor corresponding to the drive module 301 can also be adjusted, thereby changing the voltage division result.

[0113] It should also be noted that, in this embodiment of the disclosure, the pull-down module 313 may include two groups of transistors (e.g., the fifth transistor group N4 and the sixth transistor group N5), but the number of transistor groups included is specifically set according to the actual application scenario, and no limitation is made here.

[0114] Thus, still Figure 5 As a specific example, for the pull-down module 313, the resistance value of the pull-down resistor corresponding to the drive module 301 can be adjusted through the fifth transistor group N4 and the sixth transistor group N5, thereby changing the voltage division result.

[0115] In the embodiments disclosed herein, such as Figure 5 As shown, the first transistor group N1 may include a first main transistor A and at least one first auxiliary transistor; the second transistor group N2 may include a second main transistor B and at least one second auxiliary transistor; the third transistor group N3 may include a third main transistor C and at least one third auxiliary transistor; the fourth transistor group P1 may include a fourth main transistor D and at least one fourth auxiliary transistor; the fifth transistor group N4 may include a fifth main transistor E and at least one fifth auxiliary transistor; and the sixth transistor group N5 may include a sixth main transistor F and at least one sixth auxiliary transistor. That is, Figure 5The diagram shows six transistor slices, each consisting of a main transistor and at least one auxiliary transistor controlled by the target calibration parameters. However, no limit is placed on the number of transistor slices or auxiliary transistors.

[0116] Furthermore, in some embodiments, for the first main transistor A, the second main transistor B, the third main transistor C, the fourth main transistor D, the fifth main transistor E, and the sixth main transistor F, wherein:

[0117] The drain terminals of the first main transistor A, the second main transistor B, and the third main transistor C are all connected to the first power supply. The gate terminal of the first main transistor A is used to receive the first driving signal, the gate terminal of the second main transistor B is used to receive the second driving signal, and the gate terminal of the third main transistor C is used to receive the third driving signal. The source terminals of the first main transistor A, the second main transistor B, and the third main transistor C are all connected to the output node.

[0118] The source terminal of the fourth main transistor D is connected to the second power supply, the gate terminal of the fourth main transistor D is used to receive the fourth drive signal, and the drain terminal of the fourth main transistor D is connected to the output node.

[0119] The source terminals of the fifth main transistor E and the sixth main transistor F are both connected to ground. The gate terminal of the fifth main transistor E is used to receive the fifth drive signal, and the gate terminal of the sixth main transistor F is used to receive the sixth drive signal. The drain terminals of the fifth main transistor E and the sixth main transistor F are both connected to the output node.

[0120] It should be noted that, in this embodiment of the disclosure, the output node is used to output target data signals based on PAMn. See details... Figure 5 The output node can be represented by DQ. The source terminals of the first main transistor A, the second main transistor B, the third main transistor C, the fourth main transistor D, the fifth main transistor E, and the sixth main transistor F are all connected to the output node DQ to output a target data signal based on PAMn. This target data signal is the DQ signal to be transmitted. The DQ signal can be transmitted to the receiving module 304 via the channel.

[0121] It should also be noted that, in the embodiments of this disclosure, the first driving signal, the second driving signal, the third driving signal, the fourth driving signal, the fifth driving signal, and the sixth driving signal can be determined by performing logical operations based on the most significant bit (MSB) signal and the least significant bit (LSB) signal included in the input signal.

[0122] Thus, each transistor group can include a main transistor and at least one auxiliary transistor. Specifically, the first transistor group N1 can include a first main transistor A and at least one first auxiliary transistor. The switching on and off of this at least one first auxiliary transistor can adjust the driving resistance of the first main transistor A to regulate its driving capability. The second transistor group N2 can include a second main transistor B and at least one second auxiliary transistor. The switching on and off of this at least one second auxiliary transistor can adjust the driving resistance of the second main transistor B to regulate its driving capability. The third transistor group N3 can include a third main transistor C and at least one third auxiliary transistor. The switching on and off of this at least one third auxiliary transistor can adjust the driving resistance of the third main transistor C to regulate its driving capability. The fourth transistor group P1 can include a fourth main transistor D and at least one fourth auxiliary transistor. The switching on and off of this at least one fourth auxiliary transistor can adjust the driving resistance of the fourth main transistor D to regulate its driving capability. This achieves the adjustment of the pull-up driving capability of the driving circuit 10. In addition, the fifth transistor group N4 may include a fifth main transistor E and at least one fifth auxiliary transistor. The on and off states of the at least one fifth auxiliary transistor can adjust the resistance value of the drive resistor of the fifth main transistor E to regulate the drive capability of the fifth main transistor E. The sixth transistor group N5 may include a sixth main transistor F and at least one sixth auxiliary transistor. The on and off states of the at least one sixth auxiliary transistor can adjust the resistance value of the drive resistor of the sixth main transistor F to regulate the drive capability of the sixth main transistor F. This enables the adjustment of the pull-down drive capability of the drive circuit 10.

[0123] In one specific embodiment, the first main transistor A, the second main transistor B, the third main transistor C, and the fourth main transistor D are pull-up transistors, and the fifth main transistor E and the sixth main transistor F are pull-down transistors; moreover, the first main transistor A, the second main transistor B, the third main transistor C, the fifth main transistor E, and the sixth main transistor F are NMOS transistors, and the fourth main transistor D is a PMOS transistor.

[0124] like Figure 5 As shown, the drain terminals of the first main transistor A, the second main transistor B, and the third main transistor C are all connected to V. DDQ Power connection, the source terminal of the fourth main transistor D is connected to V CCThe power supply connection is as follows: the source terminals of the fifth main transistor E and the sixth main transistor F are both connected to ground. The source terminals of the first main transistor A, the second main transistor B, the third main transistor C, the fourth main transistor D, the fifth main transistor E, and the sixth main transistor F are all connected to the output node DQ, used to output the target data signal based on PAMn. Wherein, V DDQ The power supply value is lower than V. CC The power supply value is chosen to ensure that each main transistor operates in the linear resistance region and that the output node voltage meets requirements. For example, V... DDQ The power supply voltage is 0.6V. CC The power supply is set to 1.05V, but no specific limit is specified.

[0125] In addition, the gate of the first main transistor A is used to receive the first drive signal (using DR). A (Indicated), the gate terminal of the second main transistor B is used to receive the second drive signal (using DR). B (Indicated), the gate of the third main transistor C is used to receive the third drive signal (using DR). C (Indicated), the gate of the fourth main transistor D is used to receive the fourth drive signal (using DR). D (Indicated), the gate of the fifth main transistor E is used to receive the fifth drive signal (using DR). E (Indicated), the gate of the sixth master transistor F is used to receive the sixth drive signal (using DR). F (Represented). Here, the first drive signal, the second drive signal, the third drive signal, the fourth drive signal, the fifth drive signal, and the sixth drive signal can all be determined by logical operations based on the most significant bit (MSB) and least significant bit (LSB) signals included in the input signals.

[0126] It should be noted that, in this embodiment of the disclosure, a PAM encoding module (not shown in the figure) may also be included. The PAM encoding module is used to perform PAMn-based encoding processing on the received data to generate an input signal, which includes at least an MSB signal and an LSB signal.

[0127] In some embodiments, the determination of these drive signals is as follows:

[0128] The first driving signal can be the least significant bit signal;

[0129] The second driving signal can be obtained by performing an OR logic operation between the most significant bit signal and the least significant bit signal.

[0130] The third driving signal can be the most significant bit signal;

[0131] The fourth driving signal can be obtained by performing an OR logic operation on the NOT signals of the most significant bit signal and the least significant bit signal;

[0132] The fifth driving signal can be obtained by performing a NOT logic operation based on the first driving signal;

[0133] The sixth driving signal can be obtained by performing a non-logical operation based on the second driving signal.

[0134] In this embodiment, the original input signal consists of two incoherent binary random codes, one MSB signal and one LSB signal. Thus, considering the use of Gray coding, DR... A The signal can be an LSB signal, DR B The signal can be obtained by performing an OR logic operation on the MSB and LSB signals, DR C The signal can be an MSB signal, DR D The signal can be obtained by performing an OR logic operation on the negations of the MSB and LSB signals. DR E The signal can be DR A DR is obtained by performing NOT operations on the signal. F The signal can be DR B The signal is obtained by performing a NOT logical operation. The mathematical formula is as follows:

[0135] DR A =LSB (4)

[0136] DR B =MSB+LSB (5)

[0137] DR C =MSB (6)

[0138]

[0139]

[0140]

[0141] Furthermore, in some embodiments, when n equals 4, the target data signal may include a first level value, a second level value, a third level value, and a fourth level value; wherein:

[0142] When the input signal is 11, the first main transistor A, the second main transistor B, and the third main transistor C are in the on state, so that the level of the target data signal is the first level value;

[0143] When the input signal is 01, the first main transistor A, the second main transistor B, and the fourth main transistor D are in the on state, so that the level of the target data signal is the second level value;

[0144] When the input signal is 10, the second main transistor B, the third main transistor C, and the fifth main transistor E are in the on state, so that the level of the target data signal is the third level value;

[0145] When the input signal is 00, the fifth main transistor E and the sixth main transistor F are in the on state, making the target data signal level the fourth level value.

[0146] It should be noted that in this embodiment of the disclosure, if n=4, then the target data signal is a PAM4-based signal with four level values: a first level value, a second level value, a third level value, and a fourth level value.

[0147] It should also be noted that in this embodiment, different input signals correspond to different states. Here, the input signals include 00, 01, 10, and 11, corresponding to four states, and these four states correspond to four voltage levels of the target data signal. Specifically, in the first state, the input signal is 11, corresponding to the first main transistor A, the second main transistor B, and the third main transistor C being turned on, while the other main transistors are off, and the target data signal voltage level is the first voltage level. In the second state, the input signal is 01, corresponding to the first main transistor A, the second main transistor B, and the fourth main transistor D being turned on, while the other main transistors are off, and the target data signal voltage level is the second voltage level. In the third state, the input signal is 10, corresponding to the second main transistor B, the third main transistor C, and the fifth main transistor E being turned on, while the other main transistors are off, and the target data signal voltage level is the third voltage level. In the fourth state, the input signal is 00, corresponding to the fifth main transistor E and the sixth main transistor F being turned on, while the other main transistors are off, and the target data signal voltage level is the fourth voltage level. In this way, by controlling the on and off states of these main transistors, impedance matching with the receiver can be achieved, thereby improving signal integrity and signal linearity.

[0148] For example, assuming that for an NMOS transistor, 1 indicates that the main transistor is in the on state and 0 indicates that the main transistor is in the off state; and for a PMOS transistor, 0 indicates that the main transistor is in the on state and 1 indicates that the main transistor is in the off state; then combining... Figure 5 The driving module shown in Table 1 illustrates the on / off states of each main transistor under each input signal.

[0149] Table 1

[0150]

[0151] In some embodiments, the first level value is less than the second level value, the third level value is less than the first level value, and the fourth level value is less than the third level value.

[0152] It should be noted that in this embodiment, the second level value is the highest, and the fourth level value is the lowest. That is, when the input signal is 01, the highest level value (i.e., the second level value) is output; when the input signal is 11, the second highest level value (i.e., the first level value) is output; and so on, with the lowest level value (i.e., the fourth level value) output when the input signal is 00. Thus, only when the highest level value is output will a combination of NMOS and PMOS transistors be used as pull-up transistors; while when outputting other level values, an NMOS transistor is used as the pull-up transistor, thereby reducing power consumption.

[0153] It should also be noted that, in this embodiment of the disclosure, for each transistor group, impedance adjustment is required using the target calibration parameters determined by the digital logic module 303. In some embodiments, the plurality of calibration parameters may consist of a first calibration parameter C0, a second calibration parameter C1, a third calibration parameter C2, a fourth calibration parameter C3, a fifth calibration parameter C4, a sixth calibration parameter C5, a seventh calibration parameter C6, and an eighth calibration parameter C7; wherein:

[0154] The digital logic module 303 is also used to acquire the master calibration parameters of at least one transistor group, and determine the target calibration parameters of at least one transistor group based on the first calibration parameter, the second calibration parameter, the third calibration parameter, the fourth calibration parameter, the fifth calibration parameter, the sixth calibration parameter, the seventh calibration parameter, the eighth calibration parameter and the master calibration parameters of at least one transistor group.

[0155] It should be noted that in the embodiments of this disclosure, each transistor group has its own target calibration parameters. Moreover, for each transistor group, its target calibration parameters are also related to its own main calibration parameters (main code), specifically, each is subtracted from its corresponding main code. This reduces the adjustment range of the target calibration parameters, thereby achieving higher accuracy without causing a significant increase in the driving capacitance.

[0156] For example, with Figure 5For example, at least one transistor group may include a first transistor group N1, a second transistor group N2, a third transistor group N3, a fourth transistor P1, a fifth transistor group N4, and a sixth transistor group N5; then the target calibration parameters may include a first target calibration parameter codeA, a second target calibration parameter codeB, a third target calibration parameter codeC, a fourth target calibration parameter codeD, a fifth target calibration parameter codeE, and a sixth target calibration parameter codeF. Thus, for at least one auxiliary transistor in each transistor group, the target calibration parameters corresponding to that transistor group can be determined, and impedance adjustment can then be performed accordingly.

[0157] In some embodiments, for at least one first auxiliary transistor, at least one second auxiliary transistor, at least one third auxiliary transistor, at least one fourth auxiliary transistor, at least one fifth auxiliary transistor, and at least one sixth auxiliary transistor, wherein:

[0158] At least one first auxiliary transistor is impedance-adjusted based on a first target calibration parameter, at least one second auxiliary transistor is impedance-adjusted based on a second target calibration parameter, at least one third auxiliary transistor is impedance-adjusted based on a third target calibration parameter, at least one fourth auxiliary transistor is impedance-adjusted based on a fourth target calibration parameter, at least one fifth auxiliary transistor is impedance-adjusted based on a fifth target calibration parameter, and at least one sixth auxiliary transistor is impedance-adjusted based on a sixth target calibration parameter.

[0159] In other words, the target calibration parameter corresponding to the first transistor group N1 is called the first target calibration parameter codeA, and the impedance of at least one first auxiliary transistor can be adjusted based on the first target calibration parameter codeA; the target calibration parameter corresponding to the second transistor group N2 is called the second target calibration parameter codeB, and the impedance of at least one second auxiliary transistor can be adjusted based on the second target calibration parameter codeB; the target calibration parameter corresponding to the third transistor group N3 is called the third target calibration parameter codeC, and the impedance of at least one third auxiliary transistor can be adjusted based on the third target calibration parameter codeC; the target calibration parameter corresponding to the fourth transistor group P1 is called the fourth target calibration parameter codeD, and the impedance of at least one fourth auxiliary transistor can be adjusted based on the fourth target calibration parameter codeD; the target calibration parameter corresponding to the fifth transistor group N4 is called the fifth target calibration parameter codeE, and the impedance of at least one fifth auxiliary transistor can be adjusted based on the fifth target calibration parameter codeE; the target calibration parameter corresponding to the sixth transistor group N5 is called the sixth target calibration parameter codeF, and the impedance of at least one sixth auxiliary transistor can be adjusted based on the sixth target calibration parameter codeF.

[0160] In one specific embodiment, the digital logic module 303 is configured to determine a first target calibration parameter based on a first calibration parameter, a sixth calibration parameter, a seventh calibration parameter, and a main control calibration parameter corresponding to the first main transistor; and

[0161] The second target calibration parameter is determined based on the first calibration parameter, the fifth calibration parameter, the sixth calibration parameter, the seventh calibration parameter, and the main transistor calibration parameter corresponding to the second main transistor; and

[0162] The third target calibration parameter is determined based on the first calibration parameter, the fifth calibration parameter, and the main transistor calibration parameter corresponding to the third main transistor; and

[0163] Based on the third calibration parameter, the fourth calibration parameter, and the main transistor calibration parameter corresponding to the fourth main transistor, determine the fourth target calibration parameter; and

[0164] Based on the eighth calibration parameter and the main transistor calibration parameter corresponding to the fifth main transistor, determine the fifth target calibration parameter; and

[0165] The sixth target calibration parameter is determined based on the second calibration parameter, the eighth calibration parameter, and the main control calibration parameter corresponding to the sixth main transistor.

[0166] In this embodiment of the disclosure, the main calibration parameter corresponding to the first main transistor can be represented by Amain, the main calibration parameter corresponding to the second main transistor can be represented by Bmain, the main calibration parameter corresponding to the third main transistor can be represented by Cmain, the main calibration parameter corresponding to the fourth main transistor can be represented by Dmain, the main calibration parameter corresponding to the fifth main transistor can be represented by Emain, and the main calibration parameter corresponding to the sixth main transistor can be represented by Fmain.

[0167] Thus, the first target calibration parameter codeA can be calculated and determined by C0, C5, C6, and Amain; the second target calibration parameter codeB can be calculated and determined by C0, C4, C5, C6, and Bmain; the third target calibration parameter codeC can be calculated and determined by C0, C4, and Cmain; the fourth target calibration parameter codeD can be calculated and determined by C2, C3, and Dmain; the fifth target calibration parameter codeE can be calculated and determined by C7 and Emain; and the sixth target calibration parameter codeF can be calculated and determined by C1, C7, and Fmain. This can be expressed mathematically as follows:

[0168]

[0169]

[0170] codeC = C0-C4-C main (12)

[0171]

[0172] codeE = C7-E main (14)

[0173] codeF = C1-C7-F main (15)

[0174] Thus, based on the C0, C1, C2, C3, C4, C5, C6, and C7 obtained under each output level value, the digital logic module 303 calculates and finally outputs the target calibration parameters codeA, codeB, codeC, codeD, codeE, and codeF applied to the PAM4-based driver module. The operational logic for equations (10) to (15) is derived from the following formulas, and these operational logics also require subtraction of their respective supervisor calibration parameters. These formulas are as follows:

[0175]

[0176]

[0177] R ABC =Z0 (18)

[0178] R BC =4[Z0 / / (Z0-Δ2)] (19)

[0179]

[0180] In short, based on equations (16) to (20), the operational logic of equations (10) to (15) can be derived, and the target calibration parameters codeA, codeB, codeC, codeD, codeE, and codeF of the PAM4-based driving module 301 can be determined.

[0181] For example, taking the first transistor group as an example, see Figure 6 This illustrates a schematic diagram of the composition structure of a first transistor group provided in an embodiment of this disclosure. Figure 6 As shown, the first transistor group N1 may include a first main transistor A and (n+1) first auxiliary transistors, where n is an integer greater than or equal to 0. The main control calibration parameter corresponding to the first main transistor A is Amain, and the first target calibration parameter corresponding to the (n+1) first auxiliary transistors is codeA. <n:0>When calculating the first target calibration parameter codeA, it is necessary to subtract Amain corresponding to the first main transistor A, which can reduce the adjustment range of the target calibration parameter; moreover, by adjusting the impedance of these (n+1) first auxiliary transistors according to codeA, good output linearity and impedance matching can be achieved.

[0182] Taking n=5 as an example, Figure 7 A schematic diagram of the composition structure of another first transistor group provided in an embodiment of this disclosure is shown. Figure 7 In the first transistor group N1, there may be a first main transistor A and six first auxiliary transistors. For these six first auxiliary transistors, impedance adjustment can be performed using code<5:0>, and the digital logic calculation of code<5:0> has been reduced by subtracting Amain to reduce the adjustment range of code<5:0>.

[0183] Furthermore, in some embodiments, for the calibration module 302, compared to the driving module 301, the number of third-type transistor groups included in the third pull-up module 321 may be the same as the number of first-type transistor groups included in the first pull-up module 311, and the number of fourth-type transistor groups included in the fourth pull-up module 322 may be the same as the number of second-type transistor groups included in the second pull-up module 312. However, in other embodiments, these numbers may not be the same, and this disclosure does not impose any limitations. In practical applications, the transistor size (resistance value) represented by the least significant bit is the same. For example, the calibration parameter ZQ is <5:0>, and the target calibration parameter final driver is <4:0>, corresponding to the lower four bits of the calibration parameter ZQ, and the size is the same, because the final driver has a main transistor (main leg), and the resistance value of this main leg can be set as needed. For example, binary code 001 represents 1µm, 010 represents 2µm, 011 represents 3µm, 100 represents 4µm, and 101 represents 5µm. Therefore, when the main leg is set to 5µm, 101 needs to be subtracted when converting to the final driver code. In other words, in this embodiment, the code used for ZQ calibration and the code used by the PAM4-based final driver are binary codes with the same resolution.

[0184] This disclosure provides an impedance matching circuit. Because the driving module contains different transistor types, it leverages the advantages of both NMOS and PMOS transistors, avoiding the shortcomings of using only NMOS or PMOS transistors as pull-up transistors. Furthermore, by adjusting the impedance of at least one transistor group in the driving module through a calibration module and a digital logic module, an impedance matching relationship can be achieved between the impedance values ​​of the driving module and the receiving module at different output levels. This not only saves overall circuit area but also improves signal integrity and reduces power consumption while maintaining output linearity, thereby effectively improving data transmission performance.

[0185] In another embodiment of this disclosure, see Figure 8 This illustration shows a schematic diagram of the structural composition of a semiconductor memory provided in an embodiment of this disclosure. Figure 8 As shown, the semiconductor memory 80 includes at least the impedance matching circuit 30 as described in any of the foregoing embodiments.

[0186] In some embodiments, Figure 9 A schematic diagram of the composition structure of another semiconductor memory provided in an embodiment of this disclosure is shown. For example... Figure 9 As shown, the semiconductor memory 80 may include a transmitter circuit 801 and a receiver circuit 802; wherein:

[0187] Transmitter circuit 801 may include drive module 301 for outputting target data signal based on PAMn;

[0188] Receiver circuit 802 may include receiver module 304 for receiving target data signals transmitted from transmitter circuit 801 via a channel;

[0189] The impedance values ​​of the receiver circuit 802 and the transmitter circuit 801 are impedance matched.

[0190] In this embodiment of the disclosure, the semiconductor memory 80 can be a dynamic random access memory (DRAM). The DRAM can conform to memory specifications such as DDR, DDR2, DDR3, DDR4, and DDR5, as well as LPDDR, LPDDR2, LPDDR3, LPDDR4, and LPDDR5; no limitation is made here.

[0191] In this embodiment, the driving module 301 is compatible with conventional transmitter circuits based on NRZ signals. Therefore, in some embodiments, the transmitter circuit 801 of this embodiment can support both NRZ mode and PAMn mode; wherein:

[0192] The driver module 301 is used to output a target data signal based on NRZ when the set signal mode is NRZ mode; or to output a target data signal based on PAMn when the set signal mode is PAMn mode.

[0193] In other words, in the transmitter circuit 801, the driver module 301 can output both NRZ-based and PAMn-based target data signals, offering good compatibility. For example, in NRZ mode, the driver module 301 can output NRZ-based target data signals; while in PAMn mode, the driver module 301 can output PAMn-based target data signals.

[0194] Furthermore, in this embodiment of the present disclosure, for the transmitter circuit 801, the driving module can use a mixture of PMOS and NMOS transistors as pull-up transistors to provide the highest level value of the PAM4 output, while other lower level values ​​still use only NMOS transistors as pull-up transistors; in addition, each transistor is determined under two limiting conditions, considering impedance matching and output level value. Thus, compared with PAM4-based circuits in related technologies, the transmitter circuit 801 has advantages in signal integrity and linearity due to impedance matching.

[0195] For example, with Figure 5 For example, in the transmitter circuit 801, the driving module 301 may include a first transistor group N1, a second transistor group N2, a third transistor group N3, a fourth transistor group P1, a fifth transistor group N4, and a sixth transistor group N5; wherein, the first transistor group N1 includes at least a first main transistor A and at least a first auxiliary transistor, the second transistor group N2 includes at least a second main transistor B and at least a second auxiliary transistor, the third transistor group N3 includes at least a third main transistor C and at least a third auxiliary transistor, the fourth transistor group P1 includes at least a fourth main transistor D and at least a fourth auxiliary transistor, the fifth transistor group N4 includes at least a fifth main transistor E and at least a fifth auxiliary transistor, and the sixth transistor group N5 includes at least a sixth main transistor F and at least a sixth auxiliary transistor; in the receiver circuit 802, the receiving module 304 may include a seventh transistor G; and the driving module 301 and the receiving module 304 transmit data through a channel.

[0196] exist Figure 5 In the circuit, the first transistor group N1, the second transistor group N2, the third transistor group N3, and the fourth transistor group P1 form pull-up circuits, while the fifth transistor group N4 and the sixth transistor group N5 form pull-down circuits. The transistors in the first transistor group N1, the second transistor group N2, and the third transistor group N3 are NMOS transistors, and these three transistor groups are connected by V... DDQ Power supply; the transistors in the fourth transistor group P1 are PMOS transistors, which are powered by V CC Power is supplied; the transistors in the fifth transistor group N4 and the sixth transistor group N5 are NMOS transistors. Additionally, the seventh transistor G, acting as the receiver, has on-die termination (ODT) characteristics, and its impedance value is equal to the channel impedance after channel optimization. Here, the seventh transistor G is also an NMOS transistor, and the seventh transistor G is powered by V... CC Power is supplied by a power source. In this way, because the seventh transistor G has ODT characteristics, the target data signal can be completely consumed at the termination resistor, preventing these signals from being reflected in the circuit, thereby improving signal integrity.

[0197] It should be noted that, in the embodiments disclosed herein, V DDQ The power supply value can be 0.6V, V CC The power supply value can be 1.05V.

[0198] Thus, in Figure 5 The drive module 301 includes six transistor slices, each of which can be divided into a main transistor and an auxiliary transistor controlled by the target calibration parameters. By controlling the on and off of each main transistor in these six transistor slices according to Table 1, the ZQ calibration method can be used on the PAM4-based transmitter circuit, which can maintain impedance matching at all four output levels while ensuring good output linearity.

[0199] For example, see Figure 10 This illustrates a comparative diagram of the eye diagram structure at three process angles according to embodiments of the present disclosure. For example... Figure 10 As shown, (a) is an example of an eye diagram for a slow-slow (ss) process angle, with four output levels of 0.405V, 0.27V, and 0.135V; (b) is an example of an eye diagram for a fast-fast (ff) process angle, with four output levels of 0.495V, 0.33V, and 0.165V; and (c) is an example of an average-average (tt) process angle, with four output levels of 0.45V, 0.3V, and 0.15V. Here, each eye height is greater than 100mV, enabling a larger signal swing to reduce the demands on the receiver.

[0200] Thus, Table 2 shows examples of the transistor widths required for calibration at the SS, TT, and FF process corners. In Table 2, the unit for transistor width is micrometers (µm).

[0201] Table 2

[0202] C2-A 487.4 307.2 186 C3-A 643.9 398.3 244.7 C2-B 153.7 124.2 89.14 C3-B 203.2 160.5 117

[0203] Therefore, in this embodiment, for the digital logic operations shown in equations (10) to (15), the ZQ calibration codes (ZQ codes) at the three process corners are obtained after calibration using this logic. Substituting these codes into the transmitter circuit can achieve good linearity and impedance matching. In addition, the pull-up transistors at the highest level are a mixture of PMOS and NMOS transistors. In this case, the PMOS transistors need to be calibrated first, followed by the NMOS transistors, which can save the overall circuit area. The reason is that calibrating the NMOS transistors first requires a resistance of Z0 / 3Ω, while calibrating the PMOS transistors first only requires a resistance of 4Z0 / 3Ω. However, the smaller the resistance, the larger the size of the transistors required; conversely, the larger the resistance, the smaller the size of the transistors required. Furthermore, by subtracting the main code of each main transistor in the digital logic operations, the adjustment range of the ZQ code can be reduced, thereby achieving higher accuracy without causing a significant increase in the driving capacitor of the final driver. Here, the driving capacitor can be represented by pincap, which specifically refers to the capacitor value connected to the output node DQ. In this embodiment, it is desirable for this capacitor value to be as small as possible.

[0204] In one specific embodiment, see Figure 11 This illustrates a detailed structural diagram of an impedance matching circuit 30 provided in an embodiment of the present disclosure. For example... Figure 11 As shown, the pull-up transistors in the driving module may include a set of NMOS transistors and a set of PMOS transistors, and the pull-down transistors in the driving module may include a set of NMOS transistors. The output of the driving module is connected to the first output node DQ and also connected to the receiving module (with an impedance value of Rx) via a channel. The pull-up transistors in the calibration module may include a set of NMOS transistors and a set of PMOS transistors. The output of the calibration module is connected to the second output node ZQ and also connected to the first resistor R1 via the second output node ZQ. Here, the resistance value of R1 is Z0.

[0205] Additionally, ① corresponds to an output level value of In this case, the resistance of Rx is Z0, which allows us to determine the calibration parameters C0 and C1. null indicates no output; ② The corresponding output level is... In this case, the resistance of Rx is Z0+Δ1, which allows us to determine the calibration parameters C2, C3, and C4. null indicates an empty value; ③ The corresponding output level is... In this case, the resistance of Rx is Z0-Δ2, which allows us to determine the calibration parameters C5, C6, and C7. null indicates an empty value. Δ1 and Δ2 are preset values; their specific values ​​can be set according to actual conditions and are not limited here.

[0206] Specifically, when the output level value is At that time, the first calibration loop uses the first resistor R1 and R X The pull-up transistor is calibrated to obtain C0. The second calibration loop uses C0 to calibrate the pull-down transistor to obtain C1 (at this time, the receiver module is off). The output level is... At that time, the first calibration loop uses the first resistor R1 and R X To calibrate the pull-up transistors, we obtain C2 and C3. At this point, only the PMOS in the pull-up transistor is on, and then the PMOS is fixed. This is used to perform a second calibration loop to calibrate the NMOS in the pull-up transistor, resulting in C4. The output level is then set to... At that time, the first calibration loop uses the first resistor R1 and R X To calibrate the pull-up transistors, we obtain C5 and C6. Then, the NMOS in the pull-up transistor is fixed as follows: This is used to perform a second calibration loop to calibrate the pull-down transistor, resulting in C7. Then, based on the digital logic operations of equations (10) to (15), the target calibration parameters codeA, codeB, codeC, codeD, codeE, and codeF can be determined. During this process, CNT acts as a counter, comparing the output voltage with the reference voltage V. ref This is used to determine whether each calibration is complete; the output voltage can be the first output voltage at the DQ node or the second output voltage at the ZQ node.

[0207] It should also be noted that in this embodiment, the pull-down transistor in the driver module can be reused as an ODT circuit. In this case, the resistance value required for the ODT characteristics needs to be considered. In addition, in PAM4, when the input signal is 00, considering that the output node DQ needs to be pulled down to 0V, the pull-down transistor can also provide a ground path. Here, the more ground paths there are, the faster the pull-down speed of the driver module can be.

[0208] In this disclosure, the specific implementation of the aforementioned embodiments has been described in detail through the above embodiments. Based on the technical solutions of the aforementioned embodiments, it can be seen that, on the one hand, ZQ calibration is performed using an external first resistor R1 (whose resistance value is Z0) and the receiving end Rx as a reference. At this time, the size of Rx is... Figure 5 The source-drain voltage V of the seventh transistor G DQ =1 / 2V DDQ The dimension with resistance Z0 at the current process angular temperature (in other words, R) X The dimensions are fixed. On the other hand, the ZQ code obtained by calibration for each output level value is finally output by the digital logic module to the target calibration parameters (i.e., codeA, codeB, codeC, codeD, codeE, codeF) of the transmitter circuit based on PAM4. On another hand, the digital logic operation here is derived from the above equations (16) to (20). The operation logic needs to subtract the main calibration parameters (i.e., Amain, Bmain, Cmain, Dmain, Emain, Fmain). Moreover, the code used for ZQ calibration and the code used for the final driver based on PAM4 are binary codes with the same resolution. Thus, based on this ZQ calibration method, impedance matching is maintained at all four output level values ​​while ensuring good output linearity, which can improve signal integrity. On yet another hand, when calibrating the highest level value, the PMOS transistor needs to be calibrated first. The code of the NMOS transistor is obtained by performing a second round of calibration based on the obtained PMOS transistor code, which can also save the overall circuit area.

[0209] In yet another embodiment of this disclosure, see [link to relevant documentation]. Figure 12 This illustrates a flowchart of an impedance matching method provided in an embodiment of this disclosure. Figure 12 As shown, the method may include:

[0210] S1201: Determine the impedance values ​​of the first resistor connected to the calibration module and the receiver module connected to the drive module.

[0211] S1202: Based on the impedance values ​​of the first resistor and the receiving module, the calibration module and the driving module work together to perform calibration processing to determine multiple calibration parameters obtained under different output level values.

[0212] S1203: Based on multiple calibration parameters, the target calibration parameters for each of at least one transistor group in the drive module are determined by the digital logic module.

[0213] S1204: Adjust the impedance of at least one transistor group in the drive module according to the target calibration parameters so that the impedance value of the drive module and the impedance value of the receiver module have an impedance matching relationship under different output level values.

[0214] It should be noted that, in this embodiment, the impedance matching method is applied to the impedance matching circuit described in the foregoing embodiments or a semiconductor memory integrating the impedance matching circuit. In this impedance matching circuit, for the driving module, the output terminal of the driving module is connected to the receiving module, and the output terminal of the calibration module is connected to the first resistor. Furthermore, the driving module includes pull-up transistors and pull-down transistors. The pull-up transistors can be composed of NMOS and PMOS transistors, and the pull-down transistors can be composed of NMOS transistors; the pull-up transistors in the calibration module can also be composed of NMOS and PMOS transistors.

[0215] It should also be noted that, in this embodiment, by cooperating with the driving module to perform calibration processing, multiple calibration parameters obtained at different output level values ​​can be determined. Assuming that the driving module includes six transistor groups, calibration parameters such as C0, C1, C2, C3, C4, C5, C6, and C7 can be obtained through the calibration loop; then, combined with the main calibration parameters, the target calibration parameters codeA, codeB, codeC, codeD, codeE, and codeF can be determined using the digital logic operations of equations (10) to (15) so that the impedance of these six transistor groups can be adjusted so that the impedance value of the driving module and the impedance value of the receiving module have an impedance matching relationship at different output level values.

[0216] In this embodiment, the pull-up transistors are of both NMOS and PMOS types, and the combination of NMOS and PMOS transistors is used only when the output level is at its highest; otherwise, only the NMOS transistor is used. This allows the driver module to leverage the advantages of both NMOS and PMOS transistors, avoiding the shortcomings of using only one NMOS or PMOS transistor as the pull-up transistor. Furthermore, by adjusting the impedance of at least one transistor group in the driver module through the calibration module and digital logic module, impedance matching between the driver module's impedance and the receiver module's impedance can be achieved at different output levels. This not only saves overall circuit area but also improves signal integrity and reduces power consumption while maintaining output linearity, thereby effectively improving data transmission performance.

[0217] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure.

[0218] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0219] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0220] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0221] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0222] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0223] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An impedance matching circuit, characterized in that, The impedance matching circuit includes a driving module, a calibration module, a digital logic module, a receiving module, and a first resistor. The output terminal of the driving module is connected to the receiving module, and the output terminal of the calibration module is connected to the first resistor; wherein: The calibration module is used to perform calibration processing in conjunction with the driving module based on the impedance values ​​of the first resistor and the receiving module, and to determine multiple calibration parameters obtained under different output level values. The digital logic module is used to receive the plurality of calibration parameters and determine the target calibration parameters for each of at least one transistor group in the driving module; The driving module is used to receive the target calibration parameters and adjust the impedance of the at least one transistor group according to the target calibration parameters, so that there is an impedance matching relationship between the impedance value of the driving module and the impedance value of the receiving module under different output level values.

2. The impedance matching circuit according to claim 1, characterized in that, The driving module includes a first pull-up module, a second pull-up module, and a pull-down module; the calibration module includes a third pull-up module and a fourth pull-up module, wherein: One end of the first pull-up module and one end of the third pull-up module are both connected to the first power supply. One end of the second pull-up module and one end of the fourth pull-up module are both connected to the second power supply; One end of the pull-down module is grounded, and the other ends of the first pull-up module, the second pull-up module, and the pull-down module are all connected to the input end of the receiving module. The output end of the receiving module is grounded. The other end of the third pull-up module and the other end of the fourth pull-up module are both connected to one end of the first resistor, and the other end of the first resistor is grounded.

3. The impedance matching circuit according to claim 2, characterized in that, The transistors in the first pull-up module and the third pull-up module are NMOS transistors; The transistors in the second pull-up module and the fourth pull-up module are PMOS transistors; The transistors in the pull-down module are NMOS transistors.

4. The impedance matching circuit according to claim 3, characterized in that, The value of the first power supply is lower than the value of the second power supply.

5. The impedance matching circuit according to claim 3, characterized in that, The driving module is also used to output target data signals based on PAMn; where n is an integer greater than or equal to 2.

6. The impedance matching circuit according to claim 5, characterized in that, The calibration module is further configured to, when the target data signal corresponds to the maximum level value, perform PMOS transistor calibration in the second pull-up module and the fourth pull-up module in cooperation with the driving module based on the impedance values ​​of the first resistor and the receiving module, and then perform NMOS transistor calibration in the first pull-up module and the third pull-up module in cooperation with the driving module based on the calibration parameters corresponding to the second pull-up module and the fourth pull-up module.

7. The impedance matching circuit according to claim 5, characterized in that, When n equals 4, the target data signal includes at least a first level value, a second level value, and a third level value; wherein: The calibration module is configured to, when the output level is the first level value, perform a first calibration process in conjunction with the driving module based on the impedance values ​​of the first resistor and the receiving module, to determine the first calibration parameters corresponding to the first pull-up module and the third pull-up module; and, when the receiving module is turned off and the first calibration parameters corresponding to the first pull-up module and the third pull-up module are fixed, perform a second calibration process in conjunction with the driving module to determine the second calibration parameters corresponding to the pull-down module; or... The calibration module is configured to, when the output level is the second level value, perform a first calibration process in conjunction with the driving module based on the impedance values ​​of the first resistor and the receiving module, to determine a third calibration parameter corresponding to the second pull-up module and a fourth calibration parameter corresponding to the fourth pull-up module; and when the calibration parameters corresponding to the second pull-up module and the fourth pull-up module are fixed at a first preset value, perform a second calibration process in conjunction with the driving module to determine a fifth calibration parameter corresponding to the first pull-up module; or... The calibration module is configured to, when the output level value is the third level value, perform a first calibration process in conjunction with the driving module based on the impedance values ​​of the first resistor and the receiving module to determine the sixth calibration parameter corresponding to the first pull-up module and the seventh calibration parameter corresponding to the third pull-up module; and when the calibration parameters corresponding to the first pull-up module and the third pull-up module are fixed at a second preset value, perform a second calibration process in conjunction with the driving module to determine the eighth calibration parameter corresponding to the pull-down module. The first preset value is related to the third and fourth calibration parameters, and the second preset value is related to the sixth and seventh calibration parameters.

8. The impedance matching circuit according to claim 7, characterized in that, The impedance matching circuit further includes a first processing module, a second processing module, and a third processing module; wherein... The first processing module includes a first comparator and a first counter, used to receive a reference voltage and a first output voltage through the first comparator, and output a first comparison result between the reference voltage and the first output voltage; and to receive the first comparison result and a calibration clock signal through the first counter, and control the first counter to perform a counting operation when the calibration clock signal indicates that it is in calibration mode and the first comparison result meets a preset condition, to determine a first counting result, wherein the first counting result is used to determine the calibration parameters corresponding to the first pull-up module or the second pull-up module under different output level values; The second processing module includes a second comparator and a second counter, used to receive the reference voltage and the first output voltage through the second comparator, and output a second comparison result between the reference voltage and the first output voltage; and to receive the second comparison result and a calibration clock signal through the second counter, and control the second counter to perform a counting operation when the calibration clock signal indicates that it is in calibration mode and the second comparison result meets a preset condition, to determine a second counting result, wherein the second counting result is used to determine the calibration parameters corresponding to the pull-down module under different output level values; The third processing module includes a third comparator and a third counter, used to receive the reference voltage and the second output voltage through the third comparator, and output a third comparison result between the reference voltage and the second output voltage; and to receive the third comparison result and a calibration clock signal through the third counter, and control the third counter to perform a counting operation when the calibration clock signal indicates that it is in calibration mode and the third comparison result meets a preset condition, to determine a third counting result, wherein the third counting result is used to determine the calibration parameters corresponding to the third pull-up module or the fourth pull-up module at different output level values; Wherein, the first output voltage represents the voltage value at the output terminal of the drive module, and the second output voltage represents the voltage value at the output terminal of the calibration module.

9. The impedance matching circuit according to claim 7, characterized in that, The plurality of calibration parameters are composed of the first calibration parameter, the second calibration parameter, the third calibration parameter, the fourth calibration parameter, the fifth calibration parameter, the sixth calibration parameter, the seventh calibration parameter, and the eighth calibration parameter; wherein: The digital logic module is further configured to acquire the master calibration parameters of each of the at least one transistor group, and determine the target calibration parameters of each of the at least one transistor group based on the first calibration parameter, the second calibration parameter, the third calibration parameter, the fourth calibration parameter, the fifth calibration parameter, the sixth calibration parameter, the seventh calibration parameter, the eighth calibration parameter, and the master calibration parameters of each of the at least one transistor group.

10. The impedance matching circuit according to claim 9, characterized in that, The first pull-up module includes at least one group of first-type transistors, the second pull-up module includes at least one group of second-type transistors, the third pull-up module includes at least one group of third-type transistors, the fourth pull-up module includes at least one group of fourth-type transistors, and the pull-down module includes at least one group of fifth-type transistors; wherein: In the first pull-up module, the first type of transistor group includes multiple NMOS transistors; In the second pull-up module, the second type of transistor group includes multiple PMOS transistors; In the third pull-up module, the third type of transistor group includes multiple NMOS transistors; In the fourth pull-up module, the fourth type of transistor group includes multiple PMOS transistors; In the pull-down module, the fifth type of transistor group includes multiple NMOS transistors.

11. The impedance matching circuit according to claim 10, characterized in that, The at least one first-type transistor group includes a first transistor group, a second transistor group, and a third transistor group; the at least one second-type transistor group includes a fourth transistor group; and the at least one fifth-type transistor group includes a fifth transistor group and a sixth transistor group; wherein: In the first pull-up module, the first transistor group includes multiple NMOS transistors, the second transistor group includes multiple NMOS transistors, and the third transistor group includes multiple NMOS transistors; In the second pull-up module, the fourth transistor group includes multiple PMOS transistors; In the pull-down module, the fifth transistor group includes multiple NMOS transistors, and the sixth transistor group includes multiple NMOS transistors.

12. The impedance matching circuit according to claim 11, characterized in that, The first transistor group includes a first main transistor and at least one first auxiliary transistor; the second transistor group includes a second main transistor and at least one second auxiliary transistor; the third transistor group includes a third main transistor and at least one third auxiliary transistor; the fourth transistor group includes a fourth main transistor and at least one fourth auxiliary transistor; the fifth transistor group includes a fifth main transistor and at least one fifth auxiliary transistor; and the sixth transistor group includes a sixth main transistor and at least one sixth auxiliary transistor; wherein: The at least one first auxiliary transistor is impedance-adjusted based on a first target calibration parameter, the at least one second auxiliary transistor is impedance-adjusted based on a second target calibration parameter, the at least one third auxiliary transistor is impedance-adjusted based on a third target calibration parameter, the at least one fourth auxiliary transistor is impedance-adjusted based on a fourth target calibration parameter, the at least one fifth auxiliary transistor is impedance-adjusted based on a fifth target calibration parameter, and the at least one sixth auxiliary transistor is impedance-adjusted based on a sixth target calibration parameter.

13. The impedance matching circuit according to claim 12, characterized in that, The digital logic module is used to determine the first target calibration parameter based on the first calibration parameter, the sixth calibration parameter, the seventh calibration parameter, and the main control calibration parameter corresponding to the first main transistor. as well as The second target calibration parameter is determined based on the first calibration parameter, the fifth calibration parameter, the sixth calibration parameter, the seventh calibration parameter, and the main control calibration parameter corresponding to the second main transistor. as well as The third target calibration parameter is determined based on the first calibration parameter, the fifth calibration parameter, and the main control calibration parameter corresponding to the third main transistor; as well as The fourth target calibration parameter is determined based on the third calibration parameter, the fourth calibration parameter, and the main control calibration parameter corresponding to the fourth main transistor. as well as The fifth target calibration parameter is determined based on the eighth calibration parameter and the main control calibration parameter corresponding to the fifth main transistor; as well as The sixth target calibration parameter is determined based on the second calibration parameter, the eighth calibration parameter, and the main control calibration parameter corresponding to the sixth main transistor.

14. The impedance matching circuit according to claim 12, characterized in that, The drain terminals of the first main transistor, the second main transistor, and the third main transistor are all connected to the first power supply. The gate terminal of the first main transistor is used to receive the first driving signal, the gate terminal of the second main transistor is used to receive the second driving signal, and the gate terminal of the third main transistor is used to receive the third driving signal. The source terminals of the first main transistor, the second main transistor, and the third main transistor are all connected to the output node. The source terminal of the fourth main transistor is connected to the second power supply, the gate terminal of the fourth main transistor is used to receive the fourth driving signal, and the drain terminal of the fourth main transistor is connected to the output node. The source terminals of the fifth main transistor and the sixth main transistor are both connected to ground. The gate terminal of the fifth main transistor is used to receive the fifth driving signal, and the gate terminal of the sixth main transistor is used to receive the sixth driving signal. The drain terminals of the fifth main transistor and the sixth main transistor are both connected to the output node. The output node is used to output target data signals based on PAMn, and the first driving signal, the second driving signal, the third driving signal, the fourth driving signal, the fifth driving signal and the sixth driving signal are determined by logical operations based on the most significant bit signal and the least significant bit signal included in the input signal.

15. The impedance matching circuit according to claim 14, characterized in that, The first driving signal is the least significant bit signal; The second driving signal is obtained by performing an OR logic operation between the most significant bit signal and the least significant bit signal; The third driving signal is the most significant bit signal; The fourth driving signal is obtained by performing an OR logic operation between the most significant bit signal and the least significant bit signal; The fifth driving signal is obtained by performing a non-logical operation on the first driving signal; The sixth driving signal is obtained by performing a non-logical operation based on the second driving signal.

16. The impedance matching circuit according to claim 14, characterized in that, When n equals 4, the target data signal includes a first level value, a second level value, a third level value, and a fourth level value; wherein: When the input signal is 11, the first main transistor, the second main transistor, and the third main transistor are in the on state, so that the level of the target data signal is the first level value; When the input signal is 01, the first main transistor, the second main transistor, and the fourth main transistor are in the on state, so that the level of the target data signal is the second level value; When the input signal is 10, the second main transistor, the third main transistor, and the fifth main transistor are in the on state, so that the level of the target data signal is the third level value; When the input signal is 00, the fifth main transistor and the sixth main transistor are in the on state, so that the level of the target data signal is the fourth level value.

17. The impedance matching circuit according to claim 16, characterized in that, The first level value is less than the second level value, the third level value is less than the first level value, and the fourth level value is less than the third level value.

18. An impedance matching method, characterized in that, The method includes: Determine the impedance values ​​of the first resistor connected to the calibration module and the receiver module connected to the drive module; Based on the impedance values ​​of the first resistor and the receiving module, the calibration module and the driving module cooperate to perform calibration processing to determine multiple calibration parameters obtained under different output level values; Based on the plurality of calibration parameters, the target calibration parameters for each of at least one transistor group in the drive module are determined by the digital logic module. The impedance of at least one transistor group in the driving module is adjusted according to the target calibration parameters so that the impedance value of the driving module and the impedance value of the receiving module have an impedance matching relationship under different output level values.

19. A semiconductor memory, characterized in that, The semiconductor memory includes at least the impedance matching circuit as described in any one of claims 1 to 17.

20. The semiconductor memory according to claim 19, characterized in that, The semiconductor memory includes a transmitter circuit and a receiver circuit; wherein: The transmitter circuit includes the drive module, which is used to output target data signals based on PAMn; The receiver circuit includes the receiving module, which is used to receive the target data signal transmitted from the transmitter circuit through a channel; The impedance values ​​of the receiver circuit and the transmitter circuit have an impedance matching relationship.

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