Apparatus, system, and method for voltage-based random number generation

Abstract

This invention discloses apparatus, systems, and methods for voltage-based random number generation. A memory may contain multiple different voltages that can be used to power various operations of the memory. The voltages can vary during access operations to the memory, for example, when accessing a word line of the memory. The variability of the voltages can represent a source of randomness and unpredictability in the memory. A random number generator can provide random numbers based on the voltages. For example, an analog-to-binary converter (ADC) can generate binary numbers based on the voltages, and the random numbers can be based on the binary numbers.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to semiconductor devices, such as semiconductor memory devices. BACKGROUND

[0002] Semiconductor memory devices can include a plurality of memory cells for storing information. The stored information can be encoded as binary data, and each memory cell can store a single bit of information. Memory can use random numbers for various applications. For example, it can be beneficial to perform certain operations with a degree of randomness in their timing, and random numbers can be used to inject randomness. However, semiconductor memory devices can generally be deterministic devices, and it can be difficult to generate random numbers. SUMMARY

[0003] According to embodiments of the present disclosure, an apparatus is provided that includes a memory array including a plurality of word lines, wherein the memory array is configured to access selected ones of the plurality of word lines as part of an access operation; a voltage coupled to the memory array, wherein the voltage changes as part of the access operation; and a random number generator configured to generate a random number based on the voltage.

[0004] According to embodiments of the present disclosure, an apparatus is provided that includes a plurality of memory banks; a plurality of voltages each associated with one of the plurality of memory banks; and a plurality of random number generators each configured to generate a random number based on a respective one of the plurality of voltages.

[0005] According to embodiments of the present disclosure, a method is provided that includes providing a voltage to a memory array; performing an access operation on the memory array, wherein the access operation changes the voltage; and generating a random number based on the voltage. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 A block diagram of a semiconductor device according to embodiments of the present disclosure.

[0007] Figure 2 A block diagram of voltage distribution to different banks of memory according to some embodiments of the present disclosure.

[0008] Figure 3 A block diagram of a random number generator according to embodiments of the present disclosure.

[0009] Figure 4 A block diagram of different organizations of a random number generator according to some embodiments of the present disclosure.

[0010] Figure 5 A block diagram of a refresh control circuit according to embodiments of the present disclosure.

[0011] Figure 6 Block diagram of a method of generating random numbers based on memory voltage in accordance with some embodiments of the disclosure. DETAILED DESCRIPTION

[0012] The following description of certain examples is merely exemplary in nature and is in no way intended to limit the scope of the disclosure, its application, or uses. In the following detailed description of embodiments of the application, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments in which the described systems and methods can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the presently disclosed systems and methods, and it is to be understood that other embodiments can be utilized, and that structural and logical changes can be made without departing from the spirit and scope of the present disclosure. Furthermore, the following detailed description is presented in terms of specific embodiments directed to applying the principles of the present disclosure. As such, this detailed description is not intended to limit the scope of the present disclosure, and is merely intended to provide a description of some embodiments of the present disclosure. To maintain brevity, certain features of the embodiments can be omitted in the following detailed description.

[0013] Semiconductor devices, such as memory devices, can generate one or more random numbers that can be used in various operations of the memory. For example, the memory can periodically sample addresses along an address bus in order to determine the number (and / or rate) of accesses to different addresses, such as to determine whether one or more rows are being hammered. It can be beneficial to sample with a degree of randomness. Random numbers can be used to inject randomness into the timing of the sampling. Various methods can be used to generate random numbers, however, the memory (and generally semiconductor devices) can be deterministic. For example, a seed value can be generated that can then be used to generate a random number. This deterministic behavior can reduce the 'randomness' of the random number, as it can be possible to determine which random number will be generated based on an understanding of the way in which the deterministic process generates random numbers. The deterministic behavior can also reduce inter-device randomness, as it can be possible to guess the random behavior of a device based on an understanding of the process by which random numbers are generated for different devices of the same type. It can be useful to generate random numbers in a manner that is associated with the physical qualities of the device, as the physical qualities can differ even between different devices of the same type.

[0014] The present disclosure relates to devices, systems, and methods for voltage-based random number generation. Memory devices can use a variety of voltages (e.g., to represent signals of different logic levels, to drive various operations, to power various components, etc.). When a memory performs an operation, one or more of the voltages can change (e.g., 'drop') due to current draw at the beginning of the operation. The exact value of this drop can be based in part on the physical structure of the die, which can vary due to differences in production processes. The drop can also be based on which operation is being performed. For example, if an access operation to the memory is being performed, which memory cells are being accessed can change the value of the drop.

[0015] The memory can include a random number generator coupled to one or more voltages of the memory. The random number generator can include an analog-to-digital converter (ADC) that can be coupled to the voltages. In response to various triggering events (e.g., an access operation), the ADC can convert the voltages to digital values. The digital values can be used directly as random numbers, or can be used as seed values for a sequence generator (e.g., a hash circuit, a linear feedback shift register) that generates random numbers based on the seed values. In some embodiments, there can be a different random number generator for each bank of the memory. In some embodiments, the bank-level random numbers can be combined to generate a total memory random number. In some embodiments, the voltage-based random numbers can be combined with another source of randomness (e.g., fusing information, a different random number) to further increase the randomness of the random number. The use of voltage-based random numbers can be advantageous because it can be difficult to control or predict the random numbers, and the circuitry to generate the random numbers (e.g., the ADC) can be a relatively small and simple circuit compared to other types of random number generators.

[0016] Figure 1 A block diagram of a semiconductor device according to embodiments of the present disclosure. The semiconductor device 100 can be a semiconductor memory device, such as a Dynamic Random Access Memory (DRAM) device integrated on a single semiconductor chip.

[0017] The semiconductor device 100 includes a memory array 118. The memory array 118 is shown as including a plurality of memory banks. In Figure 1 In embodiments, the memory array 118 is shown as including eight memory banks BANK0-BANK7. More or fewer banks can be included in the memory array 118 of other embodiments. Each memory bank includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. Selection of the word lines WL is performed by a row decoder 108, and selection of the bit lines BL is performed by a column decoder 110. In Figure 1In this embodiment, row decoder 108 includes a corresponding row decoder for each memory bank, and column decoder 110 includes a corresponding column decoder for each memory bank. Bit line BL is coupled to a corresponding sense amplifier (SAMP). Read data from bit line BL is amplified by the sense amplifier SAMP and transmitted via complementary local data line (LIOT / B), transmission gate (TG), and complementary master data line (MIOT / B) to a read / write amplifier for transmission to local latch 120. The data can then be provided to a serializer (not shown), and subsequently, the serialized data can be provided to the data terminal DQ via I / O circuitry 122. Conversely, write data is transmitted from the DQ pad to local latch 120 via parallelizer 121. Write data is transmitted from local latch 120 to the sense amplifier SAMP via complementary master data line MIOT / B, transmission gate TG, and complementary local data line LIOT / B, and written to the memory cell MC coupled to bit line BL.

[0018] The semiconductor device 100 may employ multiple external terminals, including: a command and address (C / A) terminal coupled to a command and address bus to receive commands and addresses; a CS signal clock terminal for receiving clock CK and / or CK; a data terminal DQ for providing data; and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0019] An external clock CK and / CK are supplied to the clock terminal, which is provided to the input circuit 112. The external clocks are complementary. The input circuit 112 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 106 and to the internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used for timing operations of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 122 to time the operation of the circuits contained in the input / output circuit 122, for example, it is provided to the data receiver to time the reception of written data. The memory device 100 may also include a data strobe terminal DQS. The data strobe signal can be used to manage the timing of write operations to the memory device 100, while one or more system clock signals CLK and / CLK can manage the timing of other operations, such as read operations, refresh operations, and other operations.

[0020] The C / A terminal may supply a memory address. The memory address supplied to the C / A terminal is transmitted to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108 and the decoded column address YADD to the column decoder 110. The address decoder 104 may also supply a decoded group address BADD, which may indicate a group of memory array 118 containing the decoded row address XADD and column address YADD. Commands may be supplied to the C / A terminal. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory (e.g., read commands for performing read operations and write commands for performing write operations), and other commands and operations. Access commands may be associated with one or more row addresses XADD, column addresses YADD, and group addresses BADD to indicate one or more memory cells to be accessed.

[0021] Commands can be provided to command decoder 106 as internal command signals via command / address input circuitry 102. Command decoder 106 includes circuitry for decoding the internal command signals to generate various internal signals and commands for performing operations. For example, command decoder 106 can provide row command signals to select word lines and column command signals to select bit lines.

[0022] Device 100 can receive access commands as read commands. When a read command is received and is promptly supplied to the group address, row address, and column address, read data is read from the memory cells in memory array 118 corresponding to the row and column addresses. The read command is received via command decoder 106, which provides internal commands causing data to be read from the memory cells (e.g., along LIO and MIO) to local latch 120. For example, one or more word lines and one or more digital lines specified by the row and column addresses can be activated, and data can be read from the memory cells to a sense amplifier along the digital lines. The data can be transmitted to read / write amplifier (RWAMP) 120, which can provide the read data to I / O circuitry 122, which in turn can provide the read data to data terminal DQ.

[0023] Device 100 can receive access commands as write commands. When a write command is received and is promptly supplied to the group address, row address, and column address, write data is supplied to the read / write amplifier (RWAMP) 120 via the DQ terminal. The write data supplied to RWAMP 120 is written to the memory cells in memory array 118 corresponding to the row and column addresses. For example, one or more word lines associated with the row address XADD can be activated by coupling to the system voltage. The bit lines associated with the column address can be activated, and write data can be supplied to the sense amplifier along the local I / O line LIOT / B, and then the write data is supplied along the activated bit lines to the memory cells at the intersection of the activated bit lines and word lines. The write data is then written to those memory cells.

[0024] As part of the self-refresh mode, device 100 may also receive commands that cause it to perform one or more refresh operations. In some embodiments, the self-refresh mode command may be externally issued to memory device 100. In some embodiments, the self-refresh mode command may be generated periodically by components of the device. In some embodiments, a refresh signal AREF may also be activated when an external signal indicates a self-refresh enters command. The refresh signal AREF may be a pulse signal activated when command decoder 106 receives a signal indicating entry into self-refresh mode. The refresh signal AREF may be activated immediately after the command input and may thereafter be activated cyclically according to desired internal timing. The refresh signal AREF can be used to control the timing of refresh operations during self-refresh mode. Therefore, refresh operations may continue automatically. A self-refresh exit command may stop the automatic activation of the refresh signal AREF and return it to an idle state. The refresh signal AREF is supplied to refresh control circuitry 116. Refresh control circuitry 116 supplies a refresh row address RXADD to row decoder 108, which may refresh one or more word lines WL indicated by the refresh row address RXADD.

[0025] The power supply terminals are supplied with power potentials VDD and VSS. These power potentials VDD and VSS are supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VOD, VARY, VPERI, etc., based on the power potentials VDD and VSS supplied to the power supply terminals. Internal potential VPP is mainly used in the line decoder 108, internal potentials VOD and VARY are mainly used in the sense amplifier SAMP contained in the memory array 118, and internal potential VPERI is used in most peripheral circuit blocks.

[0026] The power supply terminals are also supplied with power potentials VDDQ and VSSQ. Power potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In embodiments of this disclosure, the power potentials VDDQ and VSSQ supplied to the power supply terminals may be the same as the power potentials VDD and VSS supplied to the power supply terminals. In another embodiment of this disclosure, the power potentials VDDQ and VSSQ supplied to the power supply terminals may be different from the power potentials VDD and VSS supplied to the power supply terminals. The power potentials VDDQ and VSSQ supplied to the power supply terminals are used in the input / output circuit 122 so that power supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0027] One or more of the voltages of memory device 100 may be coupled as inputs to random number generator 126. Random number generator 126 may use one or more voltages to generate random number Rand. Random number Rand may be used by various other circuitry of the memory. Random number generator 126 may be coupled to one or more voltages. In some embodiments, random number generator 126 may receive voltage from voltage generator 124. In some embodiments, random number generator 126 may be coupled to a voltage (e.g., VDD) supplied to the voltage terminals of the memory from an external source. For consistency and brevity, the term VDD will be used to refer to the voltage coupled to random number generator 126; however, it should be understood that any voltage of the memory may be used as an input.

[0028] Random number generator 126 can generate a random number Rand that changes over time. For example, the value of random number Rand can be based on the value of voltage VDD, which can change as the memory performs various operations. In some embodiments, random number generator 126 can update the value of random number Rand continuously (e.g., as quickly as possible). In some embodiments, random number generator 126 can update the value of random number Rand periodically. In some embodiments, random number generator 126 can be triggered by one or more internal signals of the memory (e.g., access signals) to update the value of random number Rand.

[0029] In some embodiments, a single random number generator 126 may be present to generate a total random number Rand for the memory. In some embodiments, multiple random number generators, each coupled to a different voltage of the memory, may be present. For example, the random number generator 126 may be repeated on a group-by-group basis. Each random number generator 126 may be coupled to a voltage associated with the group and may provide random numbers based on the voltage. For example, each random number generator may be coupled to a bus that distributes voltages (e.g., VDD) to the group.

[0030] Figure 2 This is a block diagram illustrating the voltage distribution to different groups of memory according to some embodiments of the present disclosure.Figure 2 Show memory groups (e.g., Figure 1 Examples of how the memory array 118 (those memory groups) can be coupled to the system voltage (e.g., VDD). It should be understood that... Figure 2 A simplified schematic layout is shown for illustrative purposes, and the physical bus and memory die can be arranged in different ways. Similarly, although Figure 2 Only four memory groups are shown in this example, but other example embodiments may use other numbers of memory groups (e.g., 8, 16, 32). The system voltage VDD may represent any number of different voltages supplied to and / or generated by the memory.

[0031] A voltage VDD is supplied to memory groups 210, 220, 230, and 240 along voltage bus 202. Voltage bus 220 may be a conductive element within the memory carrying voltage VDD. Local buses 212, 222, 232, and 242 may couple voltage VDD from voltage bus 202 to groups 210, 220, 230, and 240, respectively. The voltage carried by local buses 212, 222, 232, and 242 can be used to power various operations within groups 210, 220, 230, and 240, respectively. Since groups and local buses can be broadly similar, for simplicity, only the first group 210 and the first local bus 212 will be described in detail.

[0032] Local bus 212 may be a conductive element that couples voltage VDD from voltage bus 202 to memory group 210. Group 210 may contain multiple memory cells arranged along a plurality of word lines, here numbered WL0 to WL0. N As part of the access operation, word lines can be activated by coupling to local bus 212. Multiple switches (not shown) can control whether word lines are coupled to local bus 212, and the switches can be controlled by a row controller (e.g., responding to a row address). Figure 1 108) control.

[0033] When a word line is activated, it can represent a relatively large current draw because the word line may need to be charged to voltage VDD. Therefore, when a word line is activated, there may be a change or 'drop' in the voltage along local bus 212 and voltage bus 202. For example, in the moments immediately following word line activation, the current drawn from the activated word line can cause a voltage drop on local bus 212 and voltage bus 202. When the various drivers restore the bus to VDD, the voltage can then return to VDD. Furthermore, the amount of voltage drop and the duration of the drop can depend on which word line is activated. For example, as... Figure 2In this arrangement, word line WL0 may be closer to voltage bus 202 than word line WLN. Therefore, different resistances may exist along local bus 212 between voltage bus 202 and word line WL0, and between voltage bus 202 and word line WLN. Similarly, the same word line in different groups (e.g., WL1 in group 210 and WL1 in group 230) may cause different amounts and durations of voltage drops in voltage bus 202.

[0034] The voltage on voltage bus 202 can vary as different word lines in different groups are accessed over time. Since the amount and duration of this variation can depend on the accessed word lines, the voltage on voltage bus 202 can vary in a way that is difficult to determine. Furthermore, manufacturing tolerances can mean that even two different memory chips having the same access mode performed on them can have different voltage drops in their respective voltage buses. Therefore, the voltage along the voltage bus can contain elements of randomness and unpredictability, which can be used to generate random numbers.

[0035] Figure 3 This is a block diagram of a random number generator according to embodiments of the present disclosure. In some embodiments, the random number generator 300 may be included in some embodiments. Figure 1 The random number generator 126 receives a voltage VDD and provides a random number Rand based on the voltage VDD. In some embodiments, optional components such as combinational logic 304, sequence generator 306, and / or timing logic 308 further increase the randomness of the random number Rand and / or increase the complexity of the relationship between the voltage VDD and the random number Rand. The value RNG_VDD may be stored in latch 307 and may be used as the random number Rand until the random number generator 300 can generate a new value for the random number (e.g., RNG_VDD_New) and store it in latch 307.

[0036] Various optional components of the random number generator 300 are shown in dashed lines. Any combination of these optional components can be used in the random number generator 300.

[0037] The random number generator 300 includes an analog-to-digital converter (ADC) 302. The ADC 302 converts the analog value of voltage VDD into a digital number RNG_VDD_New. The value RNG_VDD_New can be stored in latch 307 as the value RNG_VDD. As discussed in more detail herein, various methods can be used to determine when to activate the timing signal NewRand, which allows latch 307 to capture the current value of RNG_VDD_New as the new value of RNG_VDD. Due to fluctuations in voltage VDD, the digital value RNG_VDD can be a random number. In some embodiments, the ADC 302 can focus on a specific range of voltage VDD values ​​based on the expected fluctuations in the value of VDD. For example, the maximum value of RNG_VDD can be associated with its fully specified value with the value VDD, and the minimum value of RNG_VDD can be associated with the expected minimum value of VDD during a falling period. The digital value RNG_VDD can be an N-bit binary number. For example, in some embodiments, the digital value RNG_VDD can be a 6-bit binary number. Other numbers of bits (e.g., 4 bits, 8 bits, 10 bits, etc.) can be used in other example embodiments.

[0038] In some embodiments, the ADC 302 may be selected such that it has relatively low accuracy in converting the analog voltage VDD into the digital value RNG_VDD. For example, the ADC 302 may have a large tolerance such that a given value of VDD can produce a first value RNG_VDD at a first time and a second value RNG_VDD at a second time. This reduces the predictability of the random number generator 300, which increases the randomness of the digital value RNG_VDD.

[0039] In some embodiments, the numeric value RNG_VDD can be used directly as the random number Rand (e.g., the combinational logic 304 and sequence generator 306 can be omitted). In some embodiments, the numeric value RNG_VDD can be modified to generate the random number Rand, which can further increase the randomness and / or unpredictability of the random number Rand.

[0040] In some embodiments, combinational logic 304 can be used to combine the numeric value RNG_VDD with another numeric value. For example, a unique identifier value of the memory, such as a fuse ID (FID), can be used. Combinational logic 304 can combine the numeric value RNG_VDD with the FID to produce the value SEED. For example, combinational logic 304 can use one or more XOR logic gates to combine the bits of the FID with the bits of the numeric value RNG_VDD to produce the value SEED. In some embodiments, the value SEED can be used as a random number Rand (e.g., the sequence generator 306 can be omitted).

[0041] In some embodiments, sequence generator 306 can be used to generate a random number Rand based on the value of SEED. For example, sequence generator 306 may include a linear feedback shift register (LFSR) that generates a number based on an input seed value (e.g., the value SEED). Sequence generator 306 may include hash circuitry that maps the N-bit value of SEED to the M-bit value of the random number Rand. In some embodiments, combinational logic 304 may be omitted, and the value RNG_VDD may be directly used as the seed value for sequence generator 306.

[0042] In some embodiments, the random number generator 300 may continuously (e.g., as fast as the circuit is operable) update the value of the random number Rand. In some embodiments, the latch 307 may be omitted from the random number generator 300, and the value RNG_VDD may be directly provided as the random number Rand by the ADC 302.

[0043] In some embodiments, the sequence generator 300 may include sequential logic 308 that controls when a new value for the random number Rand is provided. For example, the sequential logic 308 may provide an activation signal NewRand coupled to a clock terminal of latch 307. When the sequential logic provides the signal NewRand at an active level, the current output of the ADC RNG_VDD_New may be captured in latch 307 and provided as the value RNG_VDD (e.g., overwriting the previous value of RNG_VDD).

[0044] In some implementations, timing logic 308 can compare a previous value of a random number (e.g., RNG_VDD) with the current value of the random number (e.g., RNG_VDD_New) to determine when to update the value of the random number (e.g., when to provide the signal NewRand at an active level). For example, timing logic 308 can periodically compare the current random number RNG_VDD_New with a stored random number RNG_VDD. If the values ​​differ, timing logic 308 can update a counter. When the counter reaches a threshold (e.g., 3, 6, 9, etc.), the signal NewRand can be provided at an active level, and the counter can be reset.

[0045] In some embodiments, the timing logic 308 may use other methods (alternatively or additionally) to determine when to provide the signal NewRand at an active level. For example, the timing logic 308 may be coupled to a clock signal (or may include an oscillator and generate its own clock signal) and may periodically provide the signal NewRand. Example timing logic 308 may be coupled to memory signals (e.g., word line activation signals) and may provide the signal NewRand in response to those signals. Other methods of controlling timing may be used in other embodiments.

[0046] Figure 4 This is a block diagram of different organizations of a random number generator according to some embodiments of the present disclosure. Figure 4 Show multiple random number generators, each of which can contain relative to Figure 3 The random number generator 300 comprises one or more of the features and components discussed.

[0047] Each of the random number generators 402, 404, and 406 can be associated with a different set of memory. For example, the first random number generator 402 can be associated with a first set (e.g., ...). Figure 2 The second random number generator 404 can be associated with the second group (e.g., 210), and can be associated with the second group (e.g., Figure 2 (220) associated with, etc. Each of the random number generators 402-406 may be coupled to a voltage associated with the group. For example, the first random number generator 402 may be coupled to a first voltage Bank0_VDD. The first voltage Bank0_VDD may represent a voltage along a local voltage bus (e.g., ...). Figure 2 The voltage of 212).

[0048] Therefore, each of the random number generators 402-406 can provide random numbers Rand_Bank0 to Rand_BankN, respectively, associated with a corresponding group. Each group of random numbers can be used by group-specific circuitry. For example, the first group of random numbers, Rand_Bank0, can be used to inject randomness into the refresh control circuitry (e.g., Figure 1 In the operation of 116).

[0049] In some embodiments, one or more of the group-level random numbers Rand_Bank0 to Rand_BankN can be combined to generate a total random number Rand. The memory may include an optional total random number generator 408 that can combine group-level random numbers into the total random number Rand. In some embodiments, the total random number generator 408 may combine random numbers, for example, with one or more XOR gates. In some embodiments, the total random number generator 408 may include other sources of randomness (e.g., LFSR) and may use the combined group-level random numbers as a seed.

[0050] In some embodiments, different groups of random number generators 402 to 406 may be active at different times. For example, random number generators 402 and 404 may be active (e.g., providing values ​​for Rand_Bank0 and Rand_Bank1, respectively), while group-level RNG 406 may be inactive (e.g., not providing the signal Rand_BankN). In some embodiments, random number generators 402-406 may be activated based on which groups are active (e.g., group address BADD).

[0051] In some embodiments, groups can be grouped together into a cluster, and the cluster can be used to determine when to update the random number associated with the group. For example, when any one of the groups in the cluster receives an access command (e.g., as indicated by the group address BADD), then all random number generators associated with the group in the cluster can update their random numbers.

[0052] Figure 5 This is a block diagram of a refresh control circuit according to an embodiment of the present disclosure. In some embodiments, the refresh control circuit 516 may be included in... Figure 1 The refresh control circuit 516 is shown. Some internal components and signals of the refresh control circuit 516 are shown to illustrate its operation. Dashed lines 518 are shown to indicate that in some embodiments, each of the components (e.g., the refresh control circuit 516 and the row decoder 508) may correspond to a specific memory group, and these components may be repeated for each memory group. Therefore, multiple refresh control circuits 516, random number generators 540, and row decoders 508 may exist. For the sake of brevity, only the components for a single group will be described.

[0053] DRAM interface 526 can provide one or more signals to address refresh control circuitry 516 and row decoder 508. Refresh control circuitry 516 may include sampling timing circuitry 530, intruder detector circuitry 232, row hammer refresh (RHR) state control circuitry 536, and refresh address generator 534. DRAM interface 526 can provide one or more control signals, such as refresh signal AREF, activation and precharge signals ACT / Pre, and row address XADD. When the group associated with refresh control circuitry 516 is in refresh mode, refresh control circuitry 516 provides a timing-based refresh address XADD based on refresh signal AREF.

[0054] DRAM interface 526 can also provide a voltage VDD to random number generator 540, which in turn can provide a random number Rand based on the voltage VDD. Random number generator 540 can be a group-level circuit (e.g., for each group repetition) or a total random number generator that provides a single random number Rand to each refresh control circuit 516 of the memory. In some embodiments, random number generator 540 may be included in... Figure 1 Random number generator 126 Figure 3 Random number generator 300 and / or Figure 4 In the random number generator 402-408. The random number Rand can be used by one or more components of the refresh control circuit 516.

[0055] Figure 5The example embodiments illustrate a specific configuration in which a random number Rand is used by the sampling timing circuitry 530 and the intruder detector circuitry 532. However, in other embodiments, the random number Rand may be used by one or the other of the sampling timing circuitry 530 and the intruder detector circuitry 532. In some embodiments, the sampling timing circuitry 530 may use a first random number, and a second random number may be used by the intruder detector circuitry 532. In some embodiments, other components of the refresh control circuitry 516 may use the random number Rand.

[0056] The intruder detector circuit 532 can sample the current row address XADD in response to the activation of the sampling signal ArmSample provided by the sampling timing circuit 530. The intruder detector circuit 532 can be coupled to all row addresses XADD transmitted along the row address bus, but can only receive (e.g., process, pay attention to) the current value of the row address XADD when the sampling signal ArmSample is activated. In other example embodiments, sampling may not be used.

[0057] The received row address (the sampled address or all addresses) can be stored in the intruder circuit 532 and / or compared with previously stored addresses. The intruder detector circuit 532 can provide a matching address HitXADD based on the current row address XADD and / or the previous row address. The RHR state control circuit 536 can provide a signal RHR to indicate that a row hammer refresh should occur (e.g., refresh of the victim row corresponding to the identified intruder row). The RHR state control circuit 536 can also provide an internal refresh signal IREF to indicate that an automatic refresh should occur.

[0058] In response to the activation of RHR or IREF, refresh address generator 534 can provide a refresh address RXADD, which can be an auto-refresh address or one or more victim addresses corresponding to a victim row of an aggressor row, the aggressor row corresponding to a matching address HitXADD. RHR state control circuitry 536 can provide a set of activations of RHR and IREF in response to refresh signal AREF. Line decoder 508 can perform a refresh operation in response to refresh address RXADD and line hammer refresh signal RHR. Line decoder 508 can perform an auto-refresh operation based on refresh address RXADD and internal refresh signal IREF.

[0059] DRAM interface 526 may represent one or more components that provide signals to components of a group. In some embodiments, DRAM interface 526 may represent a device coupled to a semiconductor memory device (e.g., Figure 1 The memory controller of the device 100). In some embodiments, the DRAM interface 526 may represent, for example, Figure 1The command address input circuit 102, address decoder 104, and / or command decoder 106 are components. The DRAM interface 526 provides row address XADD, refresh signal AREF, voltage VDD, and access signals such as activation signal ACT and precharge signal Pre. Although Figure 2 Not shown, but the DRAM interface 526 may also provide a group address BADD, which indicates where the accessed row address XADD is located. The group address BADD can activate specific refresh control circuitry 516 associated with the group indicated by the group address BADD. The DRAM interface may also put the refresh control circuitry into refresh mode by providing a refresh signal AREF for activation. The refresh signal AREF may be a periodic signal provided during refresh mode, which indicates the timing of refresh operations. Typically, access signals ACT and Pre may be provided as part of the access operation along with the row address XADD. An activation signal ACT may be provided to activate a given group of memory. A precharge signal Pre may be provided to precharge a given group of memory. The row address XADD may be a signal containing multiple bits (which may be transmitted serially or in parallel) and may correspond to a specific row of the activated memory group.

[0060] exist Figure 2 In an example embodiment, refresh control circuitry 516 utilizes sampling to monitor a portion of the row address XADD provided along the row address bus. Therefore, instead of responding to each row address, refresh control circuitry 516 can sample the current value of the row address XADD on the row address bus and determine which addresses are intruders based on the sampled row addresses. The timing of sampling by refresh control circuitry 516 can be controlled by sampling timing circuitry 530, which provides a sampling signal ArmSample. Sampling timing circuitry 530 can provide activation of the sampling signal ArmSample, and each activation of the signal ArmSample indicates that the current value of the row address should be sampled. Activation of ArmSample can be a 'pulse', where ArmSample rises to a high logic level and then returns to a low logic level.

[0061] The activation of the signal ArmSample can have periodic timing, random timing, semi-random timing, pseudo-random timing, or a combination thereof. The timing of the sampling timing circuit 530 providing the signal ArmSample can be based on a random number Rand. For example, an oscillator can increment a counter, and when the counter matches the value of the random number Rand, the signal ArmSample can be provided. After providing the signal ArmSample, the sampling timing circuit 530 can trigger RNG 540 to provide a new value for the random number Rand. In other embodiments, sampling may be omitted, and the intruder detector circuit 532 can receive each value of the row address XADD along the row address bus. In such embodiments, the sampling timing circuit 530 and the sampling signal ArmSample can be omitted.

[0062] The intruder detector circuit 532 receives the row address XADD from the DRAM interface 526 and the signal ArmSample from the sampling timing circuit 530. When the DRAM interface 526 directs access operations (e.g., read and write operations) to the memory cell array (e.g., ...), ... Figure 1 When the memory cell array 118 is in a different row, the row address XADD on the row address bus can be changed. Whenever the intruder detector circuit 532 receives the activation of the signal ArmSample (e.g., a pulse), the intruder detector circuit 532 can sample the current value of XADD.

[0063] Intruder detector circuit 532 can determine an intruder address based on one or more of the sampled row addresses, and then provide the determined intruder address as a matching address HitXADD. Intruder detector circuit 532 may include a data storage unit (e.g., multiple registers) for storing the sampled row addresses. In some example embodiments, when intruder detector circuit 532 (e.g., in response to activation of ArmSample) samples a new value for row address XADD, the intruder detector circuit can compare the sampled row address with an address stored in the data storage unit. If a match exists between the sampled address and one of the stored addresses, intruder detector circuit 532 can provide a match signal Match. In some example embodiments, the matching address HitXADD may be one of the addresses stored in intruder detector circuit 532 that most frequently matches the sampled address XADD. For example, the intruder detector circuit 532 can count the number of times each address XADD is received and provide the address that has been received the most times as the matching address HitXADD.

[0064] In some embodiments, the intruder detector circuit 532 may count the number of times an address is received, and mark the address as a matching address (HitXADD) when the count exceeds a threshold. In some embodiments, the threshold may vary based on a random number (Rand). In some embodiments, the count value may vary based on a random number (Rand).

[0065] The memory device can perform a series of auto-refresh operations to periodically refresh rows of the memory device as part of a refresh mode. RHR state control circuitry 536 can determine whether a given refresh operation is an auto-refresh operation or a target refresh operation. An RHR signal can be generated to indicate that the device should refresh a specific target row (e.g., a victim row) rather than an address from an auto-refresh address sequence. RHR state control circuitry 536 can also provide an internal refresh signal IREF, which indicates that an auto-refresh operation should occur. In some embodiments, signals RHR and IREF can be generated such that they are not active simultaneously (e.g., neither is simultaneously at a high logic level). In some embodiments, IREF can be activated for each refresh operation, and an auto-refresh operation can be performed unless RHR is also active; if RHR is also active, a target refresh operation is performed instead. RHR state control circuitry can perform a series of auto-refresh operations and target refresh operations in response to the activation of one or more refresh signals AREF.

[0066] In some embodiments, the refresh control circuit 516 may perform multiple refresh operations in response to each activation of the refresh signal AREF. For example, whenever the refresh signal AREF is received, the refresh control circuit 516 may perform K different refresh operations by providing K different refresh addresses RXADD. Each refresh operation may be referred to as a 'pump'. Each of the K different refresh operations may be an automatic refresh operation or a target refresh operation. In some embodiments, the number of target and automatic refresh operations in each group of pumps may be constant in response to the activation of the refresh signal AREF. In some embodiments, the number may vary.

[0067] The refresh address generator 534 can receive a row hammer refresh signal RHR and a matching address HitXADD. The matching address HitXADD can represent an aggressor row. The refresh address generator 534 can determine the location of one or more victim rows based on the matching address HitXADD, and provide the matching address as a refresh address RXADD when the signal RHR indicates a target refresh operation. In some embodiments, victim rows may include rows that are physically adjacent to the aggressor rows (e.g., HitXADD+1 and HitXADD-1). In some embodiments, victim rows may also include rows that are physically adjacent to physically adjacent rows of the aggressor rows (e.g., HitXADD+2 and HitXADD-2). Other relationships between victim rows and identified aggressor rows can be used in other instances. For example, + / -3, + / -4, and / or other rows may also be refreshed.

[0068] The refresh address generator 534 can determine the value of the refresh address RXADD based on the row hammer refresh signal RHR. In some embodiments, when the signal RHR is inactive, the refresh address generator 534 can provide one of a series of auto-refresh addresses. When the signal RHR is active, the refresh address generator 534 can provide a target refresh address, such as a victim address, as the refresh address RXADD. In some embodiments, the refresh address generator 534 can count the activation of the signal RHR and can provide closer victim rows (e.g., HitXADD+ / -1) more frequently than victim rows further away from the aggressor address (e.g., HitXADD+ / -2).

[0069] The row decoder 508 can perform one or more operations on the memory array (not shown) based on received signals and addresses. For example, in response to the activation signal ACT and the row address XADD (and IREF and RHR at low logic levels), the row decoder 508 can direct one or more access operations (e.g., read operations) to the specified row address XADD. In response to IREF and / or RHR signal activity, the row decoder 508 can refresh the refresh address RXADD.

[0070] Figure 6 This is a block diagram of a method for generating random numbers based on memory voltage according to some embodiments of the present disclosure. In some embodiments, method 600 may be... Figures 1-5 One or more of the devices and components represented in the text.

[0071] Method 600 may typically begin at block 610, which describes providing a voltage to a memory array. The memory array may receive a system voltage (e.g., VDD) that can be used to power various operations of the memory. The voltage may be supplied along a voltage bus (e.g., ...). Figure 2 The voltage can be distributed along various group-level buses (e.g., 202).Figure 2 (212, 222, 232, and 242) are distributed to the memory group. In some embodiments, the voltage along the group-level bus can be used as a voltage.

[0072] Block 620 typically follows block 610, and describes performing an access operation on the memory array. Performing an access operation can change the voltage. For example, an access operation may involve activating word lines by coupling one or more word lines of the memory array to a voltage. This can represent a relatively large voltage draw, which can cause a voltage drop. The value and duration of the drop may be based in part on which word lines of the memory are activated as part of the access operation.

[0073] Box 630 typically follows box 620, and describes the generation of random numbers based on voltage. Because voltage can vary over time (e.g., using various access operations), random numbers can have relatively high randomness and / or unpredictability. Generating random numbers may involve generating binary numbers based on voltage using an analog-to-digital converter (ADC). In some embodiments, the binary number may be combined with additional values ​​(e.g., a fuse identifier) ​​to produce a combined value, and the random number may be based on said combined value. In some embodiments, the binary number may be used as a seed by a sequence generator to generate random numbers. In some embodiments, the binary number may be used as the random number itself.

[0074] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with or separated from one or more other examples, embodiments, and / or processes and / or performed in a separate device or device portion of a system, apparatus, or method according to the present invention.

[0075] Finally, the foregoing discussion is intended to be illustrative of the system of the invention and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, while the system of the invention has been described in detail with reference to exemplary embodiments, it should be understood that many modifications and alternative embodiments can be devised by those skilled in the art without departing from the broader and established spirit and scope of the system of the invention as set forth in the appended claims. Thus, the specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A memory device comprising: a memory array comprising a plurality of memory cells arranged along word lines, wherein the memory array is configured to access memory cells along a selected one of the plurality of word lines by activating the selected one of the plurality of word lines as part of an access operation; a supply voltage coupled to the memory array, wherein a value of the supply voltage changes to a changed value as part of the access operation, wherein current drawn from the activated selected one is configured to cause the value of the supply voltage to change to the changed value; and a random number generator configured to generate a random number based on the changed value.

2. The memory device of claim 1, wherein the random number generator includes an analog-to-digital converter (ADC) configured to generate a binary number based on the changed value of the supply voltage, and wherein the random number is based on the binary number.

3. The memory device of claim 2, wherein the random number generator further comprises a sequence generator configured to use the binary number as a seed to generate the random number.

4. The memory device of claim 2, wherein the random number generator further comprises combinational logic circuitry configured to generate a seed value based on the binary number and an additional number, wherein the random number is based on the seed value.

5. The memory device of claim 4, wherein the additional number is a fuse identification number.

6. The memory device of claim 1, wherein the random number generator comprises timing logic configured to control when a new value of the random number is generated.

7. The memory device of claim 1, further comprising refresh control circuitry configured to sample a row address off a row address bus in response to a sample signal, and configured to refresh at least one of the plurality of word lines based in part on the sampled row address, wherein the sample signal possesses a timing based on the random number.

8. The memory device of claim 1, wherein the voltage is a voltage of a bank voltage bus associated with one of a plurality of banks of the memory array.

9. A memory device comprising: a plurality of memory banks, wherein each of the plurality of memory banks comprises a plurality of memory cells arranged along word lines, wherein the each of the plurality of memory banks is configured to access memory cells along a selected one of the plurality of word lines by activating the selected one of the plurality of word lines as part of an access operation for a respective associated one of the plurality of memory banks; a plurality of supply voltages, wherein current drawn from the activated selected one is configured to cause a value of each of the plurality of supply voltages to change to a respective changed value as part of the access operation; and a plurality of random number generators each configured to generate a respective random number based on a respective one of the respective changed values.

10. The memory device of claim 9, wherein each of the plurality of random number generators includes an analog-to-digital converter (ADC) configured to generate a binary number based on the respective changed value of the respective one of the plurality of supply voltages, and wherein the respective random number is based on the binary number.

11. The memory device of claim 10, wherein each of the plurality of random number generators further comprises a sequence generator configured to use the binary number as a seed to generate the respective random number.

12. The memory device of claim 10, wherein each of the plurality of random number generators further comprises combinational logic circuitry configured to generate a seed value based on the binary number and an additional number, wherein the respective random number is based on the seed value.

13. The memory device of claim 12, wherein the additional number is a fuse identification number.

14. The memory device of claim 9, wherein each of the plurality of random number generators comprises timing logic configured to control when a new value of the respective random number is generated.

15. The memory device of claim 9, further comprising refresh control circuitry configured to sample a row address off a row address bus in response to a sample signal, and configured to refresh at least one of the plurality of word lines based in part on the sampled row address, wherein the sample signal possesses a timing based on the respective random number.

10. The memory device of claim 9, further comprising a total random number generator configured to generate a total random number based on at least two of the random numbers generated by at least two of the plurality of random number generators.

11. The memory device of claim 9, wherein a portion of the plurality of random number generators are active while a remaining portion of the plurality of random number generators are inactive.

12. The memory device of claim 9, wherein each of the plurality of random number generators comprises an analog-to-digital converter configured to generate a binary number based on a value of the associated one of the plurality of voltages.

13. The memory device of claim 12, wherein each of the plurality of random number generators further comprises a sequence generator configured to use the binary number as a seed to generate the respective random number.

14. The memory device of claim 12, wherein each of the plurality of random number generators further comprises combinational logic circuitry, and wherein the respective random number is based in part on the binary number and an additional value.

15. A method of operating a memory, comprising: providing a first supply voltage to a memory array, wherein the memory array comprises a plurality of memory cells arranged along word lines, wherein the memory array is configured to access memory cells along a selected one of the plurality of word lines as part of an access operation by activating the selected one of the plurality of word lines; performing the access operation on the memory array, wherein as part of the access operation, a current drawn from the activated selected one is configured to cause a change in a value of the first supply voltage to a first changed value; and generating a random number based on the first changed value.

16. The method of claim 15, further comprising generating a binary number based on the first changed value with an analog-to-digital converter (ADC), wherein the random number is based on the binary number.

17. The method of claim 16, further comprising combining the binary number with an additional value to generate a combined value, wherein the random number is based on the combined value.

18. The method of claim 16, further comprising generating the random number by using the binary number as a seed for a sequence generator circuit.

19. The method of claim 15, further comprising: generating a first random number based on the first changed value, wherein the first supply voltage is associated with a first group of the memory array; generating a second random number based on a second changed value of a second supply voltage associated with a second group of the memory array; and generating the random number based on the first random number and the second random number.

20. The method of claim 15, further comprising sampling a row address along a row address bus with a timing based on the random number. ​

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