high speed circuit

Abstract

A high speed circuit is provided. The high speed circuit comprises a driver circuit and a level shifter. The driver circuit comprises high voltage components operating in a high voltage domain. The level shifter comprises low voltage components operating in a low voltage domain, wherein the level shifter converts signals from the low voltage domain to the high voltage domain to generate control signals for the driver circuit. By the invention, a high speed and robust high speed circuit is provided.

Description

TECHNICAL FIELD

[0001] The present invention relates to input / output (I / O) design of high-speed circuits. BACKGROUND

[0002] High-speed circuits for implementing memories, transmitters, etc. usually use low-voltage components. Low-voltage components, also known as core devices, operate at a lower voltage (e.g., 0.95V). High-voltage devices, which operate at a higher voltage (e.g., 1.2V or 1.5V), are more robust but much slower than low-voltage components.

[0003] How to design a high-speed and robust circuit is an important issue in the art. SUMMARY

[0004] In view of the above, the present invention provides a high-speed circuit with a driver circuit. The high-speed circuit has a driver circuit and a level shifter. The driver circuit includes high-voltage components operating in a high-voltage domain. The level shifter includes low-voltage components operating in a low-voltage domain, wherein the level shifter converts a signal from the low-voltage domain to the high-voltage domain to generate a control signal for the driver circuit.

[0005] Specifically, the high-speed circuit can include a protection voltage generator, which converts a supply voltage and a supply ground voltage, to generate a first DC bias voltage and a second DC bias voltage, to bias the low-voltage components of the level shifter. The protection voltage generator is an on-chip circuit, which has input terminals coupled to a supply voltage terminal and a supply ground terminal of the high-speed circuit to receive the supply voltage and the supply ground voltage, respectively. The first voltage difference between the supply voltage and the first DC bias voltage and the second voltage difference between the second DC bias voltage and the supply ground voltage are both within the low-voltage domain. Thus, the low-voltage components in the level shifter are protected from being damaged.

[0006] The low-voltage components of the level shifter can include an input transistor and a protection transistor. The gate of the protection transistor is coupled to the first DC bias voltage or the second DC bias voltage. Since the transistor gate does not draw current, there is no need to design a strong protection voltage generator to provide the first DC bias voltage and the second DC bias voltage. In the conventional art, an extra capacitor is needed to convert a strong supply to a level suitable for the low-voltage components outside the high-speed circuit, thus the conventional circuit usually has an extra pad (or ball) to couple to the external capacitor to receive the proper power. However, in the present invention, the external capacitor and the additional pad (or ball) can be eliminated.

[0007] By the present invention, a high-speed and robust high-speed circuit is provided.

[0008] These and other objects of the present invention will become readily apparent after a reading of the following detailed description of the preferred embodiments in conjunction with the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 A high-speed circuit with a driver circuit according to an exemplary embodiment of the present invention is shown.

[0010] Figure 2 A driver circuit and a level shifter according to an exemplary embodiment of the present invention are depicted.

[0011] Figure 3 A level shifter according to another exemplary embodiment of the present invention is depicted.

[0012] Figure 4 A level shifter according to another exemplary embodiment of the present invention is depicted.

[0013] Figure 5 A pre-driver according to an exemplary embodiment of the present invention is depicted. DETAILED DESCRIPTION

[0014] Certain terms are used throughout the description and claims to refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers can refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to." Also, the term "couple" or "coupled" as used herein is intended to mean either an indirect or direct electrical connection. Thus, if a first device electrically "connects" to a second device, that connection can be through one or more intervening devices or directly, without any intervening devices.

[0015] The following description is made for the purpose of illustrating the general principles of the present invention and is not meant to limit the inventive concepts claimed herein. The scope of the present invention should be determined with reference to the appended claims.

[0016] Figure 1A high-speed circuit 100 with a driver circuit 102 is shown according to an exemplary embodiment of the present application. In addition to the driver circuit 102, the high-speed circuit 100 also has a level shifter 104. The driver circuit 102 includes high-voltage components (e.g., thick-gate transistors) that operate in a high-voltage domain (e.g., GND ~ 1.2V or GND ~ 1.5V). The level shifter 104 includes low-voltage components (e.g., thin-gate transistors) that operate in a low-voltage domain (e.g., GND ~ 0.95V). The level shifter 104 converts signals from the low-voltage domain to the high-voltage domain to generate control signals CS for the driver circuit 102.

[0017] In particular, the high-speed circuit 100 can include a protection voltage generator 106 that converts the supply voltage VDD and the supply ground voltage VSS into two different DC bias voltages VBP and VBN to bias the low-voltage components of the level shifter 104. The protection voltage generator 106 can be an on-chip circuit that has input terminals coupled to a supply voltage terminal AVDDIO and a supply ground terminal AVSSIO of the high-speed circuit 100 to receive the supply voltage VDD and the supply ground voltage VSS from a power supply. The power supply can be configured external to the high-speed circuit 100. In another exemplary embodiment of the present application, the power supply can also be configured on the high-speed circuit 100. A first voltage difference (VDD-VBP) is the difference between the supply voltage VDD and the DC bias voltage VBP. A second voltage difference (VBN-VSS) is the voltage difference between the DC bias voltage VBN and the supply ground voltage VSS. Both the first voltage difference (VDD-VBP) and the second voltage difference (VBN-VSS) are within the low-voltage domain.

[0018] In an exemplary embodiment where VDD is 1.5V and VSS is 0V, VBP is 0.55V and VBN is 0.95V to fall within the low-voltage domain of 0V ~ 0.95V. In an exemplary embodiment where VDD is 1.2V and VSS is 0V, VBP is 0.25V and VBN is 0.95V to fall within the low-voltage domain of 0V ~ 0.95V.

[0019] The low voltage components of the level shifter 104 include input transistors and protection transistors. The gates of the protection transistors are coupled to a DC bias voltage VBP or VBN. Since the transistor gate does not draw current, there is no need to design a strong protection voltage generator to provide the DC bias voltage VBP and VBN. In the conventional art, an extra capacitor is needed to convert the strong power supply to a proper level suitable for the low voltage components, thus the conventional high speed circuit usually needs an extra pad (or solder ball) to couple with an external capacitor to receive the proper power. However, in the present invention, the external capacitor and the additional pad (or solder ball) can be saved. As shown, the high speed circuit 100 does not use an extra pad (or solder ball) to receive any dedicated power supply for the low voltage components of the high speed circuit 100.

[0020] In some example embodiments, the gate voltage of the protection transistors within the level shifter 104 is related to the DC bias voltage VBP or VBN, but not limited thereto.

[0021] In some example embodiments, the protection voltage generator 106 is a low dropout regulator (LDO). The low dropout regulator can include low voltage components.

[0022] Figure 2 A driver circuit 202 and a level shifter 204 according to example embodiments of the present invention are depicted. The driver circuit 202 includes a high voltage p-channel transistor (e.g., thick gate PMOS) Mp_HV, resistors Rl and R2, and a high voltage n-channel transistor (e.g., thick gate NMOS) Mn_HV connected in series between a supply voltage terminal AVDDIO and a supply ground terminal AVSSIO. The supply voltage terminal AVDDIO is connected to the source terminal of the high voltage p-channel transistor Mp_HV, the drain terminal of the high voltage p-channel transistor Mp_HV is connected to the drain terminal of the high voltage n-channel transistor Mn_HV through the resistors Rl and R2, and the source terminal of the high voltage n-channel transistor Mn_HV is connected to the supply ground terminal AVSSIO. The connection terminal between the resistors Rl and R2 is the output terminal (I / O) of the driver circuit 202. The control signals CS1 and CS2 generated by the level shifter 204 are coupled to the gate terminal of the high voltage p-channel transistor Mp_HV and the gate terminal of the high voltage n-channel transistor Mn_HV, respectively.

[0023] The level shifter 204 includes sub-circuits 212 and 214 that output control signals CS1 and CS2, respectively. The sub-circuits 212 and 214 can be the same circuit, but not limited thereto.

[0024] As shown in sub-circuit 212, each sub-circuit includes a low voltage current mirror (e.g., formed from thin gate transistors) 216, a low voltage input pair (e.g., formed from thin gate transistors to receive a differential signal pair DIN and DINB from a preceding stage) 218, and a low voltage protection circuit (e.g., formed from thin gate transistors) 220. The low voltage current mirror 216 is coupled to a supply voltage terminal AVDDIO. The low voltage protection circuit 220 is coupled between the low voltage current mirror 216 and the low voltage input pair 218 and uses a protection transistor whose gate is biased by a DC bias voltage VBP or VBN. A control signal CS1 can be obtained from a connection between an output of the low voltage current mirror 216 and the low voltage protection circuit 220. A control signal CS2 can be obtained in a similar manner.

[0025] As shown, the low voltage protection circuit 220 includes a low voltage p-channel transistor (e.g., a thin gate PMOS) 222 and two low voltage n-channel transistors (e.g., two thin gate NMOSs) 224 and 226. A first terminal of the low voltage current mirror 216 is coupled to a drain terminal of the low voltage n-channel transistor 224, and a second terminal (i.e., an output terminal of the low voltage current mirror 216) is coupled to a source terminal of the low voltage p-channel transistor 222. A source terminal of the low voltage n-channel transistor 224 is coupled to a drain terminal of a positive transistor 228 of the low voltage input pair 218. A drain terminal of the low voltage n-channel transistor 226 is coupled to a drain terminal of the low voltage p-channel transistor 222, and a source terminal thereof is coupled to a drain terminal of a negative transistor 230 of the low voltage input pair 218. A gate terminal of the low voltage p-channel transistor 222 is coupled to the DC bias voltage VBP. Gate terminals of the low voltage n-channel transistors 224 and 226 are coupled to the DC bias voltage VBN. The control signal CS1 can also be obtained from a connection between the low voltage p-channel transistor 222 and the low voltage n-channel transistor 226. The control signal CS2 can be obtained in a similar manner.

[0026] Figure 3 A level shifter 304 according to another exemplary embodiment of the present application is depicted. Each sub-circuit (see 312) includes a high voltage current mirror 316 (e.g., formed from thick gate transistors), a low voltage input pair 318, and a low voltage protection circuit 320. The high voltage current mirror 316 is coupled to a supply voltage terminal AVDDIO. The low voltage protection circuit 320 uses a low voltage protection transistor (e.g., a thin gate transistor) biased by a DC bias voltage VBP (and / or VBN) and is coupled between the high voltage current mirror 316 and the low voltage input pair 318. A control signal CS1 is obtained from a connection between an output of the high voltage current mirror 316 and the low voltage protection circuit 320. A control signal CS2 can be provided in a similar manner.

[0027] Figure 4A level shifter 404 according to another exemplary embodiment of the present application is depicted. Each sub-circuit (referable 412) includes a high voltage cross-coupled pair (e.g., formed by thick gate transistors) 416, a low voltage input pair 418, and a low voltage protection circuit 420. The high voltage cross-coupled pair 416 is coupled to a supply voltage terminal AVDDIO. The low voltage protection circuit 420 uses a low voltage protection transistor (e.g., a thin gate transistor) biased by a DC bias voltage VBP (and / or VBN), and is coupled between the high voltage cross-coupled pair 416 and the low voltage input pair 418. Control signal CS1 is taken from a connection between an output of the high voltage cross-coupled pair 416 and the low voltage protection circuit 420. Control signal CS2 can be taken in a similar manner.

[0028] In another exemplary embodiment, the high voltage cross-coupled pair 416 can be replaced by a low voltage cross-coupled pair formed by thin gate transistors.

[0029] In some exemplary embodiments, there can be a pre-driver coupled between the level shifter and the driver circuit.

[0030] Figure 5 A pre-driver 500 according to an exemplary embodiment of the present application is depicted. The pre-driver 500 includes a high voltage component (e.g., a power amplifier formed by thick gate transistors) and has supply terminals coupled to a supply voltage terminal AVDDIO and a supply ground terminal AVSSIO. Control signals CS1 and CS2 generated by the level shifter 204 are coupled through the pre-driver 500 to the gate of a high voltage p-channel transistor Mp_HV and the gate of a high voltage n-channel transistor Mn_HV, respectively.

[0031] The foregoing high speed circuit can be implemented as a high speed chip having the foregoing high voltage driver circuit that can operate with a memory chip. The robust driver circuit can drive input and output (I / O) pins of the high speed chip coupled to the memory chip.

[0032] The foregoing high speed circuit having a driver circuit can be a transmitter circuit. The robust driver circuit drives an output pin of the transmitter circuit.

[0033] In another exemplary embodiment, the high speed circuit 100 can be designed to drive a memory module (e.g., a DDR3 or DDR4 SDRAM).

[0034] While this application has been described by way of example and preferred embodiment, it is understood that this application is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and equivalent arrangements (which would be apparent to those skilled in the art) included within the scope of the appended claims. Accordingly, the scope of the claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims

1. A high-speed circuit, comprising: Driver circuitry, including high-voltage components operating in the high-voltage domain; as well as A level shifter, including a low-voltage component operating in a low-voltage domain, wherein the level shifter converts a signal from the low-voltage domain to the high-voltage domain to generate a control signal for the driver circuitry; The low-voltage component of the level converter includes an input transistor and a protection transistor coupled to the input transistor, wherein the protection transistor is biased to protect the low-voltage component of the level converter. The driver circuit includes a high-voltage p-channel transistor, a first resistor, a second resistor, and a high-voltage n-channel transistor connected in series between the power supply voltage terminal and the power supply ground terminal of the high-speed circuit. The power supply voltage terminal is connected to the source terminal of the high-voltage p-channel transistor, the drain terminal of the high-voltage p-channel transistor is connected to the drain terminal of the high-voltage n-channel transistor through the first resistor and the second resistor, and the source terminal of the high-voltage n-channel transistor is connected to the power supply ground terminal. The connection between the first resistor and the second resistor is the output terminal of the driver circuit; and The first control signal and the second control signal generated by the level converter are respectively coupled to the gate of the high-voltage p-channel transistor and the gate of the high-voltage n-channel transistor.

2. The high-speed circuit as described in claim 1 further includes: The protection voltage generator converts the power supply voltage and the power supply ground voltage to generate a first DC bias voltage and a second DC bias voltage to bias the low-voltage component of the level converter.

3. The high-speed circuit as described in claim 2, wherein: The protection voltage generator is an internal circuit of the chip, and its input terminal is coupled to the power supply voltage terminal and the power supply ground terminal of the high-speed circuit to receive the power supply voltage and the power supply ground voltage respectively. as well as The first voltage difference between the power supply voltage and the first DC bias voltage, and the second voltage difference between the second DC bias voltage and the power supply ground voltage, are both within the low voltage domain.

4. The high-speed circuit as described in claim 2, wherein: The gate terminal of the protection transistor is coupled to either the first DC bias voltage or the second DC bias voltage.

5. The high-speed circuit as described in claim 2, wherein: The gate voltage of the protection transistor is related to either the first DC bias voltage or the second DC bias voltage.

6. The high-speed circuit as described in claim 1 further includes: A pre-driver, the pre-driver including a high-voltage component, the power supply terminal of the pre-driver being coupled to the power supply voltage terminal and the power supply ground terminal; as well as The first control signal and the second control signal generated by the level converter are coupled to the gate of the high-voltage p-channel transistor and the gate of the high-voltage n-channel transistor, respectively, through the pre-driver.

7. The high-speed circuit as described in claim 1, wherein: The level converter includes a first sub-circuit and a second sub-circuit that respectively output the first control signal and the second control signal; Both the first sub-circuit and the second sub-circuit include a low-voltage current mirror, a low-voltage input pair, and a low-voltage protection circuit. The low-voltage current mirror is coupled to the power supply voltage terminal; The low-voltage protection circuit has a protection transistor and is coupled between the low-voltage current mirror and the low-voltage input pair; as well as The first control signal or the second control signal is obtained from the connection between the output terminal of the low-voltage current mirror and the low-voltage protection circuit.

8. The high-speed circuit as described in claim 1, wherein: The level converter includes a first sub-circuit and a second sub-circuit that respectively output the first control signal and the second control signal; Both the first sub-circuit and the second sub-circuit include a low-voltage current mirror, a low-voltage input pair, a low-voltage p-channel transistor, a first low-voltage n-channel transistor, and a second low-voltage n-channel transistor. The low-voltage current mirror is coupled to the power supply voltage terminal, its first terminal is coupled to the drain terminal of the first low-voltage n-channel transistor, and its second terminal is coupled to the source terminal of the low-voltage p-channel transistor. The source terminal of the first low-voltage n-channel transistor is coupled to the drain terminal of the positive transistor of the low-voltage input pair; The drain terminal of the second low-voltage n-channel transistor is coupled to the drain terminal of the low-voltage p-channel transistor, and the source terminal of the second low-voltage n-channel transistor is coupled to the drain terminal of the negative transistor of the low-voltage input pair. The gate of the low-voltage p-channel transistor is coupled to a first DC bias voltage; The gate terminals of the first low-voltage n-channel transistor and the second low-voltage n-channel transistor are coupled to a second DC bias voltage; as well as The first control signal or the second control signal is obtained from the connection terminal between the low-voltage p-channel transistor and the second low-voltage n-channel transistor.

9. The high-speed circuit as described in claim 1, wherein: The level converter includes a first sub-circuit and a second sub-circuit that respectively output the first control signal and the second control signal; Both the first sub-circuit and the second sub-circuit include a low-voltage cross-coupled pair, a low-voltage input pair, and a low-voltage protection circuit; The low-voltage cross-coupler is coupled to the power supply voltage terminal; The low-voltage protection circuit has a protection transistor and is coupled between the low-voltage cross-coupled pair and the low-voltage input pair; as well as The first control signal or the second control signal is obtained from the connection point between the low-voltage cross-coupled pair and the low-voltage protection circuit.

10. The high-speed circuit as claimed in claim 1, wherein: The level converter includes a first sub-circuit and a second sub-circuit that respectively output the first control signal and the second control signal; Both the first sub-circuit and the second sub-circuit include a high-voltage current mirror, a low-voltage input pair, and a low-voltage protection circuit. The high-voltage current mirror is coupled to the power supply voltage terminal; The low-voltage protection circuit has a protection transistor and is coupled between the high-voltage current mirror and the low-voltage input pair; as well as The first control signal or the second control signal is obtained from the connection between the output terminal of the high-voltage current mirror and the low-voltage protection circuit.

11. The high-speed circuit as claimed in claim 1, wherein: The level converter includes a first sub-circuit and a second sub-circuit that respectively output the first control signal and the second control signal; Both the first sub-circuit and the second sub-circuit include a high-voltage cross-coupled pair, a low-voltage input pair, and a low-voltage protection circuit. The high-voltage cross-coupler is connected to the power supply voltage terminal; The low-voltage protection circuit has a protection transistor and is coupled between the high-voltage cross-coupled pair and the low-voltage input pair; as well as The first control signal or the second control signal is obtained from the connection terminal between the high-voltage cross-coupled pair and the low-voltage protection circuit.

12. The high-speed circuit as described in claim 4, wherein: The protection voltage generator is a low-dropout regulator.

13. The high-speed circuit as described in claim 12, wherein: The low-dropout regulator includes a low-voltage component.

14. The high-speed circuit as described in claim 4, wherein: The high-speed circuit is used to drive the memory module; and The driver circuit has input pins and output pins to be coupled to the memory module.

15. The high-speed circuit as described in claim 4, wherein: The high-speed circuit is a transmitter circuit; and The driver circuit drives the output pin of the transmitter circuit.

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