Memory device and operating method thereof, and integrated circuit

Abstract

The present application relates to a memory device and an operating method thereof, and an integrated circuit. The present application relates to an electronic device. A memory device capable of reducing time consumed in a program operation includes a memory cell array, a page buffer group connected to the memory cell array through a plurality of bit lines, and a voltage generator configured to generate a voltage to be applied to each of a plurality of page buffers included in the page buffer group. Each of the plurality of page buffers includes a pre-charge circuit that controls a potential level of the plurality of bit lines to be maintained at a pre-charge level.

Description

Technical Field

[0001] This disclosure relates to electronic devices, and more specifically, to a memory device and a method of operating the same. Background Technology

[0002] Storage devices store data under the control of a host device such as a computer, smartphone, or smart tablet. For storing data, storage devices include disks such as hard disk drives (HDDs) and / or semiconductor memory such as solid-state drives (SSDs) or memory cards (either of which can be non-volatile memory).

[0003] In addition to the means of storing data, the storage device may also include a storage controller that controls the storage of data in the storage device and the retrieval of data from the storage device. Typically, the storage device can be one of two types: volatile memory or non-volatile memory. Examples of non-volatile memory include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Summary of the Invention

[0004] Embodiments of this disclosure provide a memory device and a method for operating the same that can reduce verification time.

[0005] A memory device according to an embodiment of the present disclosure includes: a memory cell array; a page buffer group connected to the memory cell array via multiple bit lines; and a voltage generator configured to generate a voltage to be applied to each of a plurality of page buffers included in the page buffer group. Each of the plurality of page buffers includes a precharge circuit configured to control the potential level of the multiple bit lines to be maintained at a precharge level.

[0006] A method of operating a memory device is provided, the memory device including a memory cell array, a plurality of page buffers connected to the memory cell array via a plurality of bit lines, and a voltage generator configured to generate a voltage applied to each of the plurality of page buffers, the method comprising the steps of: increasing the potential of the plurality of bit lines during a programming operation; performing programming on selected memory cells among the plurality of memory cells included in the memory cell array; and performing verification on the selected memory cells, wherein the potential level of the bit lines pre-charged during the programming operation is maintained until the verification is performed.

[0007] According to this technology, by setting the voltage level of the bit line to the voltage level used for the verification operation during the programming operation, the verification operation can be performed without pre-charging of the bit line during the verification operation, thus reducing the time consumed in the verification operation.

[0008] An integrated circuit is provided that is connected to an array of non-volatile memory cells via a first bit line. The integrated circuit includes: a first path through which a power supply voltage is delivered to a node during a first programming operation that programs a memory cell connected to the first bit line; a second path through which the power supply voltage is delivered to the first bit line during a second programming operation that programs a memory cell connected to a second bit line, to precharge the first bit line to the power supply voltage during the second programming operation without discharging; and a transistor configured to connect a node to the first bit line during the first programming operation in response to an on signal having an on level, to precharge the first bit line to the on level minus a threshold voltage level of the transistor during the first programming operation without discharging, wherein each of the first and second programming operations includes a programming phase and a verification phase. Attached Figure Description

[0009] Figure 1 This is a block diagram showing a storage device.

[0010] Figure 2 It shows things like Figure 1 A diagram of the structure of a memory device.

[0011] Figure 3 It shows things like Figure 2 A diagram illustrating an implementation of a memory cell array.

[0012] Figure 4 This is a diagram showing a portion of the page buffers in a page buffer group.

[0013] Figure 5 This is a diagram showing the signals applied to the various lines and page buffers during programming operations.

[0014] Figure 6 This is a diagram illustrating the bitline precharge operations performed at various stages during the programming operation.

[0015] Figure 7 This is a diagram showing the bit line precharge operation.

[0016] Figure 8 It is shown for use as a reference Figure 7 A diagram of the precharge circuit for the page buffer, describing the bit line precharge operation.

[0017] Figure 9This is a diagram illustrating the signals applied to the page buffer according to an embodiment of the present disclosure.

[0018] Figure 10 This is a diagram illustrating a method for precharging bit lines that perform programming operations and bit lines that disable programming operations.

[0019] Figure 11 This is a diagram illustrating signals applied to a page buffer according to another embodiment of the present disclosure.

[0020] Figure 12 This is a diagram illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0021] Figure 13 It shows things like Figure 1 A diagram of another embodiment of the storage controller.

[0022] Figure 14 This is a block diagram illustrating a memory card system that utilizes a storage device according to an embodiment of the present disclosure.

[0023] Figure 15 This is a block diagram illustrating a solid-state drive (SSD) system using a storage device according to an embodiment of the present disclosure.

[0024] Figure 16 This is a block diagram illustrating a user system that utilizes a storage device according to an embodiment of the present disclosure. Detailed Implementation

[0025] The specific structural and functional descriptions provided herein focus on embodiments of this disclosure. However, the invention can be implemented and carried out in various forms and in various ways. Therefore, the invention is not limited to the disclosed embodiments.

[0026] The embodiments of this disclosure are described in detail below with reference to the accompanying drawings, so that those skilled in the art to which this disclosure pertains can practice and readily implement the invention. Throughout the specification, references to "implementation," "another embodiment," etc., do not necessarily refer to only one embodiment, and different references to any such phrases do not necessarily refer to the same embodiment.

[0027] Figure 1 This is a block diagram showing a storage device.

[0028] Reference Figure 1 The storage device 50 may include the memory device 100 and the storage controller 200.

[0029] The storage device 50 can store data under the control of the host 300 (e.g., a cellular phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system).

[0030] Depending on the host interface defining the communication protocol with host 300, storage device 50 can be manufactured or configured as any of various types of storage devices. For example, storage device 50 can be configured as a multimedia card in the form of SSD, MMC, eMMC, RS-MMC and micro-MMC, a secure digital card in the form of SD, mini-SD and micro-SD, a Universal Serial Bus (USB) storage device, a Universal Flash Memory (UFS) device, a PCMCIA card-type storage device, a Peripheral Component Interconnect (PCI) card-type storage device, a High Speed ​​PCI (PCI-E) card-type storage device, a Compact Flash Memory (CF) card, a Smart Media Card and / or Memory Stick.

[0031] The storage device 50 can be manufactured in any of a variety of packages. For example, the storage device 50 can be manufactured as a stacked package (POP), a system-in-package (SIP), a system-on-a-chip (SOC), a multi-chip package (MCP), a chip-on-board (COB), a wafer-level fabrication package (WFP), and / or a wafer-level stacked package (WSP).

[0032] Memory device 100 can store data. Memory device 100 operates in response to control by memory controller 200. Memory device 100 may include a memory cell array, which includes a plurality of memory cells for storing data. The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells, which can be configured with a plurality of pages. In embodiments, a page may be a unit for storing data in memory device 100 or retrieving data stored in memory device 100. A memory block may be a unit for erasing data.

[0033] In embodiments, the memory device 100 may be Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin-Torque Random Access Memory (STT-RAM), etc. In this specification, as an example, the memory device 100 is NAND flash memory.

[0034] The memory device 100 may be implemented as a two-dimensional array structure or a three-dimensional array structure. In the following description, the memory device 100 is described as having a three-dimensional array structure, but the invention is not limited to this structure. This disclosure is applicable not only to flash memory devices with charge storage layers configured by conductive floating gates (FGs), but also to charge-trapped flash memory (CTF) with charge storage layers configured by insulating films.

[0035] In one embodiment, the memory device 100 may operate as a single-level cell (SLC) method, storing one data bit in one memory cell. Alternatively, the memory device 100 may operate as a method that stores at least two data bits in one memory cell. For example, the memory device 100 may operate as a multi-level cell (MLC) method, a three-level cell (TLC) method, or a four-level cell (QLC) method, storing two data bits in one memory cell.

[0036] Memory device 100 is configured to receive commands and addresses from memory controller 200 and access address-selectable regions in a memory cell array. That is, memory device 100 can perform operations corresponding to commands on address-selectable regions. For example, memory device 100 can perform write operations (programming operations), read operations, or erase operations according to the received commands. For instance, when a programming command is received, memory device 100 can program data into the address-selectable region. When a read command is received, memory device 100 can read data from the address-selectable region. When an erase command is received, memory device 100 can erase data stored in the address-selectable region.

[0037] In one embodiment, the memory device 100 may include a voltage generator 122. The voltage generator 122 generates the voltage used by the memory device 100 when performing operations. The operations performed by the memory device 100 may be programming operations, reading operations, or erasing operations.

[0038] In one implementation, voltage generator 122 generates a voltage for pre-charging the bit lines without discharging them during both the programming and verification phases. This pre-charging voltage can be applied to the gate of a transistor included in each of the plurality of page buffers included in the page buffer group.

[0039] In one embodiment, the memory device 100 may include a page buffer group 123 configured with multiple page buffers. When the memory device 100 performs a programming operation or a read operation, one or more of the multiple page buffers in the page buffer group 123 may temporarily store data, and the temporarily stored data may be programmed into multiple memory cells included in the memory cell array in the memory device 100, or may be output to the memory controller 200.

[0040] For example, when the memory device 100 performs a programming operation, data sent from the memory controller 200 may be temporarily stored in multiple page buffers and then programmed into the memory cells. The programming operation may include a programming phase and a verification phase.

[0041] In one implementation, during the programming operation, in the programming phase where data is programmed into the memory cells and in the verification phase where the programming operation performed on the memory cells is verified, the bit lines connecting each of the multiple page buffers to the memory cell array can be precharged.

[0042] In one proposed type of memory system, during the programming phase, bit lines can be pre-charged and then discharged to program data into memory cells, and during the verification phase, bit lines can be pre-charged again and then discharged again to verify the programmed data. That is, in each of the programming and verification phases, bit lines can be pre-charged and then discharged.

[0043] Since the bit lines are pre-charged and then discharged in each of the programming and verification phases, the time consumed in the verification operation can be increased, which may mean an increase in the total programming operation time. Therefore, this disclosure proposes a method for pre-charging the bit lines without discharging them during both the programming and verification phases.

[0044] In one embodiment, each of the plurality of page buffers included in page buffer group 123 may include a precharge circuit. During both the programming and verification phases, the precharge circuit may precharge the bit lines without discharging them. The bit lines may be divided into selected bit lines to which memory cells to be programmed are connected and unselected bit lines to which memory cells to be disabled for programming are connected. In one embodiment, the selected bit lines may be precharged to a different level than the unselected bit lines.

[0045] The storage controller 200 controls the overall operation of the storage device 50.

[0046] When a power supply voltage is applied to the storage device 50, the storage controller 200 can execute firmware. When the storage device 100 is a flash memory device 100, the storage controller 200 can operate firmware such as a flash translation layer (FTL) to control communication between the host 300 and the storage device 100.

[0047] In one implementation, the storage controller 200 may include firmware (not shown) that receives data and logical block addresses (LBAs) from the host 300 and converts the LBAs into physical block addresses (PBAs) indicating the addresses of memory cells in which data included in the memory device 100 is to be stored. Additionally, the storage controller 200 may store a logical-physical address mapping table configuring the mapping between LBAs and PBAs in a buffer memory.

[0048] The storage controller 200 can control the storage device 100 to perform programming operations, read operations, erase operations, etc., according to requests from the host 300. For example, when a programming request is received from the host 300, the storage controller 200 can convert the programming request into a programming command and provide the programming command, PBA, and data to the storage device 100. When a read request is received from the host 300 along with an LBA, the storage controller 200 can convert the read request into a read command, select the PBA corresponding to the LBA, and then provide the read command and PBA to the storage device 100. When an erase request is received from the host 300 along with an LBA, the storage controller 200 can convert the erase request into an erase command, select the PBA corresponding to the LBA, and then provide the erase command and PBA to the storage device 100.

[0049] In one implementation, the storage controller 200 may generate programming commands, addresses, and data and send them to the storage device 100 without requiring a request from the host 300. For example, the storage controller 200 may provide commands, addresses, and data to the storage device 100 to perform background operations, such as programming operations for wear leveling and programming operations for garbage collection.

[0050] In one embodiment, the storage device 50 may further include a buffer memory (not shown). The storage controller 200 controls data exchange between the host 300 and the buffer memory (not shown). Alternatively, the storage controller 200 may temporarily store system data used to control the storage device 100 in the buffer memory. For example, the storage controller 200 may temporarily store data input from the host 300 in the buffer memory and then send the data temporarily stored in the buffer memory to the storage device 100.

[0051] In various embodiments, the buffer memory can be used as both operational memory and cache memory of the storage controller 200. The buffer memory can store code or commands executed by the storage controller 200. Alternatively, the buffer memory can store data processed by the storage controller 200.

[0052] In implementations, the buffer memory may be implemented as dynamic random access memory (DRAM) or static random access memory (SRAM) such as double data rate synchronous dynamic random access memory (DDR SDRAM), DDR4 SDRAM, low power double data rate 4 (LPDDR4) SDRAM, graphics double data rate (GDDR) SDRAM, low power DDR (LPDDR) or Rambus dynamic random access memory (DRAM).

[0053] In various embodiments, the buffer memory may be external to the storage device 50. In this case, an external volatile memory device operatively coupled to the storage device 50 may be used as the buffer memory.

[0054] In one implementation, the memory controller 200 can control two or more memory devices. In this case, the memory controller 200 can control the memory devices according to an interleaving method to improve operational performance.

[0055] The host 300 may communicate with the storage device 50 using at least one of various communication protocols such as Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM) and / or Load Reduction DIMM (LRDIMM).

[0056] Figure 2 It is shown Figure 1 A diagram of the structure of a memory device.

[0057] Reference Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0058] Memory cell array 110 includes multiple memory blocks BLK1 to BLKz, which are connected to row decoder 121 via row lines RL. The multiple memory blocks BLK1 to BLKz are connected to page buffer group 123 via bit lines BL1 to BLn. Each of the multiple memory blocks BLK1 to BLKz includes multiple memory cells. In this embodiment, the multiple memory cells are non-volatile memory cells. Memory cells connected to the same word line can be defined as a page. Therefore, a memory block may include multiple pages.

[0059] A row line RL may include at least one source select line, multiple word lines, and at least one drain select line.

[0060] Each memory cell included in the memory cell array 110 can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0061] Peripheral circuitry 120 can be configured to perform programming, reading, or erasing operations on selected regions of memory cell array 110 under the control of control logic 130. Peripheral circuitry 120 can drive memory cell array 110. For example, under the control of control logic 130, peripheral circuitry 120 can apply various operating voltages to row lines RL and bit lines BL1 to BLn or discharge the applied voltages.

[0062] The peripheral circuitry 120 may include a row decoder 121, a voltage generator 122, a page buffer group 123, a column decoder 124, an input / output circuit 125, and a sensing circuit 126.

[0063] The row decoder 121 is connected to the memory cell array 110 via row lines RL. The row line RL may include at least one source select line, multiple word lines, and at least one drain select line. In some embodiments, the word lines may include normal word lines and dummy word lines. In some embodiments, the row line RL may also include transistor select lines.

[0064] The row decoder 121 is configured to decode the row address RADD received from the control logic 130. The row decoder 121 selects at least one memory block from BLK1 to BLKz based on the decoded address. In addition, the row decoder 121 can select at least one word line of the selected memory block based on the decoded address to apply the voltage generated by the voltage generator 122 to at least one word line WL.

[0065] For example, during a programming operation, the line decoder 121 can apply a programming voltage to the selected word line and a programming pass voltage lower than the programming voltage to the unselected word line. During a programming verification operation, the line decoder 121 can apply a verification voltage to the selected word line and a verification pass voltage higher than the verification voltage to the unselected word line. During a read operation, the line decoder 121 can apply a read voltage to the selected word line and a read pass voltage higher than the read voltage to the unselected word line.

[0066] In this implementation, the erase operation of the memory device 100 is performed on a block-by-block basis. During the erase operation, the line decoder 121 may select a memory block based on the decoded address. During the erase operation, the line decoder 121 may apply a ground voltage to the word line connected to the selected memory block.

[0067] Voltage generator 122 operates in response to control of control logic 130. Voltage generator 122 is configured to generate multiple voltages using the external power supply voltage supplied to memory device 100. Specifically, voltage generator 122 can generate various operating voltages Vop for programming, reading, and erasing operations in response to the operation signal OPSIG. For example, voltage generator 122 can generate programming voltage, verification voltage, pass voltage, read voltage, erase voltage, etc., in response to control of control logic 130.

[0068] In this embodiment, the voltage generator 122 can generate an internal power supply voltage by adjusting the external power supply voltage. The internal power supply voltage generated by the voltage generator 122 is used as the operating voltage of the memory device 100.

[0069] In an implementation, voltage generator 122 can use an external power supply voltage or an internal power supply voltage to generate multiple voltages.

[0070] For example, voltage generator 122 may include multiple pump capacitors that receive internal power supply voltages, and multiple pump capacitors may be selectively enabled in response to control of control logic 130 to generate multiple voltages.

[0071] The generated voltages can be supplied to the memory cell array 110 via the row decoder 121.

[0072] Page buffer group 123 includes first page buffers PB1 to nth page buffers PBn, which are connected to memory cell array 110 via first bit line BL1 to nth bit line BLn, respectively. The first page buffers PB1 to nth page buffers PBn operate in response to control logic 130. Specifically, the first page buffers PB1 to nth page buffers PBn may operate in response to page buffer control signal PBSIGNALS. For example, the first page buffers PB1 to nth page buffers PBn may temporarily store data received via first bit line BL1 to nth bit line BLn, or may sense the voltage or current of bit lines BL1 to BLn during read or verification operations.

[0073] Specifically, during programming operations, when a programming voltage is applied to the selected word line, the first page buffer PB1 to the nth page buffer PBn can transmit the data DATA received through the input / output circuit 125 to the selected memory cell via the first bit line BL1 to the nth bit line BLn. The memory cell of the selected page is programmed based on the transmitted data DATA. During programming verification operations, the first page buffer PB1 to the nth page buffer PBn can read page data by sensing the voltage or current received from the selected memory cell via the first bit line BL1 to the nth bit line BLn.

[0074] During the read operation, under the control of the column decoder 124, the first page buffer PB1 to the nth page buffer PBn read data DATA from the memory cell of the selected page through the first bit line BL1 to the nth bit line BLn, and output the read data DATA to the input / output circuit 125.

[0075] During the erase operation, the first page buffer PB1 to the nth page buffer PBn can either float the first bit line BL1 to the nth bit line BLn or apply an erase voltage.

[0076] The column decoder 124 can transfer data between the input / output circuitry 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 can exchange data with the first page buffer PB1 to the nth page buffer PBn via the data line DL, or it can exchange data with the input / output circuitry 125 via the column line CL.

[0077] Input / output circuit 125 can output from Figure 1 The storage controller 200 receives commands CMD and addresses ADDR and transmits them to the control logic 130, or can exchange data DATA with the column decoder 124.

[0078] The sensing circuit 126 can generate a reference current in response to the enable bit signal VRYBIT during a read operation or verification operation, and compare the sensed voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current to output a pass signal PASS or a failure signal FAIL.

[0079] Control logic 130 can output operation signals OPSIG, row address RADD, page buffer control signals PBSIGNALS, and enable bit VRYBIT in response to command CMD and address ADDR to control peripheral circuitry 120. For example, control logic 130 can control the read operation of a selected memory block in response to a sub-block read command and address. Additionally, control logic 130 can control the erase operation of a selected sub-block included in the selected memory block in response to a sub-block erase command and address. Furthermore, control logic 130 can determine whether the verification operation passed or failed in response to a pass signal PASS or a failure signal FAIL.

[0080] Figure 3 It is shown Figure 2 A diagram illustrating an implementation of a memory cell array.

[0081] Reference Figure 2 and Figure 3 , Figure 3 It is shown that it includes Figure 2 A circuit diagram of a representative memory block BLKa among the multiple memory blocks BLK1 to BLKz in the memory cell array 110.

[0082] A first select line, a word line, and a second select line arranged in parallel to each other can be connected to a memory block BLKa. For example, the word line can be arranged in parallel between the first select line and the second select line. Here, the first select line can be a source select line (SSL), and the second select line can be a drain select line (DSL).

[0083] More specifically, the memory block BLKa may include multiple strings connected between bit lines BL1 to BLn and source line SL. Bit lines BL1 to BLn may be connected to strings individually, and source line SL may be connected to strings collectively. Since the strings can be configured to be identical to each other, as an example, the string ST connected to the first bit line BL1 will be described specifically.

[0084] A string ST may include a source selection transistor SST connected in series between the source line SL and the first bit line BL1, a plurality of memory cells (e.g., 16, denoted as F1 to F16), and a drain selection transistor DST. A string ST may include at least one source selection transistor SST and at least one drain selection transistor DST, and may include more than 16 memory cells (i.e., F1 to F16 shown in the figure).

[0085] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells F1 to F16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gate of the source select transistor SST, which is included in different strings, can be connected to the source select line SSL, the gate of the drain select transistor DST can be connected to the drain select line DSL, and the gate of the memory cells F1 to F16 can be connected to multiple word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different strings can be referred to as a physical page PPG. Therefore, the memory block BLKa can include the same number of physical pages PPG as word lines WL1 to WL16.

[0086] A memory cell can store one bit of data. This is usually called a single-level cell (SLC). In this case, a physical page (PPG) can store one logical page (LPG) of data. The number of data bits included in a logical page (LPG) can be the same as the number of memory cells in a physical page (PPG). Alternatively, a memory cell can store two or more bits of data. This is usually called a multi-level cell (MLC). In this case, a physical page (PPG) can store two or more logical pages (LPGs) of data.

[0087] A memory cell that stores two or more bits of data is generally referred to as a multilevel cell (MLC). However, recently, with the increase in memory cell capacity, the term multilevel cell (MLC) more specifically refers to a memory cell that stores two bits of data. In this case, a memory cell that stores three or more bits of data is called a three-level cell (TLC), and a memory cell that stores four or more bits of data is called a four-level cell (QLC). Generally, the present invention can be applied to a memory device 100 having memory cells that each store two or more bits of data.

[0088] In another embodiment, the memory block may have a three-dimensional structure. Each memory block includes multiple memory cells stacked on a substrate. These multiple memory cells are arranged along the +X, +Y, and +Z directions.

[0089] Figure 4 It is shown Figure 2 A diagram of a portion of one of the multiple page buffers included in a group of page buffers.

[0090] Reference Figure 2 and Figure 4 , Figure 4 Show Figure 2A portion of the first page buffer PB1 in page buffer group 123, from the first page buffer PB1 to the nth page buffer PBn. Each of the second page buffers PB2 to the nth page buffer PBn can be connected to, as follows: Figure 4 The first page buffer PB1 shown is configured in the same way.

[0091] In one implementation, the first page buffer PB1 may include a data transmitter 123_1A, a latch 123_1B, and a sixth transistor connecting the data transmitter 123_1A, the latch 123_1B, and the bit line BL.

[0092] The data transmitter 123_1A may include first transistor TR1 through fifth transistor TR5. The data transmitter 123_1A may transmit data sensed by sensing node SO to memory controller 200 or transmit data received from memory controller 200 to memory cell array 110 via bit line BL.

[0093] In the implementation, among the first transistor TR1 to the fifth transistor TR5 in the data transmitter 123_1A, the first transistor TR1 and the third transistor TR3 can be implemented as PMOS transistors, and the second transistor TR2, the fourth transistor TR4 and the fifth transistor TR5 can be implemented as NMOS transistors.

[0094] In this implementation, the first transistor TR1 can connect the power supply voltage VCORE to the second transistor TR2. The first node NODE1 connects the first transistor TR1 and the second transistor TR2. The second transistor TR2 can be connected to the sixth transistor TR6 via the second node NODE2. The third transistor TR3 can be connected in parallel with the first transistor TR1 between the power supply voltage VCORE and the first node NODE1. The fourth transistor TR4 can be connected between the first node NODE1 and the sensing node SO. The fifth transistor TR5 can be connected between the sensing node SO and the latch 123_1B.

[0095] Furthermore, the first signal PRECHSO_N, which serves as the precharge signal for the inverting sensing node, can be applied to the gate of the first transistor TR1; the second signal SA_CSOC, which serves as the current sensing signal, can be applied to the gate of the second transistor TR2; the third signal QS, which serves as the data signal, can be applied to the gate of the third transistor TR3; the fourth signal SA_PRECH_N, which serves as the precharge signal for the inverting current, can be applied to the gate of the fourth transistor TR4; and the sensing node transmission signal can be applied to the gate of the fifth transistor TR5.

[0096] In this implementation, the data can be stored in latch 123_1B. For example, data sensed by sensing node SO or data sent from storage controller 200 can be stored.

[0097] In this implementation, the sixth transistor TR6 can be implemented as an NMOS transistor. Additionally, a sixth signal PB_SENSE, serving as a page buffer sensing signal, can be applied to the gate of the sixth transistor TR6.

[0098] During programming operations, refer to Figure 5 The voltages applied to the first transistor TR1 through the sixth transistor TR6 are described in more detail.

[0099] Figure 5 This is a diagram showing the signals applied to the various lines and page buffers during programming operations.

[0100] Figure 5 This illustration shows a representative example of a plurality of programming cycles executed when the memory device 100 performs a programming operation. Each of the plurality of programming cycles may include a programming phase (PROGRAM PHASE) and a verification phase (VERIFY PHASE). Therefore, Figure 5 The diagram shows the programming phase PROGRAM PHASE and the verification phase VERIFYPHASE in each of the multiple programming cycles.

[0101] exist Figure 5 In this context, the voltage applied to each line and the voltage or signal applied to the gate of the transistor in the page buffer can be obtained from... Figure 2 The voltage generator 122 generates it.

[0102] The programming phase (PROGRAM PHASE) may include a bit line setting phase (t1 to t2) and a programming pulse application phase (t2 to t3).

[0103] In the implementation, during the bit line setup phase (t1 to t2), an application is made to... Figure 4 The gate voltages of the second transistor TR2 and the sixth transistor TR6 can be HV voltages. That is, during the bit line setup phase (t1 to t2), each of the second signal SA_CSOC applied to the second transistor TR2 and the sixth signal PB_SENSE applied to the sixth transistor TR6 can have an HV voltage level.

[0104] Since the HV voltage is applied to the gates of the second transistor TR2 and the sixth transistor TR6, the unselected BLs to which the programmable memory cells are connected can be precharged to the VCORE level.

[0105] Additionally, the voltage applied to the gate of the fourth transistor TR4 can be the VSAPRECHN voltage, and the voltage applied to the fifth transistor TR5 can be 0V (GND). That is, the fourth signal SA_PRECH_N applied to the fourth transistor TR4 can have the VSAPRECHN voltage level, and the fifth signal TRANSO applied to the fifth transistor TR5 can be 0V.

[0106] During the bit line setup phase (t1 to t2), the sixth signal PB_SENSE changes from HV level to low level, but the second signal SA_CSOC can remain at HV level, and the fourth signal SA_PRECH_N can remain at VSAPRECHN level.

[0107] Subsequently, during the programming pulse application phase (t2 to t3), when the first pass voltage VPASS1 is applied to all word lines, the sixth signal PB_SENSE can be maintained at the VDPGM level and the second signal SA_CSOC can be maintained at the HV level. Then, when the programming voltage VPGM is applied to the selected word line Selected WL, the sixth signal PB_SENSE and the second signal SA_CSOC can become 0V (GND) level.

[0108] In the implementation, during the programming pulse application phase (t2 to t3), after the first pass voltage VPASS1 is applied to all word lines ALL WLs, the programming voltage VPGM can be applied to the selected word line Selected WL and the first pass voltage VPASS1 can be maintained in the unselected word line Unselected WLs.

[0109] In this implementation, during the bit line setup phase (t1 to t2), the unselected bit lines (BLs) to which the memory cells that are disabled for programming are connected can be precharged to the VCORE level, and as the sixth signal PB_SENSE reaches the VDPGM level at t2, the selected bit lines (BLs) to which the programmed memory cells are connected can be precharged to the VDPGM level. The unselected bit lines (BLs) and the selected bit lines (BLs) can be precharged based on the data input to the page buffer.

[0110] Selected memory cells connected to the selected word line Selected WL can be programmed by applying the programming voltage VPGM to the selected word line Selected WL while the bit line is precharged.

[0111] After the selected memory cell connected to the Selected word line (Selected WL) is programmed, the Unselected bit lines (Unselected BLs) and the Selected bit line (Selected BL) can be discharged and can be precharged again during the Verify phase (VERIFYPHASE).

[0112] In this implementation, to program the selected memory cell, at time t2 (or slightly earlier than t2), a drain select line voltage VDSL can be applied to the selected drain select line Selected DSL. That is, a positive voltage above 0V can be applied to the selected drain select line Selected DSL to turn on the drain select transistor connected to the selected drain select line Selected DSL.

[0113] Additionally, during the programming pulse application phase (t2 to t3), the ground voltage GND can be applied to... Figure 3 The source line SL is connected so that ground voltage GND (i.e., 0V) can be applied to the selected source select line SSL. When ground voltage GND is applied to the selected source select line SSL, the source select transistor connected to the selected source select line SSL can be turned off.

[0114] In this implementation, during the programming pulse application phase (t2 to t3), 0V, which is the ground voltage GND, can be applied to the unselected drain select lines (DSLs) and the unselected source select lines (SSLs). That is, 0V can be applied to the unselected drain select lines (DSLs) and the unselected source select lines (SSLs) so that the unselected memory cells are not programmed.

[0115] After the programming voltage VPGM is applied to the selected word line (Selected WL) during a set time period, a second pass voltage VPASS2 can be applied to all word lines (Selected WL and Unselected WLs). That is, the same voltage level can be applied to all word lines after the programming voltage VPGM is applied to the selected word line and before the VERIFY PHASE phase. Afterward, all word lines (Selected WL and Unselected WLs) can be discharged.

[0116] After all word lines have been discharged, channel initialization can be performed in the Verify Phase.

[0117] For example, after all word lines have been discharged, the channel initialization voltage VINI can be applied to all word lines. Subsequently, the selected word lines (WLs) can be discharged, and the voltage applied to the unselected word lines (WLs) can be maintained at the channel initialization voltage VINI. The channel initialization voltage VINI can be a third pass voltage VPASS3.

[0118] Because the discharge operation is performed under the same voltage condition on all word lines, coupling between different word lines does not occur. Therefore, it prevents the phenomenon that the voltage of some word lines is relatively lower or higher than the voltage of other word lines.

[0119] In the implementation, when the programming phase PROGRAM PHASE ends, the verification phase VERIFY PHASE can be performed at t3.

[0120] During the VERIFY PHASE verification phase, channel initialization can be performed. When channel initialization is performed, the channel initialization voltage VINI can be applied to all word lines, and the drain-source line voltage VDS-SL can be applied to all drain select lines and all source select lines (Selected DSLs and Unselected DSLs, and Selected SSLs and Unselected SSLs). That is, the channel of the memory cell can be initialized before the verification voltage is applied to the selected word lines.

[0121] Subsequently, the voltage of the selected word line WL can be set to 0V. That is, before performing the verification operation, the voltage level of the selected word line WL can be set to the level of the channel initialization voltage VINI, and then discharged to be set to 0V. Since the verification operation is performed quickly while the voltage of the unselected word lines WLs is maintained at the third pass voltage VPASS3, the voltage applied to the unselected word lines WLs can be maintained at the third pass voltage VPASS3.

[0122] After the channel of the memory cell is initialized, the unselected drain select lines (DSLs) and unselected source select lines (SSLs) are discharged, so that the voltage of those lines can become 0V.

[0123] That is, in order to prevent the unselected drain selected lines (DSLs) and unselected source selected lines (SSLs) from becoming at a specific voltage level, the unselected drain selected lines (DSLs) and unselected source selected lines (SSLs) can be discharged after the drain-source line voltage VDS-SL is applied to those lines at t3.

[0124] Subsequently, a verification voltage VVFY can be applied to the selected word line (WL). This verification operation determines whether the memory cell has reached the target programming state. The voltage applied to the unselected word lines (WLs) can be maintained at the third pass voltage VPASS3.

[0125] When the verification voltage VVFY is applied to the selected word line Selected WL, the signal applied to the page buffer can be set.

[0126] Reference Figure 4 When the verification voltage VVFY is applied to the Selected word line Selected WL, the voltage applied to the gate of the sixth transistor can be set to the VPBSENSE level, the voltage applied to the gate of the second transistor can be set to the VSACSOC level, the voltage applied to the gate of the fifth transistor can be set to the VTRANSO level, and the voltage applied to the gate of the fourth transistor can be set to 0V (GND).

[0127] That is, the sixth signal PB_SENSE can be at the VPBSENSE level, the second signal SA_CSOC can be at the VSACSOC level, the fifth signal TRANSO can be at the VTRANSO level, and the fourth signal SA_PRECH_N can be a 0V signal.

[0128] After sensing the data, the fourth signal SA_PRECH_N can be set to the VSAPRECHN level, and the fifth signal TRANSO can be set to 0V.

[0129] When the verification voltage VVFY is applied to the selected word line Selected WL, the voltage of the bit line connected to the selected memory cell can be precharged by setting the levels of the sixth signal PB_SENSE, the second signal SA_CSOC, the fifth signal TRANSO, and the fourth signal SA_PRECH_N. Since verification is not performed on unselected memory cells, the bit lines connected to unselected memory cells are not precharged.

[0130] After the verification operation is performed, a third voltage can be applied to all word lines (Selected WLs and Unselected WLs), and all these word lines can be discharged simultaneously. That is, an equalization operation can be performed.

[0131] Since the verification operation has ended, the sixth signal PB_SENSE and the second signal SA_CSOC can be set to 0V (GND).

[0132] After the equalization operation is performed, all word lines Selected WL and Unselected WLs, all drain selected lines Selected DSL and Unselected DSLs, and all source selected lines Selected SSL and Unselected SSLs can be discharged and reach 0V.

[0133] In this implementation, the programming operation can end when the selected memory cell passes the verification operation. However, if the selected memory cell fails the verification operation, the next programming cycle can be executed.

[0134] Figure 6 This is a diagram illustrating the bitline precharge operations performed at various stages during the programming operation.

[0135] Reference Figure 5 and Figure 6 ,exist Figure 5 Among the voltages shown, Figure 6 This shows the voltage applied to the Selected WL and the voltage applied to the Unselected WLs, as well as the voltage levels set in the Unselected BLs to which the memory cells that are disabled for programming are connected and the Selected BLs to which the selected memory cells that are enabled for programming are connected.

[0136] In this implementation, before the first pass voltage VPASS1 is applied to the selected word lines (Selected WL) and unselected word lines (Unselected WLs), the unselected bit lines (Unselected BLs) to which the unprogrammable memory cells are connected can be precharged to the VCORE level. That is, since the unselected memory cells are not programmed, the bit lines to which the unselected memory cells are connected can be precharged to the VCORE level.

[0137] Subsequently, when the first pass voltage VPASS1 is applied to the Selected word line Selected WL and the Unselected word line Unselected WLs, the Selected bit line Selected BL, which is the bit line to which the selected memory cell is connected, can be precharged to the VDPGM level so that programming operations can be performed on the selected memory cell.

[0138] After the programming voltage is applied to the selected word line (Selected WL), a second pass voltage (VPASS2) can be applied to both the selected word line (Selected WL) and the unselected word line (Unselected WLs). When the potentials of the selected word line (Selected WL) and the unselected word line (Unselected WLs) are equal to the second pass voltage (VPASS2), the selected word line (Selected WL) and the unselected word line (Unselected WLs) can be discharged simultaneously. When the selected word line (Selected WL) and the unselected word line (Unselected WLs) are discharged, the selected bit line (Selected BL) and the unselected bit line (Unselected BLs) can also be discharged together.

[0139] In the Verification Phase, executed after the Program Phase, the channel initialization voltage VINI can be applied to all word lines Selected WLs and Unselected WLs. Afterward, the Selected WLs can be discharged, and the voltage applied to the Unselected WLs can be maintained at the channel initialization voltage VINI. The channel initialization voltage can be a third pass voltage VPASS3.

[0140] A verification voltage can be applied to the selected word line (Selected WL) to verify whether the selected memory cell has been programmed, and the selected bit line (Selected BL) to which the selected memory cell is connected can be verified by applying a voltage to... Figure 4 The difference between the voltage level VPBSENSE of the sixth transistor TR6 and the threshold voltage level VTH of the sixth transistor TR6, VPBSENSE-VTH, is used for pre-charging. When the bit line to which the selected memory cell is connected is pre-charged, the change in the magnitude of the current flowing through the sensing node SO during the verification operation can determine whether the programming has succeeded or failed.

[0141] However, in the PROGRAM PHASE and VERIFY PHASE phases, the time consumed in the programming operation can be extended because each of the selected bit lines (Selected BL) and unselected bit lines (Selected BL) is pre-charged and then discharged, i.e., because the bit lines are pre-charged in each phase.

[0142] Therefore, this disclosure proposes a method for pre-charging bit lines without discharging them during both the programming phase (PROGRAM PHASE) and the verification phase (VERIFYPHASE).

[0143] Figure 7 This is a diagram illustrating the bit line precharge operation performed in this disclosure.

[0144] Reference Figure 7 , Figure 7 This diagram illustrates the voltages applied to the Selected WL and Unselected WLs during the programming phase (PROGRAM PHASE) and the verification phase (VERIFY PHASE) of the programming operation, while the bit lines are pre-charged without being discharged. It also shows the voltage levels set to the Unselected BLs connected to the memory cells that are disabled from programming and the Selected BLs connected to the selected memory cells that are enabled from programming.

[0145] In the implementation, during the programming phase PROGRAM PHASE, time periods t1 to t2 may be the bit line setting phase, time periods t2 to t3 may be the programming pulse application phase, and the verification phase VERIFYPHASE may be performed during time periods t3 to t4.

[0146] In this implementation, before the first pass voltage VPASS1 is applied to the selected word lines (Selected WL) and unselected word lines (Unselected WLs), the unselected bit lines (Unselected BLs) to which the unprogrammable memory cells are connected can be precharged to the VCORE level. That is, since the unselected memory cells are not programmed, the bit lines to which the unselected memory cells are connected can be precharged to the VCORE level.

[0147] Subsequently, when the first pass voltage VPASS1 is applied to the Selected word line Selected WL and the Unselected word line Unselected WLs, the Selected bit line Selected BL, which is the bit line to which the selected memory cell is connected, can be precharged so that programming operations can be performed on the selected memory cell.

[0148] However, with Figure 5 and Figure 6 The processing shown differs; the selected bit line, Selected BL, can be precharged to the VPBSENSE-VTH level, which is the difference between the voltage level VPBSENSE applied to the sixth transistor TR6 and the threshold voltage level VTH of the sixth transistor TR6, unlike the VDPGM level (see [link to documentation]). Figure 5 and Figure 6 That is, in Figure 5 and Figure 6 During the verification phase, the selected bit line (Selected BL) can be precharged to the precharge level.

[0149] In this implementation, when the selected bit lines (BLs) and unselected bit lines (BLs) are pre-charged during the PROGRAM PHASE phase, the pre-charged potential level remains at the selected and unselected bit lines (BLs) even during the VERIFY PHASE phase. Therefore, since the bit lines do not undergo further discharge and pre-charge during the VERIFY PHASE phase, the time consumed in the programming operation can be shortened.

[0150] Since the selected bit line Selected BL is precharged to the VPBSENSE-VTH level, a voltage VPGM+OFFSET (where OFFSET is a positive voltage) can be applied to the selected word line Selected WL to program the selected memory cell. In this paper, the voltage VPGM is the default or starting voltage corresponding to the target state of the selected memory cell, used for programming the selected memory cell before gradually increasing as a step voltage. Furthermore, OFFSET can be greater than or equal to VPBSENSE-VTH, which is the precharge level of the selected bit line Selected BL during the VERIFY PHASE phase.

[0151] That is, because the selected bit line (Selected BL) is precharged using a higher voltage level (VPBSENSE-VTH) than the voltage used when precharging the bit lines in each of the PROGRAM PHASE and VERIFY PHASE phases, the voltage applied to the selected word line (Selected WL) is greater than or equal to the offset voltage (OFFSET). Furthermore, the VDPGM level can be the same as the VPBSENSE-VTH level.

[0152] When a voltage VPGM+OFFSET, which is greater than the programming voltage VPGM by an offset voltage OFFSET, is applied to the selected word line Selected WL, the selected memory cell can be programmed to the target programming state.

[0153] Subsequently, in the Verify Phase, the potential levels of the Selected BL and Unselected BLs can be maintained at the same levels as in the Program Phase.

[0154] For example, in the Verify Phase, the selected bit line (Selected BL) maintains a potential level of VPBSENSE-VTH, thus allowing the sensing of selected memory cells. When the unselected bit lines (Unselected BLs) maintain a potential level of VCORE, unselected memory cells can also be sensed, but this only determines whether the programming operation of the selected memory cells has succeeded; therefore, the result of sensing unselected memory cells can be ignored.

[0155] When the operation of applying the verification voltage VVFY to the selected word line is completed, the selected bit line (BL) and the unselected bit line (BLs) can be discharged.

[0156] As a result, during the programming operation, the selected bit lines (BLs) and unselected bit lines (BLs) are pre-charged in the PROGRAM PHASE phase and maintained at the pre-charge level even in the VERIFY PHASE phase, thus allowing the bit lines to be pre-charged once without discharging. Therefore, since the programming operation is performed by pre-charging the selected bit lines (BLs) and unselected bit lines (BLs), the programming operation time can be reduced.

[0157] Figure 8 This is shown for reference. Figure 7 The diagram describes the bit line precharge operation that adds a precharge circuit to the page buffer.

[0158] Reference Figure 4 and Figure 8 ,Apart from Figure 4 Outside of the first page buffer PB1, Figure 8 A first page buffer including a precharge circuit 123_1PRE is shown. In an embodiment, the precharge circuit 123_1PRE may include a seventh transistor TR7 and an eighth transistor TR8. The seventh transistor TR7 and the eighth transistor TR8 may be implemented as PMOS transistors. A third signal QS, as a data signal, may be applied to the gate of the seventh transistor TR7, and an eighth signal SA_PRE_N, as an inverted precharge signal, may be applied to the gate of the eighth transistor TR8. The third signal QS may be combined with the signal applied to... Figure 4 The gate signal of the third transistor TR3 is the same.

[0159] Figure 8 Also exists in Figure 4 The components already described in this diagram will not be described here again.

[0160] In this implementation, the third signal QS can vary depending on whether the memory cell is programmed. When the memory cell connected to the bit line is a selected memory cell to be programmed, the third signal QS can be at the VQS level during both the PROGRAM PHASE and VERIFY PHASE phases. Conversely, when the memory cell connected to the bit line is an unselected memory cell that is not programmed, the third signal QS can be at the 0V (GND) level during both the PROGRAM PHASE and VERIFY PHASE phases.

[0161] Therefore, when the memory cell connected to the bit line is the selected memory cell, since the third signal QS has a VQS level during both the PROGRAMPHASE and VERIFY PHASE phases, the seventh transistor TR7 is turned off to block the VCORE voltage from being applied to the bit line. Therefore, when the sixth signal PB_SENSE applied to the gate of the sixth transistor TR6 is at the VPBSENSE level, the bit line can be pre-charged to the VPBSENSE-VTH level. According to the embodiment, the sixth signal PB_SENSE can be 0V (GND) during the bit line setup phase (t1 to t2), and can be VPBSENSE during the programming pulse application phase (t2 to t3) and the VERIFY PHASE phase.

[0162] However, when the memory cell connected to the bit line is an unselected memory cell, since the third signal QS is 0V (GND) during both the PROGRAMPHASE and VERIFY PHASE phases, the seventh transistor TR7 is turned on during both phases. Therefore, during both the PROGRAMPHASE and VERIFY PHASE phases, when the eighth transistor TR8 is turned on (i.e., the eighth signal SA_PRE_N is 0V (GND)), the bit line can be precharged to the VCORE level.

[0163] Figure 9 This is a diagram illustrating the signals applied to the page buffer according to an embodiment of the present disclosure.

[0164] Reference Figure 8 and Figure 9 , Figure 9 It shows that it is applied to Figure 8 The first page of the buffer PB1 contains a diagram showing the gate signals of the transistors and the potential levels set to bit line BL.

[0165] Furthermore, the voltage or signal applied to the gate of the transistor included in the page buffer can be obtained from... Figure 2 The voltage generator 122 generates it.

[0166] In the implementation, during the bit line setting phase (t1 to t2), the first signal PRECHSO_N, the eighth signal SA_PRE_N, and the fourth signal SA_PRECH_N can be changed from the VCORE level to the 0V (GND) level.

[0167] Additionally, when the memory cell connected to the first page buffer PB1 via bit line BL is a selected memory cell (ALLOW), the third signal QS can be changed from 0V (GND) level to VQS level. However, when the memory cell connected to the first page buffer PB1 via bit line BL is an unselected memory cell (INHIBIT), the third signal QS can be changed from VQS level to 0V (GND) level.

[0168] During the bit line setup phases t1 to t2, the sixth signal PB_SENSE, the second signal SA_CSOC, and the fifth signal TRANSO can be maintained at 0V (GND) level.

[0169] Therefore, during the bit line setup phase (t1 to t2), when the memory cell connected to the first page buffer PB1 via bit line BL is an unselected memory cell, i.e., the unselected bit lines BLs connected to the bit lines of a memory cell that is disabled from programming can be precharged to the VCORE level. However, when the memory cell connected to the first page buffer PB1 via bit line BL is a selected memory cell, i.e., the selected bit line BL connected to the bit line of a memory cell that is enabled from programming can not be precharged and can be at the 0V (GND) level.

[0170] For example, when the memory cell connected to the first page buffer PB1 via bit line BL is an unselected memory cell, bit line BL can be precharged to the VCORE level as the second transistor TR2 and the sixth transistor TR6 are turned off and the seventh transistor TR7 and the eighth transistor TR8 are turned on. When the memory cell connected to the first page buffer PB1 via bit line BL is a selected memory cell, the potential of bit line BL can be at the 0V (GND) level during the bit line setup phase (t1 to t2) as the second transistor TR2, the sixth transistor TR6, and the seventh transistor TR7 are turned off.

[0171] After the bit line setup phase (t1 to t2), when the programming pulse application phase (t2 to t3) begins, that is, when the first pass voltage VPASS1 is applied to all word lines Selected WL and Unselected WLs, the sixth signal PB_SENSE can be changed from 0V (GND) level to VPBSENSE level, the second signal SA_CSOC can be changed from 0V (GND) level to VSACSOC level, and the fifth signal TRANSO can be changed from 0V (GND) level to VTRANSO level.

[0172] Therefore, when the programming pulse application phase (t2 to t3) begins, the memory cells connected to the first page buffer PB1 via bit line BL are unselected memory cells; that is, the unselected bit lines BLs connected to memory cells that are inhibited (INHIBIT) can be maintained at the VCORE level. However, when the memory cells connected to the first page buffer PB1 via bit line BL are selected memory cells; that is, the selected bit line BL connected to memory cells that are allowed (ALLOW) can be precharged to the VPBSENSE-VTH level.

[0173] For example, since the seventh transistor TR7 and the eighth transistor TR8 are still turned on during the programming pulse application phase (t2 to t3), the potential of the bit line BL can be maintained at the VCORE level during the programming pulse application phase (t2 to t3).

[0174] For example, when the memory cell connected to the first page buffer PB1 via bit line BL is the selected memory cell, as the first transistor TR1, the second transistor TR2, and the sixth transistor TR6 are turned on and the seventh transistor TR7 is turned off during the programming pulse application phase (t2 to t3), bit line BL can be precharged during the programming pulse application phase (t2 to t3) by the difference VPBSENSE-VTH between the voltage level VPBSENSE applied to the sixth transistor TR6 and the threshold voltage level VTH of the sixth transistor TR6.

[0175] Subsequently, the verification operation can be performed when the verification voltage is applied to the selected word line and the third pass voltage VPASS3 is applied to the unselected word line.

[0176] When the operation of applying the verification voltage to the selected word line is completed, the sixth signal PB_SENSE, the second signal SA_CSOC, and the fifth signal TRANSO can be changed to 0V (GND) level. The first signal PRECHSO_N, the eighth signal SA_PRE_N, and the fourth signal SA_PRECH_N can be changed to VCORE level.

[0177] Additionally, when the memory cell connected to the first page buffer PB1 via bit line BL is a selected memory cell, the third signal QS can be changed to 0V (GND) level, and when the memory cell connected to the first page buffer PB1 via bit line BL is an unselected memory cell, the third signal QS can be changed to VQS level.

[0178] Therefore, after the verification voltage is applied to the selected word line, both the selected bit line (BL) and the unselected bit line (BLs) can be discharged. Subsequently, in a new programming cycle, the selected bit line (BL) and the unselected bit line (BLs) can be pre-charged again.

[0179] Figure 10 This is a diagram illustrating a method for precharging bit lines for which programming operations are to be performed and bit lines for which programming operations are to be disabled.

[0180] Figure 10 The diagram shows a path 1003 where the selected bit line (BL) to which the memory cell to be programmed is connected is precharged, and a path 1001 where the unselected bit lines (BLs) to which the memory cell to be programmed is connected are precharged.

[0181] In the implementation method, during the bit line setting stage ( Figure 9 During t1 to t2), the unselected bit lines (BLs) connected to the memory cells that are not programmed (INHIBIT) can be precharged to the VCORE level.

[0182] Reference Figure 9 and Figure 10 During the bit line setup stage ( Figure 9 During t1 to t2), when the memory cell connected to the page buffer via bit line BL is an unselected memory cell, bit line BL can be precharged to the VCORE level as the second transistor TR2 and the sixth transistor TR6 are turned off and the seventh transistor TR7 and the eighth transistor TR8 are turned on. That is, the VCORE voltage can be transmitted to bit line BL (1001) via the seventh transistor TR7 and the eighth transistor TR8.

[0183] However, when the memory cell connected to the page buffer via bit line BL is the selected memory cell, bit line BL may not be precharged and may be at 0V (GND) level during the bit line setup phase (t1 to t2) as the second transistor TR2, the sixth transistor TR6 and the seventh transistor TR7 are turned off.

[0184] Subsequently, during the programming pulse application phase ( Figure 9 At the beginning of t2 to t3, if the memory cell connected to the page buffer via bit line BL is the selected memory cell, bit line BL can be precharged (1003) by the difference VPBSENSE-VTH between the voltage level VPBSENSE applied to the sixth transistor TR6 and the threshold voltage level VTH of the sixth transistor TR6, as the first transistor TR1, the second transistor TR2 and the sixth transistor TR6 are turned on and the seventh transistor TR7 is turned off.

[0185] However, when the memory cell connected to the page buffer via the bit line BL is an unselected memory cell, the potential of the bit line BL can be maintained at the VCORE level during the programming pulse application phase (t2 to t3) because the seventh transistor TR7 and the eighth transistor TR8 are still turned on.

[0186] In this implementation, during the PROGRAM PHASE phase, since the bit line to which the selected memory cell is connected is pre-charged to the VPBSENSE-VTH level, a voltage VPGM+OFFSET, which is larger than the programming voltage VPGM by an offset voltage OFFSET, can be applied to the selected word line Selected WL to which the selected memory cell is connected. In this document, the voltage VPGM is a default or starting voltage corresponding to the target state of the selected memory cell, used for programming the selected memory cell before gradually increasing as a step voltage. Furthermore, OFFSET can be greater than or equal to VPBSENSE-VTH, which is the pre-charge level of the selected bit line Selected BL during the VERIFY PHASE phase.

[0187] Figure 11 This is a diagram illustrating signals applied to a page buffer according to another embodiment of the present disclosure.

[0188] and Figure 9 different, Figure 11 This illustrates the case where the voltage increases from VPASS1 to VPGM after increasing from VPASS1 to VPGM, rather than immediately increasing from VPASS1 to VPGM+OFFSET after the first pass voltage VPASS1 is applied to the selected word line Selected WL. This excludes the pre-charge time of the selected bit line Selected BL. Figure 11 and Figure 9 Since they are the same, the repeated content will not be repeated here.

[0189] exist Figure 9In the implementation, when the first through voltage VPASS1(t21) is applied, the sixth signal PB_SENSE changes from 0V (GND) level to VPBSENSE level, the second signal SA_CSOC changes from 0V (GND) level to VSACSOC level, and the fifth signal TRANSO changes from 0V (GND) level to VTRANSO level.

[0190] However, in Figure 11 In this implementation, when the voltage applied to the Selected word line (Selected WL) increases from the VPASS1 level to the VPGM level (t22), the sixth signal PB_SENSE can change from the 0V (GND) level to the VPBSENSE level, and the second signal SA_CSOC can change from the 0V (GND) level to the VSACSOC level. Furthermore, when the voltage applied to the Selected word line (Selected WL) increases from the VPGM level to the VPGM+OFFSET level (t23), the fifth signal TRANSO can change from the 0V (GND) level to the VTRANSO level.

[0191] Therefore, when the voltage applied to the Selected word line Selected WL increases from the VPASS1 level to the VPGM level (t22), if the memory cell connected to the first page buffer PB1 via the bit line BL is an unselected memory cell, that is, the unselected bit line Unselected BLs connected to the memory cell that is in HNIBIT can be maintained at the VCORE level.

[0192] However, when the memory cell connected to the first page buffer PB1 via bit line BL is a selected memory cell, that is, when the voltage applied to the selected word line Selected WL increases from the VPASS1 level to the VPGM level (t22), the selected bit line Selected BL, which is connected to the memory cell that is allowed to be programmed (ALLOW), can be precharged to the VPBSENSE-VTH level.

[0193] As a result, when the voltage applied to the selected word line Selected WL increases from 0V to the VPASS1 level and then from the VPASS1 level to the VPGM level, that is, when the voltage applied to the selected word line Selected WL gradually increases, when the voltage increases from the VPGM level to the VPGM+OFFSET level, the selected bit line Selected BL can be precharged.

[0194] Figure 12 This is a diagram illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0195] Reference Figure 12 In operation S1201, the memory device may precharge unselected bit lines before applying a pass voltage to the selected word line. Unselected bit lines may refer to bit lines to which memory cells that are disabled for programming are connected.

[0196] In one implementation, the voltage level applied to the gate of the transistor included in the page buffer can be set to precharge the unselected bit line.

[0197] In operation S1203, when a pass voltage is applied to the selected word line, the selected bit line can be precharged. The selected bit line can be connected to the memory cell to which a programming operation is to be performed, and the selected bit line can be precharged to a voltage level corresponding to the difference between the level of the signal applied to the gate of the transistor connecting the bit line and the latch and the magnitude of the threshold voltage of the corresponding transistor.

[0198] Subsequently, in operation S1205, during both the programming and verification phases, the selected and unselected bit lines can be maintained at their respective pre-charge levels. That is, during both the programming and verification phases, the bit lines can be pre-charged only once without being discharged.

[0199] In operation S1207, after the verification voltage is applied to the selected word line, the memory device can discharge the selected and unselected bit lines during the balancing of the selected and unselected word lines. That is, since a programming cycle ends with the end of the verification phase, the selected and unselected bit lines can be discharged. Subsequently, when a new programming cycle is executed, the selected and unselected bit lines can be pre-charged again.

[0200] Figure 13 It is shown Figure 1 A diagram of another embodiment of the storage controller.

[0201] Storage controller 1000 is connected to a host and a storage device. Storage controller 1000 is configured to respond to signals from the host (e.g., ...). Figure 1 The memory controller 1000 accesses the memory device upon request from the host (300). For example, the memory controller 1000 is configured to control write operations, read operations, erase operations, and background operations of the memory device. The memory controller 1000 is configured to provide an interface between the memory device and the host. The memory controller 1000 is configured to drive firmware for controlling the memory device.

[0202] Reference Figure 13 The storage controller 1000 may include a processor 1010, a memory buffer 1020, an error correction circuit (ECC) 1030, a host interface 1040, a buffer controller (or buffer control circuit) 1050, a memory interface 1060, and a bus 1070.

[0203] Bus 1070 can be configured to provide a channel between components of storage controller 1000.

[0204] The processor 1010 controls the overall operation of the memory controller 1000 and performs logical operations. The processor 1010 can communicate with an external host via the host interface 1040 and with the memory device via the memory interface 1060. Additionally, the processor 1010 can communicate with the memory buffer 1020 via the buffer controller 1050. The processor 1010 can use the memory buffer 1020 as operational memory, cache memory, or buffer memory to control the operation of the memory device.

[0205] Processor 1010 can perform FTL functions. Processor 1010 can translate LBAs provided by the host into PBAs via FTL. FTL can use a mapping table to receive LBAs and translate them into PBAs. Any suitable address mapping method can be applied by the flash translation layer. Which mapping method is used depends on the mapping unit used by the system. For this purpose, various address mapping methods are available, including page mapping methods, block mapping methods, and hybrid mapping methods.

[0206] Processor 1010 is configured to randomize data received from the host. For example, processor 1010 may use a randomization seed to randomize data received from the host. The randomized data is provided as data to be stored to a memory device and programmed into a memory cell array.

[0207] The processor 1010 can perform randomization and derandomization via driver software or firmware.

[0208] The memory buffer 1020 can be used as the operating memory, cache memory, or buffer memory of the processor 1010. The memory buffer 1020 can store code and commands executed by the processor 1010. The memory buffer 1020 can store data processed by the processor 1010. The memory buffer 1020 may include static RAM (SRAM) or dynamic RAM (DRAM).

[0209] Error correction circuit 1030 can perform error correction. Error correction circuit 1030 can perform error correction encoding (ECC encoding) based on data to be written to the memory device via memory interface 1060. Error-corrected encoded data can be transmitted to the memory device via memory interface 1060. Error correction circuit 1030 can perform error correction decoding (ECC decoding) on ​​data received from the memory device via memory interface 1060. For example, error correction circuit 1030 can be included as a component of memory interface 1060.

[0210] Host interface 1040 is configured to communicate with an external host under the control of processor 1010. Host interface 1040 can be configured to perform communication using at least one of various communication protocols such as Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), High Speed ​​Peripheral Component Interconnect (High Speed ​​PCI), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and / or Load Reduction DIMM (LRDIMM).

[0211] The buffer controller 1050 is configured to control the memory buffer 1020 under the control of the processor 1010.

[0212] The memory interface 1060 is configured to communicate with a memory device under the control of the processor 1010. The memory interface 1060 can communicate commands, addresses, and data with the memory device via channels.

[0213] In another embodiment, the storage controller 1000 may not include the memory buffer 1020 and the buffer controller 1050. Each of these components may be provided separately and operatively coupled to the storage controller 1000.

[0214] For example, processor 1010 can use code to control the operation of memory controller 1000. Processor 1010 can load code from a non-volatile memory device (e.g., read-only memory) disposed within memory controller 1000. As another example, processor 1010 can load code from a memory device via memory interface 1060.

[0215] For example, the bus 1070 of the storage controller 1000 can be divided into a control bus and a data bus. The data bus can be configured to transmit data within the storage controller 1000, and the control bus can be configured to transmit control information such as commands and addresses within the storage controller 1000. The data bus and the control bus can be separated from each other to avoid interference or mutual influence. The data bus can be connected to the host interface 1040, the buffer controller 1050, the error correction circuit 1030, and the memory interface 1060. The control bus can be connected to the host interface 1040, the processor 1010, the buffer controller 1050, the memory buffer 1202, and the memory interface 1060.

[0216] Figure 14 This is a block diagram illustrating a memory card system that utilizes a storage device according to an embodiment of the present disclosure.

[0217] Reference Figure 14 The memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0218] Storage controller 2100 is connected to memory device 2200. Storage controller 2100 is configured to access memory device 2200. For example, storage controller 2100 is configured to control read operations, write operations, erase operations, and background operations of memory device 2200. Storage controller 2100 is configured to provide an interface between memory device 2200 and a host. Storage controller 2100 is configured to drive firmware for controlling memory device 2200. Memory device 2200 can be referenced... Figure 2 Description Figure 1 The memory device 100 is configured similarly.

[0219] As an example, the storage controller 2100 may include components such as random access memory (RAM), a processor, a host interface, a memory interface, and error correction circuitry.

[0220] Storage controller 2100 can communicate with external devices via connector 2300. Storage controller 2100 can communicate with external devices (e.g., a host) according to specific communication standards. As an example, storage controller 2100 is configured to communicate with external devices via at least one of various communication standards such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and / or NVMe. As an example, connector 2300 can be defined by at least one of the aforementioned communication standards.

[0221] As an example, the memory device 2200 may be implemented as any of a variety of non-volatile memory elements such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and / or spin-transfer torque magnetic RAM (STT-MRAM).

[0222] The storage controller 2100 and the memory device 2200 may be integrated into a semiconductor device to configure memory cards such as PC cards (Personal Computer Memory Card International Association (PCMCIA)), compact flash memory cards (CF), smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro or eMMC), SD cards (SD, miniSD, microSD or SDHC) and / or universal flash memory (UFS).

[0223] In this embodiment, when the memory device 2200 performs a programming operation, the memory device 2200 can connect to... Figure 2 The page buffers PB1 to PBn and the bit lines BL1 to BLn of the memory cell array 110 are precharged once. That is, programming operations can be performed even if the bit lines BL1 to BLn are precharged only once.

[0224] For example, during programming operations, bit lines BL1 to BLn can be pre-charged during the programming phase and then discharged, and bit lines BL1 to BLn can be pre-charged again during the verification phase. However, during the programming phase, memory device 2200 can pre-charge bit lines BL1 to BLn and then maintain the pre-charge level without discharging.

[0225] In one embodiment, the memory device 2200 may include a precharge circuit for precharging bit lines BL1 to BLn only once. The precharge circuit may be configured with multiple transistors, and these transistors may be turned on or off to precharge the bit lines.

[0226] In this implementation, bit lines BL1 to BLn can be precharged before a programming voltage is applied to the selected word line (Selected WL) to which the selected memory cell to be programmed is connected, and before a voltage is applied to the unselected word lines (Unselected WLs). Depending on whether a particular bit line includes a memory cell to be programmed, bit lines BL1 to BLn can be precharged to different levels.

[0227] For example, when a memory cell to be programmed is connected to a bit line, a voltage for pre-charging the corresponding bit line can be applied to the page buffer to which the bit line is connected. The pre-charge circuit may not be connected to the bit line and may be separate from the bit line.

[0228] As another example, when there is no memory cell to be programmed among the memory cells connected to the bit line, a voltage for pre-charging the corresponding bit line can be applied to the page buffer to which the bit line is connected. A pre-charging circuit can be connected to the bit line.

[0229] The voltage applied to the selected word line (Selected WL) can be a voltage with a larger offset voltage than the programming voltage. When bit lines BL1 to BLn are pre-charged during the programming phase, the programming voltage can be set to a large offset voltage because the potential of the bit lines connected to the selected memory cell is set to a specific level other than 0V.

[0230] In this implementation, bit lines BL1 to BLn can be precharged before the programming voltage is applied to the selected word line Selected WL, and the potentials of bit lines BL1 to BLn can continue to maintain the initial precharge level. Subsequently, when the operation of applying the verification voltage to the selected word line Selected WL is completed, bit lines BL1 to BLn can be discharged.

[0231] As a result, the time consumed during programming operations can be reduced because bit lines BL1 to BLn are not repeatedly precharged or discharged, but are only precharged or discharged once.

[0232] Figure 15 This is a block diagram illustrating a solid-state drive (SSD) system using a storage device according to an embodiment of the present disclosure.

[0233] Reference Figure 15 The SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals SIG with the host 3100 through a signal connector 3001 and receives power PWR through a power connector 3002. The SSD 3200 includes an SSD controller 3210, multiple flash memory modules 3221 to 322n, an auxiliary power supply unit 3230, and a cache memory 3240.

[0234] In this implementation, the SSD controller 3210 can perform... Figure 1 The functions of the storage controller 200.

[0235] SSD controller 3210 can control multiple flash memory modules 3221 to 322n in response to a signal SIG (which may be more than one signal) received from host 3100. As an example, the signal SIG may be based on the interface between host 3100 and SSD 3200. For instance, the signal SIG may be defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and / or NVMe.

[0236] In this implementation, when the flash memory 3221 to 322n performs a programming operation, the flash memory 3221 to 322n may precharge only once the bit lines connecting the page buffer and the memory cell array included in each of the flash memory 3221 to 322n. That is, the programming operation can be performed even if the bit lines are precharged only once.

[0237] For example, during programming operations, bit lines can be pre-charged during the programming phase and then discharged, and the bit lines can be pre-charged again during the verification phase. However, during the programming phase, flash memory 3221 to 322n can pre-charge the bit lines and then maintain the pre-charge level without discharging.

[0238] In one implementation, flash memory 3221 to 322n may include a precharge circuit for precharging the bit lines only once. The precharge circuit may be configured with multiple transistors that can be turned on or off to precharge the bit lines.

[0239] In this implementation, the bit lines may be precharged before a programming voltage is applied to the selected word line (Selected WL) to which the selected memory cell to be programmed is connected, and before a voltage is applied to the unselected word lines (Unselected WLs). Depending on whether a particular bit line includes a memory cell to be programmed, the bit line may be precharged to different levels.

[0240] For example, when a memory cell connected to a bit line contains a memory cell for which programming operations are to be performed, a voltage for pre-charging the corresponding bit line can be applied to the page buffer to which the bit line is connected. The pre-charging circuit may not be connected to the bit line and may be separate from the bit line.

[0241] As another example, when there is no memory cell to be programmed among the memory cells connected to the bit line, a voltage for pre-charging the corresponding bit line can be applied to the page buffer to which the bit line is connected. A pre-charging circuit can be connected to the bit line.

[0242] The voltage applied to the selected word line (WL) can be a voltage with a larger offset than the programming voltage. During the programming phase, when the bit line is pre-charged, the programming voltage can be set to a large offset voltage because the potential of the bit line connected to the selected memory cell is set to a specific level other than 0V.

[0243] In this implementation, the bit line can be precharged before the programming voltage is applied to the selected word line (Selected WL), and the bit line's potential can remain at the initial precharge level. Subsequently, the bit line can be discharged when the verification voltage application to the selected word line (Selected WL) is completed.

[0244] As a result, the time consumed during programming operations can be reduced because the bit lines are not repeatedly precharged or discharged, but only once.

[0245] An auxiliary power supply unit 3230 is connected to the host 3100 via a power connector 3002. The auxiliary power supply unit 3230 can receive power (PWR) from the host 3100 and can charge it. When the power supply from the host 3100 is unstable, the auxiliary power supply unit 3230 can provide power to the SSD 3200. As an example, the auxiliary power supply unit 3230 can be located inside or outside the SSD 3200. For instance, the auxiliary power supply unit 3230 can be located on the motherboard and can provide auxiliary power to the SSD 3200.

[0246] Buffer memory 3240 operates as a buffer memory for SSD 3200. For example, buffer memory 3240 may temporarily store data received from host 3100 or data received from multiple flash memory modules 3221 to 322n, or it may temporarily store metadata (e.g., a mapping table) of flash memory modules 3221 to 322n. Buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0247] Figure 16 This is a block diagram illustrating a user system that utilizes a storage device according to an embodiment of the present disclosure.

[0248] Reference Figure 16 The user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0249] Application processor 4100 can drive components, operating system (OS), user programs, etc., included in user system 4000. For example, application processor 4100 may include controllers, interfaces, graphics engines, etc., that control components included in user system 4000. Application processor 4100 may be provided as a system-on-chip (SoC).

[0250] Memory module 4200 can operate as main memory, operational memory, buffer memory, or cache memory of user system 4000. Memory module 4200 may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, application processor 4100 and memory module 4200 may be packaged in a stacked package (POP) and provided as a single semiconductor package.

[0251] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), LTE, WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. For example, network module 4300 may be included in application processor 4100.

[0252] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can send data stored in storage module 4400 to application processor 4100. For example, storage module 4400 can be implemented as a non-volatile semiconductor memory element such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, and three-dimensional NAND flash memory. For example, storage module 4400 can be provided as a removable storage device (removable drive) such as a memory card and as an external drive for user system 4000.

[0253] For example, storage module 4400 may include multiple non-volatile memory devices, each of which can be referenced. Figure 2 and Figure 3 The memory device described operates in the same manner. The memory module 4400 is compatible with the referenced... Figure 1 The storage device 50 described operates in the same manner.

[0254] In this implementation, when the storage module 4400 performs a programming operation, the storage module 4400 may precharge the bit lines connecting the page buffer and the memory cell array included in the storage module 4400 only once. That is, the programming operation can be performed even if the bit lines are precharged only once.

[0255] For example, during programming operations, bit lines can be pre-charged and then discharged during the programming phase, and can be pre-charged again during the verification phase. However, during the programming phase, the memory module 4400 can pre-charge the bit lines and then maintain the pre-charge level without discharging, without needing to separate the programming and verification phases.

[0256] In one implementation, the storage module 4400 may include a precharge circuit for precharging the bit lines only once, without separating the programming and verification phases. The precharge circuit may be configured with multiple transistors that can be turned on or off to precharge the bit lines.

[0257] In this implementation, the bit lines can be precharged before a programming voltage is applied to the selected word line (Selected WL) to which the selected memory cell to be programmed is connected, and before voltage is applied to the unselected word lines (Unselected WLs) other than the Selected WL. The bit lines can be precharged to different levels depending on whether any of the memory cells connected to the bit lines are to be programmed.

[0258] For example, when a memory cell connected to a bit line contains a memory cell for which programming operations are to be performed, a voltage for pre-charging the corresponding bit line can be applied to the page buffer to which the bit line is connected. The pre-charging circuit may not be connected to the bit line and may be separate from the bit line.

[0259] As another example, when there is no memory cell to be programmed among the memory cells connected to the bit line, a voltage for pre-charging the corresponding bit line can be applied to the page buffer to which the bit line is connected. A pre-charging circuit can be connected to the bit line.

[0260] The voltage applied to the selected word line (WL) can be a voltage with a larger offset than the programming voltage. During the programming phase, when the bit line is pre-charged, the programming voltage can have a large offset because the potential of the bit line connected to the selected memory cell is set to a specific level other than 0V.

[0261] In this implementation, the bit line can be precharged before the programming voltage is applied to the selected word line (Selected WL), and the bit line's potential can remain at the initial precharge level. Subsequently, the bit line can be discharged when the verification voltage application to the selected word line (Selected WL) is completed.

[0262] As a result, the time consumed during programming operations can be reduced because the bit lines are not repeatedly precharged or discharged, but only once.

[0263] User interface 4500 may include interfaces for inputting data or instructions to application processor 4100 or for outputting data to external devices. For example, user interface 4500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric element. User interface 4500 may include user output interfaces such as liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0264] Although the invention has been shown and described in conjunction with various embodiments, those skilled in the art will recognize, in view of this disclosure, that various modifications may be made. The invention covers all such modifications that fall within the scope of the claims.

[0265] Cross-reference to related applications

[0266] This application claims priority to Korean Patent Application No. 10-2020-0101435, filed on August 12, 2020, the entirety of which is incorporated herein by reference.

Claims

1. A memory device comprising: Multiple memory cells, which are connected to word lines and respectively connected to multiple bit lines; Multiple page buffers, each of which is connected to the multiple bit lines; as well as A voltage generator configured to generate a voltage to be applied to each of the plurality of page buffers. Each of the plurality of page buffers is configured to apply a precharge voltage higher than a preset level to the corresponding bit line among the plurality of bit lines during the time from the programming operation time when a programming voltage is applied to the word line to the verification operation time when a verification voltage is applied to the word line.

2. The memory device according to claim 1, wherein, Each of the plurality of page buffers includes a pre-charge circuit, and The pre-charging circuit includes: A first transistor, selectively connected to a power supply voltage; and A second transistor selectively connects the first transistor to any one of the plurality of bit lines.

3. The memory device according to claim 2, wherein, The voltage generator is configured to apply a voltage to the first transistor to turn it off during a programming operation in which the programming voltage is applied to the word line when the memory cell connected to the precharge circuit via one of the multiple bit lines is a selected memory cell to be programmed.

4. The memory device according to claim 3, wherein, The voltage generator applies the voltage to the first transistor to turn it off until the verification operation of applying the verification voltage to the word line is completed.

5. The memory device according to claim 3, wherein, The voltage generator applies a programming voltage to the word line that is offset by a higher voltage than the default programming voltage corresponding to the target programming state.

6. The memory device according to claim 2, wherein, The voltage generator is configured to apply a voltage to the first transistor and the second transistor to turn them on during a programming operation in which the programming voltage is applied to the word line when the memory cell connected to the precharge circuit via one of the multiple bit lines is a non-selected memory cell that is not programmed.

7. The memory device according to claim 6, wherein, The voltage generator applies the voltage to the first transistor and the second transistor to turn them on until the verification operation of applying the verification voltage to the word line is completed.

8. The memory device according to claim 1, wherein, Each of the plurality of page buffers includes: A latch, configured to store data; A data transmitter configured to transmit the data stored in the latch; and A sixth transistor is configured to connect the latch, the data transmitter, and any one of the multiple bit lines.

9. The memory device according to claim 8, wherein, When the memory cell connected to one of the bit lines is the selected memory cell to be programmed, the level of the precharge voltage applied to the bit line is based on the difference between the gate voltage of the sixth transistor and the threshold voltage of the sixth transistor.

10. The memory device according to claim 8, wherein, The data transmitter includes: A first transistor is connected between a power supply voltage and a first node; A second transistor, which is connected to the first transistor via the first node and to the sixth transistor via the second node; A third transistor is connected between the power supply voltage and the first node; A fourth transistor, which is connected between the first node and the sensing node; and A fifth transistor, which is connected to the fourth transistor and the latch.

11. The memory device according to claim 10, wherein, When the memory cell connected to the data transmitter via one of the multiple bit lines is the selected memory cell to be programmed, the bit line is pre-charged via the first transistor, the second transistor, and the sixth transistor during the programming operation in which the programming voltage is applied to the word line.

12. The memory device according to claim 10, wherein, When the memory cell connected to the data transmitter via one of the multiple bit lines is a programmable, unselected memory cell, the bit line is precharged to the level of the power supply voltage via a precharge circuit.

13. The memory device according to claim 10, wherein, When a pass voltage is applied to the word line before the programming voltage is applied to the word line, the voltage generator applies a voltage to the sixth transistor to turn it on.

14. The memory device according to claim 13, wherein, The voltage generator applies a voltage to the sixth transistor to turn it on until the verification operation of applying the verification voltage to the word line is completed.

15. The memory device according to claim 10, wherein, When a pass voltage is applied to the word line before the programming voltage is applied to the word line, the voltage generator applies a voltage to the second transistor to turn it on.

16. The memory device according to claim 15, wherein, The voltage generator applies the voltage to the second transistor to turn it on until the verification operation of applying the verification voltage to the word line is completed.

17. A method of operating a memory device, the memory device comprising a plurality of memory cells connected to a plurality of bit lines, the method comprising the steps of: Increase the potential of each of the multiple bit lines; While maintaining the increased potential of each of the plurality of bit lines, a programming operation is performed on a selected memory cell among the plurality of memory cells; as well as Following the programming operation, a verification operation is performed on the selected memory cell while maintaining the increased potential of each of the plurality of bit lines.

18. The method according to claim 17, wherein, The step of increasing the potential of each of the plurality of bit lines includes the following steps: increasing the potential of the bit line among the plurality of bit lines that is connected to the unselected memory cell that is disabled for programming.

19. The method according to claim 18, wherein, The step of increasing the potential of each of the plurality of bit lines includes the following steps: after increasing the potential of the bit line connected to the unselected memory cell, increasing the potential of the bit line connected to the selected memory cell.

20. An integrated circuit connected to an array of non-volatile memory cells via a first bit line, the integrated circuit comprising: The first path, during a first programming operation that programs a memory cell connected to the first bit line, through which the power supply voltage is delivered to the node; A second path, during a second programming operation that programs a memory cell connected to a second bit line, through which the power supply voltage is delivered to the first bit line, pre-charging the first bit line to the power supply voltage during the second programming operation without discharging; and A transistor configured to connect the node to the first bit line in response to a conduction signal having a conduction level during the first programming operation, so as to precharge the first bit line to the conduction level minus the threshold voltage level of the transistor during the first programming operation without performing a discharge. Each of the first programming operation and the second programming operation includes a programming phase and a verification phase.

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