Semiconductor structure and its formation method

Abstract

A semiconductor structure and its formation method are disclosed. The formation method includes: providing a substrate; forming a material layer to be doped and a top hard mask layer on the substrate; performing one or more patterning processes on the top hard mask layer, the patterning process including: forming a patterned structure layer on the top hard mask layer; etching the top hard mask layer using the patterned structure layer as a mask to form a mask opening; removing the patterned structure layer; and after completing the final patterning process, doping the material layer to be doped exposed through the mask opening with ions, the ion-doped material layer serving as the target patterned layer. The top hard mask layer of this invention has high etching resistance; therefore, during the formation of the mask opening, the sidewalls of the mask opening are less affected by lateral etching, thereby improving the verticality and flatness of the mask opening sidewalls, correspondingly improving the linewidth uniformity of the target patterned layer, and thus improving the pattern transfer accuracy.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology, driven by Moore's Law, continues to advance towards smaller process nodes, enabling integrated circuits to develop in the direction of smaller size, higher circuit precision, and higher circuit complexity.

[0003] In the development of integrated circuits, the functional density (i.e. the number of interconnects in each chip) usually increases gradually while the geometric size (i.e. the smallest component size that can be produced by process steps) gradually decreases, which correspondingly increases the difficulty and complexity of integrated circuit manufacturing.

[0004] Currently, with the continuous shrinking of technology nodes, improving the matching degree between the pattern formed on the wafer and the target pattern has become a challenge. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the accuracy of pattern transfer.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate; forming a material layer to be doped and a top hard mask layer located on the material layer to be doped on the substrate; performing one or more patterning processes on the top hard mask layer, the patterning process comprising: forming a patterned structure layer on the top hard mask layer; using the patterned structure layer as a mask, etching the top hard mask layer to form a mask opening in the top hard mask layer; removing the patterned structure layer after forming the mask opening; and performing ion implantation after completing the final patterning process to dope the material layer to be doped exposed by the mask opening, the ion-doped material layer being used as the target patterned layer.

[0007] Accordingly, embodiments of the present invention provide a semiconductor structure, including: a substrate; a material layer to be doped, located on the substrate; a top hard mask layer, located on the material layer to be doped, wherein a mask opening is formed in the top hard mask layer; and dopant ions, located in the material layer to be doped exposed by the mask opening, wherein the material layer to be doped with doped ions serves as a target patterning layer.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] In the formation method provided by this embodiment of the invention, a material layer to be doped and a top hard mask layer located on the material layer to be doped are formed on a substrate. Then, the top hard mask layer is subjected to one or more patterning processes. Each patterning process includes a step of etching the top hard mask layer using the patterned structure layer as a mask, and a step of removing the patterned structure layer. After the final patterning process is completed, ion implantation is performed to dope the material layer to be doped exposed by the mask opening. The ion-doped material layer to be doped serves as the target patterned layer. The patterned structure layer is composed of a stacked planarization layer, an anti-reflection coating, and a photoresist layer, and is etched and planarized. Compared to methods where ions are implanted into the exposed material layer after forming a mask opening in a planarization layer, the mask opening in this embodiment is formed in a top hard mask layer. Since the etching resistance of the top hard mask layer is greater than that of the planarization layer, the sidewalls of the mask opening are less affected by lateral etching during the etching process to form the opening. This improves the verticality and flatness of the mask opening's sidewalls. Consequently, when doping ions into the exposed material layer after the mask opening, the uniformity and controllability of the doping effect are improved, thereby enhancing the critical dimension uniformity (CDU) of the target pattern layer. For example, it improves the local CDU of the target pattern layer. Furthermore, since the target pattern layer is formed in the same implantation process, compared to methods involving multiple ion implantations, the uniformity of the doping effect is improved, which also contributes to improving the linewidth uniformity of the target pattern layer. In summary, the formation method provided by this embodiment improves the accuracy of pattern transfer. Attached Figure Description

[0010] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0011] Figure 7 yes Figures 1 to 6 In the embodiment described, a linear fitting curve of the target pattern layer linewidth and the mask opening linewidth is shown.

[0012] Figures 8 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;

[0013] Figure 15 yes Figures 8 to 14 In the embodiment described, a linear fitting curve is shown between the linewidth of the target pattern layer and the linewidth of the mask opening. Detailed Implementation

[0014] Currently, the accuracy of pattern transfer is not ideal. This paper analyzes the reasons for this poor accuracy by examining a semiconductor structure formation method.

[0015] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0016] refer to Figure 1 A substrate 10 is provided, on which a hard mask material layer 11 and a doping material layer 20 are formed.

[0017] Reference Figures 1 to 4 The material layer 20 to be doped is then subjected to doping treatment.

[0018] Specifically, the doping process includes:

[0019] like Figure 1 As shown, a patterned structure layer 30 is formed on the material layer 20 to be doped. The patterned structure layer 30 includes a planarization layer 31, an anti-reflection coating 32, and a patterned photoresist layer 33 stacked sequentially from bottom to top.

[0020] like Figure 2 As shown, the antireflective coating 32 and the planarization layer 31 are etched using the photoresist layer 33 as a mask, and a mask opening 35 is formed in the planarization layer 31 to expose the material layer 20 to be doped.

[0021] In this process, the photoresist layer 33 is removed during the formation of the mask opening 35, while the anti-reflective coating 32 on top of the planarization layer 31 is retained.

[0022] like Figure 3 As shown, ion implantation is performed to dope the material layer 20 exposed by the mask opening 35. The doped material layer 20 serves as the target pattern layer 25. The doped ions are used to improve the etching selectivity between the material layer 20 and the target pattern layer 25.

[0023] As an example, the target graphics layer 25 serves as a block layer, and the graphics are subsequently transferred to the substrate 10 using the block layer 25.

[0024] like Figure 4 As shown, after forming the target pattern layer 25, the anti-reflective coating 32 and the planarization layer 31 are removed.

[0025] refer to Figure 5 The doping process is repeated multiple times to form the target pattern layer 25 in the doped material layer 20 in other regions.

[0026] refer to Figure 6 After the final doping process is completed, the remaining material layer 20 to be doped is removed.

[0027] In subsequent processes, the target patterned layer 25 is used as a mask to etch the hard mask material layer 11 to form a patterned hard mask layer, and the hard mask layer is used as a mask to etch the substrate 10, thereby forming a functional structure (e.g., the functional structure can be a trench) in the substrate 10.

[0028] In the process of etching the planarization layer 31 to form the mask opening 35, the etching process of the planarization layer 31 includes a main etch step and an over etch step. During the over etch process, after the plasma enters the mask opening 35, it is affected by the reflection of the plasma, which will also cause the sidewall of the mask opening 35 to be affected by lateral etching.

[0029] However, the material of the planarization layer 31 usually has low etching resistance. For example, the material of the planarization layer 31 is spin-on carbon (SOC) material. Therefore, the sidewall of the mask opening 35 is significantly affected by lateral etching, resulting in low verticality and flatness of the sidewall of the mask opening 35.

[0030] Specifically, the anti-reflective coating 32 on top of the planarization layer 31 is retained, and the etching resistance of the anti-reflective coating 32 is greater than that of the planarization layer 31. Therefore, under the protection of the anti-reflective coating 32, the sidewall of the mask opening 35 is less affected by lateral etching at the position near the interface between the anti-reflective coating 32 and the planarization layer 31. That is, the linewidth variation of the top opening of the mask opening 35 is small, which causes the sidewall of the mask opening 35 to be concave inward, that is, the sidewall morphology of the mask opening 35 is bowl-shaped.

[0031] Because the sidewall morphology of the mask opening 35 is bowl-shaped, during the process of implanting ions into the doped material layer 20 exposed by the mask opening 35, the implanted ions are prone to come into contact with the sidewall of the mask opening 35 and be reflected or absorbed, thereby interfering with the implantation direction of the implanted ions. This leads to the inability to guarantee the implantation area (i.e., the problem of pattern offset is prone to occur), which in turn leads to a deterioration in the linewidth uniformity of the target pattern layer 25. For example, it leads to a deterioration in the local linewidth uniformity of the target pattern layer 25.

[0032] Moreover, the sidewalls of the mask opening 35 are affected by lateral etching, resulting in randomness in the sidewall morphology of the mask opening 35, which further reduces the linewidth uniformity of the target pattern layer 25.

[0033] Furthermore, in the above-mentioned formation method, multiple patterning processes such as exposure-etching-exposure-etching (Litho-Etch-Litho-Etch, LELE) and multiple ion implantations are combined to form the target pattern layer 25 in different regions of the material layer 20 to be doped. When multiple ion implantations are used, the uniformity of the doping effect is difficult to guarantee, thereby further reducing the linewidth uniformity of the target pattern layer 25.

[0034] Reference Figure 7 , Figure 7 This is a linear fitting curve of the target pattern layer linewidth and the mask opening linewidth in the above-described formation method. The horizontal axis represents the mask opening linewidth in the planarization layer, the vertical axis represents the target pattern layer linewidth, and curve L1 represents the linear fitting curve between the target pattern layer linewidth and the mask opening linewidth.

[0035] Depend on Figure 7 It can be seen that the fit between the target pattern layer linewidth and the mask opening linewidth is low. Specifically, the squared value of the correlation coefficient (i.e., R²) corresponding to curve L1 is... 2 The value is 0.89. This indicates that the uniformity of the linewidth in the target graphic layer is difficult to guarantee.

[0036] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate; forming a material layer to be doped and a top hard mask layer located on the material layer to be doped on the substrate; performing one or more patterning processes on the top hard mask layer, the patterning process comprising: forming a patterned structure layer on the top hard mask layer; using the patterned structure layer as a mask, etching the top hard mask layer to form a mask opening in the top hard mask layer; removing the patterned structure layer after forming the mask opening; and performing ion implantation after completing the final patterning process to dope the material layer to be doped exposed by the mask opening, the ion-doped material layer being used as the target patterned layer.

[0037] In the formation method provided by this embodiment of the invention, a material layer to be doped and a top hard mask layer located on the material layer to be doped are formed on a substrate. Then, the top hard mask layer is subjected to one or more patterning processes. Each patterning process includes a step of etching the top hard mask layer using a patterned structure layer as a mask, and a step of removing the patterned structure layer. After the final patterning process is completed, ion implantation is performed to dope the material layer to be doped exposed by the mask opening. The ion-doped material layer to be doped serves as the target patterned layer. Compared to a scheme that uses a patterned structure layer composed of a stacked planarization layer, an anti-reflection coating, and a photoresist layer, and then etches the planarization layer, forms a mask opening in the planarization layer, and then implants ions into the material layer to be doped exposed by the mask opening, this embodiment of the invention provides a more efficient mask opening process. The opening is formed in the top hard mask layer. Since the etching resistance of the top hard mask layer is greater than that of the planarization layer, the sidewalls of the mask opening are less affected by lateral etching during the etching process to form the mask opening. This helps to improve the verticality and flatness of the sidewalls of the mask opening. Correspondingly, when doping ions into the doped material layer exposed to the mask opening, it helps to improve the uniformity and controllability of the doping effect, thereby improving the linewidth uniformity of the target pattern layer. For example, it improves the local linewidth uniformity of the target pattern layer. Moreover, the target pattern layer is formed in the same implantation process, which is beneficial to improving the uniformity of the doping effect compared with the scheme of multiple ion implantation. This also helps to improve the linewidth uniformity of the target pattern layer. In summary, the formation method provided by the embodiments of the present invention improves the accuracy of pattern transfer.

[0038] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] Figures 8 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0040] refer to Figure 8 Provides a base of 100.

[0041] The substrate 100 is used to form a functional structure after an etching process.

[0042] The functional structure can be a gate structure, an interconnect trench in a back end of line (BEOL) process, a fin in a FinFET, a channel stack in a gate all-around-the-air (GAA) transistor, or a hard mask (HM) layer, etc.

[0043] The substrate 100 can be a single-layer structure or a multilayer structure. The material of the substrate 100 can include one or more of silicon, silicon germanium, titanium nitride, low-k dielectric materials (low-k dielectric materials refer to dielectric materials with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) and ultra-low-k dielectric materials (ultra-low-k dielectric materials refer to dielectric materials with a relative permittivity less than 2.6).

[0044] As an example, the substrate 100 includes an inter-metal dielectric (IMD) layer, which serves as an etchable layer for forming interconnect trenches after an etching process, i.e., the functional structure is an interconnect trench.

[0045] The inter-metal dielectric layer is used to achieve electrical isolation between metal interconnect structures in the back-end process.

[0046] As an example, the material of the inter-metal dielectric layer is an ultra-low-k dielectric material, thereby reducing the parasitic capacitance between the subsequent metal interconnect structures and thus reducing the subsequent RC delay. Specifically, the ultra-low-k dielectric material can be SiOCH.

[0047] In other embodiments, the substrate may also be an initial substrate for etching to form the substrate and the fins protruding from the substrate.

[0048] Continue to refer to Figure 8 The forming method further includes forming a bottom hard mask (HM) layer 110 on the substrate 100.

[0049] After the bottom hard mask layer 110 is subsequently etched, the pattern is transferred through the etched bottom hard mask layer 110 and then transferred downwards to the substrate 100. The bottom hard mask layer 110 helps to improve the accuracy of pattern transfer.

[0050] In this embodiment, after the bottom hard mask layer 110 is formed, the bottom hard mask layer 110 covers the entire substrate 100.

[0051] In this embodiment, the material of the bottom hard mask layer 110 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, titanium, titanium oxide, titanium nitride, tantalum, tantalum oxide, tantalum nitride, boron nitride, copper nitride, aluminum nitride, and tungsten nitride.

[0052] As an example, the bottom hard mask layer 110 is a metal hard mask (MHM) layer, and the material of the bottom hard mask layer 110 is titanium nitride.

[0053] Continue to refer to Figure 8A doped material layer 120 and a top hard mask layer 200 are formed on the substrate 100.

[0054] The material layer 120 to be doped is then doped to form the target patterned layer.

[0055] Depending on the process requirements, the target patterned layer can be a film layer that needs to be retained or a film layer that needs to be removed later.

[0056] In this embodiment, the target graphic layer is used as a barrier layer, and the graphic is subsequently transferred downward to the substrate 100 using the barrier layer.

[0057] In other embodiments, the target pattern layer is the functional structure used to form the device.

[0058] In other embodiments, the target patterned layer is a film layer to be removed, thereby forming a groove in the remaining material layer to be doped after the target patterned layer is removed.

[0059] In this embodiment, after the target pattern layer is formed, the undoped material layer 120 will be removed. Therefore, the material layer 120 is made of a material that is easy to remove, and the process of removing the material layer 120 causes less damage to the film layer below it (e.g., the bottom hard mask layer 110).

[0060] Specifically, the material to be doped layer 120 is different from the material of the bottom hard mask layer 110.

[0061] The material of the doped material layer 120 includes one or more of amorphous silicon (a-Si), silicon nitride, silicon oxide, and titanium oxide.

[0062] In this embodiment, the material layer 120 to be doped is amorphous silicon. Amorphous silicon has high process compatibility, and by selecting amorphous silicon, it is easy to change the etching resistance of certain areas in the material layer 120 to be doped through ion doping.

[0063] The top hard mask layer 200 is used as a mask when the material layer 120 to be doped is subsequently doped.

[0064] Specifically, a mask opening is subsequently formed in the top hard mask layer 200, thereby forming a target patterned layer by implanting ions into the material layer 120 exposed by the mask opening.

[0065] In this embodiment, compared to the scheme of using a patterned structure layer composed of stacked planarization layers, anti-reflection coatings, and photoresist layers as a mask when doping the material layer to be doped, that is, compared to the scheme of using a patterned structure layer composed of stacked planarization layers, anti-reflection coatings, and photoresist layers, etching the planarization layer, forming a mask opening in the planarization layer, and then implanting ions into the material layer to be doped exposed by the mask opening, in this embodiment, the top hard mask layer 200 is formed on the substrate 100 before forming the patterned structure layer, and the pattern in the patterned structure layer is subsequently transferred to the top hard mask layer 200. Mask openings are formed in the top hard mask layer 200. Since the top hard mask layer 200 has a higher etching resistance than the planarization layer, the sidewalls of the mask openings are less affected by lateral etching during the subsequent etching process to form the mask openings. This helps to improve the verticality and flatness of the sidewalls of the mask openings. Correspondingly, when ions are implanted into the doped material layer exposed by the mask openings, it helps to improve the uniformity and controllability of the doping effect, thereby improving the critical dimension uniformity (CDU) of the target pattern layer. For example, it improves the local CDU of the target pattern layer. Therefore, this embodiment improves the accuracy of pattern transfer.

[0066] In this embodiment, the target pattern layer is used as a barrier layer, and the barrier layer is used as a mask for etching the substrate 100, thereby improving the pattern accuracy of subsequent functional structures.

[0067] It should be noted that the top hard mask layer 200 needs to be etched subsequently to form a mask opening. Therefore, in order to reduce damage to the material layer 120 to be doped, thereby affecting the quality of the subsequent target pattern layer, the material of the top hard mask layer 200 is selected such that the etching selectivity ratio of the top hard mask layer 200 to the material layer 120 to be doped is greater than 5:1.

[0068] Furthermore, after the target pattern layer is formed, the top hard mask layer 200 needs to be removed. Therefore, the top hard mask layer 200 is made of a material that is easy to remove, and the process of removing the top hard mask layer 200 has little impact on the target pattern layer.

[0069] The material of the top hard mask layer 200 includes a dielectric material or a metal, wherein the dielectric material includes one or more of silicon oxide, silicon nitride, silicon, and silicon carbide, and the metal includes one or more of titanium oxide, titanium nitride, and tungsten carbide.

[0070] Specifically, the material of the top hard mask layer 200 is different from the material of the doped material layer 120.

[0071] As an example, the material of the top hard mask layer 200 is silicon dioxide.

[0072] Continue to refer to Figure 8 After forming the top hard mask layer 200, the forming method further includes forming a buffer layer 210 on the top hard mask layer 200.

[0073] Subsequently, a patterned structure layer is formed on the buffer layer 210. The material of the patterned structure layer is usually an organic material. The buffer layer 210 is located between the patterned structure layer and the top hard mask layer 200, and is used to improve the adhesion between the top hard mask layer 200 and the patterned structure layer, thereby improving the accuracy of pattern transfer.

[0074] Furthermore, before etching the top hard mask layer 200, the buffer layer 210 is etched first to form a transition opening. Then, the top hard mask layer 200 at the bottom of the transition opening is etched, transferring the pattern of the transition opening to the top hard mask layer 200, forming a mask opening in the top hard mask layer 200. Therefore, the buffer layer 210 also protects the top corner of the mask opening (i.e., the corner between the sidewall of the mask opening and the top surface of the top hard mask layer 200), thereby preventing the formation of rounded corners at the top corner of the mask opening. When doping ions into the doped material layer 120 exposed to the mask opening, this helps to improve the uniformity and controllability of the doping effect, thereby improving the linewidth uniformity of the target pattern layer.

[0075] The material of the buffer layer 210 includes a dielectric material or a metal, wherein the dielectric material includes one or more of silicon oxide, silicon nitride, silicon, and silicon carbide, and the metal includes one or more of titanium oxide, titanium nitride, and tungsten carbide.

[0076] In this embodiment, the buffer layer 210 will be removed subsequently. Therefore, the buffer layer 210 is made of a material that is easy to remove, and there is a high etching selectivity between the buffer layer 210 and the top hard mask layer 200, so that the damage to the top hard mask layer 200 is reduced when the buffer layer 210 is removed subsequently.

[0077] Specifically, the buffer layer 210 and the top hard mask layer 200 are made of different materials.

[0078] As an example, the material of the buffer layer 210 is silicon oxide. Specifically, the material of the buffer layer 210 is low-temperature oxide (LTO). By using LTO, it is beneficial to reduce the impact of the deposition process temperature for forming the buffer layer 210 on subsequent processes.

[0079] It should be noted that the thickness of the buffer layer 210 should not be too small or too large. If the thickness of the buffer layer 210 is too small, the protective effect of the top hard mask layer 200 directly below the remaining buffer layer 210 will be poor during the etching process, which will easily lead to the formation of rounded corners at the top corners of the mask opening. If the thickness of the buffer layer 210 is too large, the geometric effect of the plasma will be more severe during the etching process, and the ion directionality of the plasma will be poor, which will cause the morphology of the transition opening to have an adverse effect on the morphology of the mask opening. Therefore, in this embodiment, the thickness of the buffer layer 210 is [not specified]. to For example, the thickness of the buffer layer 210 is or

[0080] Reference Figure 8 and Figure 9 The top hard mask layer 200 is patterned, and the patterning process includes forming a patterned structure layer 300 (e.g., ...) on the top hard mask layer 200. Figure 8 (As shown); using the patterned structure layer 300 as a mask, the top hard mask layer 200 is etched to form a mask opening 220 in the top hard mask layer 200 (as shown). Figure 9 (as shown); after forming the mask opening 220, the graphic structure layer 300 is removed.

[0081] The top hard mask layer 200 is patterned to form a mask opening 220, which is used to define the formation area of ​​the subsequent target pattern layer.

[0082] In this embodiment, the patterned structure layer 300 includes a planarization layer 310, an anti-reflection coating 320, and a patterned photoresist layer 330 stacked sequentially from bottom to top.

[0083] The photoresist layer 330 has a patterned opening 340, which is used to define the position, shape and size of the mask opening.

[0084] The planarization layer 310 is used to provide a flat surface for the formation of the photoresist layer 330, which helps to improve exposure uniformity, thereby improving the size and shape accuracy of the pattern opening 340.

[0085] In this embodiment, the planarization layer 310 includes a spin-on carbon (SOC) layer. Specifically, the material of the SOC layer is amorphous carbon.

[0086] The SOC layer is formed using a spin coating process, which enables the planarization layer 310 to have a high degree of flatness on its top surface and reduces the complexity and cost of forming the planarization layer 310.

[0087] The anti-reflective coating 320 is used to improve exposure uniformity to ensure the accuracy of pattern transfer.

[0088] The anti-reflective coating 320 is made of one or more of the following materials: BARC (bottom anti-reflective coating), DARC (dielectric anti-reflective coating), and Si-ARC (silicon-based anti-reflective coating).

[0089] In this embodiment, the anti-reflective coating 320 is made of Si-ARC. The Si-ARC layer is beneficial for increasing the depth of field (DOF) during the photolithography process, improving exposure uniformity, and because the Si-ARC layer is rich in silicon, it also helps to increase the hardness of the anti-reflective coating 320, thereby further improving the transfer accuracy of the pattern.

[0090] As critical dimensions continue to shrink, the requirements for the accuracy and stability of pattern transfer are becoming increasingly stringent. By employing a layered pattern structure layer 300, the pattern in the photoresist layer 330 is first transferred to the anti-reflective coating 320. Then, using the patterned anti-reflective coating 320 as a mask, the pattern in the anti-reflective coating 320 is transferred to the planarization layer 310. Finally, the planarization layer 310 is used to transfer the pattern to the top hard mask layer 200, thereby enhancing the pattern transfer accuracy.

[0091] Accordingly, the patterning process further includes: before etching the top hard mask layer 200, using the photoresist layer 330 as a mask, etching the anti-reflection coating layer 320 and the planarization layer 310.

[0092] In other embodiments, in order to save process steps and reduce process costs, the patterned structure layer may also be a single-layer structure, and the patterned structure layer may be a photoresist layer.

[0093] In this embodiment, when etching the top hard mask layer 200, the etching selectivity ratio of the top hard mask layer 200 to the material layer 120 to be doped is greater than 5:1.

[0094] In this embodiment, in order to enable the doping of ions into the material layer 120 to be doped and subsequently exposed to the mask opening 220, the angle between the sidewall of the mask opening 220 and the surface of the substrate 100 is greater than or equal to 90 degrees, thereby avoiding the top opening size of the mask opening 220 being smaller than the bottom opening size.

[0095] However, the angle between the sidewall of the mask opening 220 and the surface of the substrate 100 should not be too large. If the angle between the sidewall of the mask opening 220 and the surface of the substrate 100 is too large, the implanted ions are likely to come into contact with the sidewall of the mask opening 220 and be reflected or absorbed, thereby interfering with the implantation direction of the implanted ions. This can lead to the implantation area not being guaranteed (i.e., the problem of pattern offset is likely to occur), which in turn leads to a decrease in the linewidth uniformity of the subsequent barrier layer.

[0096] Therefore, in this embodiment, the angle between the sidewall of the mask opening 220 and the surface of the substrate 100 is 90 to 95 degrees.

[0097] In this embodiment, an anisotropic etching process is used to etch the top hard mask layer 200. The longitudinal etching rate of the anisotropic etching process is much greater than its lateral etching rate, which is beneficial to improving the sidewall verticality and flatness of the mask opening 220.

[0098] Specifically, the anisotropic etching process is a plasma dry etching process.

[0099] In this embodiment, the parameters of the anisotropic etching process include: the etching gas includes one or more of CF-based gas and CFH-based gas, and the carrier gas includes one or more of Ar, O2, N2 and He.

[0100] In the plasma dry etching process, the reactive gas is plasmaified by the source power. Therefore, the source power of the plasma dry etching process should not be too low or too high. If the source power is too low, the dissociation effect of the reactive gas will be poor, thereby reducing the etching rate of the top hard mask layer 200, resulting in insufficient etching by-products and a decrease in etching selectivity. Consequently, it is easy to damage other film layers. If the source power is too high, the electron density of the generated plasma will be too high, resulting in too many etching by-products during the etching process, which will reduce the etching uniformity and adversely affect the sidewall verticality and flatness of the mask opening 220. Therefore, in this embodiment, the source power of the plasma dry etching process is 500W to 1500W. For example, the source power of the plasma dry etching process is 700W, 900W, or 1200W.

[0101] In the plasma dry etching process, bias radio frequency power is applied to the surface of substrate 100. This bias power drives high-energy plasma towards the surface of substrate 100, giving the plasma a high velocity and energy, thereby achieving etching. Therefore, the bias power in the plasma dry etching process should not be too low or too high. If the bias power is too low, the etching rate of the top hard mask layer 200 will be reduced, and the plasma directionality will deteriorate, thus reducing the sidewall perpendicularity of the mask opening 220. If the bias power is too high, the plasma will have excessively high velocity and energy, potentially damaging other layers (e.g., the material layer 120 to be doped). Therefore, in this embodiment, the bias power of the plasma dry etching process is between 200W and 2000W. For example, the bias power of the plasma dry etching process is 500W, 1000W, or 1500W.

[0102] The process pressure of the plasma dry etching process should not be too low or too high. If the process pressure is too low, the physical bombardment effect is strong, which can easily damage other film layers (e.g., the material layer 120 to be doped); if the process pressure is too high, the etching uniformity is poor, which can adversely affect the sidewall perpendicularity and flatness of the mask opening 220. Therefore, in this embodiment, the process pressure of the plasma dry etching process is 4 mTorr to 200 mTorr. For example, the process pressure of the plasma dry etching process is 50 mTorr, 100 mTorr, or 150 mTorr.

[0103] In this embodiment, after the mask opening 220 is formed, the pattern structure layer 300 is removed to prepare for subsequent processes.

[0104] As an example, after etching the planarization layer 310, the photoresist layer 330 is removed. Therefore, after forming the mask opening 220, the remaining planarization layer 310 and anti-reflective coating 320 are removed.

[0105] refer to Figure 10 The top hard mask layer 200 is subjected to the patterning process once or multiple times to form mask openings 220 in other areas of the top hard mask layer 200.

[0106] As circuit integration density and scale increase, critical dimensions continue to shrink. By employing multiple patterning processes such as exposure-etching-exposure-etching (Litho-Etch-Litho-Etch, LELE), mask openings 220 are formed, thereby alleviating the limitation of photolithography resolution and improving the process window of photolithography.

[0107] As an example, three graphical processes are performed to form mask openings 220 in different regions of the top hard mask layer 200.

[0108] It should be noted that a buffer layer 210 is formed on the top hard mask layer 200. Therefore, in each patterning process, the process also includes: before etching the top hard mask layer 200, using the pattern structure layer 300 as a mask, etching the buffer layer 210 to form a transition opening (not shown).

[0109] Correspondingly, the top hard mask layer 200 at the bottom of the transition opening is etched to form a mask opening 220.

[0110] Reference Figure 11 After completing the final graphical processing, the forming method further includes removing the buffer layer 210.

[0111] When the top corner of the transition opening (not shown) in the buffer layer 210 is rounded, the morphology of the transition opening can be avoided from affecting the subsequent ion implantation process by removing the buffer layer 210.

[0112] In this embodiment, a wet etching process is used to remove the buffer layer 210. The wet etching process has the characteristic of isotropic etching, which is beneficial for completely removing the buffer layer 210. Moreover, the wet etching process has a lower cost and causes less damage to other film layers.

[0113] In other embodiments, remote plasma etching can also be used to remove the buffer layer. Remote plasma etching also exhibits isotropic etching characteristics, which is beneficial for thoroughly removing the buffer layer. Furthermore, remote plasma etching also has good etching selectivity, thereby reducing the loss of the top hard mask layer or the layer to be doped during the etching process. The principle of remote plasma etching is to generate plasma outside the etching chamber (e.g., by generating plasma through a remote plasma generator), then introduce it into the etching chamber and use the chemical reaction between the plasma and the layer to be etched to perform etching. This achieves an isotropic etching effect, and because there is no ion bombardment, it does not damage other film layers.

[0114] refer to Figure 12 After removing the buffer layer 210, ion implantation is performed to dope the material layer 120 exposed by the mask opening 220 with ions. The material layer 120 doped with ions serves as the target pattern layer 130.

[0115] The doping ions are adapted to increase the etching selectivity between the material layer 120 to be doped and the target pattern layer 130.

[0116] In this embodiment, the etching selectivity ratio between the doped material layer 120 and the target patterned layer 130 refers to the ratio of the etching rates of the doped material layer 120 and the target patterned layer 130 when etching the doped material layer 120. In other words, when the doped material layer 120 is subsequently etched, the etching rate of the ion-implanted doped material layer 120 (i.e., the target patterned layer 130) is lower, thereby allowing the target patterned layer 130 to be preserved.

[0117] In other embodiments, the etching selectivity ratio between the material layer to be doped and the target patterned layer refers to the ratio of the etching rates of the target patterned layer and the material layer to be doped when etching the target patterned layer. In other words, when the target patterned layer is subsequently etched, the etching rate of the material layer to be doped is lower, thereby allowing the material layer to be doped to be retained.

[0118] In this embodiment, since the sidewall verticality and flatness of the mask opening 220 are relatively high, it is beneficial to improve the uniformity and controllability of the doping effect when doping ions are exposed in the material layer 120 to be doped through the mask opening 220, thereby improving the linewidth uniformity of the target pattern layer 130 and correspondingly improving the accuracy of pattern transfer.

[0119] Specifically, the target pattern layer 130 is used as a barrier layer, which serves as a mask for etching the substrate 100, thereby enabling higher pattern accuracy of the functional structures subsequently formed in the substrate 100.

[0120] Reference Figure 15 , Figure 15 This is a linear fitting curve of the linewidth of the target pattern layer 130 and the linewidth of the mask opening 220. The horizontal axis represents the linewidth of the mask opening 220, the vertical axis represents the linewidth of the target pattern layer 130, and curve L2 represents the linear fitting curve of the linewidth of the target pattern layer 130 and the linewidth of the mask opening 220 in one embodiment.

[0121] Depend on Figure 15 It can be seen that the fit between the target pattern layer linewidth of 130 and the mask opening linewidth of 220 is relatively high. Specifically, the squared value of the correlation coefficient (i.e., R²) corresponding to curve L2 is... 2 The value is 0.99, which shows that by forming a mask opening 220 in the top hard mask layer 200, it is beneficial to accurately transfer the pattern of the mask opening 220 to the material layer 120 to be doped, thereby improving the linewidth uniformity of the target pattern layer 130.

[0122] In this embodiment, ion implantation is used to dope the material layer 120 exposed by the mask opening 220. Ion implantation offers high process flexibility, positional accuracy, and dimensional accuracy, and makes it easy to achieve a smaller size for the target patterned layer 130.

[0123] In this embodiment, ions are doped into a portion of the material layer 120 to be doped through ion implantation, thereby creating differences in the microstructure of the material layer 120.

[0124] Specifically, the ions reduce the grain boundary gaps of silicon in the target patterned layer 130 material, thereby improving the thermal and chemical stability of the target patterned layer 130. The improved stability is beneficial to improving the corrosion resistance of the target patterned layer 130, thereby increasing the etching selectivity between the doped material layer 120 and the target patterned layer 130, so that the subsequent etching process of the doped material layer 120 has little impact on the target patterned layer 130.

[0125] In this embodiment, the implanted ions include one or more of B ions, C ions, P ions, and As ions.

[0126] As an example, boron (B) ions are used for implantation. By doping a portion of the amorphous silicon with boron ions, the material of the target patterned layer 130 is transformed into boron-doped silicon, thereby significantly improving the etch resistance of the target patterned layer 130. Furthermore, the high stability of boron atoms is beneficial for improving the thermal and chemical stability of the target patterned layer 130. In addition, boron ions are commonly used doping ions in the semiconductor field, offering high process compatibility.

[0127] In particular, by adjusting the implantation dose of the ion implantation process, the etching selectivity ratio between the material layer 120 to be doped and the target pattern layer 130 can be easily adjusted.

[0128] In this embodiment, the target patterned layer 130 is formed in the same ion implantation process. Compared with the scheme of performing multiple ion implantations, this is beneficial to improving the uniformity of the doping effect, which is also beneficial to improving the linewidth uniformity of the target patterned layer 130.

[0129] refer to Figure 13 After forming the target graphic layer 130, the top hard mask layer 200 is removed.

[0130] Removing the top hard mask layer 200 prepares for the subsequent removal of the remaining doped material layer 120.

[0131] In this embodiment, a wet etching or dry etching process is used to remove the top hard mask layer 200.

[0132] It should be noted that, in other embodiments, depending on the actual situation, the buffer layer and the top hard mask layer may be removed sequentially after the target pattern layer is formed.

[0133] refer to Figure 14 Remove the top hard mask layer 200 (e.g.) Figure 12 After (as shown), remove the remaining layer 120 of the material to be doped (as shown). Figure 13 (As shown).

[0134] In this embodiment, the target pattern layer 130 is used as a barrier layer, which serves as a mask for subsequent etching of the substrate 100. Therefore, by removing the remaining material layer 120 to be doped, preparation is made for subsequent etching of the substrate 100.

[0135] In this embodiment, a maskless etching process is used to remove the remaining material layer 120 to be doped.

[0136] The etching selectivity between the doped material layer 120 and the target pattern layer 130 is high, and the etching selectivity between the doped material layer 120 and the bottom hard mask layer 110 is also high. Therefore, during the removal of the remaining doped material layer 120, the etching rate of the target pattern layer 130 and the bottom hard mask layer 110 is low. Accordingly, a maskless etching process can be used to remove the remaining doped material layer 120, thereby simplifying the process steps and reducing costs. Moreover, by using a maskless etching process, the process window for removing the doped material layer 120 is significantly increased.

[0137] Specifically, a wet etching process is used to remove the remaining material layer 120 to be doped.

[0138] Wet etching process can easily achieve a high etching selectivity, and wet etching process removes the remaining material layer 120 to be doped by chemical reaction, which helps to reduce damage to other film layers, and also helps to remove the remaining material layer 120 to be doped cleanly.

[0139] In this embodiment, the material of the doped material layer 120 is amorphous silicon, and the etching solution used in the wet etching process is a mixed solution of Cl2 and HBr or a TMAH solution.

[0140] It should be noted that, in other embodiments, since there is a high etching selectivity between the material layer to be doped and the target pattern layer, the target pattern layer can also be removed after the top hard mask layer is removed, leaving the remaining material layer to be doped, thereby forming a groove in the remaining material layer to be doped.

[0141] Accordingly, the present invention also provides a semiconductor structure. (Continue to refer to...) Figure 12 The diagram shows a schematic representation of an embodiment of the semiconductor structure of the present invention.

[0142] The semiconductor structure includes: a substrate 100; a material layer 120 to be doped, located on the substrate 100; a top hard mask layer 200, located on the material layer 120 to be doped, wherein a mask opening 220 is formed in the top hard mask layer 200; and dopant ions, located in the material layer 120 to be doped exposed by the mask opening 220, wherein the material layer 120 to be doped with doped ions serves as a target patterning layer 130.

[0143] During the formation of the semiconductor structure, the mask opening 220 is formed by etching the top hard mask layer 200, and the area of ​​the target pattern layer 130 is determined by the mask opening 220. Compared to a scheme that uses a patterned structure layer composed of stacked planarization layers, anti-reflection coatings, and photoresist layers, and places the mask opening in the planarization layer, the mask opening 220 in this embodiment is located in the top hard mask layer 200. Since the etching resistance of the top hard mask layer 200 is greater than that of the planarization layer, the sidewalls of the mask opening 220 are less affected by lateral etching during the formation of the mask opening 200. This helps to improve the verticality and flatness of the sidewalls of the mask opening 220. Therefore, during the formation of the semiconductor structure, when ions are doped into the dopant material layer 120 exposed by the mask opening 220 using the ion implantation process, the uniformity and controllability of the doping effect are high. Correspondingly, the linewidth uniformity of the target patterned layer 130 is high. For example, the local linewidth uniformity of the target patterned layer 130 is high, thereby enabling the semiconductor structure to achieve high pattern transfer accuracy.

[0144] The substrate 100 is used to form a functional structure after an etching process.

[0145] The functional structure can be a gate structure, an interconnect trench in a back end of line (BEOL) process, a fin in a FinFET, a channel stack in a gate all-around-the-air (GAA) transistor, or a hard mask (HM) layer, etc.

[0146] The substrate 100 can be a single-layer structure or a multilayer structure. The material of the substrate 100 can include one or more of silicon, silicon germanium, titanium nitride, low-k dielectric materials (low-k dielectric materials refer to dielectric materials with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) and ultra-low-k dielectric materials (ultra-low-k dielectric materials refer to dielectric materials with a relative permittivity less than 2.6).

[0147] As an example, the substrate 100 includes an inter-metal dielectric (IMD) layer, which serves as an etchable layer for forming interconnect trenches after an etching process, i.e., the functional structure is an interconnect trench.

[0148] The inter-metal dielectric layer is used to achieve electrical isolation between metal interconnect structures in the back-end process.

[0149] As an example, the material of the inter-metal dielectric layer is an ultra-low-k dielectric material, thereby reducing the parasitic capacitance between the subsequent metal interconnect structures and thus reducing the subsequent RC delay. Specifically, the ultra-low-k dielectric material can be SiOCH.

[0150] In other embodiments, the substrate may also be an initial substrate for etching to form the substrate and the fins protruding from the substrate.

[0151] In this embodiment, the semiconductor structure further includes a bottom hard mask (HM) layer 110, located between the substrate 100 and the material layer to be doped 120, and between the substrate 100 and the barrier layer 130.

[0152] After the bottom hard mask layer 110 is subsequently etched, the pattern is transferred through the etched bottom hard mask layer 110 and then transferred downwards to the substrate 100. The bottom hard mask layer 110 helps to improve the accuracy of pattern transfer.

[0153] In this embodiment, the bottom hard mask layer 110 covers the entire substrate 100.

[0154] In this embodiment, the material of the bottom hard mask layer 110 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, titanium, titanium oxide, titanium nitride, tantalum, tantalum oxide, tantalum nitride, boron nitride, copper nitride, aluminum nitride, and tungsten nitride.

[0155] As an example, the bottom hard mask layer 110 is a metal hard mask (MHM) layer, and the material of the bottom hard mask layer 110 is titanium nitride.

[0156] The target patterned layer 130 is formed by ion implantation into the material layer 120 to be doped.

[0157] Depending on the process requirements, the target pattern layer 130 can be a film layer that needs to be retained or a film layer that needs to be removed later.

[0158] In this embodiment, the target graphic layer 130 is used as a barrier layer, and the graphic is subsequently transferred downward to the substrate 100 using the barrier layer.

[0159] In other embodiments, the target pattern layer is the functional structure used to form the device.

[0160] In other embodiments, the target patterned layer is a film layer to be removed, thereby forming a groove in the remaining material layer to be doped after the target patterned layer is removed.

[0161] In this embodiment, the undoped material layer 120 is the film layer to be removed later. Therefore, the material layer 120 is made of a material that is easy to remove, and the process of removing the material layer 120 causes less damage to the bottom hard mask layer 110 located below it.

[0162] The material to be doped layer 120 is different from the material of the bottom hard mask layer 110.

[0163] The material of the doped material layer 120 includes one or more of amorphous silicon (a-Si), silicon nitride, silicon oxide, and titanium oxide.

[0164] In this embodiment, the material layer 120 to be doped is amorphous silicon. Amorphous silicon has high process compatibility, and by selecting amorphous silicon, it is easy to change the etching resistance of certain areas in the material layer 120 to be doped through ion doping.

[0165] The dopant ions are located in the material layer 120 exposed by the mask opening 220. That is, during the formation of the semiconductor structure, ions are injected into the material layer 120 exposed by the mask opening 220. The top hard mask layer 200 is used as a mask when doping the material layer 120.

[0166] The material of the top hard mask layer 200 includes a dielectric material or a metal, wherein the dielectric material includes one or more of silicon oxide, silicon nitride, silicon, and silicon carbide, and the metal includes one or more of titanium oxide, titanium nitride, and tungsten carbide.

[0167] Specifically, the material of the top hard mask layer 200 is different from the material of the doped material layer 120.

[0168] As an example, the material of the top hard mask layer 200 is silicon dioxide.

[0169] In this embodiment, during the formation of the semiconductor structure, in order to dopant ions in the material layer 120 exposed to the mask opening 220, the angle between the sidewall of the mask opening 220 and the surface of the substrate 100 is greater than or equal to 90 degrees, thereby preventing the top opening size of the mask opening 220 from being smaller than the bottom opening size.

[0170] However, the angle between the sidewall of the mask opening 220 and the surface of the substrate 100 should not be too large. If the angle between the sidewall of the mask opening 220 and the surface of the substrate 100 is too large, the implanted ions are likely to come into contact with the sidewall of the mask opening 220 and be reflected or absorbed, thereby interfering with the implantation direction of the implanted ions. This can lead to the implantation area not being guaranteed (i.e., the problem of pattern offset is likely to occur), which in turn leads to a decrease in the linewidth uniformity of the target pattern layer 130.

[0171] Therefore, in this embodiment, the angle between the sidewall of the mask opening 220 and the surface of the substrate 100 is 90 to 95 degrees.

[0172] The doping ions are adapted to increase the etching selectivity between the material layer 120 to be doped and the target pattern layer 130.

[0173] In this embodiment, the etching selectivity ratio between the doped material layer 120 and the target patterned layer 130 refers to the ratio of the etching rates of the doped material layer 120 and the target patterned layer 130 when etching the doped material layer 120. In other words, when the doped material layer 120 is subsequently etched, the ion-doped material layer 120 (i.e., the target patterned layer 130) is etched at a lower rate, thereby allowing the target patterned layer 130 to be preserved.

[0174] In other embodiments, the etching selectivity ratio between the material layer to be doped and the target patterned layer refers to the ratio of the etching rates of the target patterned layer and the material layer to be doped when etching the target patterned layer. In other words, when the target patterned layer is subsequently etched, the etching rate of the material layer to be doped is lower, thereby allowing the material layer to be doped to be retained.

[0175] In this embodiment, since the sidewall verticality and flatness of the mask opening 220 are relatively high, it is beneficial to improve the uniformity and controllability of the doping effect when ions are injected into the material layer 120 exposed by the mask opening 220, thereby improving the linewidth uniformity of the target pattern layer 130 and correspondingly improving the accuracy of pattern transfer.

[0176] Specifically, the target graphic layer 130 is used as a barrier layer, and the graphic is subsequently transferred downward to the substrate 100 using the barrier layer. The line width uniformity of the target graphic layer 130 is relatively high, so the graphic accuracy of the functional structure is also relatively high.

[0177] The semiconductor structure can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0178] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate; forming a layer of material to be doped and a top hard mask layer on the substrate, the top hard mask layer being used as a mask for doping the layer of material to be doped; performing one or more times of patterning on the top hard mask layer, the patterning comprising: forming a pattern structure layer on the top hard mask layer; etching the top hard mask layer to form a mask opening in the top hard mask layer by taking the pattern structure layer as a mask; and removing the pattern structure layer after the mask opening is formed; after the last time of patterning, doping ions into the layer of material to be doped exposed at the bottom of the mask opening of the top hard mask layer, the layer of material to be doped doped with ions being a target pattern layer, the doped ions being suitable for increasing the etching selectivity between the layer of material to be doped and the target pattern layer, one of the target pattern layer and the layer of material to be doped not doped being a film layer to be reserved, and the other being a film layer to be removed.

2. The method of forming a semiconductor structure of claim 1, wherein, after the target pattern layer is formed, the method further comprises: removing the top hard mask layer and the remaining layer of material to be doped, or removing the top hard mask layer and the target pattern layer.

3. The method of forming a semiconductor structure of claim 1, wherein, after the top hard mask layer is formed and before the patterning on the top hard mask layer, the method further comprises: forming a buffer layer on the top hard mask layer; during the patterning, before the top hard mask layer is etched by taking the pattern structure layer as a mask, the method further comprises: etching the buffer layer.

4. The method of forming a semiconductor structure of claim 3, wherein, after the last time of patterning, before the layer of material to be doped exposed at the mask opening is doped with ions, the method further comprises: removing the buffer layer.

5. The method of forming a semiconductor structure of claim 4, wherein, The buffer layer is removed by using a wet etching process or a remote plasma etching process.

6. The method of forming a semiconductor structure of claim 1, wherein, The pattern structure layer comprises, from bottom to top, a planarization layer, an anti-reflection coating layer and a photoresist layer. The patterning further comprises: etching the anti-reflection coating layer and the planarization layer by taking the photoresist layer as a mask before the top hard mask layer is etched. Alternatively, the pattern structure layer is a photoresist layer. The material of the planarization layer comprises spin-on carbon.

7. The method of forming a semiconductor structure of claim 6, wherein, The material of the anti-reflection coating layer comprises one or more of Si-ARC, BARC and DARC.

8. The method of forming a semiconductor structure of claim 6, wherein, The material of the layer of material to be doped comprises one or more of amorphous silicon, silicon nitride, silicon oxide and titanium oxide.

9. The method of forming a semiconductor structure of claim 1, wherein, The material of the top hard mask layer comprises a dielectric material or a metal, the dielectric material comprising one or more of silicon oxide, silicon nitride, silicon and silicon oxycarbide, and the metal comprising one or more of titanium oxide, titanium nitride and tungsten carbide.

10. The method of forming a semiconductor structure of claim 1, wherein, The material of the buffer layer comprises a dielectric material or a metal, the dielectric material comprising one or more of silicon oxide, silicon nitride, silicon and silicon oxycarbide, and the metal comprising one or more of titanium oxide, titanium nitride and tungsten carbide.

11. The method of forming a semiconductor structure of claim 3, wherein, During the patterning, the etching selectivity between the top hard mask layer and the layer of material to be doped is greater than 5:

1.

12. The method of forming a semiconductor structure of claim 3, wherein, The thickness of the buffer layer is to 13. The method of forming a semiconductor structure of claim 1, wherein, ​ 14. The method of forming a semiconductor structure of claim 1, wherein, An angle between a sidewall of the mask opening and a surface of the substrate is 90 degrees to 95 degrees.

15. The method of forming a semiconductor structure of claim 1, wherein, An anisotropic etching process is used to etch the top hard mask layer.

16. The method of forming a semiconductor structure of claim 15, wherein, Parameters of the anisotropic etching process include: the etching gas includes one or more of C-F-based gas and C-F-H-based gas, the carrier gas includes one or more of Ar, O2, N2 and He, the source power is 500 W to 1500 W, the bias power is 200 W to 2000 W, and the process pressure is 4 mTorr to 200 mTorr.

17. A semiconductor structure, characterized by Comprise: a substrate; a material layer to be doped on the substrate; a top hard mask layer on the material layer to be doped, a mask opening is formed in the top hard mask layer, and the top hard mask layer is used as a mask when the material layer to be doped is doped; doping ions in the material layer to be doped exposed at the bottom of the mask opening of the top hard mask layer, wherein the material layer to be doped doped with ions is a target pattern layer, the doping ions are suitable for increasing the etching selectivity between the material layer to be doped and the target pattern layer, and one of the target pattern layer and the material layer to be doped which is not doped is a film layer to be retained, and the other is a film layer to be removed.

18. The semiconductor structure of claim 17, wherein, The material of the material layer to be doped includes one or more of amorphous silicon, silicon nitride, silicon oxide and titanium oxide.

19. The semiconductor structure of claim 17, wherein, The material of the top hard mask layer includes a dielectric material or a metal, the dielectric material includes one or more of silicon oxide, silicon nitride, silicon and silicon oxycarbide, and the metal includes one or more of titanium oxide, titanium nitride and tungsten carbide.

20. The semiconductor structure of claim 17, wherein, An angle between a sidewall of the mask opening and a surface of the substrate is 90 degrees to 95 degrees.

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