Power semiconductor module device and method of manufacturing the same

Abstract

The present disclosure relates to a power semiconductor module device and a manufacturing method thereof. A power semiconductor module device (100) includes a substrate (10) including a dielectric insulation layer (11) and a first metallization layer (111) attached to the dielectric insulation layer (11); at least one semiconductor body (20) mounted on the first metallization layer (111); and a first layer including a sealant (5), the first layer being arranged on the substrate (10) and covering the first metallization layer (111) and the at least one semiconductor body (20), wherein the first layer is configured to release a liquid or oil at a temperature exceeding a defined threshold temperature.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a power semiconductor module arrangement and to a method for manufacturing such a power semiconductor module arrangement. BACKGROUND

[0002] A power semiconductor module arrangement typically comprises a base plate which is located within an enclosure. At least one substrate is arranged on the base plate. A semiconductor device comprising a plurality of controllable semiconductor elements, for example two IGBTs in a half-bridge configuration, is arranged on each of the at least one substrate. Each substrate typically comprises a substrate layer, for example a ceramic layer, a first metallization layer deposited on a first side of the substrate layer, and a second metallization layer deposited on a second side of the substrate layer. The controllable semiconductor elements are mounted on the first metallization layer, for example. The second metallization layer is typically attached to the base plate by means of a solder layer or a sinter layer. The controllable semiconductor elements are typically mounted to the first metallization layer by means of the solder layer or the sinter layer.

[0003] The substrate layer, the metallization layers, the solder layer or the sinter layer, and the controllable semiconductor elements typically have different CTEs (coefficients of thermal expansion). When heat is generated during operation of the semiconductor device, and when the different components subsequently cool down again, the differences between the CTEs of the different materials, for example copper, aluminum, solder, can lead to undesired cracks in the substrate layer. Such cracks can extend through the entire substrate layer from the first surface on which the first metallization layer is mounted to the second surface on which the second metallization layer is mounted. This can have an adverse effect on the operation of the power semiconductor module and, in the worst case, even lead to a complete failure of the power semiconductor module arrangement.

[0004] There is a need for a power semiconductor module arrangement which reduces or even avoids the above-mentioned drawbacks and other drawbacks, and for a method which allows for manufacturing a power semiconductor module arrangement with improved performance and reliability. SUMMARY

[0005] A power semiconductor module arrangement comprises a substrate comprising a dielectric insulation layer and a first metallization layer attached to the dielectric insulation layer, at least one semiconductor body mounted on the first metallization layer, and a first layer comprising a sealant, the first layer being arranged on the substrate and covering the first metallization layer and the at least one semiconductor body, wherein the first layer is configured to release a liquid or an oil at a temperature exceeding a defined threshold temperature.

[0006] A method comprises arranging at least one semiconductor body on a substrate, the substrate comprising a dielectric insulation layer and a first metallization layer attached to the dielectric insulation layer; and forming a first layer on the substrate, the first layer covering the first metallization layer and the at least one semiconductor body, the first layer comprising a sealant, wherein the first layer is configured to release a liquid or oil at a temperature exceeding a defined threshold temperature.

[0007] The application can be better understood with reference to the following drawings and description. The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the application. Moreover, in the figures, like reference numerals designate corresponding parts throughout the different views. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a cross-sectional view of a power semiconductor module arrangement.

[0009] Figure 2 is a cross-sectional view of a defective power semiconductor module arrangement.

[0010] Figure 3 is a cross-sectional view of a power semiconductor module arrangement according to one example.

[0011] Figure 4 is a cross-sectional view of a substrate enclosed by a sealant according to one example.

[0012] Figure 5 is a cross-sectional view of Figure 4 a substrate according to another example.

[0013] Figure 6 is a cross-sectional view of a power semiconductor module arrangement according to another example. DETAILED DESCRIPTION

[0014] In the following detailed description, reference is made to the accompanying drawings. The drawings illustrate specific examples of the invention. It is understood that the features and principles described in relation to one example can be combined with those of another, unless otherwise specifically noted. In the description and claims, the identification of particular elements as “a first element,” “a second element,” “a third element,” etc. should not be understood as an exhaustive listing of elements. Rather, such designations are only used to refer to different “elements.” That is, for example, the presence of a “third element” does not necessarily require the presence of a “first element” and a “second element.” The electrical wires or connections described herein can be a single conductive element, or include at least two separate conductive elements connected in series and / or in parallel. The electrical wires and connections can include metallic and / or semiconducting materials, and can be permanently conductive (i.e., not switchable). The semiconductor body as described herein can be made of a (doped) semiconductor material, and can be or be included in a semiconductor chip. The semiconductor body has electrically connectable pads, and includes at least one semiconductor element having an electrode.

[0015] With reference to Figure 1 , a cross-sectional view of a power semiconductor module arrangement 100 is shown. The power semiconductor module arrangement 100 comprises a housing 7 and a substrate 10. The substrate 10 comprises a dielectric insulation layer 11, a (structured) first metallization layer 111 attached to the dielectric insulation layer 11, and a (structured) second metallization layer 112 attached to the dielectric insulation layer 11. The dielectric insulation layer 11 is arranged between the first metallization layer 111 and the second metallization layer 112.

[0016] Each of the first metallization layer 111 and the second metallization layer 112 can consist of or include one of the following materials: copper; a copper alloy; aluminum; an aluminum alloy; any other metal or alloy that remains solid during operation of the power semiconductor module device. The substrate 10 can be a ceramic substrate, i.e. a substrate in which the dielectric insulating layer 11 is ceramic, for example a thin ceramic layer. The ceramic can consist of or include one of the following materials: aluminum oxide; aluminum nitride; zirconium oxide; silicon nitride; boron nitride; or any other dielectric ceramic. Alternatively, the dielectric insulating layer 11 can consist of an organic compound and include one or more of the following materials: AI2O3, AIN, SiC, BeO, BN, or Si3N4. For example, the substrate 10 can be a direct copper bonding (DCB) substrate, a direct aluminum bonding (DAB) substrate, or an active metal brazing (AMB) substrate. Further, the substrate 10 can be an insulated metal substrate (IMS). The insulated metal substrate typically includes a dielectric insulating layer 11 that for example includes a (filled) material, such as an epoxy or a polyimide. For example, the material of the dielectric insulating layer 11 can be filled with ceramic particles. Such particles can include, for example, Si2O, AI2O3, AIN, SiN, or BN, and can have a diameter of about 1 pm to about 50 pm. The substrate 10 can also be a conventional printed circuit board (PCB) with a non-ceramic dielectric insulating layer 11. For example, the non-ceramic dielectric insulating layer 11 can consist of or include a cured resin.

[0017] The substrate 10 is arranged in the housing 7. In Figure 1 In the example shown, the substrate 10 is arranged on a base plate 80 forming a bottom face of the housing 7, while the housing 7 itself only includes side walls and a lid. In some power semiconductor module devices 100, more than one substrate 10 is arranged on the same base plate 80 and within the same housing 7. The base plate 80 can include a layer of a metallic material, such as copper or AlSiC. However, other materials are also possible.

[0018] The one or more semiconductor bodies 20 can be arranged on the at least one substrate 10. Each semiconductor body 20 arranged on the at least one substrate 10 can include a diode, an IGBT (insulated gate bipolar transistor), a MOSFET (metal oxide semiconductor field effect transistor), a JFET (junction field effect transistor), a HEMT (high electron mobility transistor), or any other suitable semiconductor element.

[0019] The one or more semiconductor bodies 20 can form a semiconductor device on the substrate 10. In Figure 1 In the example shown, only two semiconductor bodies 20 are exemplarily shown. Figure 1The second metallization layer 112 of the substrate 10 in Fig. 1 is a continuous layer. According to another example, the second metallization layer 112 can be a structured layer. According to further examples, the second metallization layer 112 can be omitted entirely. In Figure 1 The first metallization layer 111 is a structured layer in the example shown. “Structured layer” in this context means that the respective metallization layer is not a continuous layer, but comprises recesses between different portions of the layer. Figure 1 Such recesses are schematically shown in Fig. 1. In this example, the first metallization layer 111 comprises three different portions. Different semiconductor bodies 20 can be mounted to the same or different portions of the first metallization layer 111. The different portions of the first metallization layer 111 can have no electrical connection, or can be electrically connected to one or more other portions, e.g. using electrical connections 3 such as bond wires. The semiconductor bodies 20 can be electrically connected to each other or to the first metallization layer 111, e.g. using electrical connections 3. Instead of bond wires, the electrical connections 3 can also comprise, for example, bond ribbons, connection plates or conductive tracks, to name just a few examples. One or more semiconductor bodies 20 can be electrically and mechanically connected to the substrate 10 by a conductive connection layer 60. For example, such a conductive connection layer 60 can be a solder layer, a conductive adhesive layer or a sintered metal powder, e.g. sintered silver (Ag) powder, layer.

[0020] Figure 1 The power semiconductor module arrangement 100 shown in Fig. 1 further comprises a terminal element 4. The terminal element 4 provides an electrical connection between the interior of the housing 7 and the outside. The terminal element 4 can be electrically connected to the first metallization layer 111 with a second end 42, while a first end 41 of the terminal element 4 protrudes outside of the housing 7. The terminal element 4 can be electrically contacted from the outside at the first end 41 of the terminal element 4.

[0021] Arranging the terminal element 4 in the center of the substrate 10 is just one example. According to other examples, the terminal element 4 can be arranged closer to or adjacent to a sidewall of the housing 7. The second end 42 of the terminal element 4 can be electrically and mechanically connected to the substrate 10 by a conductive connection layer (not specifically shown in Fig. 1). For example, such a conductive connection layer can be a solder layer, a conductive adhesive layer or a sintered metal powder, e.g. sintered silver (Ag) powder, layer. Alternatively, the terminal element 4 can also be coupled to the substrate by ultrasonic welding. Figure 1

[0022] ​The power semiconductor module device 100 may also include a sealant 5. For example, the sealant 5 may be composed of or include silicone gel, or it may be a rigid molding compound. The sealant 5 may at least partially fill the interior of the housing 7, thereby covering components and electrical connections disposed on the substrate 10. Terminal elements 4 may be partially embedded in the sealant 5. However, at least their first ends 41 are not covered by the sealant 5 and protrude from the sealant 5 through the housing 7 to the exterior of the housing 7. The sealant 5 is configured to protect the components and electrical connections of the power semiconductor module device 100, especially those disposed inside the housing 7, from certain environmental conditions and mechanical damage. Typically, the housing 7 may be omitted, and only the sealant 5 may be used to protect the substrate 10 and any components mounted thereon. In this case, the sealant 5 may be, for example, a rigid material.

[0023] During use of the power semiconductor module device 100, the conductive interconnect layer 60, the dielectric insulating layer 11, the first metallization layer 111, and the second metallization layer 112 can be heated to a certain degree. This is because at least some of the semiconductor bodies 20 of the power semiconductor module device 100 typically perform multiple switching operations during operation of the power semiconductor module device 100. For example, when many switching operations are performed within a short period of time, the semiconductor bodies 20 generate heat, which, in the worst case, may cause the temperature to rise above a certain maximum threshold. The heat generated during operation of the power semiconductor module device 100 is typically dissipated from the semiconductor bodies 20 to the substrate 10 and further dissipated through the base plate 80 to the heat sink 82. A thermally conductive layer 64 is typically disposed between the base plate 80 and the heat sink 82.

[0024] Increased temperature may cause cracks to form in the dielectric insulating layer 11. Figure 2 The diagram schematically illustrates such a crack 90 in the dielectric insulating layer 11. One possible reason for the formation of this crack is the fact that the materials of the first metallization layer 111, the dielectric insulating layer 111, the second metallization layer 112, the conductive interconnect layer 60, and the semiconductor body 20 typically have different coefficients of thermal expansion. That is, when heated, the different materials expand to different degrees. The same is true when the materials are subsequently cooled again.

[0025] Cracks in the dielectric insulating layer 11 may adversely affect the operation of the power semiconductor module device 100, or even cause a complete failure of the power semiconductor module device. Cracks 90 may degrade the insulating properties of the dielectric insulating layer 11. For example, a crack can extend through the dielectric insulating layer 11 from a first surface on which the first metallization layer 111 is disposed to a second surface on which the second metallization layer 112 is disposed. Cracks often occur in areas of the dielectric insulating layer 11 that are arranged close to the edges of different portions of the metallization layers 111, 112. For example, inFigure 2 In the example shown, crack 90 is formed in the region beneath a groove in the dielectric insulating layer 11 disposed between two different portions of the first metallization layer 111. This allows a conductive path to be formed in the dielectric insulating layer 11, which is normally dielectric. That is, leakage current may occur in the dielectric insulating layer 11, leading to an undesirable short circuit.

[0026] Now for reference Figure 3 An exemplary power semiconductor module device 100 is shown, according to one example. The general structure of the power semiconductor module device 100 corresponds to that already described above. Figure 1 The power semiconductor module device 100 is described. However, Figure 3 The sealant 5 for the power semiconductor module device is different from that of... Figure 1 The power semiconductor module device 100 shown has a sealant 5. A second material (e.g., an additive or filler) 52 may be distributed within the sealant 5. Figure 3 The sealant 5, or particularly the second material 52, of the power semiconductor module device 100 liquefies at a temperature above a specific threshold temperature. For example, the threshold temperature could be 120°C. However, it is also possible for the sealant 5 to liquefy at lower or higher temperatures. That is, when the semiconductor body 20 or any other component of the power semiconductor module device 100 is heated above the threshold temperature, the sealant 5 in the region directly adjacent to the relevant component will also be heated and may subsequently liquefy at least partially in the relevant region. The sealant 5 releases at least a certain amount of liquid in the relevant region. The temperature of the semiconductor body 20 or other components will typically not remain long enough for all of the sealant 5 to be heated. Even further, heat may only be generated in a limited area. That is, the sealant 5 will not be completely liquefied in the defined region directly surrounding the heated component, but only partially liquefied.

[0027] If a crack 90 forms in the dielectric insulating layer 11 due to high temperature, the released liquid can flow into the crack 90, thereby filling the crack 90 with the dielectric insulating material. In this way, any unwanted conductive paths can be sealed by the material of the sealant 5. This is in Figure 4 and Figure 5 The middle is shown schematically. Figure 4 and Figure 5 A portion of the dielectric insulating layer 11 with cracks 90 formed therein is shown in more detail. Figure 5 Showing more details Figure 4 Detail A. Liquefaction of sealant 5 in Figure 4 and Figure 5The crack 90 is sealed by the material released from the sealant 5. Thus, even if a crack 90 is indeed formed in the dielectric insulation layer 11, the lifetime of the power semiconductor module device 100 can be significantly increased.

[0028] As already described above, the sealant 5 can comprise a silicone resin. The sealant 5 can comprise at least one of the following properties. The sealant 5 may, for example, comprise a significant amount of liquid. According to one example, the sealant 5 comprises at least 55 wt.-% or at least 60 wt.-% of liquid. However, other values are possible as well. A significant amount of liquid can be obtained by adding a non-reactive silicone oil 52 to the silicone gel (sealant 5) before filling the silicone gel into the housing 7 and curing it. The non-reactive component, e.g. the silicone oil, can remain in the sealant 5 after curing the sealant 5. The non-reactive silicone oil 52 can be uniformly distributed within the material of the sealant 5. Any liquid component 52 of the sealant 5 can be released at temperatures above a defined threshold temperature, e.g. above 120°C. According to another example, silicone resin beads 52 can be added to the silicone gel 5, wherein the silicone resin beads 52 melt at temperatures equal to or above a desired temperature, e.g. 120°C. Phase change material beads 52 can also be added to the sealant 5, wherein the phase change material beads liquefy at temperatures equal to or above a desired temperature, e.g. 120°C.

[0029] The sealant 5 can have a dielectric strength of, for example, at least 16 kV / mm or at least 17 kV / mm. However, other values of the dielectric strength are possible as well. The dielectric strength of the sealant 5 can depend on the current occurring in the power semiconductor module device 100 during operation. The sealant 5 may, for example, also have a specific resistance of at least 2*10 15 Ωcm or at least 2.5*10 15 Ωcm. However, the specific resistance can vary depending on the specific application and the current and voltage occurring in the power semiconductor module device 100 during operation. The viscosity of the liquid or oil released from the sealant 5 can be below 1 mPas. The surface tension of the liquid or oil released from the sealant 5 at room temperature can be less than 25 mNm -1 .

[0030] The sealant 5 as described above with regard to Figures 3 to 5 may be used with Figure 1The conventional encapsulant 5 used in the power semiconductor module device 100 is formed in the same manner. That is, after assembling the components of the power semiconductor module device 100 and before completely closing and sealing the housing 7, the encapsulant 5 can be filled into the housing 7 to cover the substrate 10 and the different components mounted thereon. The second material 52 can be uniformly distributed within the encapsulant 5 before the encapsulant is filled into the housing 7. The encapsulant 5 can be subsequently hardened to some extent. Typically, the encapsulant 5 has a liquid or gel-like texture when it is filled into the housing 7. The encapsulant 5 can be hardened to some extent by at least partially curing the encapsulant 5. That is, chemical bonds or links are formed between the constituents of the encapsulant 5. To achieve this, the encapsulant 5 can be heated, for example.

[0031] As described above with respect to Figure 3 As has been described, the second material 52 (e.g., silicone oil, silicone resin beads, phase change material beads) can be uniformly distributed throughout the encapsulant 5. That is, a single layer can be formed that includes both the encapsulant 5 and the second material 52 to cover the substrate 10 and the components mounted thereon. However, this is merely one example.

[0032] As Figure 6 As exemplarily shown in FIG. 5B, a first layer 502 can also be formed adjacent to the substrate 10. The first layer 502 includes both the encapsulant 5 and the second material 52 and covers the substrate 10 and the components mounted thereon. However, the first layer 502 can be relatively thin. A second layer 504 can be formed on the first layer 502 such that the first layer 502 is arranged between the second layer 504 and the substrate 10. The second layer 504 can include only the encapsulant 5 and not the second material 52. The second material 52 is typically only needed in those portions of the encapsulant 5 that are arranged close to the substrate 10 in order to be able to fill any unwanted cracks 90. However, the second material 52 is not necessary in portions of the encapsulant 5 that are arranged away from the substrate 10.

Claims

1. A power semiconductor module arrangement (100), comprising: a substrate (10) comprising a dielectric insulation layer (11) and a first metallization layer (111) attached to the dielectric insulation layer (11); at least one semiconductor body (20) mounted on the first metallization layer (111); and a first layer comprising a sealant (5), the first layer being arranged on the substrate (10) and covering the first metallization layer (111) and the at least one semiconductor body (20), wherein the first layer is configured to release a liquid or oil at temperatures exceeding a defined threshold temperature, such that, if a crack occurs in the dielectric insulation layer (11), the crack is filled by the released liquid or oil; a viscosity of the liquid or oil released from the sealant (5) is below 1 mPas; and the sealant (5) comprises a silicone gel. The surface tension of the liquid or oil released from the sealant (5) at room temperature is less than 25 mNm -1 .

2. The power semiconductor module arrangement of claim 1, wherein, A second material (52) is homogenously distributed throughout the sealant (5) of the first layer.

3. The power semiconductor module arrangement of claim 1, wherein, The sealant (5) is configured to not liquefy at temperatures exceeding the defined threshold temperature, and wherein the second material (52) is configured to liquefy at temperatures exceeding the defined threshold temperature.

4. The power semiconductor module arrangement of claim 3, wherein, The second material (52) comprises at least one of a silicone oil, a silicone resin bead, and a phase change material bead.

5. The power semiconductor module arrangement of claim 3, wherein, The first layer is configured to release a liquid or oil at temperatures of 120 °C and above.

6. The power semiconductor module arrangement according to any one of claims 1 to 5, wherein, The sealant (5) of the first layer comprises at least one of the following properties:

7. The power semiconductor module arrangement according to any one of claims 1 to 5, wherein, The sealant (5) comprises at least 55 wt.-% or at least 60 wt.-% of a liquid; The sealant (5) has a dielectric strength of at least 16 kV / mm or at least 17 kV / mm; and The second layer (504) is configured to not release a liquid or oil at temperatures exceeding a defined threshold temperature, wherein the first layer (502) is arranged between the substrate (10) and the second layer (504). The encapsulant (5) has an electrical resistivity of at least 2*10 15 Ωcm or at least 2.5*10 15 Ωcm.

8. The power semiconductor module arrangement according to any one of claims 1 to 5, further comprising a second layer (504) comprising a sealant (5), wherein, 9. A method for forming a power semiconductor module arrangement (100), comprising: arranging at least one semiconductor body (20) on a substrate (10), the substrate (10) comprising a dielectric insulation layer (11) and a first metallization layer (111) attached to the dielectric insulation layer (11); and forming a first layer on the substrate (10), the first layer covering the first metallization layer (111) and the at least one semiconductor body (20), the first layer comprising a sealant (5), wherein the first layer is configured to release a liquid or oil at temperatures exceeding a defined threshold temperature, such that, if a crack occurs in the dielectric insulation layer (11), the crack is filled by the released liquid or oil; a viscosity of the liquid or oil released from the sealant (5) is below 1 mPas; and forming the first layer comprises homogenously distributing a second material (52) throughout the sealant (5). The surface tension of the liquid or oil released from the sealant (5) at room temperature is less than 25 mNm -1 .

10. The method of claim 9, wherein, ​

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