Semiconductor structure and method of manufacturing the same

Abstract

A semiconductor structure and a method of manufacturing the same are disclosed. The semiconductor structure includes a first wafer, a second wafer, a barrier layer, a via, and a conductive material. The first wafer has a conductive pad. The second wafer is disposed over the first wafer and includes a via hole aligned with the conductive pad. An inner wall of the via hole is in contact with the conductive pad. The barrier layer covers the inner wall of the via hole. The barrier layer includes a bottom. The bottom covers the conductive pad. The via extends from the bottom of the barrier layer into the conductive pad. An inner diameter of the via is smaller than an inner diameter of the via hole. The conductive material fills the via hole and the via and is connected to the conductive pad. In this way, the overall electrical property can be further improved.

Description

Technical Field

[0001] This invention relates to semiconductor structures and methods for manufacturing the same. Background Technology

[0002] In semiconductor structures, vias are formed to electrically connect components. To avoid unintended electrical connections and protect the via structure, a sufficiently thick barrier layer should be filled inside the via. However, in the manufacturing process, this results in a thick residual barrier layer material deposited at the bottom of the via, affecting the connection of the conductive material inside the via and thus impacting the overall electrical performance.

[0003] Therefore, how to improve the electrical problems caused by the accumulated thickness of the barrier layer at the bottom of the perforation is one of the problems that those skilled in the art want to solve. Summary of the Invention

[0004] One object of the present invention relates to a semiconductor structure that can further improve the overall electrical properties of the semiconductor structure.

[0005] According to one embodiment of the present invention, a semiconductor structure includes a first wafer, a second wafer, a barrier layer, interconnects, and a conductive material. The first wafer has a conductive pad. The second wafer is disposed overlapping the first wafer and includes a through-hole aligned with the conductive pad. The inner wall of the through-hole is in contact with the conductive pad. The barrier layer covers the inner wall of the through-hole and includes a bottom, the bottom of the barrier layer covering the conductive pad. The interconnect extends from the bottom of the barrier layer into the conductive pad. The inner diameter of the interconnect is smaller than the inner diameter of the through-hole. The conductive material fills the through-hole and the interconnect and connects to the conductive pad.

[0006] In one or more embodiments, the conductive material extends into the conductive pad.

[0007] In one or more embodiments, the aforementioned semiconductor structure further includes an insulating layer. The insulating layer is located between the inner wall of the via and the barrier layer, and is in contact with the conductive pad.

[0008] In one or more embodiments, the aforementioned semiconductor structure further includes an adhesive layer. The adhesive layer is located between the first wafer and the second wafer. Through-holes extend through the adhesive layer to connect to conductive pads.

[0009] In one or more embodiments, the first wafer includes a first substrate and a first dielectric layer located on the first substrate. A conductive pad is located on the first dielectric layer.

[0010] In some embodiments, an active element is included within the first substrate. The active element is connected to the conductive pad via a line located within the first dielectric layer.

[0011] In some embodiments, the second wafer includes a second substrate and a second dielectric layer located on the second substrate. The second wafer connects the first dielectric layer and the conductive pad of the first wafer via the second dielectric layer.

[0012] In some embodiments, the second wafer further includes a passivation layer. The passivation layer is located on the surface of the second substrate relative to the second dielectric layer.

[0013] One object of the present invention relates to a method for manufacturing a semiconductor structure.

[0014] According to one embodiment of the present invention, a semiconductor structure manufacturing method includes the following steps: Connecting a second wafer to a first wafer having conductive pads. Forming vias aligned with and connected to the conductive pads on the second wafer. Depositing a barrier layer covering the vias and the conductive pads. Forming a sacrificial material filling the vias and covering the second wafer. Forming temporary channels aligned with the conductive pads within the sacrificial material, the temporary channels exposing the barrier layer. Etching the bottom of the barrier layer according to the temporary channels to form interconnect channels exposing the conductive pads. Removing the sacrificial material. Filling the vias and interconnect channels with conductive material.

[0015] In one or more embodiments, the semiconductor structure manufacturing method further includes the following steps: Before depositing a barrier layer, an insulating layer is formed covering a second wafer, vias, and conductive pads. The bottom of the insulating layer is penetrated to expose the conductive pads, wherein after depositing the barrier layer, the barrier layer further covers the insulating layer.

[0016] In one or more embodiments, the semiconductor structure manufacturing method further includes the following steps: Forming a photomask and photoresist pattern on a sacrificial material; etching temporary channels aligned with conductive pads in the sacrificial material using the photomask and photoresist pattern, the temporary channels exposing the barrier layer.

[0017] In one or more embodiments, the semiconductor structure manufacturing method further includes the following process: planarizing the conductive material.

[0018] In one or more embodiments, the semiconductor structure manufacturing method further includes the following steps: thinning a second substrate of a second wafer, wherein a second dielectric layer is located on the second substrate.

[0019] In some embodiments, the semiconductor structure manufacturing method further includes the following steps: forming a passivation layer on a second substrate, wherein the passivation layer is formed on the other surface opposite the second dielectric layer.

[0020] In summary, the present invention provides a semiconductor structure and its manufacturing method, which improves the electrical problems caused by excessively thick barrier layers by setting interconnecting channels in the barrier layer using sacrificial material.

[0021] The above description is only used to illustrate the problem to be solved by the present invention, the technical means to solve the problem, and the effects produced, etc. The specific details of the present invention will be described in detail in the following embodiments and related drawings. Attached Figure Description

[0022] The advantages of this invention and the accompanying drawings should be better understood from the embodiments listed below, and with reference to the drawings. These drawings are merely illustrative of embodiments and should not be construed as limiting the specific embodiments or the scope of the claims.

[0023] Figure 1 A cross-sectional schematic diagram of a semiconductor structure illustrated according to an embodiment of the present invention; and

[0024] Figures 2 to 13 According to an embodiment of the present invention, multiple cross-sectional schematic diagrams are illustrated in different processes of a manufacturing method for a semiconductor structure.

[0025] Explanation of key figure labels:

[0026] 100 - Semiconductor structure, 110 - First wafer, 112 - First substrate, 114 - First dielectric layer, 116 - Conductive pad, 130 - Second wafer, 132 - Second substrate, 134 - Second dielectric layer, 136 - Passivation layer, 138 - Through hole, 140 - Adhesive layer, 145 - Insulating layer, 150 - Barrier layer, 151 - Bottom, 155 - Connecting channel, 160 - Conductive material, 210 - Sacrificial material, 215 - Photomask, 220 - Photoresist, 230 - Temporary channel, D - Depth, W1 - Inner diameter, W2 - Inner diameter. Detailed Implementation

[0027] The following is a detailed description of embodiments in conjunction with the accompanying drawings. However, the provided embodiments are not intended to limit the scope of the invention, and the description of the structural operation is not intended to limit the order of execution. Any structure resulting from the recombination of elements and producing a device with equivalent functionality is within the scope of this invention. Furthermore, the drawings are for illustrative purposes only and are not drawn to their original dimensions. For ease of understanding, the same or similar elements will be designated with the same symbols in the following description.

[0028] Furthermore, unless otherwise specified, the terms used throughout this specification and claims generally have their ordinary meaning in the context of this art, the disclosure herein, and the specific content. Certain terms used to describe the invention will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing the invention.

[0029] In this document, terms such as "first," "second," etc., are used only to distinguish elements or methods of operation that have the same technical terminology, and are not intended to indicate order or limit the invention.

[0030] In addition, terms such as “include,” “including,” and “provide” are all open-ended restrictions in this article, meaning that they include but are not limited to.

[0031] Furthermore, in this document, unless otherwise specified in the text, “a” and “the” may refer to one or more. It will be further understood that the terms “comprising,” “including,” “having,” and similar words as used herein specify the features, regions, integers, steps, operations, elements, and / or components described herein, but do not exclude one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof described or additionally described herein.

[0032] To address the problem that the overall electrical performance of conductive vias in existing semiconductor structures is affected by excessively thick barrier layers, this invention provides a novel semiconductor structure and its corresponding manufacturing method to improve the aforementioned problem.

[0033] Please refer to Figure 1 . Figure 1 A cross-sectional schematic diagram of a semiconductor structure 100 according to an embodiment of the present invention.

[0034] like Figure 1 As shown, in this embodiment, the semiconductor structure 100 includes a first wafer 110 and a second wafer 130, which are connected together by an adhesive layer 140.

[0035] In some embodiments, the first wafer 110 and the second wafer 130 may each include active elements already formed thereon, such as capacitors and transistors, which can constitute a memory. Stacking the first wafer 110 and the second wafer 130 saves space, and the first wafer 110 and the second wafer 130 can form through-vias for electrical connection to the outside.

[0036] Specifically, in this embodiment, the first wafer 110 is stacked from bottom to top, including a first substrate 112, a first dielectric layer 114, and a conductive pad 116, with the conductive pad 116 disposed on the first dielectric layer 114. The first substrate 112 may contain multiple active components, including memory cells formed by transistors and capacitors, which are not shown in the figures for simplicity. The first dielectric layer 114 may contain multiple external connection lines, allowing the active components inside the first substrate 112 to be connected to the conductive pad 116 via these lines. Thus, the active components inside the first substrate 112 can be connected to the conductive pad 116 via electrical connection.

[0037] In some embodiments, the conductive pad 116 is made of aluminum.

[0038] In this embodiment, the second wafer 130 includes a second substrate 132, a second dielectric layer 134, and a passivation layer 136. The second dielectric layer 134 and the passivation layer 136 are located on opposite sides of the second substrate 132. Similar to the first wafer 110, the second substrate 132 in the second wafer 130 may also contain multiple capacitors and transistors to form memory cells arranged together. The second dielectric layer 134 may also contain multiple lines connecting the memory cells inside the second substrate 132. In some embodiments, the thickness of the second substrate 132 may be thinned as needed.

[0039] like Figure 1 As shown, the second wafer 130 is connected to the first wafer 110 with the second dielectric layer 134 facing the first dielectric layer 114. This makes the second wafer 130 substantially cover the first dielectric layer 114 and the conductive pad 116 of the first wafer 110 with the second dielectric layer 134. Subsequently, a passivation layer 136 is formed on the side of the second substrate 132 opposite to the second dielectric layer 134 to enhance the overall structural strength. In other words, the second dielectric layer 134 is closer to the first wafer 110 than the passivation layer 136.

[0040] In this embodiment, to electrically connect the conductive pad 116 of the first wafer 110, a via 138 is formed in the second wafer 130, and then the via 138 is filled with the conductive material 160 that has been connected. The via 138 extends through the adhesive layer 140 to connect with the conductive pad 116. In the horizontal direction, the via 138 has an inner diameter W1, which is smaller than the inner diameter of the conductive pad 116 of the first wafer 110 to avoid damaging other lines within the first dielectric layer 114. In other words, the inner wall of the via 138 is substantially connected to the top of the conductive pad 116.

[0041] In summary, in some embodiments, the inner diameter W1 of the via 138 can be set to be between 5 μm and 10 μm, depending on the requirements. In some embodiments, the depth of the via 138 (i.e., approximately equal to the overall thickness of the second wafer 130) ranges from 20 μm to 50 μm.

[0042] To prevent unintended connections between the conductive material 160 and the active components in the second substrate 132 of the second wafer 130, additional material is provided between the conductive material 160 and the via 138. In the semiconductor structure 100 of this embodiment, an insulating layer 145 and a barrier layer 150 are provided between the conductive material 160 and the via 138.

[0043] exist Figure 1 In this configuration, an insulating layer 145 extends from the passivation layer 136 of the second wafer 130 toward the conductive pad 116. This causes the insulating layer 145 to substantially completely cover the inner wall of the through-hole 138.

[0044] In some embodiments, the material of the insulating layer 145 is, for example, a non-conductive oxide or nitride, but is not limited thereto.

[0045] The barrier layer 150 is further provided with an insulating layer 145 covering the perforation 138, and the bottom 151 of the barrier layer 150 further covers the conductive pad 116. Generally, the barrier layer 150 can be formed in the perforation 138 by deposition. The function of the barrier layer 150 is to prevent the conductive material 160 from having unintended contact with the inner wall of the perforation 138, which would affect the electrical properties, and also to increase the strength of the overall structure.

[0046] In some embodiments, the barrier layer 150 is made of tantalum (Ta) or tantalum nitride (TaN) and can be deposited on the insulating layer 145 and conductive pad 116 within the perforation 138 by physical vapor deposition (PVD).

[0047] To ensure the barrier layer 150 has a certain thickness and can function properly as a barrier, the barrier layer 150 deposited on the conductive pad 116 typically has a considerable thickness. In this embodiment, the semiconductor structure 100 further forms an interconnecting channel 155 extending from the barrier layer 150 into the conductive pad 116. The interconnecting channel 155 extends into the conductive pad 116 and has a depth D. This allows the conductive material 160 filling the through-hole 138 to be directly connected to the conductive pad 116 through the interconnecting channel 155, avoiding overall electrical problems caused by the thickness of the barrier layer 150. Figure 1 As shown, the inner diameter W2 of the connecting channel 155 is smaller than the inner diameter W1 of the perforation 138. This corresponds to the barrier layer 150 in... Figure 1 In cross-section, it presents two L-shapes.

[0048] exist Figure 1 In this configuration, the tops of the conductive material 160, the barrier layer 150, and the insulating layer 145 are flush. In some embodiments, after the conductive material 160, the barrier layer 150, and the insulating layer 145 are formed, they can be flushed using a planarization process. The flat, exposed conductive material 160 facilitates electrical connection with other structures.

[0049] In some embodiments, the conductive material 160 includes copper.

[0050] To further illustrate the formation of the semiconductor structure 100 of the present invention, please refer to... Figures 2 to 13 . Figures 2 to 13 Multiple cross-sectional schematic diagrams are illustrated in different processes of a method for manufacturing a semiconductor structure 100 according to an embodiment of the present invention.

[0051] exist Figure 2 The system provides a first wafer 110 and a second wafer 130. The first wafer 110 and the second wafer 130 can be semiconductor wafers. In this embodiment, the first wafer 110 is stacked from bottom to top, including a first substrate 112, a first dielectric layer 114, and a conductive pad 116, with the conductive pad 116 disposed on the first dielectric layer 114. The second wafer 130 includes a second substrate 132, a second dielectric layer 134, and a passivation layer 136, with the second dielectric layer 134 and the passivation layer 136 located on opposite sides of the second substrate 132.

[0052] The first substrate 112 and the second substrate 132 are, for example, silicon substrates, but are not limited thereto. As mentioned above, active elements including memory cells and corresponding circuits may be provided on the first substrate 112 and the second substrate 132, and interconnect lines connecting the active elements may be provided on the first dielectric layer 114 and the second dielectric layer 134.

[0053] In some implementations, the thickness of the second substrate 132 may be thinned before connecting the first wafer 110 and the second wafer 130, as required.

[0054] exist Figure 2 In this process, the first dielectric layer 114 of the first wafer 110 and the second dielectric layer 134 of the second wafer 130 are connected face-to-face via the adhesive layer 140. Thus, as... Figure 2 As shown, the components stacked vertically from top to bottom are: a first substrate 112, a first dielectric layer 114, a conductive pad 116, an adhesive layer 140, a second dielectric layer 134, a second substrate 132, and a passivation layer 136 of a first wafer 110.

[0055] Continued Figure 2 ,exist Figure 3 In the second wafer 130, through-holes 138 are formed, aligned with and connected to the conductive pads 116. The through-holes 138 can be formed using a TSV patterning process, including photolithography and etching. Thus, the inner wall corresponding to the through-holes 138 is also connected to the conductive pads 116.

[0056] continue Figure 3 The process, in Figure 4 An insulating layer 145 is formed by liner deposition, covering the through-hole 138 and conductive pad 116 of the second wafer 130. For example... Figure 4 As shown, the insulating layer 145 is provided with a uniform thickness to cover the inner wall of the perforation 138 and the conductive pad 116.

[0057] Continued Figure 4 ,exist Figure 5 In this process, the bottom of the insulating layer 145 can be penetrated through a bottom liner punch etch, exposing the exposed conductive pad 116. In this way, only a small amount of the insulating layer 145 will cover the conductive pad 116.

[0058] exist Figure 6 In this embodiment, a barrier layer 150 is deposited covering the inner wall of the perforation 138 and the conductive pad 116 using a physical vapor deposition process. The barrier layer 150 further covers the insulating layer 145. In this embodiment, the barrier layer 150 is made of tantalum (Ta) or tantalum nitride (TaN) to further enhance the structural strength of the perforation 138. The material of the barrier layer 150 is conductive, minimizing its impact on the electrical properties of the overall structure. The bottom 151 of the barrier layer 150 directly covers and contacts the conductive pad 116.

[0059] continue Figure 6 The process, in Figure 7 A sacrificial material 210 is formed by deposition process, filling the vias 138 and substantially covering the second wafer 130. The sacrificial material 210 includes some polymers, which can play a role in protecting the barrier layer 150 to a certain extent in subsequent processes.

[0060] Enter Figure 8 A hard mask 215 is deposited on the sacrificial material 210 using a deposition process, and a photoresist 220 for patterning is deposited on the hard mask 215 as a photoresist pattern. The material of the hard mask 215 includes a metal oxide or a silicon oxynitride (SiON) film.

[0061] exist Figure 8In the photoresist pattern formed by photoresist 220, there are gaps at the alignment conductive pad 116. This allows for the formation of channels for alignment with the conductive pad 116 in subsequent processes.

[0062] Continued Figure 8 ,exist Figure 9 In the process, a temporary channel 230 aligned with the conductive pad 116 is etched on the sacrificial material 210 using the photoresist pattern of the photomask 215 and the photoresist 220, and the temporary channel 230 exposes the bottom 151 of the barrier layer 150. Subsequently, the bottom 151 of the barrier layer 150 can be penetrated by the remaining photomask 215.

[0063] like Figure 9 As shown, the perforation 138 has an inner diameter W1, and the temporary channel 230 is formed following the photoresist pattern of the quasi-conductive pad 116 and has an inner diameter W2, and the inner diameter W2 is smaller than the inner diameter W1.

[0064] continue Figure 9 ,exist Figure 10 In this process, the bottom 151 of the barrier layer 150 is etched based on the temporary channel 230 and the remaining photomask 215, forming a connecting channel 155 extending from the bottom 151 into the interior of the conductive pad 116. The photomask 215 is completely removed. In the presence of sacrificial material 210, the formation of the connecting channel 155 will not damage the through-hole 138, the insulating layer 145, or any portion of the barrier layer 150 other than the bottom 151.

[0065] exist Figure 10 In this process, it is ensured that the connecting channel 155 has a depth D extending to the conductive pad, so that the conductive material 160 can directly contact the conductive pad 116 when it is subsequently filled with conductive material 160.

[0066] Enter Figure 11 After the connecting channel 155 is formed, the sacrificial material 210 is removed by means including wet cleaning.

[0067] Continued Figure 11 ,exist Figure 12 The through-hole 138 and the connecting channel 155 are further filled with a conductive material 160. The conductive material 160 is, for example, copper. The conductive material 160 also covers the insulating layer 145 and the barrier layer 150 on the passivation layer 136.

[0068] In this way, the conductive material 160 can directly contact the conductive pad 116, and the thickness of the barrier layer 150 has a relatively reduced impact on the overall electrical properties.

[0069] In some embodiments, the conductive material 160 can be filled by first forming a metal seed layer within the via 138, and then conveniently filling the conductive material 160 into the metal seed layer. For example, in some embodiments, if the conductive material 160 is copper, a small amount of copper metal seed layer can be deposited in the via 138 and the connecting channel 155 using physical vapor deposition. Subsequently, copper can be easily electroplated onto the copper metal seed layer until the via 138 and the connecting channel 155 are filled.

[0070] In this process of filling the conductive material 160, after the copper plating is completed, further heating can be performed to allow the copper seed layer to form an alloy with the plated copper. In some embodiments, after the copper plating is completed, the entire structure can be placed at a temperature of 150°C to 300°C for an alloying time. In some embodiments, the alloying time can be thirty minutes. In some embodiments, the alloying time can be one to two hours. This reheating and alloying process ensures that the copper seed layer of the conductive material 160 forms an alloy with the plated copper, resulting in a more stable structure.

[0071] Furthermore, in Figure 13 In the process, after the conductive material 160 fills the vias 138 and the interconnects 155, the conductive material 160 is planarized so that it is approximately flush with the second wafer 130. Figure 13 In this configuration, the tops of the conductive material 160, the barrier layer 150, and the insulating layer 145 are substantially flush. The flat, exposed conductive material 160 facilitates integration and electrical connection with other structures. In some embodiments, planarization can be performed using chemical-mechanical planarization (CMP). This allows for the achievement of... Figure 1 The semiconductor structure 100 shown is shown.

[0072] In summary, this invention provides a semiconductor structure and a method for manufacturing the same. By additionally providing a sacrificial material during the semiconductor device manufacturing process, interconnect channels can be formed without damaging conductive vias and barrier layers. These interconnect channels allow for direct contact between electrically connected conductive materials and wafer conductive pads. This improves electrical performance issues caused by excessively thick barrier layers.

[0073] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A semiconductor structure, characterized in that, include: The first wafer has a conductive pad; A second wafer is provided, overlapping the first wafer and including a through-hole aligned with the conductive pad, wherein the inner wall of the through-hole is in contact with the conductive pad; An insulating layer covering the inner wall of the perforation; A barrier layer covering the insulating layer, wherein the barrier layer has a cross-section of two opposing L-shaped structures, the barrier layer includes a bottom, the bottom directly covering the conductive pad; A connecting channel extends from the bottom of the barrier layer into the conductive pad, wherein the inner diameter of the connecting channel is smaller than the inner diameter of the perforation, and the top of the connecting channel is located between the two L-shaped structures. as well as A conductive material is filled in the perforation and the connecting channel and connected to the conductive pad, wherein the conductive material is in direct contact with the conductive pad and the bottom surface of the conductive material is lower than the bottom surface of the barrier layer.

2. The semiconductor structure as described in claim 1, characterized in that, The conductive material extends into the conductive pad.

3. The semiconductor structure as described in claim 1, characterized in that, The insulating layer is in contact with the conductive pad.

4. The semiconductor structure as described in claim 1, characterized in that, Further includes: An adhesive layer is located between the first wafer and the second wafer, and the vias extend through the adhesive layer to connect with the conductive pad.

5. The semiconductor structure as described in claim 1, characterized in that, The first wafer includes a first substrate and a first dielectric layer located on the first substrate, and the conductive pad is located on the first dielectric layer.

6. The semiconductor structure as described in claim 5, characterized in that, The first substrate includes an active element, which is connected to the conductive pad via a line located within the first dielectric layer.

7. The semiconductor structure as described in claim 5, characterized in that, The second wafer includes a second substrate and a second dielectric layer located on the second substrate, and the second wafer connects the first dielectric layer of the first wafer and the conductive pad through the second dielectric layer.

8. The semiconductor structure as described in claim 7, characterized in that, The second wafer further includes a passivation layer located on the surface of the second substrate relative to the second dielectric layer.

9. A method for manufacturing a semiconductor structure, characterized in that, include: Connect the second wafer to the first wafer which has a conductive pad; Through-holes are formed on the second wafer and aligned with and connected to the conductive pad; An insulating layer is formed covering the second wafer, the via, and the conductive pad; Penetrate through the bottom of the insulating layer to expose the conductive pad; After the conductive pad is exposed at the bottom through the insulating layer, a barrier layer is deposited covering the insulating layer and the conductive pad within the perforation; A sacrificial material is formed to fill the perforations and cover the second wafer; A temporary channel is formed within the sacrificial material to align the conductive pad, the temporary channel exposing the barrier layer; The bottom of the barrier layer is etched according to the temporary channel to form a connecting channel that exposes the conductive pad, wherein the cross-section of the barrier layer is two opposing L-shaped structures, and the top of the connecting channel is located between the two L-shaped structures. Remove the sacrificial material; as well as A conductive material is filled into the perforation and the connecting channel, wherein the conductive material is in direct contact with the conductive pad, and the bottom surface of the conductive material is lower than the bottom surface of the barrier layer.

10. The semiconductor structure manufacturing method as described in claim 9, characterized in that, Further includes: A photomask and a photoresist pattern are disposed on the sacrificial material; as well as The temporary channel aligned with the conductive pad is etched on the sacrificial material using the photomask and the photoresist pattern, and the temporary channel exposes the barrier layer.

11. The semiconductor structure manufacturing method as described in claim 9, characterized in that, Further includes: Planarize the conductive material.

12. The semiconductor structure manufacturing method as described in claim 9, characterized in that, Further includes: A second substrate is thinned on the second wafer, wherein a second dielectric layer is located on the second substrate.

13. The semiconductor structure manufacturing method as described in claim 12, characterized in that, Further includes: A passivation layer is formed on the second substrate, wherein the passivation layer is formed on the other surface opposite to the second dielectric layer.

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