A semiconductor structure and a method of fabricating the same

Abstract

The embodiment of the present disclosure provides a semiconductor structure and a preparation method thereof. The semiconductor structure comprises: a word line structure located on a substrate and extending along a first direction, the word line structure comprising word line material layers and functional layers arranged from bottom to top along a second direction and a dielectric layer located between the word line material layers and the functional layers; the word line material layer is provided with a recess extending along the first direction adjacent to one side of the functional layer, the recess is recessed from top to bottom along the second direction and the sidewall of the recess is surrounded by the word line material layer; the dielectric layer covers the surface of the recess and the top surface of the word line material layer, the functional layer covers the surface of the dielectric layer and fills the recess, the functional layer comprises a main body part and a protruding part connected from top to bottom along the second direction, the protruding part is located in the recess, the main body part is located on the protruding part and the dielectric layer covering the top of the word line material layer, and along a third direction, the size of the protruding part is smaller than that of the main body part; the word line material layer and the functional layer both comprise conductive material.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for preparing the same. Background Technology

[0002] With technological advancements, semiconductor devices are continuously evolving towards miniaturization and higher integration. Memory, as a crucial semiconductor device, is used to store data or programs for data processing in electronic devices. However, while the size and linewidth of memory continue to decrease, many challenges remain in its manufacturing process that urgently need improvement. Summary of the Invention

[0003] This disclosure provides a semiconductor structure, the semiconductor structure comprising:

[0004] Substrate;

[0005] A word line structure is located on the substrate and extends along a first direction. The word line structure includes a word line material layer and a functional layer arranged from bottom to top along a second direction, and a dielectric layer located between the word line material layer and the functional layer. A recessed portion extending along the first direction is provided on one side of the word line material layer adjacent to the functional layer. The recessed portion is recessed from top to bottom along the second direction, and the sidewalls of the recessed portion are surrounded by the word line material layer. The dielectric layer covers the surface of the recessed portion and the top surface of the word line material layer. The functional layer covers the surface of the dielectric layer and fills the recessed portion. The functional layer includes a main body portion and a protrusion portion connected from top to bottom along the second direction. The protrusion portion is located in the recessed portion. The main body portion is located on the protrusion portion and the dielectric layer covering the top of the word line material layer. Along a third direction, the size of the protrusion portion is smaller than the size of the main body portion.

[0006] The word line material layer and the functional layer both contain conductive materials. The first direction and the third direction are parallel to the surface of the substrate and intersect each other. The second direction is parallel to the thickness direction of the substrate.

[0007] In some embodiments, the word line material layer includes a first sub-word line material layer and a second sub-word line material layer from bottom to top along a second direction, wherein the work functions of the first sub-word line material layer and the second sub-word line material layer are different.

[0008] In some embodiments, the material of the second sub-line material layer is the same as the material of the functional layer, and the material of the first sub-line material layer includes titanium nitride.

[0009] In some embodiments, in the second direction, the height ratio of the first sub-line material layer, the second sub-line material layer, and the main body portion ranges from (6-8):(4-5):(1-3); and / or

[0010] In the second direction, the height ratio of the main body and the protrusion ranges from (1-3):(1-2); and / or

[0011] The thickness of the dielectric layer is 2.5-3.5 nm; and / or

[0012] The ratio of the width of the protrusion in the third direction to the height of the protrusion in the second direction is between 1:(0.5-1); and / or

[0013] In the third direction, the ratio of the maximum width of the character line structure to the width of the protrusion is in the range of (1.8-2.2):1.

[0014] In some embodiments, the substrate includes at least one active region, the word line structure passes through at least the active region, the active region includes a channel region and a doped region, the channel region surrounds the outer sidewall of the word line structure, along the third direction, the doped region is located on both sides of the word line structure, and the doping type of the doped region is either P-type or N-type.

[0015] In some embodiments, the ratio of the work function of the functional layer to the work function of the channel region is 1:(0.95-1.05).

[0016] In some embodiments, when the doping type of the doped region is N-type, the work function of the functional layer is in the range of 3.7 eV to 4.35 eV; when the doping type of the doped region is P-type, the work function of the functional layer is in the range of 4.75 eV to 5.45 eV.

[0017] In some embodiments, the doped region includes a first doped region and a second doped region arranged from bottom to top along the second direction, wherein...

[0018] The doping concentration of the first doped region is lower than that of the second doped region; and / or,

[0019] The ratio of the distance between the lower surface of the main body and the lower surface of the first doped region to the height of the main body is in the range of (0-0.2):1, and the ratio of the distance between the upper surface of the main body and the upper surface of the first doped region to the height of the main body is in the range of (0-0.2):1.

[0020] In some embodiments, when the doping type of the doped region is N-type, the material of the word line material layer includes at least titanium nitride, wherein...

[0021] The material of the functional layer includes N-type doped polycrystalline silicon; and / or,

[0022] The material of the functional layer includes doped titanium nitride and / or doped tungsten, wherein the doping element in the doped titanium nitride includes at least one of lanthanum, niobium, and gallium, and the doping element in the doped tungsten includes at least one of lanthanum, niobium, and gallium; and / or,

[0023] The material of the functional layer includes at least one of lanthanum, niobium, and gallium; and / or,

[0024] The material of the functional layer includes a first sublayer and a second sublayer. The first sublayer is located on the dielectric layer along the third direction, covering the surface of the dielectric layer and including a portion extending along the second direction. The second sublayer covers the surface of the first sublayer and fills the space defined by the first sublayer. The material of the first sublayer includes at least one of lanthanum, niobium, gallium, lanthanum oxide, niobium oxide, and gallium oxide. The material of the second sublayer includes titanium nitride.

[0025] In some embodiments, the dielectric constant of the material of the dielectric layer is not greater than 4.

[0026] In some embodiments, the semiconductor structure further includes:

[0027] The character line trench is located on the substrate and extends along the first direction;

[0028] A gate oxide layer covers the sidewalls and bottom of the word line trench, wherein the word line structure is located within the space defined by the gate oxide layer;

[0029] A capping layer that covers the surface of the functional layer.

[0030] This disclosure also provides a method for fabricating a semiconductor structure, the method comprising:

[0031] Provide substrate;

[0032] A word line structure is formed on the substrate, the word line structure extending along a first direction and including a word line material layer and a functional layer arranged from bottom to top along a second direction, and a dielectric layer located between the word line material layer and the functional layer; a recessed portion extending along the first direction is provided on one side of the word line material layer adjacent to the functional layer, the recessed portion is recessed from top to bottom along the second direction and the sidewall of the recessed portion is surrounded by the word line material layer; the dielectric layer covers the surface of the recessed portion and the top surface of the word line material layer, the functional layer covers the surface of the dielectric layer and fills the recessed portion, the functional layer includes a main body portion and a protrusion portion connected from top to bottom along the second direction, the protrusion portion is located in the recessed portion, the main body portion is located on the protrusion portion and the dielectric layer covering the top of the word line material layer, and along a third direction, the size of the protrusion portion is smaller than the size of the main body portion;

[0033] The word line material layer and the functional layer both contain conductive materials. The first direction and the third direction are parallel to the surface of the substrate and intersect each other. The second direction is parallel to the thickness direction of the substrate.

[0034] In some embodiments, forming the word line structure includes:

[0035] The substrate is etched to form a first word trench extending along the first direction on the substrate;

[0036] A first sub-line material layer is formed, which fills the lower region of the first sub-line groove. The portion of the first sub-line groove that is not filled by the first sub-line material layer is defined as the second sub-line groove.

[0037] An initial second sub-line material layer is formed, which fills the lower region of the second sub-line groove;

[0038] A portion of the initial second letter line material layer is removed to form a recess extending in a first direction. The recess is recessed from top to bottom in a second direction, and the sidewalls of the recess are surrounded by the initial second letter line material layer. The bottom of the recess does not expose the surface of the first letter line material layer, and the remaining initial second letter line material layer constitutes the second letter line material layer.

[0039] The dielectric layer is formed, which covers the surface of the recess and the top surface of the second sub-line material layer;

[0040] A functional layer is formed, which covers the surface of the dielectric layer and fills the recess.

[0041] In some embodiments, before forming the first sub-character line material layer, the preparation method further includes:

[0042] A gate oxide layer is formed, which covers the sidewalls and bottom of the first word trench;

[0043] After forming the functional layer, the preparation method further includes:

[0044] A capping layer is formed, which covers the surface of the functional layer.

[0045] In some embodiments, the preparation method further includes:

[0046] Doped regions are formed along the third direction, and the doped regions are located on both sides of the word line structure. The doped regions include a first doped region and a second doped region from bottom to top along the second direction, wherein...

[0047] The doping concentration of the first doped region is lower than that of the second doped region; and / or,

[0048] The ratio of the distance between the lower surface of the main body and the lower surface of the first doped region to the height of the main body is in the range of (0-0.2):1, and the ratio of the distance between the upper surface of the main body and the upper surface of the first doped region to the height of the main body is in the range of (0-0.2):1.

[0049] The semiconductor structure and its fabrication method provided in this disclosure include: a substrate; a word line structure located on the substrate and extending along a first direction, the word line structure including a word line material layer and a functional layer arranged from bottom to top along a second direction, and a dielectric layer located between the word line material layer and the functional layer; a recessed portion extending along the first direction is provided on one side of the word line material layer adjacent to the functional layer, the recessed portion is recessed from top to bottom along the second direction and the sidewalls of the recessed portion are surrounded by the word line material layer; the dielectric layer covers the surface of the recessed portion and the word line material. The top surface of the material layer, the functional layer covers the surface of the dielectric layer and fills the recess, the functional layer includes a main body and a protrusion connected from top to bottom along the second direction, the protrusion is located in the recess, the main body is located on the protrusion and the dielectric layer covering the top of the word line material layer, and along the third direction, the size of the protrusion is smaller than the size of the main body; wherein, both the word line material layer and the functional layer contain conductive material, the first direction and the third direction are parallel to the surface of the substrate and intersect, and the second direction is parallel to the thickness direction of the substrate. In this embodiment, since the functional layer is made of a conductive material, the recessed portion on the side of the word line material layer adjacent to the functional layer, surrounded by the word line material layer, helps to increase the contact area between the dielectric layer and the functional layer and the word line material layer. When the transistor structure based on the word line structure is working, the increased contact area helps to increase the capacitive coupling effect between the word line material layer and the functional layer, which helps to reduce the lateral electric field strength in the channel region contained in the transistor structure, thereby effectively improving the occurrence of hot carrier injection (HCI), i.e., improving the hot carrier effect. In addition, in this embodiment, the arrangement of the word line material layer surrounding the recessed portion helps to increase the contact area between the dielectric layer and the functional layer and the word line material layer, while allowing the word line material layer around the recessed portion and the channel region to still be arranged in the original layout in terms of position and distance. This helps to improve the transistor structure performance while making structural changes, without causing a decrease in transistor performance due to structural changes or being forced to adjust other settings to accommodate structural changes. Furthermore, in the embodiments of this disclosure, the word line material layer located around the recess can be selected using a work function material with an appropriate range of values, depending on the type of transistor structure. This is beneficial for reducing the electric field strength between the word line structure and the drain region of the transistor structure, thereby improving the gate-induced drain leakage (GIDL) leakage and resulting in a semiconductor structure with improved performance, good electrical performance, and high reliability.

[0050] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification and drawings. Attached Figure Description

[0051] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0053] Figure 2 for Figure 1 A partially enlarged view of the provided semiconductor structure;

[0054] Figure 3 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure;

[0055] Figure 4 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0056] Figure 5 This is one of the schematic diagrams of the semiconductor structure during the fabrication process provided in the embodiments of this disclosure;

[0057] Figure 6 This is the second schematic diagram of the semiconductor structure provided in the embodiments of this disclosure during the fabrication process;

[0058] Figure 7 This is the third schematic diagram of the semiconductor structure during the fabrication process provided in the embodiments of this disclosure;

[0059] Figure 8 This is the fourth schematic diagram of the semiconductor structure during the fabrication process provided in the embodiments of this disclosure;

[0060] Figure 9 Fifth schematic diagram of the semiconductor structure provided in the embodiments of this disclosure during the fabrication process;

[0061] Figure 10 This is the sixth schematic diagram of the semiconductor structure provided in the embodiments of this disclosure during the fabrication process. Detailed Implementation

[0062] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0063] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0064] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0065] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as a second element, component, area, layer, or part. And the discussion of a second element, component, area, layer, or part does not imply that the first element, component, area, layer, or part necessarily exists in this disclosure.

[0066] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0067] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0068] In semiconductor devices, such as DRAM, the transistor structure is a crucial component. For a transistor to function properly, a certain voltage must be applied to its gate and channel regions. However, in practice, due to miniaturization or ease of implementation with compatible processes, leakage current or device functional degradation often occurs at certain locations within the transistor structure due to high electric field strength, affecting the normal use of the semiconductor structure.

[0069] Based on this, the following technical solutions are proposed for embodiments of this disclosure:

[0070] This disclosure provides a semiconductor structure, which includes:

[0071] Substrate;

[0072] A word line structure is located on a substrate and extends along a first direction. The word line structure includes a word line material layer and a functional layer arranged from bottom to top along a second direction, and a dielectric layer located between the word line material layer and the functional layer. A recessed portion extending along the first direction is provided on one side of the word line material layer adjacent to the functional layer. The recessed portion is recessed from top to bottom along the second direction, and the sidewall of the recessed portion is surrounded by the word line material layer. The dielectric layer covers the surface of the recessed portion and the top surface of the word line material layer. The functional layer covers the surface of the dielectric layer and fills the recessed portion. The functional layer includes a main body portion and a protrusion portion connected from top to bottom along the second direction. The protrusion portion is located in the recessed portion, and the main body portion is located on the protrusion portion and the dielectric layer covering the top of the word line material layer. Along a third direction, the size of the protrusion portion is smaller than the size of the main body portion.

[0073] The word line material layer and the functional layer both contain conductive materials. The first direction and the third direction are parallel to the surface of the substrate and intersect each other, while the second direction is parallel to the thickness direction of the substrate.

[0074] In this embodiment, since the functional layer is made of a conductive material, the recessed portion on the side of the word line material layer adjacent to the functional layer, surrounded by the word line material layer, helps to increase the contact area between the dielectric layer and the functional layer and the word line material layer. When the transistor structure based on the word line structure is working, the increased contact area helps to increase the capacitive coupling effect between the word line material layer and the functional layer, which helps to reduce the lateral electric field strength in the channel region contained in the transistor structure, thereby effectively improving the occurrence of hot carrier injection (HCI), i.e., improving the hot carrier effect. In addition, in this embodiment, the arrangement of the word line material layer surrounding the recessed portion helps to increase the contact area between the dielectric layer and the functional layer and the word line material layer, while allowing the word line material layer around the recessed portion and the channel region to still be arranged in the original layout in terms of position and distance. This helps to improve the transistor structure performance while making structural changes, without causing a decrease in transistor performance due to structural changes or being forced to adjust other settings to accommodate structural changes. Furthermore, in the embodiments of this disclosure, the word line material layer located around the recess can be selected using a work function material with an appropriate range of values, depending on the type of transistor structure. This is beneficial for reducing the electric field strength between the word line structure and the drain region of the transistor structure, thereby improving the gate-induced drain leakage (GIDL) leakage and resulting in a semiconductor structure with improved performance, good electrical performance, and high reliability.

[0075] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0076] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 2 for Figure 1 A partially enlarged view of the provided semiconductor structure; Figure 3 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure.

[0077] The semiconductor structure provided in the embodiments of this disclosure will now be described in further detail with reference to the accompanying drawings.

[0078] like Figures 1 to 3 As shown, the semiconductor structure includes:

[0079] Substrate 10;

[0080] A word line structure WL is located on a substrate 10 and extends along a first direction. The word line structure WL includes a word line material layer WLa and a functional layer GL arranged from bottom to top along a second direction, and a dielectric layer L1 located between the word line material layer WLa and the functional layer GL. A recessed portion A extending along the first direction is provided on the side of the word line material layer WLa adjacent to the functional layer GL. The recessed portion A is recessed from top to bottom along the second direction, and the sidewall of the recessed portion A is surrounded by the word line material layer WLa. The dielectric layer L1 covers the surface of the recessed portion A and the top surface of the word line material layer WLa. The functional layer GL covers the surface of the dielectric layer L1 and fills the recessed portion A. The functional layer GL includes a main body portion B1 and a protrusion portion B2 connected from top to bottom along the second direction. The protrusion portion B2 is located in the recessed portion A. The main body portion B1 is located on the protrusion portion B2 and the dielectric layer L1 covering the top of the word line material layer WLa. Along a third direction, the size of the protrusion portion B2 is smaller than the size of the main body portion B1.

[0081] The word line material layer WLa and the functional layer GL both contain conductive materials. The first direction and the third direction are parallel to the surface of the substrate 10 and intersect each other. The second direction is parallel to the thickness direction of the substrate 10.

[0082] Here, substrate 10 can be a semiconductor substrate; the material of the semiconductor substrate specifically includes elemental semiconductor materials (e.g., silicon (Si) substrates, germanium (Ge) substrates, etc.), or III-V compound semiconductor materials (e.g., gallium nitride (GaN) substrates, gallium arsenide (GaAs) substrates, indium phosphide (InP) substrates, etc.), or II-VI compound semiconductor materials, or organic semiconductor materials, or other semiconductor materials known in the art. In a specific embodiment, substrate 10 is a silicon substrate.

[0083] In this embodiment of the disclosure, the third direction can be perpendicular to the first direction, and the second direction from bottom to top can specifically refer to the direction from the word line material layer WLa to the functional layer GL.

[0084] In some embodiments, the substrate 10 includes at least one active region AA, and the word line structure WL passes through at least a portion of the active region AA. The active region AA includes a channel region C (which can be understood as the portion of the active region AA surrounding the word line structure WL excluding the two doped regions D) and two doped regions D located on both sides of the channel region C along a third direction. The channel region C surrounds the outer wall of the word line structure WL, and the doped regions D are located on both sides of the word line structure WL along a third direction. The doping type of the doped regions D is either P-type or N-type.

[0085] Understandably, a transistor structure can be derived based on the doped region D, the channel region C, and the portion of the word line structure WL covering the channel region. Of the two doped regions D, one can be used as the source of the transistor structure, and the other as the drain. Depending on whether the doping type of the doped region D is P-type or N-type, a PMOS transistor structure or an NMOS transistor structure can be obtained, respectively. Because the channel region C and the doped region D have different doping types in the same transistor structure, a junction region is formed at the junction of the channel region C and the doped region D.

[0086] In some embodiments, the semiconductor structure further includes:

[0087] The word line trench T is located on the substrate 10 and extends along a first direction;

[0088] Gate oxide layer L2 covers the sidewalls and bottom of word line trench T, and word line structure WL is located in the space defined by gate oxide layer L2;

[0089] The cap layer L3 covers the surface of the functional layer GL.

[0090] Here, both the gate oxide layer L2 and the capping layer L3 can participate in the formation of the transistor structure.

[0091] In some embodiments, the material of the gate oxide layer L2 includes, but is not limited to, a material with a low dielectric constant or a material with a high dielectric constant. When it is a material with a low dielectric constant, it can be an oxide, such as silicon oxide.

[0092] However, this is not the only limitation. In some embodiments, the gate oxide layer L2 can also be made of a high dielectric constant material, such as aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), or zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2), Hafnium silicon oxide (HfS) ix O y Hafnium silicon nitride oxide (HfSiON), hafnium zirconate (HfZrO4), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y ), Hafnium aluminum oxide (HfAl) x O y ) and / or praseodymium oxide (Pr2O3), etc.

[0093] In some embodiments, the material of the capping layer L3 includes, but is not limited to, nitrides, such as silicon nitride.

[0094] In some embodiments, the word line material layer WLa includes a first sub-word line material layer WL1 and a second sub-word line material layer WL2 arranged from bottom to top along a second direction, wherein the work functions of the first sub-word line material layer WL1 and the second sub-word line material layer WL2 are different.

[0095] In some embodiments, the material of the second sub-word line material layer WL2 is the same as the material of the functional layer GL, and the material of the first sub-word line material layer WL1 includes titanium nitride.

[0096] Here, the first sub-word line material layer WL1 containing titanium nitride can serve as the main word line material in the word line structure WL, which is mainly used to realize the turn-on and turn-off of the transistor structure.

[0097] Understandably, by setting different work functions for the first sub-word line material layer WL1 and the second sub-word line material layer WL2, these two material layers can select their work function values ​​based on their location, the type of transistor structure, and other factors. This provides favorable conditions for obtaining semiconductor structures with desired functions, such as improving gate-induced drain leakage (GIDL).

[0098] In practice, when the transistor structure is NMOS, a large electric field can easily occur at the gate-drain overlap region due to various possible reasons when the transistor is in the off state. This leads to severe band bending. If the band bending is not addressed and mitigated in time, current leakage can occur, a phenomenon known as gate-induced drain leakage (GIDL). Sometimes, even applying a negative gate voltage can turn off the transistor. This phenomenon increases the power consumption of the semiconductor structure, reduces the data retention capability of the memory cells, and affects the electrical performance stability and reliability of the semiconductor structure. Furthermore, as the size of semiconductor structures continues to shrink, the filling performance of multiple materials used as word lines simultaneously has been challenged. If only a single material type is used for filling, the performance of the final semiconductor structure is easily reduced. For example, in an NMOS structure, when only titanium nitride (TIN) is used as a word line, the row hammer effect is more likely to be aggravated than when only tungsten (W) is used as a word line. The row hammer effect can be understood as the fact that when a certain row of memory cells is repeatedly activated, it is easy to cause bit flips in the surrounding rows, resulting in inaccurate stored data.

[0099] It is understandable that when a product contains a PMOS structure, and the PMOS is part of the memory cell, it can also be understood that when the transistor structure in the memory cell is a PMOS, the gate-induced drain leakage (GIDL) phenomenon is likely to occur near the drain region.

[0100] The inventors of this application discovered that when the transistor structure is NMOS, if the work function of the word line structure WL near the junction region, i.e., the second word line layer WL2, is close to the conduction band energy level of the material contained in the channel region C in the active region AA, it can improve the band bending and reduce the leakage current value of gate-induced drain leakage (GIDL). This is because when the work function of the word line structure WL near the junction region is close to the conduction band energy level of the material contained in the channel region C in the active region AA, it can effectively reduce the surface electric field intensity at the junction of the drain and the gate, reduce the gate's control over the channel region C and the drain junction region, and help reduce the surface electric field intensity, thereby effectively improving the band bending. It is equivalent to "flattening" the bent band, making it less likely for tunneling effects caused by band bending to occur, thus effectively reducing the leakage current value of gate-induced drain leakage (GIDL).

[0101] In some embodiments, when the doping type of the doped region D is N-type, the work function of the second sub-word line material layer WL2 ranges from 3.7 eV to 4.35 eV (inclusive), such as 3.8 eV, 3.9 eV, 4 eV, 4.1 eV, 4.2 eV, 4.3 eV, etc.; when the doping type of the doped region is P-type, the work function of the second sub-word line material layer WL2 ranges from 4.75 eV to 5.45 eV (inclusive), such as 4.8 eV, 4.9 eV, 5 eV, 5.1 eV, 5.2 eV, 5.3 eV, 5.4 eV, etc.

[0102] Based on the above, it can be seen that since the conduction band energy level of the channel region C in the active region AA of the NMOS structure is around 4eV, selecting a material with a work function of the second sub-word line material layer WL2 within the above range helps to improve the effect of gate-induced drain leakage (GIDL).

[0103] In some embodiments, in NMOS, by setting the work function of the second sub-word line material layer WL2 accordingly, it is beneficial to improve data retention capability, increase fault tolerance, and improve electrical performance stability. This can reduce the probability of bit flipping in the memory cell. At the same time, the titanium nitride material contained in the first sub-word line material layer WL1, which has a high work function, helps to increase the threshold voltage of the transistor structure. Thus, the impact of noise on the data in adjacent rows during repeated activation of a certain row can be significantly reduced, bit flipping can be reduced, and the row hammer effect can also be reduced.

[0104] Furthermore, in products incorporating PMOS structures, where the PMOS is part of the memory cell, the inventors of this application have discovered that when the transistor structure is PMOS, a larger work function of the word line structure WL near the junction region, i.e., the second sub-word line material layer WL2, can improve the leakage current value of gate-induced drain leakage (GIDL) due to band bending. This is because a larger work function of the word line structure WL near the junction region, i.e., the second sub-word line material layer WL2, helps to increase the threshold voltage, weakening the gate's control over the channel region C. Consequently, the electric field in the drain junction region may weaken, effectively improving band bending and reducing the likelihood of tunneling. This is equivalent to "flattening" the bent band, making it less prone to tunneling due to band bending, thus effectively reducing the leakage current value of gate-induced drain leakage (GIDL).

[0105] Similarly, in the PMOS structure, due to the need to reduce the channel control capability, a material layer with a high work function is required. Therefore, when the work function of the second sub-word line material layer WL2 can be selected within the above range, it helps to reduce the gate-induced drain leakage (GIDL) leakage.

[0106] In some embodiments, when the doping type of the doped region D is N-type, the material of the first sub-word line material layer WL1 includes at least titanium nitride (work function approximately 4.8 eV), wherein,

[0107] The material of the second sub-line material layer WL2 includes N-type doped polycrystalline silicon (work function approximately 4.1 eV); and / or,

[0108] The material of the second sub-line material layer WL2 includes doped titanium nitride and / or doped tungsten, wherein the doping element in the doped titanium nitride includes at least one of lanthanum, niobium, and gallium, and the doping element in the doped tungsten includes at least one of lanthanum, niobium, and gallium; and / or,

[0109] The material of the second sub-character line material layer WL2 includes at least one of lanthanum, niobium, and gallium; and / or,

[0110] The material of the second sub-line material layer WL2 may also include multiple sub-layers (not shown in the figure), such as a sub-layer with a U-shaped cross-section along the third direction, and a sub-layer surrounded by the U-shaped sub-layer, wherein the former is made of at least one of lanthanum, niobium, gallium, lanthanum oxide, niobium oxide and gallium oxide, and the latter is made of titanium nitride.

[0111] In some embodiments, the size range of the word line structure WL in the third direction can be between 18nm and 22nm (including endpoint values), for example, 19nm, 20nm, 21nm, 22nm, etc.

[0112] In some embodiments, the sum of the dimensions of the word line structure WL in the second direction and the dimensions of the cap layer L3 in the second direction can be between 110nm and 130nm (including endpoint values), for example, 115nm, 120nm, 125nm, 130nm, etc.

[0113] In some embodiments, the size of the first sub-line material layer WL1 in the second direction ranges from 28nm to 43nm (including endpoint values), such as 29nm, 30nm, 32nm, 34nm, 36nm, 40nm, 41nm, etc.

[0114] In some embodiments, the maximum size of the second sub-line material layer WL2 in the second direction ranges from 18 nm to 27 nm (including endpoint values), for example, 20 nm, 22 nm, 24 nm, 25 nm, 26 nm, etc.

[0115] In the embodiments disclosed herein, such as Figure 2 As shown, the recess A in the second word line material layer WL2 is recessed in the direction from the top of the second word line material layer WL2 towards the middle region of the second word line material layer WL2. It can be seen that, along the third direction, the recess A is located in the middle region of the second word line material layer WL2, rather than on the edge region. This arrangement helps maintain the original distance and relative positional relationship between the second word line material layer WL2 and the channel region C. It can also be understood that although the recess A is added, the relatively stable relationship between the word line material layer WLa surrounding the recess A and the surrounding structure is not changed. This allows the semiconductor structure to achieve the beneficial effects of the recess A while maintaining high reliability. Furthermore, the above arrangement of the recess A does not cause a change in the height of the second word line material layer WL2 surrounding the recess A in the second direction, allowing the word line structure WL to maintain good control over the channel region C and preventing performance degradation.

[0116] In one embodiment, all sidewalls of the recess A are surrounded by a word line material layer, and in the third direction, the recess A is located in the middle region of the word line material layer.

[0117] Furthermore, in this embodiment of the disclosure, although a recessed portion A is provided, the first sub-line material layer WL1 located at the bottom is not exposed by the recessed portion A, which helps the material layer that serves as the main sub-line function to perform stably.

[0118] In some embodiments, only one recess A may be provided along the third direction, but this is not limited to this; multiple recesses may also be provided, such as 2, 3, 5, 6, 8, or even more. The specific configuration can be determined according to requirements and is not specifically limited here.

[0119] In some implementations, the recessed portion A is located not only in the middle region of the second sub-word line material layer WL2a in the third direction, but also in the middle region of the second sub-word line material layer WL2a in its extension direction, that is, in the first direction. In other words, in the embodiments of this disclosure, the recessed portion A can be surrounded by the second sub-word line material layer WL2a in any direction parallel to the substrate plane, that is, it can be located in the middle region of the second sub-word line material layer WL2a. This helps to ensure that the relative positional relationship between the second sub-word line material layer WL2a and other structures is not passively changed when the recessed portion A is introduced, which is beneficial to the stability and reliability of the semiconductor structure.

[0120] Understandably, hot carrier injection is most severe when the gate voltage (which can be understood as the voltage applied to the word line) is 1 / 2 VDD (supply voltage), easily leading to hot carrier injection into the gate oxide layer, resulting in device performance degradation, affecting functionality and lifespan. However, in the embodiments of this disclosure, the introduction of the recess A and the structure obtained by the functional layer GL following the shape change of the recess A significantly improve this situation, as will be explained later.

[0121] In practice, when the transistor structure is in operation, appropriate voltage values ​​can be applied to the first sub-word line material layer WL1 and the second sub-word line material layer WL2. Meanwhile, no voltage needs to be applied to the functional layer GL during this process.

[0122] In some embodiments, in the second direction, the ratio of the height of the first sub-word line material layer WL1, the maximum height of the second sub-word line material layer WL2, and the height d3 of the main body portion B1 ranges from (6-8):(4-5):(1-3) (including endpoint values); for example, 1:0.7:0.4, 7:4.5:2, 7:(4-5):(1-3), (6-8):4.5:(1-3), or (6-8):(4-5):2, etc. In this configuration, a semiconductor structure with a superior size ratio can be obtained.

[0123] In some embodiments, the thickness of the dielectric layer L1 is 2.5-3.5 nm (including endpoint values), for example, 2.8 nm, 3 nm, 3.2 nm, etc.

[0124] In some embodiments, the dielectric constant of the material of the dielectric layer L1 is not greater than 4, for example, it can be 1.7, 2.0, 2.4, 3.3, 3.9, etc.

[0125] In this way, while achieving the effect of increasing the coupling ratio between the functional layer GL and the second sub-word line material layer WL2 (the coupling ratio can be understood as the ratio of the capacitive coupling structure obtained by the two layers to the total capacitive coupling), the gate voltage (voltage of the word line structure WL) is not excessively diverted, and the gate's good control over the channel region C can be maintained.

[0126] In some embodiments, in the second direction, the height ratio of the main body portion B1 to the protrusion portion B2 ranges between (1-3): (1-2) (including endpoint values), for example, 0.5, 0.8, 1, 1.2, 1.5, 1.7, 1.8, 2.0, 2.2, 2.5, 2.8, 3, etc.

[0127] In this way, the multiple material layers contained in the word line structure WL can have a more suitable size ratio in the second direction. When the first sub-word line material layer WL1 and the second sub-word line material layer WL2 have a suitable height relationship, it helps the word line structure WL to exert a good control effect on the transistor structure. When the first sub-word line material layer WL1, the second sub-word line material layer WL2 and the main body B1 have a suitable size ratio in the second direction, it helps the transistor structure to improve the hot carrier injection effect during normal operation without significantly increasing the height of the word line structure WL, thus still achieving the effect of size miniaturization.

[0128] Furthermore, based on the aforementioned dimensional settings, constraining the thickness of the dielectric layer L1 helps increase the coupling capacitance between the second sub-word line material layer WL2 and the functional layer GL during transistor operation. This enhances the coupling effect, reduces the kinetic energy of carriers in the channel region C, minimizes hot carrier injection, prevents functional degradation, and improves the performance of the semiconductor structure. Moreover, it achieves a balance between breakdown voltage and coupling effect.

[0129] Furthermore, in this embodiment, the presence of the protrusion B2 allows the dielectric layer L1 located between the functional layer GL and the second sub-line material layer WL2 in the cross-sectional structure obtained in the third direction to include multiple regions in the direction perpendicular to the thickness. For example, there are two regions extending in the third direction on the top of the second sub-line material layer WL2, a region extending in the third direction but located at the bottom of the recess A, and multiple regions extending in the second direction and located on the sidewall of the recess A. The arrangement of these multiple regions helps to achieve coupling between the functional layer GL and the second sub-line material layer WL2 at multiple locations. It can also be understood as helping to reduce the transverse electric field in the channel region C at multiple locations. At the same time, the recess of the protrusion B2 from the functional layer GL to the second sub-line material layer WL2 helps to make the location of the coupling between the two materials closer to the area where the channel region C is located. In the case that the shape of the protrusion B2 itself helps to attract conductive ions, the proximity further helps to enhance the effect of reducing the transverse electric field and effectively improve the hot carrier injection (HCI) situation.

[0130] In some embodiments, the size of the main body portion B1 in the second direction ranges from 5 to 15 nm (including the endpoint value), such as 6 nm, 7 nm, 8 nm, 10 nm, 12 nm, 13 nm, etc. The size of the protrusion portion B2 in the second direction ranges from 5 to 10 nm (including the endpoint value), such as 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, etc.

[0131] In some embodiments, the width of the protrusion B2 in the third direction is around 10nm, such as 9nm, 11nm, etc.

[0132] In some embodiments, the ratio of the width d1 of the protrusion B2 in the third direction to the height d2 of the protrusion B2 in the second direction is in the range of 1:(0.5-1) (including endpoint values), such as 1, 1.2, 1.5, 1.8, 2, etc.

[0133] In some embodiments, in the third direction, the ratio of the maximum width of the word line structure WL to the width of the protrusion B2 is in the range of (1.8-2.2):1 (including endpoint values), such as 1.9, 2, 2.1, etc.

[0134] In this way, the protrusion B2 and the main body B1 can be made to have suitable dimensions, while also being compatible with the overall size setting of the word line structure WL, so that when it plays a role in improving the function, it will not bring burdens such as increased device height and volume.

[0135] In some embodiments, the ratio of the work function of the functional layer GL to the work function of the channel region C is 1:(0.95-1.05).

[0136] In some embodiments, the work function of the functional layer GL can be the same as the work function of the channel region C.

[0137] In some embodiments, such as in an NMOS structure, the work function of the functional layer GL can be close to or the same as the conduction band energy level of the channel region C, while in a PMOS structure, the work function of the functional layer GL can be close to or the same as the valence band energy level of the channel region C.

[0138] Here, by constraining the work function of the functional layer GL, ensuring that the difference between the work function of the functional layer GL and the channel region C is equal to or close to 0, it means that under thermal equilibrium (without external bias), there is no charge transfer between the functional layer GL and the channel region C, and the energy band is flat. When a voltage is applied to the word line material layer WLa, the potential of the functional layer GL is raised due to capacitive coupling. However, because it matches the work function of the channel region C, it does not induce additional, strong energy band bending on the surface of the channel region C, preventing leakage. Furthermore, if a work function mismatch exists, even if the voltage of the word line material layer WLa is 0, a depletion region or even an inversion layer will be induced on the channel surface, severely interfering with the transistor's switching characteristics, causing a drastic and uncontrollable threshold voltage shift. Therefore, the work function matching between the functional layer GL and the channel region C makes the threshold voltage primarily determined by the work function of the word line itself and the channel doping, making it more stable and predictable.

[0139] In some embodiments, when the doping type of the doped region D is N-type, the work function of the functional layer GL ranges from 3.7 eV to 4.35 eV (inclusive), such as 3.8 eV, 3.9 eV, 4 eV, 4.1 eV, 4.2 eV, 4.3 eV, etc.; when the doping type of the doped region D is P-type, the work function of the functional layer GL ranges from 4.75 eV to 5.45 eV (inclusive), such as 4.8 eV, 4.9 eV, 5 eV, 5.1 eV, 5.2 eV, 5.3 eV, 5.4 eV, etc.

[0140] In some embodiments, the doped region D includes a first doped region D1 and a second doped region D2 arranged from bottom to top along a second direction, wherein...

[0141] The doping concentration of the first doped region D1 is lower than that of the second doped region D2;

[0142] In some embodiments, the ratio between the distance between the lower surface of the main body B1 and the lower surface of the first doped region D1 and the height of the main body B1 is in the range of (0-0.2):1 (including the endpoint values), such as 0.05, 0.1, 0.15, etc., and the ratio between the distance between the upper surface of the main body B1 and the upper surface of the first doped region D1 and the height of the main body B1 is in the range of (0-0.2):1 (including the endpoint values), such as 0.05, 0.1, 0.15, etc.

[0143] In this embodiment, the hot carrier injection (HCI) phenomenon can be reduced by setting the functional layer GL, which is similar to the function of a lightly doped drain (LDD). Simultaneously, the setting of the first doped region D1 in this embodiment can also achieve the function of a lightly doped drain (LDD), further contributing to the improvement of the hot carrier injection (HCI) phenomenon. By setting a high constraint between the first doped region D1 and the main body B1, it is beneficial to achieve a 5%-10% increase in ion current when the device is turned on.

[0144] In some embodiments, when the doping type of the doped region is N-type, the word line material layer WLa comprises at least titanium nitride, wherein...

[0145] The material of the functional layer GL includes N-type doped polysilicon; and / or,

[0146] The material of the functional layer GL includes doped titanium nitride and / or doped tungsten, wherein the doping element in the doped titanium nitride includes at least one of lanthanum, niobium, and gallium, and the doping element in the doped tungsten includes at least one of lanthanum, niobium, and gallium; and / or,

[0147] The material of the functional layer GL includes at least one of lanthanum, niobium, and gallium.

[0148] In some embodiments, such as Figure 3 As shown, the material of the functional layer GL includes a first sublayer La and a second sublayer Lb. The first sublayer La is located on the dielectric layer L1. Along the third direction, the first sublayer La covers the surface of the dielectric layer L1 and includes a portion extending along the second direction (corresponding to...). Figure 3 (The area Q circled in the middle); the second sublayer Lb covers the surface of the first sublayer La and fills the space defined by the first sublayer La. The material of the first sublayer La includes at least one of lanthanum, niobium, gallium, lanthanum oxide, niobium oxide and gallium oxide. The material of the second sublayer Lb includes titanium nitride.

[0149] like Figure 3 As shown, the first sublayer La includes not only the portion covering the surface of the dielectric layer L1, but also a portion extending along the second direction (corresponding to...). Figure 3The arrangement of the area Q circled in the middle makes the outer wall of the first sub-layer La the same as the outer wall of the functional layer GL that is in contact with the surrounding structure. Since the first sub-layer La itself already contains materials that have the purpose of improving functionality, the second sub-layer Lb, which is surrounded by it, can have a wider range of material choices, which helps to reduce the difficulty of material selection and reduce implementation costs.

[0150] In some embodiments, along the second direction, the ratio between the distance between the top surface of the first sublayer La and the upper surface of the first doped region D1 and the height of the main body B1 is in the range of (0-0.2):1 (including the endpoint value), for example, 0.05, 0.1, 0.15, etc.

[0151] In some embodiments, along the second direction, the top surface of the first sublayer La along the second direction can be flush with the upper surface of the first doped region D1. Specifically, this can be configured according to requirements, and no specific limitation is made here.

[0152] In some embodiments, when the material of the functional layer is doped titanium nitride and / or doped tungsten, the atomic percentage of the doping element ranges from 10% to 50% (including endpoints), such as 15%, 20%, 25%, 30%, 35%, 40%, 45%, etc.

[0153] In summary, it can be seen that in the structure provided by the embodiments of this disclosure, the word line structure WL includes a first sub-word line material layer WLa comprising a first sub-word line material layer WL1 and a second sub-word line material layer WL2. The optimized configuration of these multiple material layers in terms of material composition and size helps to improve the gate-induced drain leakage (GIDL) phenomenon. Furthermore, the presence of a recess A in the second sub-word line material layer WL2 allows for corresponding changes in the shape of the dielectric layer L1 and the functional layer GL. Since these material layers are also optimized in other aspects, including but not limited to size, position, and material, this helps to improve the poor performance of hot carrier injection (HCI) without increasing the size and volume burden on the semiconductor structure. In addition, while providing improved effects, the word line structure WL does not require the introduction of a high-dielectric-constant material fabrication process, which helps to reduce process complexity.

[0154] This disclosure also provides a method for fabricating a semiconductor structure, such as... Figure 4 As shown, the method includes the following steps:

[0155] Step S101: Provide a substrate;

[0156] Step S102: Form a word line structure on a substrate. The word line structure extends along a first direction and includes a word line material layer and a functional layer arranged from bottom to top along a second direction, as well as a dielectric layer located between the word line material layer and the functional layer. A recess extending along the first direction is provided on one side of the word line material layer adjacent to the functional layer. The recess is recessed from top to bottom along the second direction, and the sidewall of the recess is surrounded by the word line material layer. The dielectric layer covers the surface of the recess and the top surface of the word line material layer. The functional layer covers the surface of the dielectric layer and fills the recess. The functional layer includes a main body and a protrusion connected from top to bottom along the second direction. The protrusion is located in the recess, and the main body is located on the protrusion and the dielectric layer covering the top of the word line material layer. Along a third direction, the size of the protrusion is smaller than the size of the main body.

[0157] The word line material layer and the functional layer both contain conductive materials. The first direction and the third direction are parallel to the surface of the substrate and intersect each other, while the second direction is parallel to the thickness direction of the substrate.

[0158] The preparation method provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings.

[0159] First, execute step S101, as follows: Figure 5 As shown, a substrate 10 is provided.

[0160] In some embodiments, after providing the substrate 10, the method further includes:

[0161] Multiple initially active regions AA1 are formed on substrate 10 using a self-aligned double patterning (SADP) process;

[0162] In some embodiments, insulating material is filled into the gaps between adjacent active regions AA to form an isolation structure STI.

[0163] Next, proceed with step S102, as follows: Figures 5 to 10As shown, a word line structure WL is formed on a substrate 10. The word line structure WL extends along a first direction and includes a word line material layer WLa and a functional layer GL arranged from bottom to top along a second direction, as well as a dielectric layer L1 located between the word line material layer WLa and the functional layer GL. A recessed portion A extending along the first direction is provided on the side of the word line material layer WLa adjacent to the functional layer GL. The recessed portion A is recessed from top to bottom along the second direction, and the sidewall of the recessed portion A is surrounded by the word line material layer WLa. The dielectric layer L1 covers the surface of the recessed portion A and the top surface of the word line material layer WLa. The functional layer GL covers the surface of the dielectric layer L1 and fills the recessed portion A. The functional layer GL includes a main body portion B1 and a protrusion portion B2 connected from top to bottom along the second direction. The protrusion portion B2 is located in the recessed portion A, and the main body portion B1 is located on the protrusion portion B2 and the dielectric layer L1 covering the top of the word line material layer WLa. Along the third direction, the size of the protrusion portion B2 is smaller than the size of the main body portion B1.

[0164] The word line material layer WLa and the functional layer GL both contain conductive materials. The first direction and the third direction are parallel to the surface of the substrate 10 and intersect each other. The second direction is parallel to the thickness direction of the substrate 10.

[0165] In some embodiments, forming a word line structure WL includes:

[0166] Etching substrate 10 to form a first word line trench T1 extending along a first direction on substrate 10 (see details). Figure 5 );

[0167] A first sub-line material layer WL1 is formed, which fills the lower region of the first sub-line groove T1. The portion of the first sub-line groove T1 not filled by the first sub-line material layer WL1 is defined as the second sub-line groove T2 (see details). Figure 6 );

[0168] An initial second sub-line material layer WL2a is formed, which fills the lower region of the second sub-line groove T2 (see details). Figure 7 );

[0169] A portion of the initial second letter line material layer WL2a is removed to form a recess A extending along a first direction. Recess A is recessed from top to bottom along a second direction, and its sidewalls are surrounded by the initial second letter line material layer WL2a. The bottom of the recess A does not expose the surface of the first letter line material layer WL1. The remaining initial second letter line material layer WL2a constitutes the second letter line material layer WL2 (see details). Figure 8 );

[0170] A dielectric layer L1 is formed, which covers the surface of the recess A and the top surface of the second sub-line material layer WL2 (see details). Figure 8 and Figure 9 );

[0171] A functional layer GL is formed, which covers the surface of the dielectric layer L1 and fills the recess A (see details). Figure 9 ).

[0172] In one embodiment, along a third direction, the recess A is located in the middle region of the initial second letter line material layer WL2a.

[0173] In some embodiments, such as Figure 8 and Figure 9 As shown, a dielectric layer L1 is formed, comprising:

[0174] A dielectric material layer L1a is formed, which covers the surface of the recess A and the top surface of the second sub-line material layer WL2, and covers the sidewall of the area of ​​the second sub-line groove T2 not covered by the second sub-line material layer WL2.

[0175] Remove the portion of the dielectric material layer L1a covering the sidewall of the second letter groove T2 to form the dielectric layer L1.

[0176] In some embodiments, only one recess A may be provided along the third direction, but this is not limited to this; multiple recesses may also be provided, such as 2, 3, 5, 6, 8, or even more. The specific configuration can be determined according to requirements and is not specifically limited here.

[0177] In some embodiments, when the recess A is positioned in the first direction, it can also be a structure extending along the first direction but discontinuous in that direction. In this case, the dielectric layer L1 can be a continuous structure in the first direction. When forming the recess A, a continuous recess A can be formed first in the first direction, but a dielectric material of a larger height, such as the same material as the dielectric layer L1, can be filled at positions where at least part of the active region AA is not provided, to obtain multiple recesses A that are discontinuous in the first direction. Alternatively, the recesses A can be obtained by filling the recesses A with the dielectric layer L1, and then removing a portion of the material layer at the position corresponding to the active region AA to obtain the dielectric layer L1.

[0178] Thus, the resulting functional layer GL can be a discontinuous structure in the first direction, which helps to reduce hot carrier injection at the position corresponding to the channel region C. However, at the positions between the channel regions C, there will be no situation where a large coupling capacitance causes a large number of word line voltages to be diverted, which is conducive to the normal functioning of the transistor structure.

[0179] In this embodiment of the disclosure, the presence of protrusion B2 causes the dielectric layer L1 located between the functional layer GL and the second sub-line material layer WL2 in the third-direction cross-sectional structure to include multiple regions in the portion perpendicular to the thickness direction. For example, a region extending along the third direction at the top of the second sub-line material layer WL2, a region extending along the third direction but located at the bottom of the recess A, and a region extending along the second direction and located on the sidewall of the recess A. The arrangement of these multiple regions helps to achieve coupling between the functional layer GL and the second sub-line material layer WL2 at multiple locations. It can also be understood as helping to reduce the transverse electric field in the channel region C at multiple locations. At the same time, the recess of protrusion B2 from the functional layer GL to the second sub-line material layer WL2 helps to make the location of the coupling between the two materials closer to the area where the channel region C is located. In the case that the shape of protrusion B2 itself helps to attract conductive ions, the proximity further helps to enhance the effect of reducing the transverse electric field and effectively improve the hot carrier injection (HCI) situation.

[0180] In some embodiments, the preparation method further includes, prior to forming the first sub-character line material layer WL1a:

[0181] like Figure 6 As shown, a gate oxide layer L2 is formed, which covers the sidewalls and bottom of the first word line trench T1;

[0182] After forming the functional layer GL, the fabrication method also includes:

[0183] like Figure 10 As shown, a capping layer L3 is formed, which covers the surface of the functional layer GL.

[0184] In some embodiments, Figure 10 After the steps are completed, as Figure 1 As shown, the preparation method also includes:

[0185] A doped region D is formed along the third direction, located on both sides of the word line structure WL. The doped region D includes a first doped region D1 and a second doped region D2 from bottom to top along the second direction.

[0186] The doping concentration of the first doped region D1 is lower than the doping concentration of the second doped region D2; and / or,

[0187] The ratio of the distance between the lower surface of the main body B1 and the lower surface of the first doped region D1 to the height of the main body B1 is in the range of (0-0.2):1 (including the endpoint values), for example, 0.05, 0.1, 0.15, etc.; and the ratio of the distance between the upper surface of the main body B1 and the upper surface of the first doped region D1 to the height of the main body B1 is in the range of (0-0.2):1 (including the endpoint values), for example, 0.05, 0.1, 0.15, etc.

[0188] It should be noted that during the preparation process, the number of word line structures (WL) formed can include multiple lines. The number shown in the attached figure is only for illustrative purposes and is not intended to be limiting.

[0189] In some embodiments, when the doping type of the doped region D is N-type, the work function of the second sub-word line material layer WL2 ranges from 3.7 eV to 4.35 eV (inclusive), such as 3.8 eV, 3.9 eV, 4 eV, 4.1 eV, 4.2 eV, 4.3 eV, etc.; when the doping type of the doped region is P-type, the work function of the second sub-word line material layer WL2 ranges from 4.75 eV to 5.45 eV (inclusive), such as 4.8 eV, 4.9 eV, 5 eV, 5.1 eV, 5.2 eV, 5.3 eV, 5.4 eV, etc.

[0190] The above settings help to improve gate-induced drain leakage (GIDL) in both NMOS and PMOS structures.

[0191] The technical features described in the embodiments provided in this disclosure can be arbitrarily combined without conflict.

[0192] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes: A substrate, the substrate including at least one active region, the active region including a channel region and a doped region; A word line structure extending at least through the active region, the word line structure being located on the substrate and extending along a first direction, the channel region surrounding the outer wall of the word line structure, along a third direction, the doped regions being located on both sides of the word line structure, the word line structure including a word line material layer and a functional layer arranged from bottom to top along a second direction, and a dielectric layer located between the word line material layer and the functional layer; a recess extending along the first direction is provided on the side of the word line material layer adjacent to the functional layer, the recess being recessed from top to bottom along the second direction and the sidewall of the recess being surrounded by the word line material layer; the dielectric layer covering the surface of the recess and the top surface of the word line material layer, the functional layer covering the surface of the dielectric layer and filling the recess, the functional layer including a main body portion and a protrusion connected from top to bottom along the second direction, the protrusion being located in the recess, the main body portion being located on the protrusion and the dielectric layer covering the top of the word line material layer, and along a third direction, the size of the protrusion being smaller than the size of the main body portion; The word line material layer and the functional layer both contain conductive materials. The first direction and the third direction are parallel to the surface of the substrate and intersect each other. The second direction is parallel to the thickness direction of the substrate.

2. The semiconductor structure according to claim 1, characterized in that, The word line material layer includes a first sub-word line material layer and a second sub-word line material layer from bottom to top along a second direction, and the work functions of the first sub-word line material layer and the second sub-word line material layer are different.

3. The semiconductor structure according to claim 2, characterized in that, The material of the second sub-line material layer is the same as the material of the functional layer, and the material of the first sub-line material layer includes titanium nitride.

4. The semiconductor structure according to claim 2, characterized in that, In the second direction, the height ratio of the first sub-line material layer, the second sub-line material layer, and the main body portion ranges from (6-8):(4-5):(1-3); and / or In the second direction, the height ratio of the main body and the protrusion ranges from (1-3):(1-2); and / or The thickness of the dielectric layer is 2.5-3.5 nm; and / or The ratio of the width of the protrusion in the third direction to the height of the protrusion in the second direction is between 1:(0.5-1); and / or In the third direction, the ratio of the maximum width of the character line structure to the width of the protrusion is in the range of (1.8-2.2):

1.

5. The semiconductor structure according to any one of claims 1-4, characterized in that, The doping type of the doped region is either P-type or N-type.

6. The semiconductor structure according to claim 5, characterized in that, The ratio of the work function of the functional layer to the work function of the channel region is 1:(0.95-1.05).

7. The semiconductor structure according to claim 5, characterized in that, When the doping type of the doped region is N-type, the work function of the functional layer is in the range of 3.7 eV to 4.35 eV; when the doping type of the doped region is P-type, the work function of the functional layer is in the range of 4.75 eV to 5.45 eV.

8. The semiconductor structure according to claim 5, characterized in that, The doped region includes a first doped region and a second doped region arranged from bottom to top along the second direction, wherein... The doping concentration of the first doped region is lower than that of the second doped region; and / or, The ratio of the distance between the lower surface of the main body and the lower surface of the first doped region to the height of the main body is in the range of (0-0.2):1, and the ratio of the distance between the upper surface of the main body and the upper surface of the first doped region to the height of the main body is in the range of (0-0.2):

1.

9. The semiconductor structure according to claim 5, characterized in that, When the doping type of the doped region is N-type, the material of the word line material layer includes at least titanium nitride, wherein, The material of the functional layer includes N-type doped polycrystalline silicon; and / or, The material of the functional layer includes doped titanium nitride and / or doped tungsten, wherein the doping element in the doped titanium nitride includes at least one of lanthanum, niobium, and gallium, and the doping element in the doped tungsten includes at least one of lanthanum, niobium, and gallium; and / or, The material of the functional layer includes at least one of lanthanum, niobium, and gallium; and / or, The material of the functional layer includes a first sublayer and a second sublayer. The first sublayer is located on the dielectric layer along the third direction, covering the surface of the dielectric layer and including a portion extending along the second direction. The second sublayer covers the surface of the first sublayer and fills the space defined by the first sublayer. The material of the first sublayer includes at least one of lanthanum, niobium, gallium, lanthanum oxide, niobium oxide, and gallium oxide. The material of the second sublayer includes titanium nitride.

10. The semiconductor structure according to any one of claims 1-4 and 6-9, characterized in that, The dielectric constant of the material of the dielectric layer is no greater than 4.

11. The semiconductor structure according to any one of claims 1-4 and 6-9, characterized in that, The semiconductor structure also includes: The character line trench is located on the substrate and extends along the first direction; A gate oxide layer covers the sidewalls and bottom of the word line trench, wherein the word line structure is located within the space defined by the gate oxide layer; A capping layer that covers the surface of the functional layer.

12. A method for fabricating a semiconductor structure, characterized in that, The method includes: Provide substrate; A word line structure is formed on the substrate, the portion of the substrate surrounding the outer wall of the word line structure forming a channel region. The word line structure extends along a first direction and includes a word line material layer and a functional layer arranged from bottom to top along a second direction, as well as a dielectric layer located between the word line material layer and the functional layer. A recessed portion extending along the first direction is provided on the side of the word line material layer adjacent to the functional layer. The recessed portion is recessed from top to bottom along the second direction, and the sidewall of the recessed portion is surrounded by the word line material layer. The dielectric layer covers the surface of the recessed portion and the top surface of the word line material layer. The functional layer covers the surface of the dielectric layer and fills the recessed portion. The functional layer includes a main body portion and a protrusion portion connected from top to bottom along the second direction. The protrusion portion is located in the recessed portion, and the main body portion is located on the protrusion portion and the dielectric layer covering the top of the word line material layer. Along a third direction, the size of the protrusion portion is smaller than the size of the main body portion. A doped region is formed, the channel region and the doped region constitute an active region, the word line structure passes through at least the active region along a third direction, and the doped region is located on both sides of the word line structure; The word line material layer and the functional layer both contain conductive materials. The first direction and the third direction are parallel to the surface of the substrate and intersect each other. The second direction is parallel to the thickness direction of the substrate.

13. The preparation method according to claim 12, characterized in that, Forming the word line structure includes: The substrate is etched to form a first word trench extending along the first direction on the substrate; A first sub-line material layer is formed, which fills the lower region of the first sub-line groove. The portion of the first sub-line groove that is not filled by the first sub-line material layer is defined as the second sub-line groove. An initial second sub-line material layer is formed, which fills the lower region of the second sub-line groove; A portion of the initial second letter line material layer is removed to form a recess extending in a first direction. The recess is recessed from top to bottom in a second direction, and the sidewalls of the recess are surrounded by the initial second letter line material layer. The bottom of the recess does not expose the surface of the first letter line material layer, and the remaining initial second letter line material layer constitutes the second letter line material layer. The dielectric layer is formed, which covers the surface of the recess and the top surface of the second sub-line material layer; A functional layer is formed, which covers the surface of the dielectric layer and fills the recess.

14. The preparation method according to claim 13, characterized in that, Before forming the first sub-character line material layer, the preparation method further includes: A gate oxide layer is formed, which covers the sidewalls and bottom of the first word trench; After forming the functional layer, the preparation method further includes: A capping layer is formed, which covers the surface of the functional layer.

15. The preparation method according to any one of claims 12-14, characterized in that, Forming the doped region includes: Doped regions are formed along the third direction, and the doped regions are located on both sides of the word line structure. The doped regions include a first doped region and a second doped region from bottom to top along the second direction, wherein... The doping concentration of the first doped region is lower than that of the second doped region; and / or, The ratio of the distance between the lower surface of the main body and the lower surface of the first doped region to the height of the main body is in the range of (0-0.2):1, and the ratio of the distance between the upper surface of the main body and the upper surface of the first doped region to the height of the main body is in the range of (0-0.2):1.

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