Memory device and electronic apparatus

Abstract

The application provides a memory and an electronic device. The memory device comprises: a storage array, the storage array comprising a first storage area and a second storage area, the first storage area being configured to store normal data, and the second storage area being configured to store metadata; an on-chip controller, the on-chip controller being configured to receive a first read-write command in a first mode, the first read-write command comprising a target data read-write command and a metadata read-write command appearing in sequence, the on-chip controller intercepting the metadata read-write command and outputting the target data read-write command in the first mode; wherein the storage array is configured to access the first storage area and the second storage area in parallel in response to the target data read-write command in the first mode.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a memory device and an electronic device. Background Technology

[0002] Semiconductor memories are classified into volatile memories such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM) and non-volatile memories such as Flash memory, Phase Change Material Random Access Memory (PRAM), Magnetic Random Access Memory (MRAM), Resistive Random-access Memory (RRAM), or Ferroelectric Random Access Memory (FRAM). Volatile memories lose the data stored in them when power is off, while non-volatile memories retain the data stored in them even when power is off.

[0003] DRAM memory is a common type of volatile memory. DRAM memory works by storing charge in capacitors within memory cells to write data to the memory, and by reading the charge from the capacitors within the memory cells to read data from the memory. With the development of semiconductor technology, DRAM integration is becoming increasingly sophisticated, and the possibility of data errors during data read or write operations is also increasing. Summary of the Invention

[0004] This application provides a storage device and an electronic device that at least improve the performance of the storage device.

[0005] This application provides a storage device, comprising: a storage array including a first storage area and a second storage area, the first storage area for storing normal data and the second storage area for storing metadata; and an on-chip controller configured to receive a first read / write command in a first mode, the first read / write command including a target data read / write command and a metadata read / write command appearing sequentially, wherein in the first mode, the on-chip controller intercepts and processes the metadata read / write command and outputs the target data read / write command; wherein the storage array is configured to, in the first mode, in response to the target data read / write command, access the first storage area and the second storage area in parallel.

[0006] In addition, the first storage area and the second storage area are located in the same storage unit.

[0007] In addition, the first storage area includes a plurality of first storage blocks, and the second storage area includes at least one second storage block.

[0008] In addition, parallel access to the first storage area and the second storage area includes: the target data read / write command corresponds to a burst transmission, wherein the first storage area and the second storage area are accessed within a burst transmission.

[0009] Additionally, the storage device further includes a data bus coupled between the on-chip controller and the storage array, wherein, in the first mode, in response to the target data read / write command, the data transmitted on the data bus during each read / write operation includes the normal data and the metadata.

[0010] Additionally, the on-chip control includes: a latch circuit configured to receive the first read / write command and perform delay processing on the first read / write command to generate and output a delay command; and a shielding circuit configured to receive a target decoding signal and the delay command, wherein, in the first mode, if the delay command is obtained based on the metadata read / write command, the target decoding signal has a first state; and in the first mode, if the delay command is obtained based on the target data read / write command, the target decoding signal has a second state; the shielding circuit is configured to shield the delay command in response to the target decoding signal having the first state, and to output the delay command as the target data read / write command in response to the target decoding signal having the second state.

[0011] Additionally, the latch circuit includes: a D flip-flop, the data input of which receives the first read / write command, and the output of which outputs the delay command; and / or, the shielding circuit includes: a latch, the data input of which receives the target decoding signal, the clock input of which receives the delay command, and outputs the target decoding signal when the delay command is enabled; and a NOR gate, one input of which is connected to the output of the latch, the other input of which receives the inverted signal of the delay command, and the output of which is used to output the target data read / write command.

[0012] In addition, the on-chip controller further includes: a first decoding circuit for outputting the first read / write command to the latch circuit; and a second decoding circuit for outputting the target decoding signal to the shielding circuit.

[0013] In addition, the on-chip controller is configured to receive a second read / write command in a second mode, the second read / write command being used to instruct the parallel storage or reading of normal data and metadata in the storage array, and the on-chip controller outputs the second read / write command in the second mode; wherein, the storage array is further configured to, in the second mode, in response to the second read / write command, access the first storage area and the second storage area in parallel.

[0014] Additionally, the second mode includes a first-width mode or a second-width mode. In the first-width mode, the metadata accessed in a single access to the second storage area has a first-width, and in the second-width mode, the metadata stored in a single access to the second storage area has a second-width. The first-width is smaller than the second-width.

[0015] Additionally, the storage device further includes: a column decoder, which is connected to the first storage area via multiple first column select lines and to the second storage area via multiple second column select lines; the parallel access to the first storage area and the second storage area in response to the target data read / write command includes: storing normal data based on a first column address and storing metadata based on a second column address, or reading the normal data based on the first column address and reading the metadata based on the second column address, wherein the first column address is used to select multiple first column select lines and the second column address is used to select multiple second column select lines.

[0016] Additionally, the storage device is configured to operate in a third mode, in which the storage array is configured to store normal data based on the first column address, the first column address being used to select multiple first column selection lines and at least a portion of the second column selection lines.

[0017] This application also provides an electronic device including the storage device provided in any of the above claims.

[0018] The technical solution provided in this application has at least the following advantages:

[0019] This application provides a storage device with superior structural performance, including a storage array and an on-chip controller. The storage array includes a first storage area and a second storage area. The first storage area stores normal data, and the second storage area stores metadata. The on-chip controller is configured to receive a first read / write command in a first mode. The first read / write command includes a target data read / write command and a metadata read / write command that occur sequentially. In the first mode, the on-chip controller intercepts and processes the metadata read / write command and outputs the target data read / write command. The storage array is configured to access the first and second storage areas in parallel in response to the target data read / write command in the first mode. Using the storage device provided by this application, there is no need to place a metadata register, and it can also achieve the purpose of parallel storage or reading of normal data and metadata, saving the area and cost overhead of metadata registers, and improving the utilization of the data bus to improve data transmission efficiency. Attached Figure Description

[0020] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrative descriptions do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this application or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is an architecture diagram of a storage device in related technologies;

[0022] Figure 2 A functional block diagram of a storage device provided in some embodiments of this application;

[0023] Figure 3 A schematic diagram of the structure of a storage device provided in some embodiments of this application;

[0024] Figure 4 This is an architecture diagram of a storage array;

[0025] Figure 5 An architecture diagram for a single repository;

[0026] Figure 6 The diagram illustrates a layout architecture for a single storage unit within a repository.

[0027] Figure 7 for Figure 6 An architecture diagram of a storage block;

[0028] Figure 8 This is a schematic diagram of a storage device in a first mode;

[0029] Figure 9 This is a functional block diagram of an on-chip controller;

[0030] Figure 10 A schematic diagram of a circuit structure for a latching circuit and a shielding circuit;

[0031] Figure 11 for Figure 10 A timing diagram of each signal in the diagram;

[0032] Figure 12 This is another functional block diagram of the on-chip controller;

[0033] Figure 13 A functional block diagram of a storage device provided in a second mode for some embodiments of this application;

[0034] Figure 14 Another functional block diagram for storage devices;

[0035] Figure 15 This is a schematic diagram showing the relationship between the first and second storage areas and the corresponding column selection lines in a single storage unit.

[0036] Figure 16 A schematic diagram of a single storage unit in the third mode;

[0037] Figure 17 A block diagram of an electronic device provided in an embodiment of this application.

[0038] Explanation of reference numerals in the attached figures:

[0039] 1. On-chip controller; 2. Memory array; 21. First part; 22. Second part; 11. Metadata register; 3. Host.

[0040] 101. Storage array; 102. On-chip controller; I. ​​First storage area; II. Second storage area; WR1 / RD1. First read / write command; WR / RD. Target data read / write command; 10. Host; 100. Storage chip; BK1~BKn. Storage bank; Sections 1-16k are storage units; MAT1 is the first storage block; MAT2 is the second storage block; CSL is the column select line; WL1-WLi are word lines; BL1-BLj are bit lines; MC is the storage cell; BUS is the data bus; 112 is the latch circuit; 122 is the shielding circuit; WR1 / RD1_D is the delay command; Meta_D is the target decoding signal; CK is the clock signal; 1121 is the D flip-flop; D1 is the first latch; D2 is the second latch; CKN is the inverted signal of the clock signal; 1221 is the latch; 1222 is the NOR gate; 132 is the first decoding circuit; 142 is the second decoding circuit; WR2 / RD2 is the second read / write command; 103 is the column decoder; CSL1 is the first column select line; CSL2 is the second column select line; 401 is the processor; 402 is the storage device.

[0041] Section, storage section; WLp-1~WLp, word lines. Detailed Implementation

[0042] To improve data integrity, reliability, and management efficiency, metadata is introduced into the storage device, which can be transferred from the host to the storage device along with normal data.

[0043] Metadata can be used to describe information such as the background, content, structure, or permissions of normal data. For example, metadata can serve as an Error Correction Code (ECC) for detecting and correcting errors in normal data. For instance, every 128 bits of data corresponds to 8 bits of ECC metadata. The controller calculates and stores these check bits when writing data and recalculates and compares them when reading. If a single-bit error is detected, it can be corrected immediately; if a multi-bit error is detected, it is reported to the system, thus ensuring the accuracy of critical data. Furthermore, metadata can also be used for memory management and addressing, describing information such as memory layout, timing parameters, frequency, or capacity.

[0044] Figure 1 This is an architecture diagram of a storage device in related technologies.

[0045] refer to Figure 1 The storage device includes an on-chip controller 1 and a storage array 2. The storage array 2 includes a first part 21 and a second part 22, and the on-chip controller 1 has a metadata register 11.

[0046] With metadata mode enabled, the principles for storing and retrieving both normal data and metadata include:

[0047] The host 3 sends a normal write command to the on-chip controller 1, which receives and outputs the normal write command. Based on the normal write command, normal data is stored in the first part 21, and metadata is registered in the metadata register 11.

[0048] Host 3 sends a metadata write command to on-chip controller 1, which receives and outputs the metadata write command. Based on the metadata write command, the metadata registered in metadata register 11 is stored in the second part 22. It is understandable that host 3 typically sends a metadata write command after issuing multiple normal write commands.

[0049] The host 3 sends a normal read command to the on-chip controller 1, which receives and outputs the normal read command. Based on the normal read command, normal data is read from the first part 21 and transmitted to the host 3, and metadata is read from the second part 22 and stored in the metadata register 11.

[0050] Host 3 sends a metadata read command to on-chip controller 1, which receives and outputs the metadata read command. Based on the metadata read command, metadata is read from metadata register 11 and output to host 3. It is understandable that host 3 typically sends a metadata read command before issuing multiple normal read commands.

[0051] In the above scheme, the performance of the storage device needs to be improved. For example, the metadata register used to store metadata occupies a large area and has low data transfer efficiency.

[0052] To address or improve the aforementioned technical problems, embodiments of this application provide a storage device including a storage array and an on-chip controller. The on-chip controller can mask metadata read / write commands in a first read / write command and output target data read / write commands in the first read / write command. In a first mode, the storage array responds to the target data read / write command by accessing a first storage area and a second storage area in parallel. The first storage area is used to store normal data, and the second storage area is used to store metadata. This saves on the overhead of metadata registers, reduces cost and power consumption, and improves data transmission efficiency because normal data and metadata can be written to or read from the storage array together. In summary, the performance of the storage device provided by embodiments of this application can be improved.

[0053] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0054] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined. Similarly, "multiple sets" refers to two or more sets (including two sets), and "multiple pieces" refers to two or more pieces (including two pieces).

[0055] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0056] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. In addition, the character " / " in this document generally indicates that the related objects before and after it have an "or" relationship.

[0057] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application. For example, if the device or element in the illustration is inverted, then the element described as "below," "under," "below," or "bottom" of other elements or features will be oriented "above" or "top" of said other elements or features. Therefore, the term "below" may cover both above and below orientation depending on the context in which the term is used, which will be obvious to those skilled in the art. Materials may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0058] In the description of the embodiments of this application, when a component "includes" another component, other components are not excluded unless otherwise stated, and other components may be further included.

[0059] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various embodiments and the appended claims, the term "component" is also intended to include the plural form unless the context clearly indicates otherwise. Components include layers, films, regions, or plates, etc.

[0060] Figure 2 This is a functional block diagram of a storage device provided in an embodiment of this application.

[0061] refer to Figure 2 The storage device includes a storage array 101 and an on-chip controller 102. The storage array 101 includes a first storage area I and a second storage area II. The first storage area I is used to store normal data, and the second storage area II is used for metadata. The on-chip controller 102 is configured to receive a first read / write command WR1 / RD1 in a first mode. The first read / write command WR1 / RD1 includes a target data read / write command WR / RD and a metadata read / write command appearing sequentially. In the first mode, the on-chip controller 102 intercepts and processes the metadata read / write command and outputs the target data read / write command WR / RD. The storage array 101 is configured to, in the first mode, in response to the target data read / write command WR / RD, access the first storage area I and the second storage area II in parallel.

[0062] In the above technical solution, the on-chip controller 102 is designed to receive a first read / write command WR1 / RD1 in a first mode. The first read / write command WR1 / RD1 includes a target data read / write command and a metadata read / write command that appear sequentially. In the first mode, the on-chip controller intercepts the metadata command and only outputs the target data read / write command WR / RD. Correspondingly, the storage array includes a first storage area I and a second storage area II. In the first mode, the storage array 101 is configured to, in response to the target data read / write command WR / RD, access the first storage area I and the second storage area II in parallel to store normal data and metadata in parallel, or to read normal data and metadata in parallel. Thus, by using the storage device provided in this embodiment, the purpose of parallel storage or reading of normal data and metadata can be achieved, saving the area and cost overhead of the metadata register, and also improving the utilization rate of the data bus to enhance data transmission efficiency.

[0063] The storage devices provided in the embodiments of this application will be described in more detail below with reference to the accompanying drawings.

[0064] In some embodiments, the storage device may be a storage device that includes volatile memory cells. For example, the storage device may include various dynamic random access memories (DRAMs), such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, DDR6 SDRAM, or Low Power Double Data Rate (LPDDR) SDRAM.

[0065] In other embodiments, the storage device includes, in addition to volatile memory cells, non-volatile memory cells such as SRAM, NAND flash memory, NOR flash memory, RRAM, FRAM, PRAM, TRAM, or MRAM.

[0066] Figure 3 This is a schematic diagram of a storage device.

[0067] refer to Figure 3 The storage array 101 and the on-chip controller 102 can be located on the same storage chip 100.

[0068] refer to Figure 3The on-chip controller 102 may be coupled to the host 10. The host 10 may represent any device that communicates with the on-chip controller 102, including any device that sends and / or receives data, addresses, and / or commands. For example, the host 10 may include at least one programmable or reconfigurable device. The programmable device may be a central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), a system-on-chip (SoC), or a neural network processing unit (NPU). The reconfigurable device may be a field-programmable gate array (FPGA).

[0069] The host 10 can communicate with the on-chip controller 102 based on any protocol. As an example, the host 10 can communicate with the on-chip controller 102 based on the following protocols: Serial Advanced Technology Attachment (SATA) interface, Peripheral Component Interconnect Fast (PCIe) interface, Universal Serial Bus (USB), Universal Flash Memory (UFS) interface, Embedded Multimedia Controller (eMMC) interface, etc.

[0070] The host 10 can send commands and / or addresses to the on-chip controller 102 to control the storage array 101. Furthermore, the host 10 can send data to or receive data from the storage array 101. The storage array 101 can receive data from the host 10 and store the received data. The storage array 101 can read stored data in response to a request from the host 10 and send the read data back to the host 10.

[0071] The on-chip controller 102 is a control logic circuit inside the memory chip 100. Its functions include: receiving external commands from the outside (such as the host) and compiling the external commands into internal commands required to drive the memory array 101.

[0072] The on-chip controller 102 can be used for command decoding and address management. For example, the on-chip controller 102 parses various commands (such as ACT activation command, READ read command, WRITE write command, or PRE precharge command) and address signals sent by the host 10, and decomposes them into specific row addresses, column addresses, and bank addresses. The on-chip controller 102 can also be used for timing generation and timing control, refresh management, and mode register configuration.

[0073] The storage device can operate in a first mode. In the first mode, normal data and metadata need to be stored in storage array 101, or the stored metadata and normal data need to be read from storage array 101. Therefore, in some examples, the first mode may also be a metadata-enabled mode. Metadata can refer to data used to improve the performance of the storage device or enhance its security. For example, metadata can be parity data to perform error correction operations on the corresponding normal data. For example, metadata may include information about the type, length, and attributes of the corresponding normal data, but the example embodiments are not limited thereto.

[0074] In the first mode, the first read / write command WR1 / RD1 received by the on-chip controller 102 can be: receiving m consecutive target data read / write commands followed by receiving a metadata read / write command; or receiving a metadata read / write command first, followed by receiving m consecutive target data read / write commands. m can be any positive integer greater than 1, for example, m can be 12, 14, or 16, etc.

[0075] It is understandable that for storage array 101, there are read operations and write operations. The target data read / write command corresponding to the read operation is the target data read command, and the metadata read / write command corresponding to the read operation is the metadata read command; the target data read / write command corresponding to the write operation is the target data write command, and the metadata read / write command corresponding to the write operation is the metadata write command.

[0076] Both the target data read / write command and the metadata read / write command can be sent from the host 10 to the on-chip controller 102.

[0077] In the first mode, the on-chip controller 102 processes the received first read / write command WR1 / RD1 to output the target data read / write command WR / RD and intercept the metadata read / write command, that is, the metadata read / write command will not be sent to the storage array 101.

[0078] In the first mode, the on-chip controller 102 processes the received first read / write command WR1 / RD1. When the first read / write command WR1 / RD1 is a target data read / write command WR / RD, it outputs the target data read / write command WR / RD. In the first mode, the storage array 101 responds to the target data read / write command WR / RD to perform normal read / write operations. During normal read / write operations, it simultaneously accesses the first storage area I and the second storage area II to store normal data in the first storage area I or read normal data from the first storage area I, and to store metadata in the second storage area II or read metadata from the second storage area II.

[0079] In the first mode, the on-chip controller 102 processes the received first read / write command WR1 / RD1. When the first read / write command WR1 / RD1 is a metadata read / write command, it intercepts the metadata read / write command, that is, it blocks the metadata read / write operation corresponding to the metadata read / write command, so that the storage array 101 will not receive instructions related to the metadata read / write command.

[0080] The storage array 101 can be one or more memory array tiles (MATs). Each memory array tile includes multiple memory cells, and the location of the memory cells is accessed through corresponding rows (i.e., word lines) and columns (i.e., bit lines). In some examples, the memory cells can be DRAM cells. It should be noted that the embodiments of this application do not limit the type of memory cells; for example, the memory cells can also be any other non-volatile memory cells besides DRAM cells.

[0081] It is understandable that the architecture of the first storage area I is the same as that of the second storage area II, that is, both include a cell array composed of multiple storage units.

[0082] Storage array 101 can also be one or more storage sections, each including multiple storage blocks. Storage array 101 can also be one or more banks, each including multiple storage sections. Different banks can be implemented to include the same type of storage units or to include different types of storage units.

[0083] Multiple repositories can be divided into multiple storage groups (BGs) according to operational needs, with each storage group comprising a number of repositories. For example, a storage array 101 containing 32 repositories can be divided into 8 storage groups, with each storage group containing 4 repositories. As another example, a storage array 101 containing 16 repositories can be divided into 4 storage groups, with each storage area containing 4 repositories.

[0084] Storage array 101 can also be a memory module, such as a single-in-line-memory module (SIMM) or a dual-in-line-memory module (DIMM). A memory module can include one or more memory blocks (RANKs), such as one RANK, two RANKs, or four or more RANKs.

[0085] Figure 4 This is an architecture diagram of a storage array. Figure 5 An architecture diagram for a single repository. (Reference) Figure 4 and Figure 5 Storage array 101 may include multiple repositories BK1 to BKn, and each repository BK1 may include multiple storage sections Section1 to Sectionk, where k and n are arbitrary positive integers. In some embodiments, at least one of the multiple repositories BK1 to BKn may include a first storage area I and a second storage area II, where the first storage area I stores normal data and the second storage area II stores metadata. Alternatively, each of the multiple repositories BK1 to BKn may include both a first storage area I and a second storage area II. In some embodiments, read operations on normal data and metadata can be performed simultaneously for the same repository, and write operations on normal data and metadata can also be performed simultaneously.

[0086] Figure 4 The first storage area I and the second storage area II are illustrated in the middle repository BK1. At least one of the other repositories may also include the first storage area I and the second storage area II.

[0087] The first storage area I and the second storage area II can be located within the same storage unit. Since the same word line within the same storage unit runs through both the first storage area I and the second storage area II, when a word line within the same storage unit is activated, both the first storage area I and the second storage area II can be prepared to store or read normal data. Compared to a scheme where the first and second storage areas do not have different storage units, this approach helps reduce power consumption and timing complexity.

[0088] In some embodiments, at least one of the multiple storage sections (Section 1 to Section k) in the same repository may include a first storage area I and a second storage area II, wherein the first storage area I stores normal data and the second storage area II stores metadata. In other embodiments, each of the multiple storage sections (Section 1 to Section k) in the same repository may include a first storage area I and a second storage area II.

[0089] Figure 6 The diagram illustrates a layout architecture of a single storage unit in repository BK1.

[0090] refer to Figure 5 The repository BK1 includes multiple storage sections Section1 to Sectionk arranged along the first direction Y. (See reference...) Figure 6 Each storage section includes multiple storage blocks along the second direction X.

[0091] Multiple storage blocks may include multiple first storage blocks MAT1 and at least one second storage block MAT2. It can be understood that each first storage block corresponds to a storage block MAT1, and each second storage block corresponds to a storage block MAT2.

[0092] It is understandable that, for memory blocks within the same memory section, each memory block has a corresponding sub-word line driver (SWD) and a sensor amplifier (SA). The sub-word line driver is used to activate or select the corresponding word line in the memory block, and the sensor amplifier is used to sense and amplify the signal of the corresponding bit line in the memory block. It is also understandable that the sub-word line drivers of different memory blocks can be independent of each other, or adjacent memory blocks can share a sub-word line driver; similarly, the sensor amplifiers of different memory blocks can be independent of each other, or adjacent memory blocks in different memory sections can share a sensor amplifier.

[0093] Normal data and its corresponding metadata can be stored in the same storage block. Alternatively, normal data and its corresponding metadata can be stored in different storage blocks, i.e., normal data is stored in multiple first storage blocks MAT1, and metadata is stored in second storage blocks MAT2.

[0094] Each storage block includes multiple column select lines (CSLs), and each CSL can be electrically connected to multiple bit lines within the storage block. For example, in the first mode, during a write or read operation, the column select line corresponding to normal data and the column select line corresponding to metadata can be activated simultaneously, and the normal data and the corresponding metadata can be stored or read together.

[0095] For example, in the first mode, the column selection line (CSL) in the storage block used to store metadata and the column selection line (CSL) in the storage block used to store normal data can be activated simultaneously to write metadata into or read from the storage block, and to write normal data into or read from the storage block.

[0096] Understandably, a single storage section can share a set of global sensitive amplifiers and column selection logic. For example, for the same storage section, activating a word line can activate the corresponding row in all storage blocks within the same storage section.

[0097] Figure 7 for Figure 6 An architecture diagram of a storage block.

[0098] refer to Figure 7 The storage block may include multiple word lines WL1 to WLi, multiple bit lines BL1 to BLj, and multiple storage cells MC located at the intersections of word lines WL1 to WLi and bit lines BL1 to BLj. The storage block also includes word line WLp and word line WLp-1, where i, j, and p are all positive integers, and p-1 < i.

[0099] In some embodiments, each memory cell MC may be a DRAM cell. For example, each memory cell MC may include a cell transistor connected to word lines and bit lines, and a cell capacitor connected to the cell transistor.

[0100] The storage block also includes multiple column select lines (CSLs).

[0101] A single column select line (CSL) can be electrically connected to multiple bit lines. For example, a single column select line (CSL) can be electrically connected to 4 or 8 bit lines. In some implementations, taking a single column select line (CSL) electrically connected to 8 bit lines as an example, 8 bits of data can be read from or written to the memory cell (MC) via a single word line and the single column select line (CSL). However, this is just an example, and the single column select line (CSL) can be implemented to be electrically connected to different numbers of bit lines.

[0102] The column select line (CSL) receives column control signals corresponding to column addresses. These control signals can be issued by the column decoder based on the column address. In other words, the CSL is activated or selected in response to the received column control signal. A single CSL can typically be electrically connected to multiple bit lines to enable parallel access. A 64-bit data bus width requires the simultaneous selection of 64 memory bits, which may necessitate multiple CSLs operating concurrently, each controlling a portion of the data. Figure 7 As shown, each column select line (CSL) can control 8 bit lines.

[0103] It is understandable that the aforementioned single column select line (CSL) can be electrically connected to multiple bit lines. This means that when a column select line (CSL) is activated, it conducts the column selection switches between the corresponding multiple bit lines and the local data lines (local IO, LIO), thus electrically connecting the multiple bit lines to their corresponding local data lines (LIO). When the column select line (CSL) is not activated, the column selection switches controlled by it are in the off state.

[0104] Each repository can include corresponding row decoders and column decoders. A row decoder can activate a selected word line from multiple word lines based on its row address. A column decoder can activate a selected column selection line from multiple column selection lines based on its column address.

[0105] Each storage block may have the same number of column select lines (CSLs). Alternatively, each storage block may have a different number of CSLs, at least some of which may have different numbers of CSLs.

[0106] Continue to refer to Figure 6 The first storage area I and the second storage area II can be located in the same storage section, and the first storage area I includes a plurality of first storage blocks MAT1, and the second storage area II includes at least one second storage block MAT2.

[0107] In other words, the storage blocks used to store normal data and the storage blocks used to store metadata belong to different storage blocks. In the first mode, in response to a target data read / write command, multiple first storage blocks MAT1 are accessed to write or read normal data, while at least one second storage block MAT2 is also accessed to write or read metadata.

[0108] In multiple first storage blocks MAT1, each first storage block MAT1 may have the same number of column select lines (CSLs). In other examples, the number of column select lines (CSLs) may also differ among the multiple first storage blocks MAT1.

[0109] For example, a portion of the multiple first storage blocks MAT1 may have the same number of column select lines (CSLs), such as all having the first number. The remaining portions of the first storage blocks MAT1 may also have the same number of column select lines (CSLs), such as all having the second number, and the first number may be greater than the second number. Of course, in other embodiments, the first number may also be equal to the second number.

[0110] Figure 6 Taking the second storage area II with one second storage block MAT2 as an example, it can be understood that the second storage area II can also have two or more second storage blocks MAT2. This is related to the number of bits of metadata accessed in a single access and the number of bits of data that can be accessed in a single second storage block MAT2 in a single access. If the number of bits of metadata accessed in a single access is large and the number of bits of data that can be accessed in a single second storage block MAT2 in a single access is small, then two or more second storage blocks can be laid out.

[0111] Furthermore, the second storage block MAT2 has a third number of column select lines (CSLs), which can be the same as or different from the first or second number. Alternatively, the third number can be different from both the first and second number.

[0112] In some embodiments, parallel access to the first storage area I and the second storage area II may include: the target data read / write command corresponds to a burst transfer, and within a burst length, the first storage area I and the second storage area II are accessed.

[0113] Within a single burst transfer, multiple consecutive column addresses (logical addresses) corresponding to the same activated word line in the same storage section can be accessed. These column addresses can be physically mapped to multiple first storage blocks MAT1 and at least one second storage block MAT2, respectively, to achieve the purpose of accessing multiple first storage blocks MAT1 to write or read normal data, and accessing at least one second storage block MAT2 to write or read metadata.

[0114] A burst transfer has a length of N, meaning that after a selected word line is activated, N consecutive column addresses can be accessed sequentially to store or read data. The selected column selection lines (CSLs) corresponding to each column address can be distributed across different storage blocks, such as in the first storage block MAT1 and the second storage block MAT2. It can be understood that the target data and metadata are transmitted within a single burst transfer, which can be considered as parallel access to the first storage area I and the second storage area II. In other words, in response to a single activation command, multiple first storage blocks MAT1 and second storage blocks MAT2 can be selected simultaneously. Therefore, in response to target data read / write commands, multiple first storage blocks MAT1 and second storage blocks MAT2 can be accessed simultaneously, i.e., simultaneous access to the first storage area I and the second storage area II.

[0115] Taking a target data of 256 bits and metadata of 16 bits as an example, the maximum data bit width for a single access to each first storage block MAT1 can be 16 bits, and the maximum data bit width for a single access to each second storage block MAT2 can also be 16 bits. Therefore, the length of a single burst transfer can be 9 bits, sequentially accessing 8 first storage blocks MAT1 and 1 second storage block MAT2. 16 bits of target data are stored or read within each first storage block MAT1, and 16 bits of metadata are stored within a single second storage block MAT2. Since each repository opens two half-banks simultaneously, the number of first storage blocks MAT1 opened can be doubled, and the amount of target data stored or read from the first storage blocks MAT1 can also be doubled.

[0116] Taking a target data of 256 bits and metadata of 32 bits as an example, the maximum data bit width for a single access to each first storage block MAT1 can be 16 bits, and the maximum data bit width for a single access to each second storage block MAT2 can also be 16 bits. Therefore, the length of a single burst transfer can be 9 bits, sequentially accessing 8 first storage blocks MAT1 and 1 second storage block MAT2. 16 bits of target data are stored or read within each first storage block MAT1, and 16 bits of metadata are stored within a single second storage block MAT2. Since each repository simultaneously opens two half-banks, the number of open first storage blocks MAT1 and second storage blocks MAT2 can be doubled, and the target data stored or read from first storage blocks MAT1 and second storage blocks MAT2 can also be doubled.

[0117] It is understandable that in related technologies, for schemes targeting 256 bits of data, since metadata does not need to be transmitted within a single burst transmission, the length of a single burst transmission can be 8 bits to achieve access to the 256-bit target data. In some embodiments, within a single burst transmission, multiple first storage blocks MAT1 in the first storage area I can be accessed first to write or read all bits of normal data from the first storage area I, and then the second storage block MAT2 in the second storage area II can be accessed to write or read all bits of metadata from the second storage area II. Alternatively, within a single burst transmission, multiple first storage blocks MAT1 in the first storage area I can be accessed first to write or read some bits of normal data from the first storage area I, and then the second storage block MAT2 in the second storage area II can be accessed to write or read all bits of metadata from the second storage area II, and then the other first storage blocks MAT1 in the first storage area I can be accessed to write or read the remaining bits of normal data from the first storage area I. Alternatively, within a single burst transmission, the second storage block MAT2 in the second storage area can be accessed first to write all bits of metadata to or read from the second storage area II, and then multiple first storage blocks MAT1 in the first storage area I can be accessed to write all bits of normal data to or read from the first storage area I.

[0118] It is understood that the embodiments of this application do not limit the specific steps for retrieving normal data and metadata in a single burst transfer. The order of transmitting normal data and metadata in a single burst transfer may also be different depending on the physical layout of the column address and the selected column selection line in the single burst transfer.

[0119] Storing or retrieving metadata and normal data within a single burst transfer maximizes the utilization of single-row activation commands, reducing access latency and power consumption. It also reduces command overhead, lowers the complexity and scheduling difficulty of the on-chip controller, and increases the effective transmission bandwidth of the data bus. Furthermore, since normal data and their corresponding metadata are logically related, storing or writing them within a single burst transfer ensures temporal and spatial consistency during storage and retrieval.

[0120] It is understood that in other embodiments, the first and second storage areas may be accessed separately within different burst transmissions.

[0121] Figure 8 This is a schematic diagram of a storage device in the first mode.

[0122] refer to Figure 8 The storage device also includes a data bus BUS coupled between the on-chip controller 102 and the storage array 101. In the first mode, in response to the target data read / write command WR / RD, the data transmitted on the data bus BUS during each read / write operation includes normal data and metadata.

[0123] The on-chip controller 102 can be located in a sub-channel, and correspondingly, the data bus BUS is also a data bus connecting the sub-channel and the storage array 101.

[0124] In technologies requiring metadata registers, the data bus between the on-chip controller and the memory array does not transmit normal data and metadata simultaneously; only one of them is transmitted. However, in the solution of this application embodiment, the data bus transmits both normal data and metadata simultaneously, which improves the utilization rate of the data bus.

[0125] Figure 9 This is a functional block diagram of an on-chip controller.

[0126] refer to Figure 9 The on-chip controller 102 includes a latch circuit 112 and a shielding circuit 122.

[0127] The latch circuit 112 is configured to receive the first read / write command WR1 / RD1 and perform delay processing on the first read / write command WR1 / RD1 to generate and output the delay command WR1 / RD1_D.

[0128] The shielding circuit 122 is configured to receive the target decoding signal Meta_D and the delay command WR1 / RD1_D. In a first mode, if the delay command WR1 / RD1_D is obtained based on the metadata read / write command, the target decoding signal Meta_D has a first state. In the first mode, if the delay command WR1 / RD1_D is obtained based on the target data read / write command WR / RD, the target decoding signal Meta_D has a second state. The shielding circuit 122 is configured to shield the delay command WR1 / RD1_D in response to the target decoding signal Meta_D having the first state, and to output the delay command WR1 / RD1_D as the target data read / write command WR / RD in response to the target decoding signal Meta_D having the second state.

[0129] The latch circuit 112 receives the clock signal CK and outputs a delayed command WR1 / RD1_D on the transition edge of the clock signal CK. The latch circuit 112 can be used to perform timing synchronization processing on the first read / write command WR1 / RD1. For example, the delayed command WR1 / RD1_D can be output when the clock signal CK transitions from a high level to a low level.

[0130] In some examples, the first state can be a logic high level, i.e., logic "1". In this case, the first read / write command WR1 / RD1 in the first mode is a metadata read / write command. Therefore, the shielding circuit 122 needs to shield the delay command WR1 / RD1_D, and thus will not output the target data read / write command WR / RD. At this time, the target data read / write command WR / RD is invalid, and the storage array 101 will not perform the corresponding read / write action. The second state can be a logic low level, i.e., logic "0". In this case, the first read / write command WR1 / RD1 in the first mode is the target data read / write command WR / RD. Therefore, the shielding circuit needs to output the target data read / write command WR / RD so that the storage array 101 responds to the target data read / write command WR / RD to store normal data and metadata, or responds to the target data read / write command WR / RD to read normal data and metadata.

[0131] Figure 10 This is a schematic diagram of a circuit structure for a latching circuit and a shielding circuit.

[0132] refer to Figure 10 The latch circuit 112 may include a D flip-flop 1121. The data input terminal of the D flip-flop 1121 receives the first read / write command WR1 / RD1, and the output terminal of the D flip-flop outputs the delay command WR1 / RD1_D.

[0133] The D flip-flop 1121 includes a first latch D1 and a second latch D2. The data input terminal of the first latch D1 receives a first read / write command WR1 / RD1, the clock terminal of the first latch D1 receives a clock signal CK, the output terminal of the first latch D1 is connected to the data input terminal of the second latch D2, the clock terminal of the second latch D2 receives the inverted clock signal CKN, and the output terminal of the second latch D2 outputs a delay command WR1 / RD1_D.

[0134] In other embodiments, the latch circuit may also include a D flip-flop and a latch connected in sequence. The data input of the D flip-flop receives the first read / write command WR1 / RD1, the output of the D flip-flop is connected to the data input of the latch, and the output of the latch outputs the delay command WR1 / RD1_D. The clock inputs of both the D flip-flop and the latch receive the clock signal CK.

[0135] Continue to refer to Figure 10 The shielding circuit 122 may include a latch 1221 and an NOR gate 1222.

[0136] The data input of latch 1221 receives the target decoding signal Meta_D, and the clock input of latch 1221 receives the delay command WR1 / RD1_D. When the delay command WR1 / RD1_D is enabled, latch 1221 outputs the target decoding signal Meta_D. One input of NOR gate 1222 is connected to the output of latch 1221, and the other input of NOR gate 1222 receives the inverted signal WR1 / RD1_DN of the delay command. The output of NOR gate 1222 is used to output the target data read / write command WR / RD.

[0137] In some cases, the high level of the delay command WR1 / RD1_D corresponds to the logic "1" period, which means that the delay command WR1 / RD1_D is enabled.

[0138] Figure 11 for Figure 10 A timing diagram of each signal in the diagram. Figure 11 In case (a), the target decoded signal has the first state. Figure 11 In (b), the target decoding signal has a second state.

[0139] Reference Figure 10 and Figure 11 The working principle of the on-chip controller 102 includes the following:

[0140] In the first mode, when the first read / write command WR1 / RD1 is the target data read / write command WR / RD, the target decoding signal Meta_D has a second state, corresponding to... Figure 11In case (b), the target decoding signal Meta_D is always at a low logic level, i.e., logic "0". In this case, the output of latch 1221 is always logic "0". Therefore, when the delay command WR1 / RD1_D is logic "0", the inverted signal WR1 / RD1_DN of the delay command is logic "1", and the output of NOR gate 1222 is logic "0"; when the delay command WR1 / RD1_D is logic "1", the inverted signal WR1 / RD1_DN of the delay command is logic "0", and the output of NOR gate 1222 is logic "1". Thus, the final output target data read / write command WR / RD is valid, meaning the target data read / write command WR / RD has an enable period, i.e., a logic "1" period.

[0141] In the second mode, when the first read / write command WR1 / RD1 is a metadata read / write command, the target decoding signal Meta_D has a first state, corresponding to... Figure 11 In case (a), the target decoding signal Meta_D has an enable period synchronized with the enable period of the delay command WR1 / RD1_D. When enabled, the target decoding signal is logic "1". In this case, the output of latch 1221 is synchronized with the target decoding signal Meta_D. Therefore, when the delay command WR1 / RD1_D is logic "0", the inverted signal WR1 / RD1_DN of the delay command is logic "1", the target decoding signal Meta_D is logic "0", and the output of NOR gate 1222 is logic "0"; when the delay command WR1 / RD1_D is logic "1", the inverted signal WR1 / RD1_DN of the delay command is logic "0", the target decoding signal Meta_D is logic "1", and the output of NOR gate 1222 is logic "0". Thus, the target data read / write command WR / RD is always invalid, meaning that the target data read / write command WR / RD never has an enable period, which is equivalent to disabling the metadata read / write command, so no metadata read / write command will be output.

[0142] Figure 12 This is another functional block diagram of the on-chip controller.

[0143] refer to Figure 12 The on-chip controller 102 may further include a first decoding circuit 132 and a second decoding circuit 142. The first decoding circuit 132 is used to output a first read / write command WR1 / RD1 to the latch circuit 112. The second decoding circuit 142 is used to output a target decoding signal Meta_D to the shielding circuit 122.

[0144] The first decoding circuit 132 can be a command decoding circuit, which decodes the command address signal (CA, command / address) to obtain the first read / write command WR1 / RD1. The command address signal can be sent by the host, so it can also be understood that the command address signal includes the first read / write command WR1 / RD1. In other words, the first read / write command WR1 / RD1 is a command provided by the host.

[0145] The second decoding circuit 142 can be a decoding circuit that determines whether to perform metadata operations according to the definition of metadata specified in the specification (SPEC). If yes, the second decoding circuit 142 outputs a target decoding signal Meta_D with a first state; if no, the second decoding circuit 142 outputs a target decoding signal Meta_D with a second state.

[0146] Figure 13 This is a functional block diagram of a storage device in the second mode.

[0147] refer to Figure 13 The on-chip controller 102 can also be configured to receive a second read / write command WR2 / RD2 in the second mode. The second read / write command WR2 / RD2 includes a target data read / write command WR / RD, which instructs the parallel storage or retrieval of normal data and metadata in the storage array 101. In the second mode, the on-chip controller 102 outputs the target data read / write command WR / RD. The storage array 101 is further configured to, in the second mode, in response to the target data read / write command WR / RD, access the first storage area I and the second storage area II in parallel.

[0148] The second mode is also a metadata-enabled mode. In the first mode, the first read / write command WR1 / RD1 sent by the host is intended to sequentially store normal data and metadata in the storage array 101 in a serial access manner, or to sequentially read normal data and metadata in a serial access manner. Therefore, the first read / write command WR1 / RD1 includes the sequentially issued target data read / write command WR / RD and metadata read / write command. Unlike the first mode, in the second mode, the second read / write command WR2 / RD2 sent by the host is intended to store normal data and metadata in the storage array 101 in a parallel access manner. Therefore, the second read / write command WR2 / RD2 only includes the target data read / write command WR / RD and does not include the metadata read / write command. That is to say, in the second mode, the on-chip controller 102 will not receive the metadata read / write command.

[0149] In the second mode, in response to the target data read / write command WR / RD, the first storage area I is accessed to store or read normal data, and the second storage area II is also accessed to store or read metadata. In some embodiments, in the second mode, during a write operation, in response to the target data read / write command WR / RD, normal data is written to the first storage area I, and metadata is written to the second storage area II; in the second mode, during a read operation, in response to the target data read / write command WR / RD, normal data is read from the first storage area I, and metadata is read from the second storage area II.

[0150] For example, in a write operation, normal data received from the host is directly stored in the first storage area I, and metadata received from the host is directly stored in the second storage area II; in a read operation, normal data read from the first storage area I is directly transmitted to the host, and metadata read from the second storage area II is directly transmitted to the host.

[0151] In addition, in the second mode, the first storage area I can be accessed to store normal data and the second storage area II can be accessed to store metadata within a single burst transmission; or, the first storage area I can be accessed to read normal data and the second storage area II can be accessed to read metadata within a single burst transmission.

[0152] For details on the specific methods of accessing the first storage area I and the second storage area II within a single burst transmission, please refer to the corresponding description in the aforementioned first mode, which will not be repeated here.

[0153] As can be seen from the above analysis, the embodiments of this application can adopt the same storage array architecture, and lay out a vertically extending curve out (i.e., a second storage area II extending along the second direction) in the storage array. This can realize the purpose of accessing various metadata-related requests sent by the host, including requests for serial transmission of normal data and metadata sent by the host (corresponding to the first mode), and requests for parallel transmission of normal data and metadata sent by the host (corresponding to the second mode). This helps to solve the problems of area overhead caused by the layout of metadata registers, complex read timing, and a large number of buses used for transmitting metadata and normal data in related technologies. Therefore, it helps to save the overhead of metadata registers, increase the data bit width of parallel transmission, improve the transmission efficiency of data transmission bus, and also support multiple different working modes.

[0154] In some examples, the second mode may also include a first-width mode or a second-bit-width mode, in which the metadata accessed by a single access to the second storage area II in the first-width mode has a first-width, and in the second-bit-width mode, the metadata stored by a single access to the second storage area II in the second-bit-width mode has a second-bit-width, and the first-width is less than the second-bit-width.

[0155] For example, the first bit width can be 16 bits, and the second bit width can be 32 bits. It is understood that in other embodiments, the specific number of bits for the first and second bit widths can also be other numbers.

[0156] It is understandable that the second bit width is less than or equal to the data bit width that can be stored in the second storage area II at one time.

[0157] Figure 14 This is another functional block diagram for storage devices. Figure 15 This is a schematic diagram showing the relationship between the first and second storage areas and the corresponding column selection lines in a single storage unit.

[0158] refer to Figure 14 and Figure 15 The storage device may also include a column decoder 103. The column decoder 103 is connected to a first storage area I via multiple first column select lines CSL1 and to a second storage area II via multiple second column select lines CSL2.

[0159] In response to the target data read / write command WR / RD, parallel access to the first storage area I and the second storage area II includes: in the first mode, storing normal data based on the first column address and storing metadata based on the second column address, or reading normal data based on the first column address and reading metadata based on the second column address, wherein the first column address is used to select multiple first column selection lines CSL1 and the second column address is used to select multiple second column selection lines CSL2.

[0160] In the first mode, the first column address can be understood as the logical address used to activate the corresponding first column selection line CSL1, and the second column address can be understood as the logical address used to activate the corresponding second column selection line CSL2.

[0161] Based on the received first column address, column decoder 103 activates or selects corresponding first column select lines CSL1 in a first mode to store or read normal data in the first storage area I. For example, in the first mode, corresponding first column select lines CSL1 in multiple first storage blocks MAT1 are activated to store normal data in or read normal data from multiple first storage blocks MAT1.

[0162] The column decoder 103 also activates or selects corresponding multiple second column select lines CSL2 in the first mode based on the received second column address, thereby storing or reading metadata in the second storage area II. For example, in the first mode, corresponding second column select lines CSL2 in multiple second storage blocks MAT2 are activated to store metadata in or read metadata from the second storage block MAT2.

[0163] It is understandable that, in the second mode, the storage device can also adopt the aforementioned method. Figure 14 and Figure 15 The column decoder, the first column selection line CSL1, and the second column selection line CSL2 read and write normal data in the first storage area I and metadata in the second storage area II, which will not be described in detail here.

[0164] Figure 16 This is a schematic diagram of a single storage unit in the third mode.

[0165] Reference Figure 2 and Figure 16 The storage device is also configured to operate in a third mode, in which the storage array 101 is configured to store normal data based on a first column address, the first column address being used to select multiple first column select lines CSL1 and at least a portion of the second column select lines CSL2.

[0166] The third mode is a metadata-disabled mode, or in other words, a metadata-free mode. In the third mode, the storage blocks originally used for storing metadata can be used to store normal data. Therefore, without changing the architecture of storage array 101, the storage devices have more selectable operating modes, and in the third mode, the second storage area II can also be used to store normal data. This allows the amount of normal data that a single storage section can store or retrieve in the third mode to be greater than the amount of data corresponding to the first mode, thereby further improving the normal data transfer rate in the third mode.

[0167] Furthermore, the way the storage array 101 is accessed in the first mode and the third mode is also adaptively adjusted. For example, in the first mode, the first storage area I is accessed to retrieve normal data and the second storage area II is accessed to retrieve metadata. In the third mode, the first storage area I and the second storage area II are accessed to retrieve normal data. In this way, the storage device can optimize storage performance in both the first mode and the third mode.

[0168] In the third mode, for the same storage section, in addition to multiple first storage blocks MAT1 being used to store normal data, second storage blocks MAT2 can also be used to store normal data. For example, within a single burst transmission, multiple first storage blocks MAT1 and second storage blocks MAT2 in the same storage section can be accessed simultaneously to write normal data into or read normal data from multiple first storage blocks MAT1 and second storage blocks MAT2.

[0169] In the third mode, the first column address may include multiple address units, each address unit corresponding to a first storage block MAT1. Each address unit is used to select multiple first column selection lines CSL1 in the corresponding first storage block MAT1, and each address unit is also used to select a portion of the second column selection lines CSL2 in the second storage block MAT2. Therefore, when the column decoder receives each address unit, the corresponding first storage block MAT1 and a portion of the second storage block MAT2 can store normal data or read out normal data.

[0170] It is understandable that different address units can be used to select the same or different number of second column selection lines (CSL2). For example, one address unit can be used to select 4 second column selection lines (CSL2), while another address unit can be used to select 2 second column selection lines (CSL2). Yet another example is that each address unit can be used to select 4 second column selection lines (CSL2).

[0171] The storage device may also include a mode register, which is used to set a first mode, a second mode, or a third mode.

[0172] The above technical solution adopts an optimized on-chip controller and storage array design, and uses the same storage array 101 architecture and on-chip controller architecture. It can support a variety of different working modes related to metadata, and does not require setting up a metadata register, thus saving the overhead of the metadata register and reducing the design complexity such as timing complexity in the access process.

[0173] Furthermore, in the first mode, the first and second storage areas can be accessed in parallel to enable access to normal data and metadata, which helps to increase parallel data bandwidth and improve data transmission efficiency.

[0174] Accordingly, embodiments of this application also include an electronic device that includes the storage device provided in any of the foregoing embodiments. Therefore, the descriptions of the foregoing embodiments are also applicable to embodiments of the electronic device.

[0175] Figure 17 A block diagram of an electronic device provided in an embodiment of this application.

[0176] refer to Figure 17 The electronic device includes a processor 401 and a storage device 402, the storage device 402 being coupled to the processor 401, and the storage device 402 including the storage device provided in any of the foregoing embodiments.

[0177] The processor 401 described above can refer to one or more processors. For example, processor 401 may include one or more central processing units (CPUs), or it may include a CPU and a graphics processing unit (GPU), or it may include an application processor and a coprocessor (e.g., a microcontroller unit or neural network processor). When processor 401 includes multiple processors, these multiple processors may be integrated on the same chip or may be independent chips. A processor may include one or more physical cores, where a physical core is the smallest processing module.

[0178] As illustrated, the processor 401 can be implemented in at least one of the following hardware forms: Digital Signal Processing (DSP), Field Programmable Gate Array (FPGA), and Programmable Logic Array (PLA).

[0179] Processor 401 may integrate one or more of the following: a central processing unit (CPU), a graphics processing unit (GPU), and a modem. Electronic devices may include one or more of the following: for example, smartphones, personal computers (PCs), mobile phones, video phones, e-book readers, desktop PCs, laptop PCs, netbooks, workstations, servers, personal digital assistants (PDAs), portable media players (PMPs), MPEG 1 audio layer 3 (Moving Picture Experts Group Audio Layer III) players, mobile medical devices, cameras, home appliances, medical devices, Internet of Things (IoT) devices, and wearable devices. Wearable devices may be accessory-type, fabric or clothing-type, body-attached type, or implantable circuit type. Accessory-type wearable devices may include, for example, watches, rings, bracelets, anklets, necklaces, glasses, contact lenses, or head-mounted displays (HMDs). This electronic device can also be used in large servers, such as data centers or AI computers.

[0180] Those skilled in the art will understand that the above-described embodiments are specific examples of implementing this application, and in practical applications, various changes can be made in form and detail without departing from the spirit and scope of the embodiments of this application. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this application; therefore, the scope of protection of the embodiments of this application should be determined by the scope defined in the claims.

Claims

1. A storage device, characterized in that, include: A storage array, comprising a first storage area and a second storage area, wherein the first storage area is used to store normal data and the second storage area is used to store metadata; An on-chip controller is configured to receive a first read / write command in a first mode, the first read / write command including a target data read / write command and a metadata read / write command that appear sequentially. In the first mode, the on-chip controller intercepts and processes the metadata read / write command and outputs the target data read / write command. The storage array is configured to, in the first mode, access the first storage area and the second storage area in parallel in response to the target data read / write command.

2. The storage device according to claim 1, characterized in that, The first storage area and the second storage area are located in the same storage unit.

3. The storage device according to claim 2, characterized in that, The first storage area includes a plurality of first storage blocks, and the second storage area includes at least one second storage block.

4. The storage device according to any one of claims 1 to 3, characterized in that, Parallel access to the first storage area and the second storage area includes: the target data read / write command corresponds to a burst transmission, wherein the first storage area and the second storage area are accessed within a burst transmission.

5. The storage device according to any one of claims 1 to 3, characterized in that, The storage device further includes a data bus coupled between the on-chip controller and the storage array, wherein, in the first mode, in response to the target data read / write command, the data transmitted on the data bus during each read / write operation includes the normal data and the metadata.

6. The storage device according to claim 1, characterized in that, The on-chip controller includes: The latch circuit is configured to receive the first read / write command and perform delay processing on the first read / write command to generate and output a delayed command; A shielding circuit receives a target decoding signal and the delay command, wherein, in a first mode, if the delay command is obtained based on the metadata read / write command, the target decoding signal has a first state; and in the first mode, if the delay command is obtained based on the target data read / write command, the target decoding signal has a second state. The shielding circuit is configured to shield the delay command in response to the target decoding signal having the first state, and to output the delay command as the target data read / write command in response to the target decoding signal having the second state.

7. The storage device according to claim 6, characterized in that, The latching circuit includes: A D flip-flop, wherein the data input terminal of the D flip-flop receives the first read / write command, and the output terminal of the D flip-flop outputs the delayed command; and / or, the shielding circuit includes: A latch, wherein the data input terminal of the latch receives the target decoding signal, the clock terminal of the latch receives the delay command, and outputs the target decoding signal when the delay command is enabled; The NOR gate has one input connected to the output of the latch, the other input receiving the inverted signal of the delay command, and the output output for outputting the target data read / write command.

8. The storage device according to claim 6, characterized in that, The on-chip controller also includes: The first decoding circuit is used to output the first read / write command to the latch circuit; The second decoding circuit is used to output the target decoding signal to the shielding circuit.

9. The storage device according to claim 1, characterized in that, The on-chip controller is also configured to receive a second read / write command in a second mode, the second read / write command being used to instruct normal data and metadata to be stored or read in parallel in the storage array, and the on-chip controller outputs the second read / write command in the second mode. The storage array is further configured to, in the second mode, access the first storage area and the second storage area in parallel in response to the second read / write command.

10. The storage device according to claim 9, characterized in that, The second mode includes a first-width mode or a second-width mode. In the first-width mode, the metadata accessed in a single access to the second storage area has a first-width, and in the second-width mode, the metadata stored in a single access to the second storage area has a second-width. The first-width is smaller than the second-width.

11. The storage device according to claim 1, characterized in that, The storage device further includes: A column decoder, wherein the column decoder is connected to the first memory area via multiple first column select lines and to the second memory area via multiple second column select lines; The parallel access to the first storage area and the second storage area in response to the target data read / write command includes: Normal data is stored based on the first column address and metadata is stored based on the second column address, or the normal data is read based on the first column address and the metadata is read based on the second column address. The first column address is used to select multiple first column selection lines, and the second column address is used to select multiple second column selection lines.

12. The storage device according to claim 11, characterized in that, The storage device is also configured to operate in a third mode, in which the storage array is configured to store normal data based on the first column address, the first column address being used to select multiple first column selection lines and at least a portion of the second column selection lines.

13. An electronic device, characterized in that, Includes the storage device as described in any one of claims 1 to 12.

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