Interface for a semiconductor device and interface method thereof

Abstract

The present invention discloses an interface for a semiconductor device and an interface method thereof. The semiconductor device has a single master device and a plurality of slave devices that are conductively connected and stacked together. The interface includes a master interface built in the master device and including a master interface circuit having a master connection pad matrix. Additionally, a slave interface is implemented in each slave device and includes a slave interface circuit having a slave connection pad matrix to correspondingly connect to the master connection pad matrix. Clock wiring transmits a clock signal through the master interface and the slave interface. The master device transmits instructions and slave identification codes to all slave interfaces through the master interface. The slave device corresponding to the slave identification code responds with the result of executing the instructions to the master device through the slave interface and the master interface.

Description

Technical Field

[0001] The present invention relates to the manufacture of semiconductor devices, and more particularly, to an interface for a semiconductor device and an interface method for a semiconductor device. Background Art

[0002] Digital electronic devices based on semiconductor integrated circuits (such as mobile phones, digital cameras, personal digital assistants (PDAs), etc.) are designed to have more powerful functionality to adapt to various applications in the modern digital world. However, with the trend of semiconductor manufacturing, digital electronic devices are intended to be smaller and lighter while enhancing functionality and improving performance. A semiconductor device can be packaged as a 3D semiconductor device, in which several circuit chips can be stacked together and integrated into a larger integrated circuit, where connection pads and through-silicon vias (TSVs) are used for connection between chips.

[0003] System-on-integrated-chip (SoIC) packaging, wafer-on-wafer (WoW) packaging, and chip-on-wafer-on-substrate (CoWoS) packaging technologies have been proposed, as well as packaging multiple chips stacked together by height.

[0004] However, the communication between the main chip and multiple slave chips as a 3D stack is still under development to have better performance in a compact structure. Summary of the Invention

[0005] The present invention provides an interface for a 3D semiconductor device, in which a single main chip is stacked with multiple slave chips thereon to form a 3D package structure. The interface allows communication between the single main chip and the slave chips in an efficient manner.

[0006] In an embodiment, the present invention provides an interface for a semiconductor device. The semiconductor device includes a main device and multiple slave devices. The main device and the slave devices are stacked together via a conductive connection. The interface includes a main interface, a slave interface, and a clock route. The main interface is built in the main device and includes a main interface circuit having a main bond pattern. The slave interface is built in each slave device and includes a slave interface circuit having a slave bond pattern to correspondingly connect to the main bond pattern. The clock route is used to transmit a clock signal through the main interface and the slave interface. The main device transmits an instruction and a slave identification code to all slave interfaces through the main interface. The slave device corresponding to the slave identification code responds with the result of the executed instruction to the main device through the slave interface and the main interface.

[0007] In an embodiment, the present invention further provides an interface method for a semiconductor device. The semiconductor device includes a single master device and a plurality of slave devices. The master device and the slave devices are stacked together via a conductive connection. The interface method includes constructing a master interface in the master device, the master interface including a master interface circuit having a master connection pad matrix. Additionally, a slave interface is constructed in each slave device, the slave interface including a slave interface circuit having a slave connection pad matrix for correspondingly connecting to the master connection pad matrix. A clock wiring is constructed to transmit a clock signal through the master interface and the slave interfaces. The master device transmits instructions and slave identification codes to all slave interfaces through the master interface. The slave device corresponding to the slave identification code responds with the result of executing the instructions to the master device through the slave interface and the master interface.

[0008] To make the foregoing content easier to understand, several embodiments with accompanying drawings are described in detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure.

[0010] Figure 1 is a drawing schematically showing a cross-sectional stacked structure of a 3D semiconductor device according to an embodiment of the present invention;

[0011] Figure 2 is a drawing schematically showing a cross-sectional stacked structure of a 3D semiconductor device having an interface according to an embodiment of the present invention;

[0012] Figure 3 is a drawing schematically showing a perspective stacked structure of a 3D semiconductor device having a communication mechanism with an interface according to an embodiment of the present invention;

[0013] Figure 4 is a drawing schematically showing a communication mechanism of an interface between a master chip and a slave chip according to an embodiment of the present invention;

[0014] Figure 5 is a drawing schematically showing a 3D communication mechanism of an interface between a master chip and a slave chip according to an embodiment of the present invention;

[0015] Figure 6 is a drawing schematically showing a circuit structure of an interface between a master chip and a slave chip according to an embodiment of the present invention;

[0016] Figure 7 is a drawing schematically showing a circuit structure of an interface between a master chip and a slave chip according to a further embodiment of the present invention;

[0017] Figure 8 is a diagram schematically showing a read cycle of an interface between a main chip and a slave chip according to a further embodiment of the present invention;

[0018] Figure 9 is a diagram schematically showing a circuit structure of an interface between a main chip and a slave chip based on the DDR mode according to an embodiment of the present invention;

[0019] Figure 10 is a diagram schematically showing signal forms of various signals involved in an interface according to an embodiment of the present invention;

[0020] Figure 11 is a diagram schematically showing a partial circuit of a slave interface having a clock tree mechanism according to an embodiment of the present invention.;

[0021] Figure 12 is a diagram schematically showing signal forms of various signals involved in an interface based on the DDR mode according to an embodiment of the present invention;

[0022] Figure 13 is a diagram schematically showing signal forms of various signals involved in an interface according to an embodiment of the present invention.

[0023] Description of the reference numerals in the drawings

[0024] 10: 3D semiconductor device;

[0025] 20, 30: Substrate;

[0026] 22, 32: Circuit layer;

[0027] 24, 34: Circuit chip;

[0028] 26, 36: TSV structure;

[0029] 38: Connection pad portion;

[0030] 40: Interface area;

[0031] 100: Main chip;

[0032] 102, K, N: Slave chip;

[0033] 104, 104M, 104S: Connection pad structure;

[0034] 110: CPU block;

[0035] 112: Cache block;

[0036] 120: SRAM block;

[0037] 130: Logic circuit;

[0038] 132, 202, 210, 222, 222a, 222b, 224: Flip - flop block;

[0039] 200: Interface;

[0040] 200M: Main interface;

[0041] 200S: Slave interface;

[0042] 204: Flip - flop block;

[0043] 204A: First - in - first - out block;

[0044] 206: Multiplexer;

[0045] 208, 220: Connection pad matrix;

[0046] 224a: Enable flip - flop block;

[0047] 226: Slave multiplexer;

[0048] 228a, 228b: Output control block;

[0049] 230: Circuit block;

[0050] 230a, 230b: Delay - locked loop block;

[0051] 230c: Delay control unit;

[0052] 240: Inverter;

[0053] 250: Read instruction;

[0054] 270: Time delay;

[0055] 300, NOP, PA, RD, s_cmd: Instructions;

[0056] 302, clk, clk_in, clk_out, CACd_clk: Clocks;

[0057] 400 Clock tree;

[0058] DID: slave_identification signal;

[0059] rd_data, rx_data, tx_data: Data;

[0060] s_did: Slave identification;

[0061] S_CMD, S_DID: Instruction signals;

[0062] tx_en: Enable signal. Detailed implementation

[0063] The present invention relates to an interface for 3D semiconductor devices, where the interface is also manufactured based on 3D packaging technology. The interface can link a single master chip, such as a processor, with multiple slave chips, such as static random access memory (SRAM).

[0064] In the present invention, the interface allows communication between a single master chip and multiple slave chips. The communication signal can include instructions from the master chip and response information from the selected slave chip. The interface provides reliable communication. In addition, the signal delay between the master chip and each slave chip can be substantially constant and predictable. Due to the control of the delay, the triggering edge of the effective clock can be appropriately set corresponding to the data packet, which can also be called the data eye.

[0065] Several embodiments are provided to describe the present invention, but the present invention is not limited to the described embodiments.

[0066] Figure 1 is a drawing schematically showing the structure of a 3D semiconductor device in a cross-sectional view according to an embodiment of the present invention. Refer to Figure 1 , the 3D semiconductor device 10 includes multiple chips 24 and multiple chips 34. In addition to the horizontal distribution of the chips, the multiple chips 24 and multiple chips 34 are also vertically stacked together. Thus, a 3D semiconductor device including chips is formed.

[0067] In an example, the circuit chip 24 can be regarded as the master chip, which generally includes a substrate 20 and a circuit layer 22. Several other circuit chips 34, such as acting as slave chips, will be stacked above the circuit chip 24, where a via structure based on the packaging process, such as a TSV structure 26 with connection pads, can be formed between the circuit chip 24 and the circuit chip 34. The circuit chip 34 includes a substrate 30 and a circuit layer 32 and can also include a TSV structure 36 at the corresponding position to be electrically connected to the circuit chip 24. In addition, connection pads 38 can also be formed at the outermost surface corresponding to the TSV structure 36.

[0068] 3D packaging technologies have been proposed in various stacking structures, such as system-on-integrated-chips (SoIC) packaging, Wafer-on-Wafer (WoW) packaging, and Chip-on-Wafer-on-Substrate (CoWoS). The present invention is based on 3D packaging but is not limited to the type of 3D packaging.

[0069] Figure 2 FIG. is a cross-sectional stacked structure of a 3D semiconductor device with an interface according to an embodiment of the present invention. Refer to Figure 2 , based on the 3D packaging structure, in an embodiment, the 3D semiconductor device 10 may further include an interface region 40, where interfaces in each of the circuit chips 24 and 34 are formed at the interface region 40. The interface may link the circuit chip 24 acting as the master chip to all the circuit chips 34 acting as slave chips. Communication between the circuit chip 24 and the circuit chip 34 may be through the interface at the interface region 40.

[0070] The circuit of the interface implemented within the interface region 40 will be described in detail later. In an embodiment, it should also be noted that multiple interface regions 40 may be formed in the circuit chip, depending on actual needs, and not limited to a single interface region.

[0071] Figure 3 FIG. is a perspective stacked structure of a 3D semiconductor device with a communication mechanism having an interface according to an embodiment of the present invention.

[0072] Refer to Figure 3 , as can be seen in the 3D stacked structure in the operation of the interface, the master chip 100 (e.g., a processor chip) is included in the semiconductor device as a base chip. A plurality of slave chips 102 (e.g., SRAM chips) are stacked above the master chip 100. The master chip 100 includes a master interface and each slave chip includes a slave interface. The master interface and the slave interface are formed as an interface 200, which may also be referred to as Glink-3D. The master chip 100 and the slave chips 102 are linked through the interface 200 to communicate using information / data / signals.

[0073] In an exemplary operation, the master chip 100 of the processor has an instruction to access data stored in the slave chip 102 of the SRAM chip. Due to the implemented interface, the read latency can be controlled to be approximately constant and small, e.g., 2 nanoseconds or 5 nanoseconds in the example. A single clock is used in the interface for distribution to all the slave chips, and the path length from the master chip 100 to each slave chip 102 is approximately the same and reliable. The latency can be adjusted to be approximately constant as predictable.

[0074] Figure 4 FIG. is a diagram schematically showing a communication mechanism of an interface between a master chip and a slave chip according to an embodiment of the present invention. Refer to Figure 4 , a communication mechanism between the master chip 100 having a master interface 200M and the slave chip 102 having a slave interface 200S through a connection pad structure 104 in a 3D package is described. The master interface 200M and the slave interface 200S are formed as before Figure 3The interface 200 described in []. Inside the main chip 100, the CPU block 110 with the cache block 112 in the example forms a processor. The processor is connected to the main interface 200M to transmit or receive signals at the main interface 200M, such as when intending to communicate with the slave chip 102.

[0075] Inside the slave chip 102, there is also an SRAM block 120 and a slave interface 200S. The SRAM block 120 is connected to the slave interface 200S for communication with the main chip 100. In the communication, the main interface 200M and the slave interface 200S are connected through the connection pad structure 104. Depending on the packaging process, the connection pad structure 104 may include TSVs with a hybrid connection pad matrix. The connection is bidirectional. Generally, the connection pad matrix may correspond to a data bus. All signals are transmitted or received in parallel. In the example, the clock rate can be 2.5 gigahertz. The signal latency between the main chip 100 and the slave chip 102 through the interfaces of the main interface 200M and the slave interface 200S is reliable, and as an example, it can be about 2 nanoseconds in one way.

[0076] Figure 5 is a drawing schematically showing a 3D communication mechanism of the interface between the main chip and the slave chip according to an embodiment of the present invention. Refer to Figure 5 , based on the operation mechanism described previously, the main chip 100 and the slave chip 102 in the 3D structure are shown in more detail as an example. The main chip 100 (such as a processor) includes a main interface 200M, and the main interface 200M includes a connection pad structure 104M. The connection pad structure 104M in the example includes a connection pad matrix composed of multiple connection pad parts in the example. Therefore, depending on the data size of the bus, the connection pad parts are formed into an array, where one tile corresponds to a group of binary data (such as 16-bit data with power connection pads, clock bonds, and other specified connection pads). Multiple connection pad tiles form the entire connection pad matrix of the main interface 200M. As pointed out, the data from the processor communicates bidirectionally with the main interface 200M.

[0077] Similarly, the chip 102 may include SRAM and a slave interface 200S. The SRAM communicates with the slave interface 200S, and the slave interface 200S communicates with the master interface 200M through a connection pad structure 104S, which is composed of a plurality of connection pad portions arranged in an array to form a connection pad matrix, and each connection pad portion is represented by a square unit. Similarly, the connection pad matrix is also divided into a plurality of tiles. In 3D packaging technology, the master interface 200M and the slave interface 200S are connected through the connection pad structure 104M and the connection pad structure 104S having matching connection pad matrices. Therefore, based on 3D packaging technology, the master interface 200M and the slave interface 200S are connected as a complete interface to communicate between the master chip 100 and the slave chip 102. As pointed out, a plurality of slave chips 102 are stacked on top of the master chip 100, where the master interface 200M and the slave interface 200S are connected together in the vertical direction.

[0078] The circuit descriptions of the master interface 200M and the slave interface 200S are as follows. Figure 6 FIG. is a schematic diagram showing the circuit structure of the interface between the master chip and the slave chip according to an embodiment of the present invention.

[0079] Refer to Figure 6 , the master interface 200M of the master chip 100 and the slave interface 200S of the slave chip 102 are described with the implemented circuit. For the master interface 200M, it includes a flip-flop (FF) block 202 to receive instructions expected by the core circuit of the master chip 100. The instructions input in the example may include data tx_data and / or a cluster of instructions, but are not specifically limited. Depending on actual needs, the number of flip-flop blocks 202 may be one unit (FF) or multiple units (FFs), but is not limited thereto. The instructions from the master chip 100 in the example may include the instructions and data clusters to be transmitted. The instructions may also include a slave identification code, which is used to select the slave chip 102 to execute the instructions from the master chip 100.

[0080] The multiplexer 206 receives the output of the flip-flop block 202. The multiplexer 206 in the example is of the double data rate (DDR) type consistent with the input data at the flip-flop block 202. The output of the multiplexer 206 is transmitted to the corresponding connection pad portion of the connection pad matrix 208 in the master interface 200M.

[0081] As pointed out, a single clock clk is provided to the slave chip 102 through the master interface 200M and the slave interface 200S. The flip-flop block 202 and the multiplexer 206 are controlled by the clock clk_in timing. In the master interface 200M, the flip-flop block 202 and the master multiplexer 206 form a transmission path to transmit instructions to the slave chip 102.

[0082] The main interface 200M also includes a receive path to receive responses from the slave chip 102 via the corresponding connection pad portions of the connection pad matrix 208 from the interface 200S and the main interface 200M. The first-in-first-out (FIFO) block 204A receives the responses from the slave interface 200S. The FIFO block 204A in the example includes a plurality of flip-flop blocks 204. The output of the FIFO block 204A is provided to another flip-flop block 210 and then transmitted inward to the core of the main chip 100. The flip-flop block 210 is controlled by the clock clk_in. The FIFO block 204A is controlled by a feedback clock from the slave chip 102, and the feedback clock has an enable control corresponding to the response data from the slave chip 102.

[0083] In an example of a read operation, the instructions of the main chip 100 are received by the flip-flop block 202 of the main interface 200M. The selected slave chip 102 responds with the requested data to the FIFO block 204A of the main interface 200M.

[0084] In the slave interface 200S of the chip 102, the connection pad matrix 220 corresponds to the connection pad matrix 208. The instructions of the main chip 100 are then received by the flip-flop block 222, which also controls the clock clk. The flip-flop block 222 in the slave interface 200S then further transmits the instructions (such as rx_data and / or instructions) inward to the SRAM of the slave chip 102. In the example, the main chip 100 sends an instruction to read data from the SRAM of the slave chip 102.

[0085] Subsequently, the slave chip 102 provides a data cluster requested from the main chip 100 (also labeled as tx_data sent to the slave chip 102 in the example) to the circuit block 230. The circuit block 230 is also controlled by the clock clk and the enable signal tx_en. The circuit block 230 includes a flip-flop block 224, an enable flip-flop block 224a, a slave multiplexer 226, and output control blocks 228a and 228b.

[0086] The clock signal clk in each slave interface 200S for control is also provided to the third flip-flop block 222, the fourth flip-flop block 224, the slave multiplexer 226, the enable flip-flop block 224a, and the output control block 228a.

[0087] The flip-flop block 224 outputs data to the slave multiplexer 226 and then to the output control block 228b. The enable flip-flop block 224a receives the enable signal tx_en and the clock signal clk and provides a control signal to control the output control block 228a. The data provided by the slave chip 102 is then transmitted to the main chip 100 through the connection pad portion of the connection pad matrix 220.

[0088] In order to perform appropriate timing control on the clock signal clk to respond to the main chip 100, another output control block 228b also receives the original clock signal clk and is controlled by the enable signal from the enable flip-flop 224a.

[0089] The data output from the slave interface 200S is then received by the FIFO block 204A in the master interface 200M. For the master interface 200M, the data rx_data is a response from the slave chip 102 relative to the instruction.

[0090] In an embodiment, there are a large number of slave chips 102 stacked above the main chip 100. Instructions from the main chip 100 are sent to all the slave chips 102. In this case, the instructions of the main chip 100 also include a slave identification code, which is used to select a slave chip 102 to execute the instructions from the main chip 100. The slave interface 200S also has the ability to distinguish the slave identification code. Each slave interface 200S has its own identification code. The slave interface 200S that matches the slave identification code will be enabled to respond to the instructions from the main chip 100 at the time slot allocated by the main instruction. Interference between the slave chips can be effectively avoided.

[0091] Figure 7 is a diagrammatic view schematically showing the circuit structure of the interface between the main chip and the slave chip according to a further embodiment of the present invention. Refer to Figure 7 for a further description of the connection between the slave interface 200S and the SRAM 120 in the example.

[0092] In the example, the instruction 300 may include an instruction, an address, write data, and a slave identification code. The data rx_data from the flip-flop block 222 of the slave interface 200S is output to the SRAM 120. However, the slave interface 200S may also include a logic circuit 130 and a fifth flip-flop block 132. The logic circuit 130 also receives the instruction (such as the data rx_data) output from the third flip-flop block 222 to determine the type signal of the instruction / read_data / write_data (CS / RD / WR) and also generates a preliminary enable signal sent to the fifth flip-flop block 132, and the fifth flip-flop block 132 outputs the enable signal to the enable flip-flop block 224a accordingly. The SRAM 120 receives the type signal of CS / RD / WR to respond to the instructions from the main chip 100. Once the slave chip 102 (such as the SRAM 120) finishes the instruction, it responds with the result (such as the data rd_data for reading the instruction) to the slave interface 200S as the input data tx_data of the slave interface 200S.

[0093] As further pointed out, in the structure of the present invention that includes an interface connected to multiple slave chips 102 (e.g., 16 slave chips), write instructions and read instructions can overlap and then be executed simultaneously. The size of the data bus can be 256 bits, with some reserved bits in addition. As Figure 5 shown, the connection pad matrix 208 and the connection pad matrix 220 have the number of connection pad portions that transmit data signals through multiple bond tiles.

[0094] Figure 8 is a drawing schematically showing a read cycle of the interface between the master chip and the slave chip further according to an embodiment of the present invention. Refer to Figure 8 , and a read instruction from the master chip 100 is used as an example for description.

[0095] The read instruction 250 of the instruction 300 from the core circuit of the master chip 100 is input to the flip - flop block 202 of the master interface 200M. A single clock clk_in is also input to the master interface 200M to control the flip - flop block 202 and the master multiplexer 206. The instruction is sent to the corresponding connection pad portion of the connection pad matrix 208. The connection pad matrix 208 is connected one - to - one to the connection pad matrix 220 of the slave interface 200S. Also as previously described, the instruction enters the SRAM 120 of the master chip 102 to read data at the address in the instruction 300. After the read operation in the SRAM 120, the read data rd_data is obtained and sent back to the circuit block 230 of the slave interface 200S. The logic circuit 130 and the flip - flop 132 determine the time slot so that the read data rd_data in response to the instruction 300 can be sent to the master interface 200M and output as data rx_data at the flip - flop block 210. The data rx_data in the example is the result requested by the master chip 100.

[0096] It is further pointed out that a single clock is used for the entire read operation. The data delay can be reliably adjusted to have a predictable constant.

[0097] To accelerate data transfer, a double - data - rate (DDR) mechanism can also be involved. In the example, the clock frequency can be 2.5 gigahertz. The DDR mechanism allows data to be transferred at a rate of 5 gigahertz, where both the rising edge and the falling edge of the clock pulse are provided as trigger edges. Figure 9 is a drawing schematically showing the circuit structure of the interface between the master chip and the slave chip based on the DDR method according to an embodiment of the present invention.

[0098] Refer to Figure 9, for an instruction 300 from the main chip 100, in the example, the data tx_data as the instruction 300 may contain 32-bit data. The instruction adapts the DDR mechanism and can divide the 32 bits into two groups of 16-bit data that are respectively input to the flip-flop block 202. The main multiplexer 206 also operates under the DDR mechanism. After the instruction 300 is transmitted to the slave chip 102, the two parts of the data enter the flip-flop block 222a and the flip-flop block 222b through two paths respectively. The flip-flop block 222a and the flip-flop block 222b correspond to Figure 6 the flip-flop block 222 in

[0099] . The clock clk also controls the flip-flop block 222a and the flip-flop block 222b.

[0100] Figure 10 is a diagrammatic view schematically showing the signal forms of various signals involved in the interface according to an embodiment of the present invention. Referring to Figure 9 and Figure 10 , the timing of the data signal relative to a single clock clk_in is shown.

[0101] The clock clk_in in the example is 2.5 gigahertz. Based on the DDR bus for transmitting data, the 32-bit data tx_data[31:0] is divided into two 16-bit data clusters, D0[15:0] and D0[31:16], at the connection pads. Each data cluster of 16 bits as presented by the shape can also be referred to as a data eye. As marked by the bar graph, the adjusted clocks from the DLLr 230a and the DLLf 230b have rising edges and falling edges at approximately the middle of a data eye.

[0102] It is possible to find the position in the timing of the rising edge and the falling edge relative to the data eye in the initial stage, and the position is basically located in the middle of the data eye to ensure that the data in the data cluster can be correctly sensed. Once the size of the data eye is shifted by environmental conditions (such as temperature or voltage changes), the position of the trigger edge is adjusted proportionally according to the change in the size of the data eye under monitoring. The trigger edge also causes the data to enter the slave interface 102 in two paths. The output clock clk_out has the same form as the input clock clk_in, but is slightly delayed due to the traveling path from the master interface 200M to the slave interface 200S. Subsequently, the data rx_data[31:0] marked by D0[31:0] at the clock CACd_clk is output by the slave interface. The delay 270 can be reliably set to 2 cycles plus the slight delay of the output clock clk_out.

[0103] Figure 11 FIG. is a schematic diagram showing a partial circuit of a slave interface having a clock tree mechanism according to an embodiment of the present invention. In order to supply clocks to multiple slave chips, a single input clock clk_in can use the clock tree to distribute the clocks one by one to the next slave interface.

[0104] Reference Figure 8 and Figure 11 , as an example, the circuit block 230 in the slave interface 200S also needs to receive the output clock clk for the SRAM 120, also called clk_out. Subsequently, the clock tree 400 mechanism branches a single clock clk_out 302 into multiple branches corresponding to multiple slave interfaces 200S respectively. Subsequently, as previously described, each slave interface 200S has the same operating mechanism. Here, the circuit block 230 in Figure 6 can be further modified using the clock tree 400 mechanism. Therefore, one master chip 100 can be efficiently and identically connected to multiple slave chips 102 based on 3D packaging technology.

[0105] Figure 12 FIG. is a schematic diagram showing the signal forms of various signals involved in the DDR-based interface according to an embodiment of the present invention. Reference Figure 12 , taking the read latency as an example for description. Based on the Figure 11 circuit structure in for operating multiple slave chips, the relevant signals in the timing relationship are described.

[0106] The clock signal clk_in refers to the original clock entering the main interface. The main chip uses the slave_identification (ID) signal DID of the slave chip to schedule the instructions PA and RD, and then decodes the instruction signals S_CMD and S_DID and sends them to the connection pads of the main interface. Here, in the example, the instruction RD indicates a read operation, and the instruction PA refers to the preamble information of which slave device should be ready to send data. The instruction s_did[3:0] in the example defines which slave device should send data and then take over the data bus to prepare to send data. The slave interface based on the clock tree and the identification code DID is used to obtain the clock and instructions to read data at the SRAM 120. In operation, the main chip must schedule the instruction PA when it changes from one DID to another. The tx_data from the slave chip K and the tx_data from the slave chip N have a one-cycle delay. However, the control mechanism with instructions and actions depends on the actual needs. The present invention need not be limited to the specific examples in operation. However, the interface provides the transfer of instructions and data between the master device and the slave device in a reliable and efficient manner.

[0107] In the example of the read operation, in the case where 2 or more turn-around cycles are required, the main chip also needs to send the instruction NOP. Therefore, multiple slave chips in the read operation require approximately 2 cycles, which is called the read latency. The read latency is reliable and constant for each slave chip.

[0108] Figure 13 FIG. is a diagram schematically showing the signal forms of various signals involved in the interface according to an embodiment of the present invention. Refer to Figure 13 , in the operation of multiple slave chips between input and output, the output of the selected slave chip needs to be controlled by the enable signal tx_en at the time slot, as shown in Figure 7 and Figure 8 . The output clock clk_out in the slave chip 200S is used to control the flip-flop block to receive the data tx_data and then output the data. For reference, the signal of the instruction s_cmd and the slave identification s_did in the main chip are also shown.

[0109] The enable signal tx_en can ensure the data from the selected slave chip at the time slot based on the clock tree mechanism to respond to the data without interfering with other slave chips. The enable signal tx_en in the embodiment starts a clock before the selected slave chip drives the input data tx_data.

[0110] In an embodiment, slave chip N and slave chip K (as two of them) are used to investigate read latency. After a signal under the conditions of s_cmd = PA and s_did = slave_ID, the enable signal tx_en starts to be driven at the read_latency clock clk. When s_cmd = (PA or RD) and s_did = slave_ID, the enable signal tx_en will be confirmed. As estimated, for each slave chip, the read latency is estimated to be about two cycles.

[0111] In other words, a single clock clk from the master chip 100 can be distributed in a stacked form to all slave chips. The slave ID is identified by the corresponding slave chip, and accordingly induces the enable signal tx_en to control the output at the connection pad portion of the connection pad matrix. The read latency of each slave chip can be controlled to be substantially constant. In addition, a delay locked loop is involved to ensure that the bit data of the data eye is correctly sensed.

[0112] Interface-based signals can be transmitted under reliable conditions. Subsequently, the interface can be fabricated according to 3D packaging technology. Thus, a 3D semiconductor device including the interface is formed in a quite compact structure.

[0113] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. Given the foregoing, the disclosure is intended to cover modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims

1. An interface for a semiconductor device, the semiconductor device comprising a master device and a plurality of slave devices, wherein the master device and the slave devices are stacked together through electrical connections, and the interface includes: A master interface built in the master device and comprising a master interface circuit having a master connection pad matrix; A slave interface built in each of the slave devices and comprising a slave interface circuit having a slave connection pad matrix for correspondingly connecting to the master connection pad matrix; And Clock wiring for transmitting a clock signal through the master interface and the slave interface, wherein the master device transmits instructions and slave identification codes to all the slave interfaces through the master interface; wherein the slave device corresponding to the slave identification code responds with the result of executing the instruction to the master device through the slave interface and the master interface.

2. The interface for a semiconductor device according to claim 1, wherein the instructions from the master device are transmitted based on a double data rate mechanism and a master multiplexer combines the instructions, and wherein a flip-flop block in the slave interface circuit converts the instructions from the master device from the double data rate form into an instruction form used internally in the slave device.

3. The interface for a semiconductor device according to claim 1, wherein the master device comprises a processor and the slave devices comprise memory devices.

4. The interface for a semiconductor device according to claim 1, wherein the master interface and the slave interface are connected together using a three-dimensional stack at least through the master connection pad matrix and the slave connection pad matrix, and wherein a plurality of through-silicon vias are included for connecting the master connection pad matrix and the slave connection pad matrix.

5. The interface for a semiconductor device according to claim 1, wherein the master interface circuit includes: A master transmission path comprising a first flip-flop block and a master multiplexer connected in series, wherein the first flip-flop block receives the instruction and the master multiplexer outputs the instruction to the slave device through a first part of the master connection pad matrix; A master reception path comprising a first-in-first-out block and a second flip-flop block connected in series, wherein the first-in-first-out block is connected to a second part of the master connection pad matrix to receive the result from the slave device and the second flip-flop block outputs the result to the master device; And A first part of clock wiring connected to a third part of the master connection pad matrix to receive the clock signal and transmit the clock signal to the slave interface, wherein the clock signal in the master interface for control is also provided to the first flip-flop block, the second flip-flop block, and the master multiplexer.

6. The interface for a semiconductor device according to claim 5, wherein the slave interface circuit in each slave device includes: A third flip-flop block connected to a first part of the slave connection pad matrix to transmit the instruction to the slave device; A circuit block comprising: A fourth flip-flop block for receiving the result from the slave device; A slave multiplexer receiving the result from the fourth flip-flop block; An output control block, connected between the slave multiplexer and a second part of the slave connection pad matrix to transfer the result from the fourth flip-flop block to a master device interface controlled by an enable signal; and An enable flip-flop block, configured to receive the enable signal and control the output control block; and A second part of clock wiring, connected to a third part of the slave connection pad matrix to transfer the clock signal to the slave device, wherein the clock signal in each slave interface for control is also provided to the third flip-flop block, the fourth flip-flop block, the slave multiplexer, the enable flip-flop block, and the output control block.

7. The interface for a semiconductor device according to claim 6, wherein the clock signal in each slave interface is received from a branch of a slave clock tree, and the clock tree transfers the clock signal as a single signal used in the master device and the slave device.

8. The interface for a semiconductor device according to claim 6, wherein the slave interface further comprises: Logic circuitry; and A fifth flip-flop block, wherein the logic circuitry also receives the instruction output from the third flip-flop block to determine a signal sent to the fifth flip-flop block, and the fifth flip-flop block outputs the enable signal to the enable flip-flop block accordingly.

9. The interface for a semiconductor device according to claim 6, wherein the instruction from the master device is folded into two instruction parts as two data eyes, and the first flip-flop block in the master interface circuit comprises a pair of flip-flop units to respectively receive the two instruction parts, and the two instruction parts are combined by the master multiplexer using a double data rate structure.

10. The interface for a semiconductor device according to claim 9, wherein the slave interface circuit further comprises a first delay locked loop, a second delay locked loop having an inverter, and a delay control unit which respectively receive the clock signal and output a first signal, a second signal, and a third signal, wherein the third flip-flop block comprises: A first path, having three flip-flop units connected in series and respectively receiving the first signal, the second signal, and the third signal; and A second path, having two flip-flop units connected in series and respectively receiving the second signal and the third signal, wherein the first signal and the second signal provide trigger edges to the correspondingly connected flip-flop units, wherein the third signal triggers the timing of the correspondingly connected flip-flop units to output the two instruction parts of the instruction to the slave device.

11. The interface for a semiconductor device according to claim 10, wherein the first delay locked loop and the second delay locked loop adjust the timing of the rising edge and the falling edge to be at optimized time points relative to the data eye of the instruction.

12. An interface method for a semiconductor device, the semiconductor device comprising a master device and a plurality of slave devices, wherein the master device and the slave devices are stacked together through electrical connections, and the interface method comprises: Construct a master interface in the master device, the master interface including a master interface circuit having a master connection pad matrix; Construct a slave interface in each of the slave devices, the slave interface including a slave interface circuit having a slave connection pad matrix for correspondingly connecting to the master connection pad matrix; And Construct a clock wiring to transmit a clock signal through the master interface and the slave interface, wherein the master device transmits instructions and slave identification codes to all the slave interfaces through the master interface; wherein one of the slave devices corresponding to the slave identification code executes the instruction and responds with a result to the master device through the slave interface and the master interface.

13. The interface method for a semiconductor device according to claim 12, wherein the instructions from the master device are transmitted based on a double data rate mechanism and a master multiplexer combines the instructions, and wherein a flip-flop block in the slave interface circuit converts the instructions from the master device from the double data rate form into an instruction form used internally in the slave device.

14. The interface method for a semiconductor device according to claim 12, wherein the constructed master device includes a processor and the slave device includes a memory device.

15. The interface method for a semiconductor device according to claim 12, wherein the master interface and the slave interface are connected together at least through the master connection pad matrix and the slave connection pad matrix using a three-dimensional stack, wherein a plurality of through-silicon vias are included for connecting the master connection pad matrix and the slave connection pad matrix.

16. The interface method for a semiconductor device according to claim 12, wherein the constructed master interface circuit includes: Construct a master transmission path, the master transmission path including a first flip-flop block and a master multiplexer connected in series, wherein the first flip-flop block receives the instruction and the master multiplexer outputs the instruction to the slave device through a first part of the master connection pad matrix; Construct a master reception path, the master reception path including a first-in first-out block and a second flip-flop block connected in series, wherein the first-in first-out block is connected to a second part of the master connection pad matrix to receive the result from the slave device and the second flip-flop block outputs the result to the master device; And Construct a first part of the clock wiring, the first part of the clock wiring being connected to a third part of the master connection pad matrix to receive the clock signal and transmit the clock signal to the slave interface, wherein the clock signal in the master interface for control is also provided to the first flip-flop block, the second flip-flop block, and the master multiplexer.

17. The interface method for a semiconductor device according to claim 16, wherein the slave interface circuit constructed in each slave device includes: Construct a third flip-flop block, the third flip-flop block being connected to a first part of the slave connection pad matrix to transmit the instruction to the slave device; Construct a circuit block, the circuit block including: A fourth flip-flop block for receiving the result from the slave device; A slave multiplexer receiving the result from the fourth flip-flop block; An output control block, connected between the slave multiplexer and the second part of the slave connection pad matrix to transfer the result from the fourth flip-flop block to the master device interface controlled by an enable signal; and An enable flip-flop block, configured to receive the enable signal and control the output control block; and Construct a second part of the clock wiring, which is connected to the third part of the slave connection pad matrix to transfer the clock signal to the slave device, wherein the clock signal in each slave interface for control is also provided to the third flip-flop block, the fourth flip-flop block, the slave multiplexer, the enable flip-flop block, and the output control block.

18. The interface method for a semiconductor device according to claim 17, wherein the clock signal in each slave interface is received from a branch of the slave clock tree, and the clock tree transfers the clock signal as a single signal used in the master device and the slave device.

19. The interface method for a semiconductor device according to claim 17, wherein further constructing the slave interface includes: Constructing a logic circuit; and Constructing a fifth flip-flop block, wherein the logic circuit also receives the instruction output from the third flip-flop block to determine the signal sent to the fifth flip-flop block, and the fifth flip-flop block outputs the enable signal to the enable flip-flop block accordingly.

20. The interface method for a semiconductor device according to claim 17, wherein the instruction from the master device is folded into two instruction parts as two data eyes, and the first flip-flop block in the master interface circuit includes a pair of flip-flop units to receive the two instruction parts respectively, and the two instruction parts are combined by the master multiplexer using a double data rate structure.

21. The interface method for a semiconductor device according to claim 20, wherein the slave interface circuit further includes a first delay locked loop, a second delay locked loop with an inverter, and a delay control unit, which receive the clock signal respectively and output a first signal, a second signal, and a third signal, wherein the constructed third flip-flop block includes: Constructing a first path, which has three flip-flop units connected in series and receives the first signal, the second signal, and the third signal respectively; and Constructing a second path, which has two flip-flop units connected in series and receives the second signal and the third signal respectively, wherein the first signal and the second signal provide trigger edges to the corresponding connected flip-flop units, wherein the third signal triggers the timing of the corresponding connected flip-flop units to output the two instruction parts of the instruction to the slave device.

22. The interface method for a semiconductor device according to claim 21, wherein the first delay locked loop and the second delay locked loop adjust the timing of the rising edge and the falling edge to be at optimized time points relative to the data eye of the instruction.

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