Single-well transistor and capacitor non-volatile memory device and integration scheme

Abstract

The present disclosure relates to single-trap transistor and capacitor non-volatile memory devices and integration schemes. A non-volatile memory device is provided. The non-volatile memory device includes an active region surrounded by an isolation structure. A floating gate can be disposed over the active region, the floating gate having a first end and a second end located over the isolation structure. A first doped region can be provided in the active region adjacent a first side of the floating gate, and a second doped region can be provided in the active region adjacent a second side of the floating gate. A first capacitor can be provided over the floating gate, whereby a first electrode of the first capacitor is electrically coupled to the floating gate. A second capacitor can be provided, whereby a first electrode of the second capacitor is located over the isolation structure and adjacent the floating gate.

Description

Technical Field

[0001] The disclosed embodiments generally relate to non-volatile memory devices, and more specifically, to non-volatile memory devices having high density, compact size and improved reliability. Background Technology

[0002] Even when power is off, non-volatile memory devices retain the stored data. Examples of non-volatile memory devices include electrically erasable programmable read-only memory (EEPROM) and flash memory EEPROM. In a typical flash memory architecture, a floating gate can be used to store charge. The floating gate can be disposed on an active region such as a p-well. A source region can be formed in the p-well adjacent to a first side of the floating gate, and a drain region can be formed in the p-well adjacent to a second side of the floating gate. An n-well capacitor adjacent to the floating gate can be used to bias the floating gate. The n-well capacitor can include a polysilicon layer on top of the n-well and a highly doped n+ region serving as an input terminal. An isolation structure can separate the n-well from the adjacent p-well.

[0003] Programming can be performed via hot electron injection. For example, during programming, a high voltage of 9V or more can be applied to the n-well capacitor to bias the floating gate and drain regions. A moderate voltage, such as 4V, can be applied to the source region, and the substrate terminals of the memory device can be grounded. A strong vertical orientation electric field can be generated across the channel region between the source and drain, resulting in hot electron injection into the edge portion of the floating gate near the drain. Erasing can be performed via hot hole injection. For example, during erasing, a high voltage of 9V or more can be applied to the drain. The n-well capacitor, source, and substrate terminals can be grounded. Electron-hole pairs can be generated in the drain region via band-to-band tunneling (BTB). The generated holes can be accelerated toward the channel region between the source and drain by a lateral electric field, and some of the holes can acquire high energy. Hot holes can be injected into the floating gate and recombine with electrons stored in the floating gate.

[0004] High programming and erase voltages can lead to increased stress on the dielectric layer between the floating gate and the channel region, thus reducing reliability. The erase mechanism is inefficient because negative voltage cannot be applied to the n-well capacitor. Negative voltage can induce unwanted positive bias currents between the n-well capacitor and the adjacent p-well. The n-well capacitor results in a large lateral dimension of the memory device, thus hindering further scaling. Therefore, overcoming these challenges is urgently needed. Summary of the Invention

[0005] In this disclosure, a non-volatile memory device is provided. The non-volatile memory device includes an active region surrounded by an isolation structure. A floating gate may be disposed over the active region, the floating gate having a first end and a second end located over the isolation structure. A first doped region may be disposed in the active region adjacent to a first side of the floating gate, and a second doped region may be disposed in the active region adjacent to a second side of the floating gate. A first capacitor may be disposed over the floating gate, whereby a first electrode of the first capacitor is electrically coupled to the floating gate.

[0006] In another aspect of this disclosure, a non-volatile memory device array is provided. The non-volatile memory device array includes a first active region, a second active region, and an isolation structure surrounding each active region, wherein a portion of the isolation structure is located between the first active region and the second active region. A first floating gate array is located over the first active region, and a second floating gate array is located over the second active region, wherein a first end and a second end of each floating gate are located over the isolation structure. A first doped region is located in each active region and adjacent to a first side of each floating gate, and a second doped region is located in each active region and adjacent to a second side of each floating gate. A first capacitor is located over each floating gate, wherein a first electrode of the first capacitor is electrically coupled to each floating gate.

[0007] In another aspect of this disclosure, a method of manufacturing a non-volatile memory device is provided. The method includes providing an active region surrounded by an isolation structure. A floating gate may be provided over the active region, whereby a first end and a second end of the floating gate are located over the isolation structure. A first doped region may be provided in the active region adjacent to a first side of the floating gate, and a second doped region may be provided in the active region adjacent to a second side of the floating gate. A first capacitor may be provided over the floating gate, whereby a first electrode of the first capacitor is electrically coupled to the floating gate.

[0008] Many advantages can be obtained through the embodiments described below. These embodiments provide compact non-volatile memory devices with high coupling ratios, high density, and improved reliability. Attached Figure Description

[0009] The disclosed embodiments will be better understood by reading the following detailed description in conjunction with the accompanying drawings:

[0010] Figure 1A This is a top view of a non-volatile memory device array according to an embodiment of the present disclosure.

[0011] Figure 1B According to embodiments of this disclosure Figure 1AA cross-sectional view of a non-volatile memory device array taken by section line B-B'.

[0012] Figure 1C According to embodiments of this disclosure Figure 1A A simplified schematic diagram of a non-volatile memory device taken by the cross-section line C-C'.

[0013] Figure 1D This is a top view of a non-volatile memory device array according to an embodiment of the present disclosure, showing a portion of the active region located below the floating gate and the area of ​​the first capacitor.

[0014] Figure 2A This is a top view of a non-volatile memory device array according to another embodiment of the present disclosure.

[0015] Figure 2B According to embodiments of this disclosure Figure 2A A cross-sectional view of a non-volatile memory device array taken by section line D-D'.

[0016] Figures 3 to 6 Some embodiments according to this disclosure are shown. Figure 1A The manufacturing process flow of the array of non-volatile memory devices shown.

[0017] Figures 7 to 10 Other embodiments according to this disclosure are shown. Figure 2A The manufacturing process flow of the array of non-volatile memory devices shown.

[0018] For simplicity and clarity, the accompanying drawings illustrate general construction methods, and specific descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the discussion of embodiments of the described devices. Furthermore, elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be enlarged relative to other elements to aid in understanding embodiments of the devices. The same reference numerals in different drawings denote the same elements, and similar reference numerals may, but do not necessarily, denote similar elements. Detailed Implementation

[0019] The following detailed description is exemplary in nature and is not intended to limit the devices or their applications and uses. Furthermore, it is not bound by prior background information on these devices or any theory presented in the following detailed description.

[0020] Figure 1A This is a top view of a non-volatile memory device array 100 according to an embodiment of the present disclosure. Reference Figure 1AThe non-volatile memory device array 100 includes a first active region 110a and a second active region 110b, and an isolation structure 118 surrounding each active region 110a and 110b. The isolation structure 118 is shown as a dashed outline. In an embodiment, the isolation structure 118 may be shallow trench isolation (STI). A portion of the isolation structure 118 is located between the first active region 110a and the second active region 110b. The isolation structure 118 and the active regions 110a and 110b may be formed in a semiconductor substrate 180. The first active region 110a and the second active region 110b may be collectively referred to as active region 110.

[0021] A first floating gate array 112a may be provided over a first active region 110a, and a second floating gate array 112b may be provided over a second active region 110b. The first floating gate array 112a and the second floating gate array 112b may be collectively referred to as floating gates 112. Each floating gate 112 may have a first end 170a and a second end 170b opposite to the first end. The first end 170a and the second end 170b of each floating gate 112 may be arranged over an isolation structure 118. A first doped region 106 may be provided in each active region 110a and 110b adjacent to the first side of each floating gate 112, and a second doped region 108 may be provided in each active region 110a and 110b adjacent to the second side of each floating gate 112 opposite to the first side. For example, the first doped region 106 may be the source of a non-volatile memory device array 100, and the second doped region 108 may be its drain. Contacts 18 may be provided over the source 106 and drain 108 for connection to external input terminals. The term "floating gate" may refer to a gate electrode that is electrically isolated from the input terminals and can be capacitively coupled to the input terminals. During device operation, no DC current flows from the input terminals to the floating gate. A first capacitor 168 may be provided over each floating gate 112 to provide a compact design for the non-volatile memory array 100. Contacts 150 may electrically couple the first capacitor 168 to external input terminals. The first capacitor 168 has an area at least equal to or greater than the area of ​​each floating gate 112. In one embodiment, the first capacitor 168 may be a metal-insulator-metal (MIM) capacitor. In another embodiment, the first capacitor 168 may be a metal-oxide-semiconductor (MOM) capacitor. Although not shown, the non-volatile memory device array 100 may include substrate contacts.

[0022] Each active region 110a and 110b can be a p-well. Each floating gate 112 above each active region 110a and 110b, and the source 106 and drain 108 adjacent to a first side and a second side of each floating gate 112, respectively, can operate as an independent non-volatile memory transistor 188. The advantage of the non-volatile memory device array 100 is its compact design because a single p-well is used for each independent non-volatile memory transistor 188. The source 106 and drain 108 can be arranged alternately along each active region 110a and 110b, wherein each floating gate 112 shares a source 106 or a drain 108 with an adjacent floating gate 112. In an embodiment, the source 106 and drain 108 can be structurally identical. For example, in an embodiment, the source 106 and drain 108 can have the same doped region. In another embodiment, the source 106 and drain 108 can be structurally different. For example, the drain 108 can have a deeper doped region compared to the source 106.

[0023] Figure 1B According to embodiments of this disclosure Figure 1A A cross-sectional view of the non-volatile memory device array 100 taken along section line B-B'. (Reference) Figure 1B A first floating gate 112a and a second floating gate 112b are respectively disposed on the first active region 110a and the second active region 110b. First ends 170a and second ends 170b of the first floating gate 112a and the second floating gate 112b are disposed on the isolation structure 118. The advantage of placing the first ends 170a and the second ends 170b of the first floating gate 112a and the second floating gate 112b on the isolation structure 118 is that it allows for tolerances in the alignment and patterning of the first floating gate 112a and the second floating gate 112b. For simplicity, the first capacitor 168 is not shown in this cross-sectional view.

[0024] Figure 1C According to embodiments of this disclosure Figure 1A A simplified schematic diagram of the non-volatile memory device 100, taken along section line C-C'. (Reference) Figure 1C A first floating gate 112a may be provided above the first active region 110a. A dielectric layer 102 may be provided between the first floating gate 112a and the first active region 110a. A source 106 may be formed in the first active region 110a adjacent to a first side of the first floating gate 112a. A drain 108 may be formed in the first active region 110a adjacent to a second side of the first floating gate 112a opposite to the source 106. An isolation structure 118 may be formed in the first active region 110a adjacent to the source 106 or the drain 108. A substrate contact 116 may be formed on the upper surface of the first active region 110a adjacent to the isolation structure 118. For simplicity, Figure 1A Substrate contact 116 is not shown. A first capacitor 168 may be provided over the first floating gate 112a. Line 120 indicates the electrical coupling between the first electrode 126 of the first capacitor 168 and the first floating gate 112a. A dielectric layer 132 may be provided over the first electrode 126. A second electrode 128 may be provided over the dielectric layer 132. Line 122 indicates the electrical coupling between the second electrode 128 of the first capacitor 168 and an external input terminal.

[0025] Figure 1D This is a top view of a non-volatile memory device array 100 according to an embodiment of the present disclosure, showing a portion 136 of the active region 110 located below the floating gate 112 and the area 138 of the first capacitor 168. Floating gate capacitance C 112 The area A of the portion 136 of the active region 110 below the floating gate 112 is equal to the area of ​​the portion 136 below the floating gate 112. 136 Multiplied by the dielectric constant ε of the dielectric layer 102 located between the floating gate 112 and the active region 110 102 With the thickness T of dielectric layer 102 102 The ratio. C 112 =A 136 ×ε 102 / T 102 The capacitance C of the first capacitor 168 The area of ​​the first capacitor (168) is equal to 138, A. 138 Multiplied by the dielectric constant ε of the dielectric layer 132 of the first capacitor 168 132 With the thickness T of dielectric layer 132 132 The ratio. C 168 =A 138 ×ε 132 / T 132 The coupling ratio of the non-volatile memory device array 100 is equal to the capacitance C of the first capacitor. 168 Divide by the capacitance C of the first capacitor 168 With floating gate capacitor C 112 The sum. Therefore, the coupling ratio of the non-volatile memory device array 100 = C 168 / (C 168 +C 112 The term "coupling ratio" indicates the voltage transfer capability from the first capacitor 168 to the floating gate 112. This can be achieved by increasing the capacitance C of the first capacitor. 168 Or by reducing the floating gate capacitance C 112 This can increase the coupling ratio of the non-volatile memory device array 100. For example, this can be achieved by increasing the area 138A of the first capacitor 168. 138 Or the dielectric constant ε of the dielectric layer 132 of the first capacitor 168 132This increases the coupling ratio of the non-volatile memory device array 100. For example, the area of ​​the first capacitor 168 is 138 A. 138 The area A of the portion 136 of the active region 110 below the floating gate 112 is larger than that of the floating gate 112. 136 This provides a high coupling ratio.

[0026] Figure 1A A set of exemplary bias conditions for an embodiment of the non-volatile memory device array 100 shown are listed in Table 1. Programming can be performed via hot electron injection. For example, during programming, a suitable voltage of approximately 3 to 8 V can be applied to the first capacitor 168 and the drain 108 of the selected non-volatile memory transistor 188. A suitable voltage of approximately 3 V can be applied to the source 106 of the selected non-volatile memory transistor 188, and the substrate terminal can be grounded. An inhibitor voltage of approximately 4 to 8 V can be applied to the source 106 of the unselected memory transistor 188 to prevent electron injection into the floating gate 112 of the unselected non-volatile memory transistor 188. The first capacitor 168, the drain 108 of the unselected non-volatile memory transistor 188, and the substrate terminal can be grounded. A strong vertical orientation electric field can be generated across the channel region between the source 106 and the drain 108 of the selected nonvolatile memory transistor 188, thereby causing hot electrons to be injected into the edge portion of the floating gate 112 near the drain 108.

[0027] Table 1

[0028]

[0029] Erasure can be performed via hot hole injection. For example, during erasure, a negative voltage of approximately -2.5V can be applied to the first capacitor 168 to bias the floating gate 112. A suitable voltage of approximately 6 to 8V can be applied to the drain 108. The source 106 and the substrate terminal 116 can be grounded. Hot holes can be generated in the channel region and injected into the floating gate 112 to recombine with electrons stored in the floating gate 112. The memory device array 100 can be erased simultaneously.

[0030] During a read operation, a positive bias of approximately 2.5V can be applied to the first capacitor 168, and a voltage of approximately 1V can be applied to the drain 108 of the selected non-volatile memory transistor 188. The source 106 and substrate terminal of the selected non-volatile memory transistor 188 can be grounded. Depending on the threshold voltage of the selected non-volatile memory transistor 188, a current can be detected at the drain 108. For example, the threshold voltage of the selected non-volatile memory transistor 188 is lower after erasure, and a current can be detected at the drain 108. A programming operation may result in a higher threshold voltage of the selected non-volatile memory transistor 188, and a small or negligible current may be detected at the drain 108. The first capacitor 168, the source 106 and drain 108 of the unselected non-volatile memory transistor 188, and the substrate terminal are grounded.

[0031] Figures 1A to 1D The illustrated embodiments can be modified to form alternative embodiments within the scope of this disclosure. For example, Figure 2A This is a top view of a non-volatile memory device array 200 according to another embodiment of the present disclosure. Figures 1A to 1D Using the same reference number in Figure 2A The same character is also used to indicate the same feature. (and) Figure 1A and Figure 1D The non-volatile memory device array 100 shown is the opposite. Figure 2A The illustrated non-volatile memory device array 200 includes a first electrode 208 of a second capacitor adjacent to a first floating gate 112a and a second floating gate 112b. The first floating gate 112a is disposed over a first active region 110a and the second floating gate 112b is disposed over a second active region 110b. The first electrode 208 of the second capacitor may be disposed adjacent to the first floating gate 112a and the second floating gate 112b on an isolation structure 218 and located between the first active region 110a and the second active region 110b. A contact 228 located on the first electrode 208 of the second capacitor may be electrically coupled to an input terminal.

[0032] refer to Figure 2AThe second electrode of the second capacitor may include a first floating gate 112a and a second floating gate 112b. A first capacitor 168 may be disposed above either the first floating gate 112a or the second floating gate 112b. The area of ​​the first capacitor 168 may be larger than the area of ​​either the first floating gate 112a or the second floating gate 112b. The first capacitor 168 may partially overlap with the first electrode 208 of the second capacitor. The first electrode 208 of the second capacitor may be disposed between an end of the first floating gate 112a (e.g., the second end 170b) and an end of the second floating gate 112b (e.g., the first end 170a), thereby not resulting in an increase in the lateral dimension of the non-volatile memory device array 200. The second capacitor may allow independent control of the first floating gate 112a and the second floating gate 112b and result in an increased coupling ratio, thereby further reducing voltage requirements for more efficient programming and erasing.

[0033] Figure 2B According to embodiments of this disclosure Figure 2A A cross-sectional view of the non-volatile memory device array 200 taken along section line D-D'. (Reference) Figure 2B A spacer dielectric 210 may be formed between the first electrode 208 of the second capacitor and the adjacent first floating gate 112a or second floating gate 112b. The spacer dielectric 210 may be formed on the sidewall of the first electrode 208 of the second capacitor and on the sidewall of the adjacent first floating gate 112a or second floating gate 112b. For simplicity, the first capacitor 168 located on the first floating gate 112a or second floating gate 112b is not shown in this cross-sectional view.

[0034] Figures 3 to 6 Some embodiments according to this disclosure are shown. Figure 1A The manufacturing process flow of the non-volatile memory device array 100 shown. Figure 3 According to embodiments of this disclosure Figure 1A The section cut along line A-A' is a cross-sectional view of the completed non-volatile memory device array 100. (Reference) Figure 3A semiconductor substrate 180 may be provided. An isolation structure 118 may be formed in the semiconductor substrate 180. The formation of the isolation structure 118 may include forming openings in the semiconductor substrate 180 by conventional photoresist processes followed by wet or dry etching processes. A photoresist layer may be deposited on the semiconductor substrate 180 and patterned to form a suitable photoresist pattern. A wet or dry etching process may be used to remove a portion of the semiconductor substrate 180 not covered by the photoresist pattern, thereby forming openings in the semiconductor substrate 180. The photoresist layer may then be removed. A suitable insulating material layer, such as silicon dioxide, may be deposited in the openings in the semiconductor substrate 180 and on the top surface of the semiconductor substrate 180. A suitable planarization process (e.g., chemical mechanical planarization or CMP) may be used to remove the silicon dioxide layer from the top surface of the semiconductor substrate 180, leaving a silicon dioxide layer located in the openings of the semiconductor substrate, thereby forming the isolation structure 118. The semiconductor substrate 180 adjacent to the isolation structure 118 may be doped with a suitable p-type dopant, such as boron (B), at a doping concentration of approximately 10. 15 Up to 10 18 cm -3 A p-well is formed to provide a first active region 110a and a second active region 110b. An isolation structure 118 surrounds the first active region 110a and the second active region 110b, thereby defining the areas of the first active region 110a and the second active region 110b.

[0035] Figure 4 According to embodiments of this disclosure Figure 1A The cross-sectional view taken along section line A-A' shows the portion of the non-volatile memory device array 100 completed after the formation of the dielectric layer 102, the first floating gate 112a, the second floating gate 112b, and the spacer dielectric 210. (See reference...) Figure 4The formation of the dielectric layer 102 may include depositing a suitable dielectric material layer, such as silicon dioxide (SiO2) or hafnium dioxide (HfO2), over the first active region 110a, over the second active region 110b, and over the isolation structure 118. A polysilicon layer may be deposited over the silicon dioxide layer. The polysilicon layer may be doped with phosphorus (P), arsenic (As), or antimony (Sb) to form n+ type doped polysilicon. The doped polysilicon and silicon dioxide layers may be patterned by conventional photoresist processes and wet or dry etching processes to form a first floating gate 112a over the first active region 110a, a second floating gate 112b over the second active region 110b, and a dielectric layer 102 between the first floating gate 112a and the first active region 110a, and between the second floating gate 112b and the second active region 110b. Although not shown, the ends 170a or 170b of the first floating gate 112a and the second floating gate 112b are formed on the isolation structure 118. A spacer dielectric 210 may be formed on the sidewalls of the first floating gate 112a and the second floating gate 112b. The formation of the spacer dielectric 210 may include depositing a suitable dielectric material layer, such as silicon dioxide (SiO2) or silicon nitride (Si3N4), on the sidewalls and top surface of the first floating gate 112a and the second floating gate 112b, and on the top surface of the first active region 110a and the second active region 110b. A suitable process, such as anisotropic etching, can be used to remove a portion of the silicon dioxide layer from the top surfaces of the first floating gate 112a and the second floating gate 112b, as well as the top surfaces of the first active region 110a and the second active region 110b, leaving another portion of the silicon dioxide layer located above the sidewalls of the first floating gate 112a and the second floating gate 112b, thereby forming the spacer dielectric 210. The term "anisotropic etching" can refer to an etching process that is inherently oriented.

[0036] Figure 5 According to embodiments of this disclosure Figure 1A The cross-sectional view of the non-volatile memory device array 100, taken along section line A-A', shows the portion after the formation of the source region 106, drain region 108, and substrate contact 116. (See reference...) Figure 5The source region 106 and drain region 108 can be formed by doping the upper surfaces of the active regions 110a and 110b with a suitable dopant such as phosphorus (P), arsenic (As), or antimony (Sb) to form n+ doped regions adjacent to a first side of the first floating gate 112a and the second floating gate 112b, and adjacent to a second side of the first floating gate 112a and the second floating gate 112b opposite to the first side, respectively. The substrate contact 116 can be formed by doping the upper surface of the first active region 110a or the second active region 110b with a suitable dopant such as boron (B) or boron fluoride (BF2) to form a p+ doped region adjacent to the isolation structure 118.

[0037] Figure 6 According to embodiments of this disclosure Figure 1A The cross-sectional view of the non-volatile memory device array 100 after the formation of the first capacitor 168 is taken along section line A-A'. (See reference) Figure 6 A silicide layer 152 can be formed over the source 106, drain 108, and the first floating gate 112a and the second floating gate 112b. In another embodiment, the source 106 and drain 108 can be partially silicided. The formation of the silicide layer 152 is well known in the art and will not be described in further detail. An interlayer dielectric (ILD) layer 156a can be formed over the first active region 110a, the second active region 110b, the first floating gate 112a, the second floating gate 112b, and the isolation structure 118. The formation of the interlayer dielectric layer 156a may include depositing a suitable insulating dielectric material layer, such as silicon dioxide (SiO2), by a suitable deposition process such as atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any other suitable deposition process. Contact pillar 138 may be formed in the interlayer dielectric layer 156a and located above the first floating gate 112a and the second floating gate 112b. Formation of contact pillar 138 may include forming via openings in the interlayer dielectric layer 156a using a conventional photoresist process followed by a wet or dry etching process. A suitable conductive material layer, such as tungsten (W) or copper (Cu), may be deposited in the via openings and on the top surface of the interlayer dielectric layer 156a using ALD, PVD, CVD, or any other suitable deposition process. A suitable planarization process, such as chemical mechanical planarization (CMP), may be used to remove a portion of the tungsten layer from the top surface of the interlayer dielectric layer 156a, leaving another portion of the tungsten layer in the via openings, thereby forming contact pillar 138.

[0038] A first capacitor 168 may be formed over contact pillars 138 and interlayer dielectric 156a. The formation of the first capacitor 168 may include depositing a suitable conductive material layer, such as tantalum (Ta) or titanium nitride (TiN), over the interlayer dielectric layer 156a and contact pillars 138 by ALD, CVD, PVD, or any other suitable deposition process. A suitable insulating dielectric material layer, such as silicon nitride (Si3N4), hafnium oxide (HfO2), or aluminum oxide (Al2O3), may be deposited over the first tantalum layer by ALD, CVD, PVD, or any other suitable deposition process. A second suitable conductive material layer, such as tantalum (Ta) or titanium nitride (TiN), may be deposited over the silicon nitride layer by ALD, CVD, PVD, or any other suitable deposition process. The first tantalum layer, silicon nitride layer, and second tantalum layer may be patterned by conventional photoresist processes and subsequent wet or dry etching to form the first electrode 126, dielectric layer 132, and second electrode 128 of the first capacitor 168, respectively. An interlayer dielectric layer 156b may be formed over the first capacitor 168 and the interlayer dielectric layer 156a, and a contact post 150 may be formed over the second electrode 128 of the first capacitor 168 for connection to an external input terminal. Although not shown, contact posts may be formed over the source 106, drain 108, or substrate contact 116 to provide electrical coupling to an external input terminal.

[0039] Figures 7 to 10 Other embodiments according to this disclosure are shown. Figure 2A The manufacturing process flow of the non-volatile memory device array 200 shown. Figure 7 According to embodiments of this disclosure Figure 2A A cross-sectional view of the completed non-volatile memory device array 200, taken along section line E-E'. (Reference) Figure 7 A semiconductor substrate 180 can be provided. An isolation structure 218 can be formed in the semiconductor substrate 180. A first active region 110a and a second active region 110b can be formed adjacent to the isolation structure 218. The formation of the isolation structure 218, the first active region 110a, and the second active region 110b are respectively similar to Figure 3 The isolation structure 118, the first active region 110a, and the second active region 110b are shown.

[0040] Figure 8 According to embodiments of this disclosure Figure 2AThe cross-sectional view taken along line E-E' shows the partially completed non-volatile memory device array 200 after the formation of dielectric layer 102, first floating gate 112a, second floating gate 112b, first electrode 208 of the second capacitor, and spacer dielectric 210. The formation of dielectric layer 102 may include depositing a suitable dielectric material layer, such as silicon dioxide, over the first active region 110a, the second active region 110b, and over the isolation structure 218. A polysilicon layer may be deposited over the silicon dioxide layer and then doped with a suitable n-type dopant (e.g., phosphorus). The doped polysilicon layer and silicon dioxide layer may be patterned using conventional photoresist processes and subsequent wet and dry etching to form the first floating gate 112a, the second floating gate 112b, the first electrode 208 of the first capacitor located between the first floating gate 112a and the second floating gate 112b, and dielectric layer 102, respectively. The formation of the first floating gate 112a, the second floating gate 112b, and the first electrode 208 of the second capacitor located between the first floating gate 112a and the second floating gate 112b can be accomplished by the same process and by the same doped polysilicon layer.

[0041] The spacer dielectric 210 can be formed on the sidewalls of the first floating gate 112a, the second floating gate 112b, and the first electrode 208 of the second capacitor. Forming the spacer dielectric layer 210 may include depositing a suitable dielectric layer, such as silicon dioxide, on the first floating gate 112a, the first electrode 208 of the second capacitor, the second floating gate 112b, the first active region 110a, and the second active region 110b. An anisotropic etching process can be used to remove the silicon dioxide layer from the top surfaces of the first floating gate 112a, the first electrode 208 of the second capacitor, the second floating gate 112b, the first active region 110a, and the second active region 110b, leaving a silicon dioxide layer on the sidewalls of the first floating gate 112a, the first electrode 208 of the second capacitor, and the second floating gate 112b, thereby forming the spacer dielectric 210.

[0042] Figure 9 According to embodiments of this disclosure Figure 2AThe image shows a cross-sectional view of the non-volatile memory device array 200 partially completed after the formation of source 106 and substrate contact 116, taken along section line E-E'. The formation of source 106 may include doping the upper surfaces of the first active region 110a and the second active region 110b adjacent to the side regions of the first floating gate 112a and the second floating gate 112b with a suitable dopant (e.g., phosphorus) to form an n+ region. Although not shown, drain 108 may be formed adjacent to one side of the first floating gate 112a and the opposite side of the second floating gate 112b to source 106. The formation of substrate contact 116 is similar to... Figure 6 The formation of substrate contact 116 is shown.

[0043] Figure 10 According to embodiments of this disclosure Figure 2A The image shows a cross-sectional view of the non-volatile memory device array 200 taken along section line E-E' after the formation of the interlayer dielectric layer 156, contact pillar 138, first capacitor 168, and contact pillar 150. (See reference...) Figure 10 An interlayer dielectric layer 156a can be formed over the first active region 110a, the first floating gate 112a, the first electrode 208 of the second capacitor, the second floating gate 112b, and the second active region 110b. Contact posts 138 can be formed in the interlayer dielectric layer 156a, over the first floating gate 112a, and over the second floating gate 112b. The formation of the contact posts 138 may include forming openings in the interlayer dielectric layer 156a, over the first floating gate 112a, and over the second floating gate 112b, and then depositing a suitable metal, such as tungsten, into the openings to form the contact posts 138. A first capacitor 168 can be formed over the contact posts 138 and over the interlayer dielectric layer 156a. The first capacitor 168 is electrically coupled to the first floating gate 112a and the second floating gate 112b via the contact posts 138. The formation of the first capacitor 168 is similar to... Figure 6 The formation of the first capacitor 168 is shown. The first capacitor 168 may be separated from the first electrode 208 of the second capacitor by an interlayer dielectric layer 156a. An interlayer dielectric layer 156b may be formed on the first capacitor 168 and on the interlayer dielectric layer 156a. Contact posts 150 may be formed on the first capacitor 168 to provide electrical coupling between the first capacitor 168 and an external input terminal. Although not shown, contact posts may be formed on the first electrode 208 of the second capacitor, on the source electrode 106, and on the substrate contact 116 for connection to an external input terminal.

[0044] The terms “first,” “second,” “third,” etc. (if any) in the specification and claims are used to distinguish between similar elements and are not necessarily used to describe a particular order or temporal sequence. It should be understood that the terms used so far are interchangeable where appropriate so that embodiments of the devices described herein can operate, for example, in an order other than that shown or otherwise described herein. The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “above,” “below,” etc. (if any) in the specification and claims are used for descriptive purposes only and are not necessarily used to describe permanently relative positions. It should be understood that the terms used so far are interchangeable where appropriate so that embodiments of the devices described herein can operate, for example, in an orientation other than that shown or otherwise described herein. Similarly, if the method described herein comprises a series of steps, the order of these steps presented herein is not necessarily the only order in which these steps can be performed; some said steps may be omitted and / or certain other steps not described herein may be added to the method. Furthermore, the terms “comprising,” “including,” “having,” and any variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device that includes a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to those processes, methods, articles, or devices.

[0045] Although several exemplary embodiments have been presented in the above detailed description of the device, it should be understood that many variations exist. It should be further understood that the embodiments are merely examples and are not intended to limit the scope, applicability, size, or configuration of the device in any way. Rather, the above detailed description will provide a convenient guide for those skilled in the art to implement exemplary embodiments of the device, and it will be understood that various changes can be made to the function and arrangement of the elements described in the exemplary embodiments and their methods of manufacture without departing from the scope of this disclosure set forth in the appended claims.

Claims

1. A non-volatile memory device, comprising: an active region surrounded by an isolation structure; a floating gate over the active region, the floating gate having a first end and a second end that overlap the isolation structure in a direction perpendicular to the active region; a dielectric layer between the floating gate and the active region, wherein at least a portion of the dielectric layer overlaps the isolation structure in the direction perpendicular to the active region; a first doped region in the active region adjacent a first side of the floating gate and a second doped region in the active region adjacent a second side of the floating gate; a first capacitor over the floating gate, the first capacitor comprising a first electrode, a second electrode, and a capacitor dielectric between the first electrode and the second electrode, wherein the first electrode of the first capacitor is electrically coupled to the floating gate, wherein an area of the first capacitor is greater than an area of the floating gate; a second capacitor, wherein a first electrode of the second capacitor is over the isolation structure adjacent the floating gate, wherein the first electrode of the second capacitor partially overlaps the first capacitor; and a contact disposed over the first doped region, the second doped region, and the second electrode of the first capacitor, wherein the contact couples the first doped region, the second doped region, and the second electrode of the first capacitor to an input terminal.

2. The nonvolatile memory device of claim 1, wherein, a second electrode of the second capacitor comprises the floating gate.

3. The non-volatile memory device of claim 2, further comprising: a spacer dielectric between the first electrode of the second capacitor and the second electrode of the second capacitor.

4. The non-volatile memory device of claim 1, further comprising: an insulating layer separating the first capacitor from the first electrode of the second capacitor.

5. The nonvolatile memory device of claim 1, wherein, the active region comprises a p-well region.

6. The nonvolatile memory device of claim 1, wherein, the first doped region is a source region and the second doped region is a drain region.

7. The nonvolatile memory device of claim 1, wherein, the first electrode of the second capacitor and the floating gate are made of a same material.

8. An array of non-volatile memory devices, comprising: a first active region, a second active region, and an isolation structure surrounding each active region, wherein a portion of the isolation structure is between the first active region and the second active region; a first array of floating gates over the first active region and a second array of floating gates over the second active region, wherein a first end and a second end of each floating gate overlap the isolation structure in a direction perpendicular to the first active region and the second active region; a dielectric layer between each floating gate from the first array of floating gates and the first active region and between each floating gate from the second array of floating gates and the second active region, wherein at least a portion of the dielectric layer overlaps the isolation structure in the direction perpendicular to the first active region and the second active region; a first doped region in the first active region adjacent a first side of the floating gates from the first array of floating gates and a second doped region in the first active region adjacent a second side of the floating gates from the first array of floating gates, and a first doped region in the second active region adjacent a first side of the floating gates from the second array of floating gates and a second doped region in the second active region adjacent a second side of the floating gates from the second array of floating gates; and a first capacitor over the floating gates from the first array of floating gates, the first capacitor comprising a first electrode, a second electrode, and a capacitor dielectric between the first electrode and the second electrode, wherein the first electrode of the first capacitor is electrically coupled to the floating gates from the first array of floating gates, wherein an area of the first capacitor is greater than an area of the floating gates from the first array of floating gates. a first doped region in each active region and proximate a first side of each floating gate, and a second doped region in each active region and proximate a second side of each floating gate; a first capacitor over each floating gate, the first capacitor including a first electrode, a second electrode, and a capacitor dielectric between the first electrode and the second electrode, wherein the first electrode of the first capacitor is electrically coupled to each floating gate, wherein an area of the first capacitor is greater than an area of each floating gate; a second capacitor, wherein a first electrode of the second capacitor is disposed over the portion of the isolation structure between the first active region and the second active region and proximate each floating gate, wherein the first electrode of the second capacitor partially overlaps the first capacitor; and a contact disposed over the first doped region, the second doped region, and the second electrode of the first capacitor, wherein the contact couples the first doped region, the second doped region, and the second electrode of the first capacitor to an input terminal.

9. A method of manufacturing a non-volatile memory device, comprising: providing an active region surrounded by an isolation structure; providing a floating gate over the active region, wherein a first end and a second end of the floating gate overlap the isolation structure in a direction perpendicular to the active region; providing a dielectric layer between the floating gate and the active region, wherein at least a portion of the dielectric layer overlaps the isolation structure in the direction perpendicular to the active region; providing a first doped region in the active region proximate a first side of the floating gate and a second doped region in the active region proximate a second side of the floating gate; providing a first capacitor over the floating gate, the first capacitor including a first electrode, a second electrode, and a capacitor dielectric between the first electrode and the second electrode, wherein the first electrode of the first capacitor is electrically coupled to the floating gate, wherein an area of the first capacitor is greater than an area of the floating gate; providing a second capacitor, wherein a first electrode of the second capacitor is over the isolation structure and proximate the floating gate, wherein the first electrode of the second capacitor partially overlaps the first capacitor; and providing a contact over the first doped region, the second doped region, and the second electrode of the first capacitor, wherein the contact couples the first doped region, the second doped region, and the second electrode of the first capacitor to an input terminal.

10. The method of claim 9, wherein, providing an active region surrounded by an isolation structure further comprises: providing a substrate; forming an isolation structure in the substrate; and forming an active region in the substrate, wherein the active region is surrounded by the isolation structure.

11. The method of claim 9, wherein, providing a floating gate over the active region, wherein a first end and a second end of the floating gate overlap the isolation structure further comprises: providing a polysilicon layer over the active region and over the isolation structure; and providing a dielectric layer over the polysilicon layer. patterning the polysilicon layer to form a floating gate over the active region, wherein a first end and a second end of the floating gate overlap the isolation structure.

12. The method of claim 11, wherein, providing a second capacitor further comprises: patterning the polysilicon layer to form the first electrode of the second capacitor adjacent to the floating gate and over the isolation structure.

13. The method of claim 12, further comprising: forming a spacer dielectric adjacent to sidewalls of the floating gate and sidewalls of the first electrode of the second capacitor.

14. The method of claim 9, wherein, providing a first capacitor over the floating gate, whereby a first electrode of the first capacitor is electrically coupled to the floating gate further comprises: forming an insulating layer over the active region, over the floating gate, and over the isolation structure; forming a contact pillar in the insulating layer over the floating gate; and forming a first electrode of the first capacitor over the contact pillar and over the insulating layer.

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