Global shutter cmos image sensor and method of manufacturing the same

Abstract

The application discloses a global shutter CMOS image sensor, adopts non-uniform storage diffusion area doping to reduce the leakage of storage points, ensures that when the depth of a photodiode and the number of pixels increase, the carriers of the rear reading line can be all transferred to the storage diffusion area, and ensures that when the global shutter transistor is opened, the loss of the carriers in the storage diffusion area is not caused, and ensures that when the row-by-row reading is performed, even if the number of pixel unit rows increases, the carriers from the storage diffusion area can be completely transferred to the floating diffusion area through a second transfer tube. The application further discloses a manufacturing method of the global shutter CMOS image sensor.

Description

TECHNICAL FIELD

[0001] The present application relates to the semiconductor technology, and particularly relates to a global shutter (GS) CMOS image sensor (CIS) and a manufacturing method thereof. BACKGROUND

[0002] With the development of the automobile industry, the Internet of Things and monitoring equipment, the consumption of image sensors gradually increases. The mainstream image sensor technology is the CMOS image sensor technology compatible with the CMOS process, and among them, the backside illumination (BSI) structure that can capture more light has become the mainstream way.

[0003] Recently, the demand for near-infrared for vehicle recorders and monitoring equipment gradually increases, which is mainly used for image capture in dark light conditions, so that the image can obtain more details. For the acquisition of near-infrared light (wavelength greater than 760 nm), the common structure and method for front-side illumination (FSI) CMOS image sensors at present mainly includes two kinds: one is to use ultra-high energy implantation on an N-type substrate to realize ultra-deep boron (B) implantation (energy greater than 4 MeV) and phosphorus (P) implantation (energy greater than 7 MeV). These pinned photodiodes can reach a depth of 6 um, and have good electrical isolation and strong potential barrier to isolate the illuminated pixels and adjacent pixels. The other is to use a thick high-resistance P-type substrate, in which the collection efficiency depends on the thickness of the original silicon wafer and the heat budget experienced. The high-resistance substrate is mainly used to reduce the interference of adjacent pixels caused by the pinned photodiode-induced potential.

[0004] With the decrease of the pixel unit, in order to increase the light amount, the CMOS image sensor adopts the backside illumination (BSI) configuration. The backside illumination (BSI) CMOS image sensor has increased light amount due to no metal obstruction.

[0005] The intensity of light of four wavelengths changes with depth, in silicon, the depth of blue light intensity decay to 1 / e is about 0.42 um, the depth of green light is 1.40 um, the depth of red light is 2.42 um, and the depth of near-infrared is very deep due to long wavelength. The larger the wavelength is, the stronger the corresponding storage node parasitic effect is. For the near-infrared device, it will be more serious.

[0006] Due to the need to thin the silicon wafer to increase the light transmission, while considering the absorption of visible red light, it is generally defined as 2.4um (the light intensity of red light is 1 / e of the original). The existing near-infrared design focuses on the requirements of continuous image processing (video monitoring, driving recorders, and automatic driving cameras), and less on the consideration of static high speed. For the global shutter (Global shutter) of high-speed photography, the existing global shutter (Global shutter) technology uses tungsten to shield the storage node, thereby realizing accurate signal transfer. With the requirement of small pixel unit and high pixel, new requirements are put forward for the global technology to realize near-infrared. Because the depth of the near-infrared photodiode is large, it takes longer time to remove residual electrons in the process of using the shutter gate, resulting in easy loss of storage diffusion point electrons; with the increase of the number of rows, the last row (pixel area above) is read, and the storage time of the electrons is longer, and the electrons are more likely to be lost, resulting in reduced final image quality.

[0007] As Figure 1 is a structural schematic diagram of a pixel unit circuit of a 6T global shutter CMOS image sensor; each pixel unit of the global shutter CMOS image sensor comprises a photodiode (PD), a storage diffusion area (Storage Diffusion, SD) 106, and a first reset area 105.

[0008] The photodiode comprises a semiconductor layer 101 of a second conductive type, and a first light-sensing doped area 103 of a first conductive type formed on the top of the semiconductor layer 101. The semiconductor layer 101 is a silicon layer. The first light-sensing doped area 103 is an ion implantation area. Figure 1 In the first light-sensing doped area 103, the bottom further comprises a doped area 1031 and a doped area 1032 of the first conductive type, the doping concentration of the doped area 1031 is less than that of the doped area 1032, and the doping concentration of the doped area 1032 is less than that of the first light-sensing doped area 103.

[0009] The storage diffusion area 106 has a first conductive type doping, and a gate structure of a first transfer tube M2 is formed on the top of the semiconductor layer 101 between the first light-sensing doped area 103 and the storage diffusion area 106, and the gate structure is formed by stacking a gate dielectric layer 110 and a polysilicon gate 111.

[0010] The first reset area 105 has a first conductive type doping, and the first reset area 105 is connected with a power supply voltage VDD, and a gate structure of a global shutter transistor M1 is formed on the top of the semiconductor layer 101 between the first light-sensing doped area 103 and the first reset area 105.

[0011] A pinned layer 104 of a second conductivity type is formed on the surface of the first light-doped region 103.

[0012] The pixel unit of the CMOS image sensor further comprises a floating diffusion (FD) 108, and a gate structure of a second transfer transistor M3 is formed on the top of the semiconductor layer 101 between the floating diffusion 108 and the storage diffusion 106.

[0013] The pixel unit of the CMOS image sensor further comprises a reset transistor M4, a gate structure of the reset transistor M4 is arranged between the floating diffusion 108 and a second reset region 109, the second reset region 109 is doped with a first conductivity type, and the second reset region 109 is connected with a power voltage VDD. Both the floating diffusion 108 and the second reset region are formed in a second conductivity type well 107.

[0014] Generally, the first conductivity type is N type, and the second conductivity type is P type. Alternatively, the first conductivity type is P type, and the second conductivity type is N type.

[0015] The pixel unit of the CMOS image sensor further comprises an amplification transistor M5 and a selection transistor M6, a gate of the amplification transistor M5 is connected with the floating diffusion 108, a source of the amplification transistor M5 outputs an amplified signal, a drain of the amplification transistor M5 is connected with the power voltage VDD, the selection transistor M6 is used for selecting the amplified signal output by the amplification transistor M5, and a gate of the selection transistor M6 is connected with a selection signal Rs.

[0016] A shallow trench isolation 102 structure is arranged around the pixel unit of the CMOS image sensor.

[0017] Taking the first conductivity type as N type and the second conductivity type as P type as an example, the operation sequence of the pixel unit circuit of the existing 6T global shutter CMOS image sensor is as follows:

[0018] (1). Light enters a photodiode (PD) to generate photo-generated carriers, and photoelectrons enter the first light-doped region 103 of the photodiode (PD).

[0019] (2). The first transfer transistor M2 is turned on to transfer the charges of all pixel units from the first light-doped region 103 to the storage diffusion region (SD) 106.

[0020] (3). The first transfer transistor M2 is turned off, and photo-generated electrons exist in the storage diffusion region (SD) 106.

[0021] (4). The gate structure of the global shutter transistor M1 connected to the photodiode (PD) is opened, so that the residual charges in the first light-sensing doped region 103 of the photodiode (PD) are transferred to the first reset region 105, while any light-sensing is prevented to generate additional photoelectrons.

[0022] (5). The charges are read out in a row manner from the storage diffusion region (SD) 106 through the second transfer transistor M3 and the floating diffusion region 108.

[0023] The existing global shutter CMOS image sensor has the following technical problems:

[0024] (1) In the near-infrared (NIR) technology, in order to increase the amount of infrared light, the depth of the photodiode (PD) is deeper than normal, which results in a longer transfer time and makes it difficult to ensure that all the electrons in the photodiode (PD) of the entire pixel are transferred to the storage diffusion region (SD) in the same time.

[0025] (2) With the widespread application of the near-infrared (NIR) technology, the size is reduced, which results in an increase in the gate leakage of the global shutter transistor M1, so that the electrons in the storage diffusion region (SD) may be lost, N electrons in the photodiode (PD) are transferred to the storage diffusion region (SD), and N-m electrons are lost. It is difficult to ensure that the opening of the global shutter transistor M1 does not cause the loss of electrons in the storage diffusion region (SD).

[0026] (3). When the N rows of pixel units are read out row by row, if the charges in the storage diffusion region (SD) in the last few rows are lost (flow to the photodiode (PD), junction leakage, since the floating diffusion region (FD) is at a low potential at this time, no leakage will be caused), it cannot be ensured that the original signal is guaranteed. This is more serious with the increase of pixels, the increase of the number of rows, and the increase of the reading time, and it is difficult to ensure that the electrons from the storage diffusion region (SD) can be completely transferred to the floating diffusion region (FD) through the second transfer transistor M3 when read row by row. SUMMARY

[0027] The technical problem to be solved by the present application is that when the depth of the photodiode is increased and the number of pixels is increased, the carriers of the read row can be completely transferred to the storage diffusion region, and the loss of carriers in the storage diffusion region is not caused when the global shutter transistor is opened.

[0028] To solve the above technical problems, the global shutter CMOS image sensor provided by the application comprises N rows of pixel units arranged in sequence, each pixel unit comprises a first reset area 105, a global shutter transistor M1, a photodiode, a first transfer tube M2, a storage diffusion area 106, a second transfer tube M3, a floating diffusion area 108, a reset tube M4 and a second reset area 109 arranged in sequence.

[0029] The photodiode comprises a semiconductor layer 101 of a second conductive type, and a first light-sensing doped area 103 of a first conductive type formed on the top of the semiconductor layer 101.

[0030] The storage diffusion area 106 is doped with the first conductive type, and the top of the semiconductor layer 101 between the first light-sensing doped area 103 and the storage diffusion area 106 is formed with a gate structure of the first transfer tube M2.

[0031] The first reset area 105 is doped with the first conductive type, and the first reset area 105 is connected with a power supply voltage, and the top of the semiconductor layer 101 between the first light-sensing doped area 103 and the first reset area 105 is formed with a gate structure of the global shutter transistor M1.

[0032] A pinning layer 104 doped with the second conductive type is formed on the surface of the first light-sensing doped area 103.

[0033] The top of the semiconductor layer 101 between the floating diffusion area 108 and the storage diffusion area 106 is formed with a gate structure of the second transfer tube M3.

[0034] The gate structure of the reset tube M4 is formed between the floating diffusion area 108 and the second reset area 109.

[0035] The second reset area 109 is doped with the first conductive type, and the second reset area 109 is connected with the power supply voltage.

[0036] Both the floating diffusion area 108 and the second reset area 109 are formed in a second conductive type well 107.

[0037] The concentration of the first conductive type doping of the storage diffusion area 106 of the first M rows of the N rows of pixel units is less than the concentration of the first conductive type doping of the storage diffusion area 106 of the remaining N-M rows, N is an integer greater than 10, and M is an integer less than or equal to N / 2.

[0038] Preferably, the first conductive type is N type, and the second conductive type is P type; or,

[0039] The first conductive type is P type, and the second conductive type is N type.

[0040] Preferably, the concentration of the first conductive type doping of the storage diffusion region 106 of the first M rows of the N rows of pixel units is smaller on the side of the photodiode than on the side of the floating diffusion region.

[0041] Preferably, the semiconductor layer 101 is a silicon layer.

[0042] The first light-sensing doping region 103 is an ion implantation region.

[0043] The semiconductor layer 101 is formed with a first light-sensing lightly-doped region 1030 of the first conductive type.

[0044] The first light-sensing lightly-doped region 1030 is located below the first light-sensing doping region 103 and extends laterally below the first transfer transistor M2.

[0045] The doping concentration of the first light-sensing lightly-doped region 1030 is smaller than the doping concentration of the first light-sensing doping region 103.

[0046] Preferably, each of the pixel units of the CMOS image sensor further comprises an amplification transistor M5 and a selection transistor M6.

[0047] The gate of the amplification transistor M5 is connected to the floating diffusion region 108.

[0048] The source of the amplification transistor M5 outputs an amplified signal.

[0049] The drain of the amplification transistor M5 is connected to a power supply voltage.

[0050] The selection transistor M6 is used to select the amplified signal output by the amplification transistor M5 for output.

[0051] The gate of the selection transistor M6 is connected to a selection signal.

[0052] Preferably, each of the pixel units of the CMOS image sensor is surrounded by a shallow trench isolation 102 on the side thereof.

[0053] Preferably, the gate structure is formed by stacking a gate dielectric layer 110 and a polysilicon gate 111.

[0054] To solve the above technical problems, the manufacturing method of the global shutter CMOS image sensor provided by the present application performs secondary shallow ion implantation on the storage diffusion region 106 of the N rows of pixel units of the global shutter CMOS image sensor.

[0055] The first shallow ion implantation is ion implantation of the first conductive type, and is performed on all the N rows of pixel units.

[0056] The second shallow ion implantation is ion implantation of the second conductive type, and is performed only on the storage diffusion region 106 of the first M rows of pixel units.

[0057] The first shallow ion implantation is preferably performed on the whole storage diffusion region 106,

[0058] The second shallow ion implantation is performed on the adjacent first transfer tube M2 of the storage diffusion region 106.

[0059] The first conductive type is preferably N type and the second conductive type is P type;

[0060] The first shallow ion implantation of the storage diffusion region 106 is phosphorus with an energy of 15KeV-45KeV and a dose of 1E12-4E13;

[0061] The second shallow ion implantation of the storage diffusion region 106 is boron with an energy of 5KeV-10KeV and a dose of 5E13-1E15.

[0062] The global shutter CMOS image sensor and the manufacturing method thereof adopt non-uniform storage diffusion region (SD) 106 doping to reduce the leakage of the storage point, ensure that when the depth of the photodiode (PD) increases, the carriers of the rear reading line can be completely transferred to the storage diffusion region (SD) 106 when the pixel increases, and ensure that when the global shutter transistor M1 is turned on, the loss of the carriers in the storage diffusion region (SD) 106 is not caused, and when the row-by-row reading is performed, even if the number of pixel unit rows increases, the carriers from the storage diffusion region (SD) 106 can be completely transferred to the floating diffusion region (FD) 108 through the second transfer tube M3. BRIEF DESCRIPTION OF DRAWINGS

[0063] In order to more clearly illustrate the technical solutions of the present application, the following briefly introduces the drawings needed to be used by the present application, and obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without paying creative labor on the basis of these drawings.

[0064] Figure 1 is a structural schematic diagram of a pixel unit circuit of a 6T type global shutter CMOS image sensor at present;

[0065] Figure 2 is a structural schematic diagram of a pixel unit circuit of an embodiment of the global shutter CMOS image sensor of the present application;

[0066] Figure 3 is a potential diagram of a pixel unit along the AA' direction of an embodiment of the global shutter CMOS image sensor of the present application. DETAILED DESCRIPTION

[0067] The technical solutions of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0068] Example 1

[0069] like Figure 2 As shown, the global shutter CMOS image sensor includes N rows of pixel units arranged sequentially. Each pixel unit includes a first reset area 105, a global shutter transistor M1, a photodiode (PD), a first transfer transistor M2, a storage diffusion area (SD) 106, a second transfer transistor M3, a floating diffusion area (FD) 108, a reset transistor M4, and a second reset area 109 arranged sequentially.

[0070] The photodiode (PD) includes a semiconductor layer 101 of a second conductivity type and a first photosensitive doped region 103 of a first conductivity type formed on top of the semiconductor layer 101;

[0071] The storage diffusion region (SD) 106 has a first conductivity type doping, and a gate structure of a first transfer transistor M2 is formed on the top of the semiconductor layer 101 between the first photosensitive doped region 103 and the storage diffusion region (SD) 106.

[0072] The first reset region 105 has a first conductivity type doping and is used to connect to the power supply voltage VDD. The top of the semiconductor layer 101 between the first photosensitive doped region 103 and the first reset region 105 has a gate structure of a global shutter transistor M1.

[0073] A pinning layer 104 of a second conductivity type is formed on the surface of the first photosensitive doped region 103;

[0074] A gate structure of a second transfer transistor M3 is formed on top of the semiconductor layer 101 between the floating diffusion region (FD) 108 and the storage diffusion region (SD) 106.

[0075] The gate structure of the reset transistor M4 is disposed between the floating diffusion region 108 and the second reset region 109.

[0076] The second reset region 109 has a first conductive type doping, and the second reset region 109 is connected with a power voltage VDD;

[0077] The floating diffusion region 108 and the second reset region are both formed in a second conductive type well 107;

[0078] The first conductive type doping concentration of the storage diffusion region (SD) 106 of the first M rows of the N rows of pixel units is less than the first conductive type doping concentration of the storage diffusion region (SD) 106 of the remaining N-M rows;

[0079] The first conductive type is N type, and the second conductive type is P type; or,

[0080] The first conductive type is P type, and the second conductive type is N type.

[0081] The embodiment one global shutter CMOS image sensor adopts non-uniform storage diffusion region (SD) 106 doping to reduce the leakage of the storage point, to ensure that with the increase of the depth of the photodiode (PD) and the increase of the pixel, the carriers of the rear reading row can be completely transferred to the storage diffusion region (SD) 106, and to ensure that when the global shutter transistor M1 is turned on, the loss of the carriers in the storage diffusion region (SD) 106 is not caused, and to ensure that when reading row by row, even if the number of pixel units increases, the carriers from the storage diffusion region (SD) 106 can be completely transferred to the floating diffusion region (FD) 108 through the second transfer tube M3.

[0082] Embodiment two

[0083] Based on the global shutter CMOS image sensor of the embodiment one, the first conductive type doping concentration of the storage diffusion region 106 of the first M rows of the N rows of pixel units is less than that near the floating diffusion region (FD).

[0084] Embodiment three

[0085] Based on the global shutter CMOS image sensor of the embodiment one, the semiconductor layer 101 is a silicon layer;

[0086] The first light-sensing doping region 103 is an ion implantation region;

[0087] The first conductive type first light-sensing lightly doped region 1030 is formed in the semiconductor layer 101;

[0088] The first light-sensing lightly doped region 1030 is located below the first light-sensing doping region 103 and extends laterally below the first transfer tube M2;

[0089] The first light-sensing lightly-doped region 1030 has a doping concentration less than that of the first light-sensing doped region 103.

[0090] The global shutter CMOS image sensor of the third embodiment enables back-side illumination (BSI) structure photodiodes (PDs) to capture more light.

[0091] The fourth embodiment

[0092] Based on the global shutter CMOS image sensor of the first embodiment, each of the pixel units of the CMOS image sensor further comprises an amplification transistor M5 and a selection transistor M6.

[0093] The gate of the amplification transistor M5 is connected to the floating diffusion region 108.

[0094] The source of the amplification transistor M5 outputs an amplified signal.

[0095] The drain of the amplification transistor M5 is connected to a power supply voltage VDD.

[0096] The selection transistor M6 is configured to select the amplified signal output by the amplification transistor M5 for output.

[0097] The gate of the selection transistor M6 is connected to a selection signal Rs.

[0098] Preferably, each of the pixel units of the CMOS image sensor is surrounded by a shallow trench isolation structure 102.

[0099] Preferably, the gate structure is formed by a gate dielectric layer 110 and a polysilicon gate 111.

[0100] The fifth embodiment

[0101] The method for manufacturing the global shutter CMOS image sensor of the first embodiment comprises a secondary shallow ion implantation on the storage diffusion region (SD) 106 of each of the N rows of pixel units.

[0102] The first shallow ion implantation is a first-conductivity-type ion implantation, and is performed on all of the N rows of pixel units.

[0103] The second shallow ion implantation is a second-conductivity-type ion implantation, and is performed only on the storage diffusion region (SD) 106 of the first M rows of pixel units.

[0104] The manufacturing method of the global shutter CMOS image sensor of the second embodiment is to perform secondary ion implantation on the storage diffusion region (SD) 106 of the global shutter CMOS image sensor; the first time is shallow layer ion implantation of the first conductive type, which is performed on all N rows of pixel units; the shallow layer ion implantation of the first time makes the leakage of the storage diffusion region (SD) 106 within the opening time of the global shutter transistor M1, and the carriers of the storage diffusion region (SD) 106 are not transferred; the second time is shallow layer ion implantation of the second conductive type, which is performed on the storage diffusion region (SD) 106 of the first M rows of pixel units by using an additional mask; the second time is to perform reverse type implantation to reduce the leakage of the storage diffusion region (SD) 106.

[0105] By Figure 3 It can be seen that the newly added asymmetric reverse type implantation increases the potential barrier of the storage diffusion region (SD) 106 near the photodiode (PD) region. The manufacturing method of the global shutter CMOS image sensor of the second embodiment reduces the leakage problem caused by the increase of the photodiode reset and row-by-row reading time of the small-size global shutter high-pixel near-infrared CMOS image sensor by forming an asymmetric and non-uniform storage diffusion region (SD) 106 through two times of ion implantation, thereby improving the image quality and ensuring that the CMOS image sensor realizes small size, high pixel, and global near-infrared.

[0106] Embodiment six

[0107] Based on the manufacturing method of the global shutter CMOS image sensor of the fifth embodiment, the first shallow layer ion implantation is performed on the entire storage diffusion region (SD) 106,

[0108] The second shallow layer ion implantation is performed on the adjacent first transfer tube M2 of the storage diffusion region (SD) 106.

[0109] The manufacturing method of the global shutter CMOS image sensor of the sixth embodiment can ensure that the carrier transfer from the storage diffusion region (SD) 106 to the floating diffusion region (FD) 108 is not affected by the opening of the global shutter transistor M1 during actual reading, and an internal potential is formed, which can increase the reading speed.

[0110] Embodiment seven

[0111] Based on the manufacturing method of the global shutter CMOS image sensor of the fifth embodiment, the first conductive type is N type, and the second conductive type is P type;

[0112] The first shallow layer ion implantation of the storage diffusion region 106 is phosphorus (P) with an energy of 15KeV-45KeV and a dose of 1E12-4E13;

[0113] The second time shallow ion implantation of the storage diffusion region 106 is boron (B) with an energy of 5KeV-10KeV and a dose of 5E13-1E15.

[0114] The above description is only the preferred embodiment of the present application, and is not used to limit the present application, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A global shutter CMOS image sensor, characterized by, It includes N rows of pixel units arranged in front and back, each pixel unit includes first reset area (105), global shutter transistor (M1), photodiode, first transfer tube (M2), storage diffusion area (106), second transfer tube (M3), floating diffusion area (108), reset tube (M4) and second reset area (109) arranged in turn; The photodiode includes a semiconductor layer (101) of a second conductive type, and a first light-sensing doped area (103) of a first conductive type formed on the top of the semiconductor layer (101); The storage diffusion area (106) has a first conductive type doping, and the top of the semiconductor layer (101) between the first light-sensing doped area (103) and the storage diffusion area (106) forms a gate structure of the first transfer tube (M2); The first reset area (105) has a first conductive type doping, and the first reset area (105) is connected with a power supply voltage, and the top of the semiconductor layer (101) between the first light-sensing doped area (103) and the first reset area (105) forms a gate structure of the global shutter transistor (M1); A pinning layer (104) of a second conductive type is formed on the surface of the first light-sensing doped area (103); The top of the semiconductor layer (101) between the floating diffusion area (108) and the storage diffusion area (106) forms a gate structure of the second transfer tube (M3); The gate structure of the reset tube (M4) is formed between the floating diffusion area (108) and the second reset area (109); The second reset area (109) has a first conductive type doping, and the second reset area (109) is connected with a power supply voltage; The floating diffusion area (108) and the second reset area (109) are both formed in a second conductive type well (107); The first conductive type doping concentration of the storage diffusion area (106) of the first M rows of the N rows of pixel units is less than the first conductive type doping concentration of the storage diffusion area (106) of the remaining N-M rows, N is an integer greater than 10, and M is a positive integer less than or equal to N / 2.

2. The global shutter CMOS image sensor according to claim 1, wherein The first conductive type is N type, and the second conductive type is P type; or The first conductive type is P type, and the second conductive type is N type.

3. The global shutter CMOS image sensor according to claim 1, wherein The first conductive type doping concentration of the storage diffusion area (106) of the first M rows of the N rows of pixel units is less than the first conductive type doping concentration of the storage diffusion area (106) of the remaining N-M rows, N is an integer greater than 10, and M is a positive integer less than or equal to N / 2.

4. The global shutter CMOS image sensor according to claim 1, wherein The semiconductor layer (101) is a silicon layer; The first light-sensing doped area (103) is an ion implantation area; The semiconductor layer (101) forms a first light-sensing lightly doped area (1030) of a first conductive type. A first light-sensing lightly-doped region (1030) is located below the first light-sensing doped region (103) and extends laterally below the first transfer tube (M2); The doping concentration of the first light-sensing lightly-doped region (1030) is less than the doping concentration of the first light-sensing doped region (103).

5. The global shutter CMOS image sensor according to claim 1, wherein Each of the pixel units of the CMOS image sensor further comprises an amplification tube (M5) and a selection tube (M6); The gate of the amplification tube (M5) is connected to the floating diffusion region (108); The source of the amplification tube (M5) outputs an amplified signal; The drain of the amplification tube (M5) is connected to a power supply voltage; The selection tube (M6) is configured to select the amplified signal output by the amplification tube (M5) for output; The gate of the selection tube (M6) is connected to a selection signal.

6. The global shutter CMOS image sensor according to claim 1, wherein A shallow trench isolation (102) is arranged around each of the pixel units of the CMOS image sensor.

7. The global shutter CMOS image sensor according to claim 1, wherein The gate structure is formed by stacking a gate dielectric layer (110) and a polysilicon gate (111).

8. A method for manufacturing the global shutter CMOS image sensor according to claim 1, wherein The storage diffusion region (106) of N rows of pixel units of the global shutter CMOS image sensor is subjected to secondary shallow ion implantation; The first shallow ion implantation is ion implantation of a first conductive type, and is performed on all N rows of pixel units; The second shallow ion implantation is ion implantation of a second conductive type, and is performed only on the storage diffusion region (106) of the first M rows of pixel units.

9. The method for manufacturing the global shutter CMOS image sensor according to claim 8, wherein The first shallow ion implantation is performed on the entire storage diffusion region (106), The second shallow ion implantation is performed on the storage diffusion region (106) adjacent to the first transfer tube (M2).

10. The method for manufacturing the global shutter CMOS image sensor according to claim 8, wherein The first conductive type is N-type, and the second conductive type is P-type; The first shallow ion implantation of the storage diffusion region (106) is performed with phosphorus as the impurity, at an energy of 15KeV-45KeV, and a dose of 1E12-4E13; The second shallow ion implantation of the storage diffusion region (106) is performed with boron as the impurity, at an energy of 5KeV-10KeV, and a dose of 5E13-1E15.

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