Boost switch driver for high-speed signal switching

Abstract

The present disclosure relates to a boost switch driver for high-speed signal switching. An example boost switch driver circuit includes two branches. The first branch includes a first transistor. The second branch includes a second transistor and a level shifter circuit. One of the transistors is an N-type transistor and the other is a P-type transistor. The circuit is configured to split an input clock signal between the first branch and the second branch, so that a portion of the input clock signal split to the first branch is provided to the first transistor, and a portion of the input clock signal split to the second branch is level-shifted by the level shifter circuit to generate a level-shifted input clock signal, and the level-shifted input clock signal is provided to the second transistor. The circuit is further configured to combine the output of the first transistor with the output of the second transistor to generate an output clock signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is related to U.S. patent application No. 63 / 065,590, filed on August 14, 2020, entitled “BOOSTED SWITCH DRIVERS FOR HIGH-SPEED SIGNAL SWITCHING,” the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to electronic devices and systems, and more particularly to switch drivers. Background Art

[0004] In electronic instrumentation and signal processing, a switch driver is a device that controls a switch. For example, a sample-and-hold analog-to-digital converter (ADC) contains multiple switches and multiple switch drivers configured to control different switches. A switch driver can be described as "boosted" when the output voltage of the driver can swing beyond the core supply rails in a given circuit. For example, a boosted switch driver can be used in a radio frequency (RF) sampling ADC to control a switch with a high gate voltage while being able to handle large signal swings.

[0005] The cost, quality, and robustness of a boost switch driver can be affected by a variety of factors. Physical limitations, such as space / surface area, can further limit boost switch driver requirements or specifications, so compromises and ingenuity must be applied when designing the best boost switch driver for a given application. Designing a boost switch driver for high-speed signal switching (e.g., for an RF ADC) is particularly challenging. Summary of the invention

[0006] According to one aspect of the present disclosure, an electronic component is provided, comprising: one or more switches; and a switch driver circuit for driving the one or more switches, the switch driver circuit comprising: an input for receiving an input clock signal; an output for providing an output clock signal; a first transistor and a second transistor, each comprising a first terminal and a second terminal; a third transistor coupled to the first transistor in a common source and common gate arrangement; and a level shifter circuit for level shifting the input clock signal to generate a level-shifted input clock signal, wherein: the first terminal of the first transistor is used to receive a signal indicating the input clock signal, the first terminal of the second transistor is used to receive a signal indicating the level-shifted input clock signal, the second terminal of the first transistor is coupled to the third terminal of the third transistor, and the second terminal of the third transistor is coupled to the output, and the second terminal of the second transistor is coupled to the output.

[0007] According to another aspect of the present disclosure, an electronic component is provided, comprising: one or more switches; and a switch driver circuit for driving the one or more switches, the switch driver circuit comprising: an input for receiving an input clock signal; an output for providing an output clock signal; a first transistor and a second transistor, each comprising a first terminal and a second terminal; a first level shifter circuit for level-shifting the input clock signal to generate a level-shifted input clock signal; and a second level shifter circuit; wherein: the first terminal of the first transistor is used to receive a signal indicating the input clock signal, the first terminal of the second transistor is used to receive a signal indicating the level-shifted input clock signal, the second terminal of the second transistor is coupled to the second level shifter circuit, each of the second terminal of the first transistor and the second terminal of the second transistor is coupled to the output, the first level shifter circuit is used to control a high voltage value of the level-shifted input clock signal, and the second level shifter circuit is used to control a high voltage level of the output clock signal.

[0008] According to another aspect of the present disclosure, a switch driver circuit is provided, which includes: an input for receiving an input clock signal; an output for providing an output clock signal; a first transistor and a second transistor, each including a first terminal and a second terminal; a first level shifter circuit for level-shifting the input clock signal to generate a level-shifted input clock signal; and a second level shifter circuit; wherein: the first terminal of the first transistor is used to receive a signal indicating the input clock signal, the first terminal of the second transistor is used to receive a signal indicating the level-shifted input clock signal, the second terminal of the second transistor is coupled to the second level shifter circuit, and each of the second terminal of the first transistor and the second terminal of the second transistor is coupled to the output. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] To provide a more complete understanding of the present disclosure and its features and advantages, reference is made to the following description taken in conjunction with the accompanying drawings, wherein like reference numerals represent like parts, and in which:

[0010] Figure 1 Provides a circuit diagram of an example circuit in which a boost switch driver with level shifting in a branch of a P-type transistor may be used according to some embodiments of the present disclosure;

[0011] Figure 2 Provides a circuit diagram of an example circuit having a boost switch driver with level shifting in a branch of a P-type transistor according to some embodiments of the present disclosure;

[0012] Figure 3 Provides a circuit diagram of an example level shifter circuit configured to perform level shifting while controlling a maximum / high signal level according to some embodiments of the present disclosure;

[0013] Figure 4 A circuit diagram is provided for an example circuit having a boost switch driver having a P-type transistor in a branch using a Figure 3 The level shifting is implemented by a level shifter circuit;

[0014] Figure 5 Provides a circuit diagram of an example circuit having a boost switch driver with level shifting in a branch of a P-type transistor and having an additional transistor provided as a cascode transistor to an N-type transistor according to some embodiments of the present disclosure;

[0015] Figure 6Provides a circuit diagram of an example circuit having a boost switch driver with level shifting in a branch of a P-type transistor and having an additional level shifter configured to control a minimum / low signal level according to some embodiments of the present disclosure;

[0016] Figure 7 Provides a circuit diagram of an example circuit in which a boost switch driver with level shifting in a branch of an N-type transistor may be used according to some embodiments of the present disclosure;

[0017] Figure 8 Provides a circuit diagram of an example circuit having a boost switch driver with level shifting in a branch of an N-type transistor according to some embodiments of the present disclosure;

[0018] Fig. 9 Provides a circuit diagram of an example level shifter circuit configured to perform level shifting while controlling a minimum / low signal level according to some embodiments of the present disclosure;

[0019] Fig.10 A circuit diagram is provided of an example circuit having a boost switch driver having a branch using an N-type transistor according to some embodiments of the present disclosure. Fig. 9 The level shifting is implemented by a level shifter circuit;

[0020] Fig.11 Provides a circuit diagram of an example circuit having a boost switch driver with level shifting in a branch of an N-type transistor and having an additional transistor provided as a cascode transistor to a P-type transistor according to some embodiments of the present disclosure;

[0021] Fig.12 Provides a circuit diagram of an example circuit having a boost switch driver with level shifting in a branch of an N-type transistor and having an additional level shifter configured to control a minimum / low level according to some embodiments of the present disclosure;

[0022] Fig.13 Provides a schematic illustration of example components in which one or more boost switch drivers may be implemented according to some embodiments of the present disclosure;

[0023] Fig.14 is a block diagram of an example system that may include one or more boost switch drivers according to some embodiments of the present disclosure;

[0024] Fig.15 is a block diagram of an example RF device that may include one or more boost switch drivers according to some embodiments of the present disclosure; and

[0025] Fig.16 A block diagram is provided that illustrates an example data processing system that may be configured to control the operation of one or more boost switch drivers according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0026] Overview

[0027] The systems, methods, and devices of the present disclosure each have several innovative aspects, no single one of which is responsible for all of the desirable attributes disclosed herein. The details of one or more implementations of the subject matter described in this disclosure are set forth in the following description and the accompanying drawings.

[0028] Embodiments of the present disclosure relate to switch driver circuits, and devices and systems in which such circuits can be implemented. In one aspect of the present disclosure, an example switch driver circuit includes two branches. The first branch includes a first transistor (e.g., transistor m5 shown in the drawings of the present disclosure). The second branch includes a second transistor (e.g., transistor m6 shown in the drawings of the present disclosure) and a level shifter circuit. One of these transistors is an N-type transistor and the other is a P-type transistor. The circuit is configured to split an input clock signal between the first branch and the second branch, so that a portion of the input clock signal split to the first branch is provided to the first transistor, and a portion of the input clock signal split to the second branch is level-shifted by the level shifter circuit to generate a level-shifted input clock signal, and the level-shifted input clock signal is provided to the second transistor. In the context of the input clock signal having a low voltage value and a high voltage value, level shifting the input clock signal includes the level shifter circuit changing each of the low voltage value and the high voltage value of the input signal to generate a level-shifted input signal. The switch driver circuit is further configured to combine the output of the first transistor with the output of the second transistor to generate an output clock signal. Various embodiments of this circuit are described below as "boost switch driver circuits" (or simply "boost switch drivers") because they can allow output voltage swings that exceed the core supply rails to be provided. The boost switch drivers described herein can advantageously allow extremely fast boost edges to be provided where high speed signal processing requires additional swing, which can help maximize both clock speed and dynamic range. Other aspects of the present disclosure provide systems (e.g., RF transceivers) that can include one or more boost switch drivers as described herein and methods for providing such boost switch drivers.

[0029] The precise design of the boost switch driver described herein can be achieved in many different ways, all of which are within the scope of the present disclosure.

[0030] In one example of design variations according to various embodiments of the present disclosure, a choice may be made individually for each of the transistors of the boost switch driver according to any of the embodiments described herein to employ a bipolar transistor (e.g., where the various transistors may be NPN or PNP transistors), a field effect transistor (FET), such as a metal oxide semiconductor (MOS) technology transistor (e.g., where the various transistors may be N-type MOS (NMOS) or P-type MOS (PMOS) transistors), or a combination of one or more FETs and one or more bipolar transistors, as long as one of the transistors of the first branch and the second branch of the boost switch driver circuit is an N-type transistor (e.g., if the transistor is a bipolar transistor, one of the transistors is an NPN transistor, or if the transistor is a FET, one of the transistors is an NMOS transistor), and the other is a P-type transistor (e.g., if the transistor is a bipolar transistor, the other is a PNP transistor, or if the transistor is a FET, the other is a PMOS transistor). In the figures of the present disclosure, the transistors are shown as FETs, and the description therefore refers to their terminals as gate terminals, drain terminals, and source terminals. However, in further embodiments of the present disclosure, any of the FETs shown in the accompanying drawings may be replaced with a corresponding bipolar transistor. Therefore, the description provided below with reference to the "gate terminal" may be considered to refer to the "first terminal", wherein if the transistor is a FET, the term "first terminal" of the transistor is used to refer to the gate terminal, or if the transistor is a bipolar transistor, it is used to refer to the base terminal. Similarly, the description provided below with reference to the "drain terminal" may be considered to refer to the "second terminal", wherein if the transistor is a FET, the term "second terminal" of the transistor is used to refer to the drain terminal, or if the transistor is a bipolar transistor, it is used to refer to the collector terminal, and the description provided below with reference to the "source terminal" may be considered to refer to the "third terminal", wherein if the transistor is a FET, the term "third terminal" of the transistor is used to refer to the source terminal, or if the transistor is a bipolar transistor, it is used to refer to the emitter terminal. These terms remain unchanged regardless of whether the transistor of a given technology is an N-type transistor or a P-type transistor.

[0031] In another example, in various embodiments, a choice as to what type of transistor architecture to employ may be made individually for each of the transistors of any of the boost switch drivers as described herein. For example, any of the transistors of the boost switch drivers as described herein implemented as FETs may be planar transistors or may be non-planar transistors (some examples of the latter include FinFETs, nanowire transistors, and nanoribbon transistors).

[0032] As will be appreciated by those skilled in the art, aspects of the present disclosure, in particular, aspects of the boost switch driver as presented herein, may be embodied in various ways, for example, as a method, system, computer program product, or computer-readable storage medium. Thus, aspects of the present disclosure may take the form of a fully hardware embodiment, a fully software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software aspects with hardware aspects, all of which may be generally referred to herein as a "circuit," "module," or "system." The functions described in the present disclosure may be implemented as an algorithm executed by one or more hardware processing units (e.g., one or more microprocessors) of one or more computers. In various embodiments, different steps and portions of steps of each of the methods described herein may be performed by different processing units. In addition, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer-readable media, preferably non-transitory, on which computer-readable program code is embodied (e.g., stored). In various embodiments, this computer program may, for example, be downloaded (updated) to existing devices and systems (e.g., existing RF ADCs, transceivers, and / or controllers thereof, etc.), or stored when these devices and systems are manufactured.

[0033] The following detailed description presents various illustrations of certain embodiments. However, the innovation described herein can be embodied in numerous different ways, such as defined and encompassed by the selected examples.

[0034] In the following description, reference is made to the accompanying drawings, in which similar reference numbers may indicate the same or functionally similar elements. It will be understood that the elements shown in the accompanying drawings are not necessarily drawn to scale. Moreover, some embodiments may incorporate any suitable combination of features from two or more of the accompanying drawings. In addition, it will be understood that certain embodiments may include more elements than the elements shown in the accompanying drawings and / or a subset of the elements shown in the accompanying drawings. In general, although some of the accompanying drawings provided herein illustrate various aspects of the boost switch driver, and systems in which such circuits may be implemented, the details of these systems may be different in different embodiments. For example, the various components of the boost switch driver presented herein may have other components that are not specifically shown in the accompanying drawings, such as logic, storage, passive elements (e.g., resistors, capacitors, inductors, etc.) or other elements (e.g., transistors, etc.) included therein or coupled thereto. In another example, the details shown in some of the accompanying drawings, such as the specific arrangement of the various components of the boost switch driver presented herein and the example implementation details (e.g., details of the level shifter circuit) and / or the specific arrangement of the coupling connection may be different in different embodiments, wherein the illustration of the accompanying drawings of the present disclosure only provides some examples of how these components can be used together to implement the boost switch driver. In yet another example, while some embodiments shown in the figures of the present disclosure illustrate a specific number of components (e.g., a specific number of level shifter circuits in a boost switch driver), it should be understood that these embodiments may be implemented in a boost switch driver or in any other device or system having any number of these components, based on the description provided herein. In addition, while certain elements, such as the various elements of the boost switch driver presented herein, may be depicted in the figures as being communicatively coupled using a single depicted line, in some embodiments, any of these elements may be coupled via multiple conductive lines, such as those that may be present in a bus or when differential signals are involved.

[0035] The description may use the phrase "in one embodiment" or "in an embodiment", which phrases may each refer to one or more of the same or different embodiments. Unless otherwise specified, the use of ordinal adjectives "first", "second" and "third" etc. to describe a common object only indicates that the different examples of similar objects are referred to, and is not intended to imply that the object described in this way must be in a given sequence in time, space, level or in any other way. In addition, for the purposes of this disclosure, the phrase "A and / or B" or the symbol "A / B" means (A), (B) or (A and B), and the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C). As used herein, the symbol "A / B / C" means (A, B and / or C). When used with reference to a measurement range, the term "between..." includes the end of the measurement range.

[0036] Various aspects of the illustrative embodiments are described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the term "connected" means a direct electrical connection between the things being connected without any intermediate devices / components, while the term "coupled" means a direct electrical connection between the things being connected, or an indirect electrical connection through one or more passive or active intermediate devices / components. In another example, the term "circuit" or "circuitry" (used interchangeably) refers to one or more passive and / or active components that are arranged to cooperate with each other to provide the desired functionality. Sometimes, in this description, the term "circuit" may be omitted (e.g., a boost switch driver circuit may be referred to simply as a "boost switch driver"; a level shifter circuit may be referred to simply as a "level shifter", etc.). If used, the terms "substantially", "approximately", "about", etc. may be generally used to refer to within + / -20% of a target value, for example, within + / -10% of a target value, based on the context of a specific value as described herein or as known in the art.

[0037] Boost switch driver circuit with two branches and level shift in one branch

[0038] All embodiments of the boost switch driver presented herein are based on splitting an input signal to the boost switch driver circuit between two branches and then combining the outputs of the two branches to produce an output signal from the boost switch driver circuit. In addition, all embodiments include a level shifter circuit in at least one of the branches, which allows the output signal from the boost switch driver circuit to have a larger signal swing than the input signal and carefully controls the maximum / high signal level, minimum / low signal level, or both of the output signal. One of the branches includes a P-type transistor and the other branch includes an N-type transistor. When only one of the branches includes a level shifter circuit, the embodiments of the boost switch driver presented herein can be roughly divided into the following two groups of embodiments: One group of embodiments includes a P-type transistor (such as Figures 1 to 6 ) on one side (ie, in the branch containing the P-type transistors), and one set of embodiments has a level shift on the N-type transistors (eg, Figures 7 to 12 ) has a level shift on one side (i.e., in the branch containing the N-type transistor). However, further embodiments are possible and within the scope of the present disclosure in which the level shift is performed on both the side of the P-type transistor and the side of the N-type transistor. Such embodiments may be considered as referring to Figures 1 to 6 The level shifting described is similar to that described in reference Figures 7 to 12 Combinations of level shifting are described, all of which are within the scope of the present disclosure.

[0039] Example boost switch driver circuit with level shifting in the branch of the P-type transistor

[0040] Figure 1 A circuit diagram of an example circuit 100 is provided in which a boost switch driver with level shifting in the branch of a P-type transistor may be used according to some embodiments of the present disclosure. Figure 1 , the circuit 100 may include a series of first inverters 102 and second inverters 104 coupled to a switch 106. The first inverter 102 may be a fast inverter (e.g., a basic two-transistor inverter having one PMOS and one NMOS transistor, using a core MOS transistor with a core supply voltage) configured to drive the second inverter 104, which may include any of the boost switch drivers described herein with level shifting performed in the branches of the P-type transistors. The first inverter 102 may be configured to receive a digital signal having a range of voltage values ​​(e.g., a clock signal) and provide an inverted version of the signal to the second inverter 104. For example, the digital signal provided to the first inverter 102 may be a range of voltage values ​​between a low voltage value (e.g., 0 volts (V)) and a high voltage value (e.g., 1 V), examples of which are shown in FIG. Figure 1 The output of the first inverter 102 corresponding to this input is shown as signal 112 (schematically shown in the dashed box labeled "112"). Figure 1 14 (schematically shown within the dashed box labeled "114"). Thus, the output swing of the first inverter 102 is 1V. The second inverter 104 may be a boost switch driver that is powered up (i.e., configured to boost / increase the output swing). This Figure 1 In the embodiment, the second inverter 104 receives a signal having an output swing of 1V (ie, small graph 114) and outputs an inverted and boosted version of the signal. Figure 1 1 is shown as a signal 116 (schematically shown within the dashed box labeled "116") still having a low voltage value of 0V, but now having a high voltage value of 1.4V. The output of the second inverter 104 may then be used to drive a switch 106, which in some embodiments may be implemented as Figure 1 The transistor shown in .

[0041] In various embodiments, the inverter may include any of the boost switch driver circuits with level shifting in the branch of the P-type transistor presented herein. In various embodiments, the signals 112, 114, 116 may be different, for example, the signals may have different high values ​​and low values. Similarly, the low supply voltage and the high supply voltage coupled to each of the first inverter 102 and the second inverter 104 may be different in different embodiments in which any of the boost switch driver circuits with level shifting in the branch of the P-type transistor presented herein is used to implement the inverter 104. Moreover, in further embodiments, the second inverter 104 including any of the boost switch driver circuits with level shifting in the branch of the P-type transistor presented herein may be included in a circuit other than the circuit 100, and in particular, may not necessarily be implemented with the first inverter 102, as Figure 1 As shown in .

[0042] Figure 2 A circuit diagram of an example circuit 200 having a boost switch driver with a level shift on one side of a P-type transistor according to some embodiments of the present disclosure is provided. The circuit 200 can be considered as an example of the circuit 100, where the boost switch driver is used to Figure 1 The reference numbers of the circuit 100 are used to refer to the circuit 100 with respect to Figure 2 Those elements shown in the circuit 200 are identical or functionally similar elements, so that the description of these elements provided with respect to one figure is not repeated for another figure, and only the differences are described (the same is true for other figures of the present disclosure).

[0043] like Figure 2 , in some embodiments, the first inverter 102 may be implemented as a pair of complementary transistors m3, m4 (i.e., one of the transistors is N-type and the other is P-type). For example, the gate terminal of transistor m3 may be coupled to the gate terminal of transistor m4, and both may be coupled to the input clock signal 112, the drain terminal of transistor m3 may be coupled to the drain terminal of transistor m4, and both may be coupled to the output 114, and the source terminals of transistors m3 and m4 may be coupled to a low supply voltage and a high supply voltage for the first inverter 102. For example, transistor m3 may be an N-type transistor (e.g., an NMOS transistor, as in ) having its source terminal coupled to a low supply voltage (e.g., 0V). Figure 2 ), and transistor m4 may be a P-type transistor (eg, a PMOS transistor, as shown in FIG. 1 ) having its source terminal coupled to a high supply voltage (eg, 1 V). Figure 2As described above, the output clock signal 114 of the first inverter 102 may be used as the basis for the input clock signal to the second inverter 104.

[0044] Figure 2 Further shown is a boost switch driver circuit 204, which may be, for example, an example of the second inverter 104 described above. Figure 2 As shown in FIG. 2 , circuit 204 may include an input 222, an output 224, and two branches 226 between input 222 and output 224. The first branch, at Figure 2 The second branch is schematically indicated by the dot-dash line 226-1, which may include a transistor m5. Figure 2 As schematically indicated by dashed line 226-2 in FIG. 2 , a transistor m6 and a level shifter circuit 230 may be included. One of transistors m5 and m6 may be an N-type transistor and the other may be a P-type transistor. Figure 2 An embodiment is shown with level shifting done on one side of a P-type transistor, so transistor m6 is a P-type transistor (e.g., a PMOS transistor, as in Figure 2 ), while transistor m5 is an N-type transistor (e.g., an NMOS transistor, as shown in Figure 2 2. The circuit 204 may be configured to split an input clock signal (e.g., signal 114) between a first branch 226-1 and a second branch 226-2 such that a portion of the input clock signal 114 split into the first branch 226-1 is provided to the transistor m5 of the branch, and a portion of the input clock signal split into the second branch 226-2 is level-shifted by the level shifter circuit 230 to generate a level-shifted signal 214-2, and the level-shifted signal 214-2 is provided to the transistor m6. Figure 2 2 shows a signal 214-1 provided to transistor m5 (i.e., the gate terminal of transistor m5), and a signal 214-2 provided to transistor m6 (i.e., the gate terminal of transistor m6). Signal 214-1 is similar to signal 114 in its voltage swing (e.g., from about 0 to about 1 V, as shown for Figure 2), while signal 214-2 may be substantially the same in terms of level shifted signal 114-2 having a voltage swing from about 0.5V to about 1.4V compared to signal 114. Circuit 204 is further configured to combine the output of transistor m5 (e.g., the output from the drain terminal of transistor m5) with the output of transistor m6 (e.g., the output from the drain terminal of transistor m6) to generate output clock signal 116. Thus, the gate terminal of each of transistors m5 and m6 may be coupled to input 222, except that the gate terminal of transistor m6 is coupled to input 222 via a level shifter circuit 230 configured to perform level shifting before providing the signal to transistor m6. Similarly, the drain terminal of each of transistors m5 and m6 may be coupled to output 224, which may be coupled to switch 106 to be driven by switch driver circuit 204.

[0045] In some embodiments, the level shifter circuit 230 may include a voltage controller circuit 232 that may be configured to receive a reference signal 234 as an input and generate an output 236, such as Figure 2 . In addition, the level shifter circuit 230 may further include a coupling capacitor 238 coupled to the voltage controller circuit 232. For example, a first capacitor electrode of the coupling capacitor 238 may be coupled to the input 222, and a second capacitor electrode of the coupling capacitor 238 may be coupled to each of the voltage controller circuit 232 and the gate terminal of the transistor m6. In other words, a portion of the input clock signal 114 split to the second branch 226-2 of the circuit 204 may be configured to be applied to the first capacitor electrode of the coupling capacitor 238, and a second capacitor electrode of the coupling capacitor 238 may be coupled to each of the output 236 of the voltage controller circuit 232 and the gate terminal of the transistor m6. The input 234 to the voltage controller circuit 232 may be a reference voltage or any other control signal configured to control the maximum voltage level set by the voltage controller circuit 232. The output 236 from the voltage controller circuit 232 may form the basis for the level-shifted input clock signal 214-2 to be provided to the gate terminal of the transistor m6.

[0046] When the transistor m6 is a P-type transistor (such as Figure 2 ), the voltage controller circuit 232 may be configured to control the maximum voltage value in the level-shifted input clock signal 214-2 provided to transistor m6, and thus in the output signal 116. To this end, the input to NMOS transistor m5 may come directly from the 1V domain inverter output 114 (swinging 0V to 1V), as shown in FIG. Figure 2, and the input to the PMOS transistor m6 can be level-shifted via the coupling capacitor 238 and the voltage controller circuit 232 to provide, for example, a maximum switching voltage of 1.4V, and an ideal minimum switching voltage of 1.4V-1V=0.4V. Due to the capacitor charge redistribution, the capacitor-coupled signal swing at the output Nout of the level shifter circuit 230 can be attenuated by a ratio related to the size of the coupling capacitor 228 and the size of the capacitance on the gate of the PMOS transistor m6 plus the wiring parasitic capacitance. Thus, the signal at the output Nout of the level shifter circuit 230 can swing from 1.4V to 1.4V-0.9V=0.5V (rather than the ideal 0.4V, which would result in a 1V swing from the input Nin of the level shifter circuit 230 to the output of the level shifter circuit 230), as shown in FIG. Figure 2 As shown in the signal 214-2 shown in FIG. Figure 2 The voltage controller circuit 232 or level shifter circuit 230 shown in FIG. 2 may be referred to as a “maximum level controller” because it is configured to set a maximum voltage value for the level-shifted input clock signal 214-2. The minimum voltage value for the level-shifted input clock signal 214-2 may then be automatically adjusted based on the ratio between the capacitance of the coupling capacitor 238 and the capacitance of the load for the voltage controller circuit 232.

[0047] In a level shifter circuit (e.g., such as a P-type transistor coupled to a boost switch driver circuit) Figure 2 In some embodiments (shown in ), the high supply voltage coupled to the source terminal of the P-type transistor (i.e., transistor m6 in this case) can be substantially the same as the maximum voltage value controlled by the voltage controller circuit 232 (e.g., both can be 1.4V), although in other embodiments, these voltages can be different. In general, the value of the supply voltage coupled to the source terminal of the P-type transistor of the branch that also includes the maximum level controller (i.e., transistor m6 in this case) can correspond to (e.g., substantially equal to) the high voltage in the level-shifted input clock signal 214-2. In some embodiments of the circuit 204, the low supply voltage coupled to the source terminal of the N-type transistor of the branch that does not include the level shifter circuit (i.e., transistor m5 in this case) can be substantially the same as the minimum voltage value in the output signal 116 (e.g., both can be 0V), although in other embodiments, these voltages can be different (e.g., in the case of including a second level shifter circuit, such as Figure 6 ).

[0048] In various embodiments, the level shifter circuit 230 may be implemented in any manner that allows careful control of the maximum value of the level-shifted input clock signal 214-2 to be provided to the P-type transistor m6. An example is shown in Figure 3 However, in other embodiments of circuit 204, level shifter circuit 230 may be implemented differently. Figure 3 A circuit diagram of an example level shifter circuit 300 is provided according to some embodiments of the present disclosure, which can be used with or in a boost switch driver, for example, as the level shifter circuit 230 of the boost switch driver 204, to perform level shifting in a situation where a maximum / high signal level is controlled.

[0049] like Figure 3 , the level shifter circuit 300 may include a pair of cross-coupled transistors m1 and m2. Transistors m1 and m2 are cross-coupled because the gate terminal of transistor m1 is coupled to the drain terminal of transistor m2 and the gate terminal of transistor m2 is coupled to the drain terminal of transistor m1. The source terminal of each of transistors m1 and m2 is coupled to a reference voltage 234, which is provided to the level shifter circuit 300 to control the maximum voltage level set by the level shifter circuit 300. When the level shifter circuit 300 is a maximum level controller ( Figure 3 ), transistors m1 and m2 may be P-type transistors, for example, as in Figure 3 and a PMOS transistor shown in subsequent figures of the maximum level controller. In addition, when the level shifter circuit 300 is a maximum level controller, the value of the reference voltage 234 can be configured to correspond to a high voltage in the level-shifted input clock signal 214-2 output by the circuit. In some embodiments, the reference voltage 234 can be substantially the same as the supply voltage to which the source terminal of the transistor m6 is coupled (e.g., for Figure 2 and Figure 3 In the example shown in , both can be approximately 1.4V) and can come from the same voltage source.

[0050] like Figure 3As further shown in , the level shifter circuit 300 may also include a pair of capacitors C1 and C2, and an inverter Inv coupled between the capacitors, for example by coupling an input of the inverter Inv to a first capacitor electrode of the capacitor C1 and coupling an output of the inverter Inv to a first capacitor electrode of the capacitor C2. A second capacitor electrode of the capacitor C1 may be coupled to a drain terminal of the transistor m1, and a second capacitor electrode of the capacitor C2 may be coupled to a drain terminal of the transistor m2. An input to the level shifter circuit 300 may be applied / provided to a node Nin, which is coupled to the first capacitor electrode of the capacitor C1 and the input of the inverter Inv, as shown in FIG. Figure 3 , and may be the input signal 114. The level shifter circuit 300 may generate an output signal from an output node Nout, which is coupled to one or more of the second capacitor electrode of the capacitor C1, the drain terminal of the transistor m1, and the gate terminal of the transistor m2. The output signal from the output node Nout may be the level-shifted input clock signal 214-2 as described above, and may drive a load coupled to the output node Nout (at Figure 3 Capacitor C Load express).

[0051] Since the level shifter circuit 300 is a maximum level controller, the reference voltage 234 applied to the source terminals of the transistors m1 and m2 can accurately control the maximum / high level of the output voltage of the signal 214-2 (e.g., ensure that the level is about 1.4V). The minimum / low level of the output voltage of the signal 214-2 can then be determined based on the capacitor C1 and the load capacitance C Load The voltage swing of the output signal 214-2 can be based on the value of the reference voltage 234 provided to the level shifter circuit 300 and based on the capacitor C1 and the load capacitance C Load Charge redistribution between capacitors.

[0052] Figure 4 A circuit diagram is provided of an example circuit 400 having a boost switch driver with a transistor m6 on one side using a Figure 3 The circuit 400 may be viewed as an example of the circuit 200, wherein the level shifter circuit 230 is implemented as the level shifter circuit 300, and thus (in Figure 4 ) is replaced by the level shifter circuit 300. Figure 4 In, used for Figures 1 to 3 The circuit reference numbers are used to refer to the Figures 1 to 3The same or functionally similar elements shown in FIG. 1 are not necessarily the same or functionally similar elements as those shown in FIG. 1 , so that the description of those elements is no longer specific to the Figure 4 Repeat. In addition, Figure 3 Various components of the level shifter circuit 300 shown in FIG. 1 and described above, such as transistors m1 and m2, capacitors C1 and C2, and inverter Inv, are also shown in FIG. Figure 4 In order to clearly show how the level shifter circuit 300 of this embodiment replaces Figure 2 The level shifter circuit 230 shown in FIG. Figure 4 In the embodiment of the present invention, the coupling capacitor 238 of the level shifter circuit 230 is implemented by the capacitor C1 of the level shifter circuit 300. In the context of the circuit 400, Figure 4 . The input node Nin and the output node Nout of the level shifter circuit 300 are shown in FIG.

[0053] Figure 5 A circuit diagram of an example circuit 500 having a boost switch driver with level shifting in a branch of a P-type transistor (i.e., transistor m6 for the example shown) and having an additional transistor provided as a cascode transistor to an N-type transistor of another branch (i.e., transistor m5 for the example shown) according to some embodiments of the present disclosure is provided. Circuit 500 may be viewed as a further embodiment of circuit 400, wherein, similar to circuit 400, level shifter circuit 230 is implemented as level shifter circuit 300, and thus in Figure 5 In the schematic illustration of , the level shifter circuit 300 is replaced. Figure 5 In, used for Figures 1 to 4 The circuit reference numbers are used to refer to the Figures 1 to 4 The same or functionally similar elements as those shown in FIG. Figure 5 The circuit 500 is different from the circuit 400 in that the circuit 500 further includes an additional transistor m7 provided as a common-source common-gate transistor to the transistor m5 described above. To this end, the transistors m5 and m7 may be transistors of the same type (for example, both are N-type transistors, such as Figure 5 ). The cascode transistor m7 can be considered as part of the first branch 226-1. Figure 5, the drain terminal of transistor m5 may be coupled to output 224 by coupling the drain terminal of transistor m5 to the source terminal of cascode transistor m7 and coupling the drain terminal of cascode transistor m7 to output 224. In various embodiments, the gate terminal (e.g., gate terminal) of cascode transistor m7 may be coupled to a suitable reference voltage 534. For example, for embodiments where cascode transistor m7 is an N-type transistor as shown (i.e., for embodiments where the level shifter circuit included in circuit 500 is a maximum level controller), reference voltage 534 may be substantially 1 V. However, in other embodiments, the value of reference voltage 534 may be different.

[0054] although Figure 5 Only one cascode transistor m7 is shown in FIG. Figure 5 In other embodiments of the circuit shown in FIG. 2 , more than one cascode transistor m7 may be included in the first branch 226 - 1 . Figure 5 Combination Figure 3 The level shifter circuit 300 shows a cascode transistor m7, but in Figure 2 In a further embodiment of the circuit 200 shown in FIG. 1 , the first branch 226-1 of the circuit 200 may include at least one such cascode transistor m7, wherein the level shifter circuit 230 may but need not be implemented as the level shifter circuit 300. In addition, any of the embodiments of the boost switch driver having a level shift in the branch of the P-type transistor (e.g., referring to FIG. 1 ) may include at least one such cascode transistor m7. Figures 1 to 6 In any of the described embodiments, one or more additional transistors m8 (not specifically shown in the figures) may be provided as cascode transistors to transistor m6 (i.e., as P-type transistors provided to the level shifter circuit as cascode transistors). To this end, transistors m6 and m8 may be transistors of the same type (e.g., both are P-type transistors), and one or more cascode transistors m8 may be part of the second branch 226-2. For example, the gate terminal of such cascode transistor m8 may be coupled to a ground potential; the source terminal of transistor m8 may be coupled to the drain terminal of transistor m6; and the drain terminal of cascode transistor m8 may be coupled to the output 224.

[0055] Figure 6 A circuit diagram of an example circuit 600 having a boost switch driver with a level shift in a branch of a P-type transistor and having an additional level shifter circuit configured to control a minimum / low level according to some embodiments of the present disclosure is provided. Circuit 600 may be viewed as a further embodiment of circuit 500, wherein, similar to circuit 500, level shifter circuit 230 is implemented as level shifter circuit 300, and thus (in Figure 6) is replaced by the level shifter circuit 300. Also similar to the circuit 500, the circuit 600 further includes a cascode transistor m7. Figure 6 In, used for Figures 1 to 5 The circuit reference numbers are used to refer to the Figures 1 to 5 The same or functionally similar elements as those shown in FIG. Figure 6 Circuit 600 differs from circuit 500 in that circuit 600 further includes an additional level shifter circuit 630 configured to control a minimum / low level of an output signal from circuit 600. Therefore, circuit 630 may be referred to as a "minimum level controller".

[0056] In some embodiments, the additional level shifter circuit 630 may be implemented in a manner similar to the level shifter circuit 300 , except that the P-type transistors m1 and m2 of the level shifter circuit 300 are replaced by N-type transistors in the level shifter circuit 630 to control the minimum / low level of the output signal from the level shifter circuit 630 . Fig. 9 A more detailed description of this circuit is provided (ie, the additional level shifter circuit 630 may be implemented as Fig. 9 ). The level shifter circuit 900 shown in FIG.

[0057] like Figure 6 , the level shifter circuit 630 may include a pair of cross-coupled transistors m1 and m2. Transistors m1 and m2 are cross-coupled because the gate terminal of transistor m1 is coupled to the drain terminal of transistor m2 and the gate terminal of transistor m2 is coupled to the drain terminal of transistor m1. The source terminal of each of transistors m1 and m2 is coupled to a reference voltage 634, which is provided to the level shifter circuit 630 to control the minimum voltage level set by the level shifter circuit 630. When the level shifter circuit 630 is a minimum level controller, transistors m1 and m2 may be N-type transistors, for example, as in Figure 6 and NMOS transistors shown in subsequent figures of minimum level controllers. In addition, when level shifter circuit 630 is a minimum level controller, the value of reference voltage 634 can be configured to correspond to a low voltage in level-shifted clock signal 616 output by circuit 630.

[0058] like Figure 6As further shown in , the level shifter circuit 630 may also include a pair of capacitors C1 and C2, and an inverter Inv coupled between the capacitors, for example, by coupling an input of the inverter Inv to a first capacitor electrode of the capacitor C1 and coupling an output of the inverter Inv to a first capacitor electrode of the capacitor C2. A second capacitor electrode of the capacitor C1 may be coupled to the switch 106 to be driven by the switch driver 600, while a second capacitor electrode of the capacitor C2 may be coupled to the drain terminal of the transistor m2 (and correspondingly to the gate terminal of the transistor m1, since the drain terminal of the transistor m2 is coupled to the gate terminal of the transistor m1).

[0059] The input to the level shifter circuit 630 may be applied / provided to a node Nin of the circuit 630, which is coupled to a first capacitor electrode of the capacitor C1 and, in some embodiments, to an input of the inverter Inv, such as Figure 6 In some embodiments, the input to the level shifter circuit 630 may be based on the output signal 116 from the boost switch driver circuit 204, i.e., for Figure 6, based on a signal from 0V to 1.4V. The level shifter circuit 630 may generate an output signal from an output node Nout of the circuit 630, which is coupled to one or more of the second capacitor electrode of the capacitor C1, the drain terminal of the transistor m1, and the gate terminal of the transistor m2. The output signal 616 from the output node Nout of the level shifter circuit 630 may be a level-shifted version of the input signal (e.g., signal 116) provided at the input node Nin of the level shifter circuit 630, where the minimum / low value of the signal is carefully controlled based on the reference signal 634. For example, if the input signal provided at the input node Nin of the level shifter circuit 630 is the signal 116 having minimum and maximum voltage values ​​of 0V and 1.4V, respectively, as described above, the level shifter circuit 630 may shift these values ​​by approximately 0.5V (i.e., the value of the reference voltage 634). In particular, the level shifter circuit 630 is configured to carefully control the value to which the minimum voltage value is shifted based on the reference voltage 634, i.e., for the example shown, the minimum voltage value is shifted from 0V to 0.5V. Ideally, the maximum switch voltage would be 1.4V+0.5V=1.9V. However, similar to the maximum voltage controller, due to capacitor charge redistribution, the capacitor-coupled signal swing at the output Nout of the level shifter circuit 630 may be attenuated by a ratio related to the size of the coupling capacitor C1 of the level shifter circuit 630 and the size of the capacitance on the gate of the transistor that may implement the switch 106 plus the wiring parasitic capacitance. Thus, the signal at the output Nout of the level shifter circuit 630 may swing from 0.5V to 0.5V+1.3V=1.8V (rather than the ideal 1.9V, which would result in a 1.4V swing from the input Nin of the level shifter circuit 630 to the output Nout of the level shifter circuit 630), as shown in FIG. Figure 6 6. Thus, the level shifter circuit 630 can carefully control the minimum / low value of the level-shifted clock signal 616 based on the reference signal 634, while the maximum / high voltage value of the level-shifted clock signal 616 can then be automatically adjusted based on the ratio between the capacitance of the coupling capacitor C1 of the level shifter circuit 630 and the capacitance of the load (including parasitic capacitance) for the level shifter circuit 630. In other words, since the level shifter circuit 630 is a minimum level controller, the reference voltage 634 applied to the source terminals of the transistors m1 and m2 of the level shifter circuit 630 can accurately control the minimum / low level of the output voltage of the signal 616 (e.g., ensure that the level is approximately 0.5V). The maximum / high level of the output voltage of the signal 616 can then be automatically adjusted based on the ratio between the capacitance of the coupling capacitor C1 of the level shifter circuit 630 and the capacitance of the load for the level shifter circuit 630 (including parasitic capacitance). LoadThe voltage swing of the output signal 616 can be established by the capacitor charge redistribution between the level shifter circuit 300 and the load capacitance C1 of the level shifter circuit 630, which is based on the ratio of these capacitances. Therefore, the voltage swing of the output signal 616 can be based on the value of the reference voltage 234 provided to the level shifter circuit 300, the value of the reference voltage 634 provided to the level shifter circuit 630, and the capacitor C1 of the level shifter circuit 630 and the load capacitance C1 of the level shifter circuit 630. Load Charge redistribution between capacitors.

[0060] Despite Figure 6 6, but in other embodiments of the circuit 630, the input to the inverter Inv of the level shifter circuit 630 may be based on an inverted version of the input signal 114 provided to the input 222, rather than from the Figure 6 . In such embodiments, the inverter of the level shifter circuit 630 may be decoupled from the signal 116, but instead coupled to an inverted version of the signal 114, which may be advantageous in situations where driving the inverter of the level shifter circuit 630 with a signal having a signal swing greater than about 1 V may be unreliable. In such embodiments, one of the capacitor electrodes of the capacitor C1 of the level shifter circuit 630 is still driven by the signal 116, so that the level shifter circuit 630 may then generate an output signal provided at an output node Nout of the level shifter circuit 630 as a level-shifted version of the signal 116 provided at an input node Nin of the level shifter circuit 630, wherein the minimum / low value of the signal is carefully controlled based on the reference signal 634.

[0061] Figure 6 FIG. 6 is a diagram showing one way in which the level shifter circuit 630 may be implemented to provide control of the minimum / low level of the output voltage of the signal 616 as described above. In other embodiments of the circuit 600, the level shifter circuit 630 may be configured to provide control of the minimum / low level of the output voltage of the signal 616 as described above. Figure 6 Any other implementation than that shown in will suffice as long as it provides sufficiently accurate control of the minimum / low level of the output voltage of signal 616, with the maximum / high level being adjusted accordingly.

[0062] Although Figure 6 Combination Figure 3 The level shifter circuit 300 shows an additional level shifter circuit 630, but in Figure 2 In a further embodiment of the circuit 200 shown in FIG. 1 , an additional level shifter circuit 630 may be included to receive the signal 116 as an input and generate an output 616, as shown in FIG. Figure 6 As described above, the level shifter circuit 230 may, but need not, be implemented as the level shifter circuit 300. Figure 6 Combination Figure 5The cascode transistor m7 shows an additional level shifter circuit 630, but in Figure 2 In a further embodiment of the circuit 200 shown in FIG. 1 , the circuit 200 may include a circuit 200 as shown in FIG. Figure 6 The additional level shifter circuit 630 is described without the cascode transistor m7. Figure 2 In a further embodiment of the circuit 200 shown in FIG. 1 , the circuit 200 may include a circuit 200 as shown in FIG. Figure 6 The additional level shifter circuit 630 described herein does not have the cascode transistor m7, and wherein the level shifter circuit 230 is implemented differently from the level shifter circuit 300. In any of these embodiments, the level shifter circuit 630 may be implemented in addition to the cascode transistor m7. Figure 6 Any other implementation than that shown in will suffice as long as it provides sufficiently accurate control of the minimum / low level of the output voltage of signal 616 as described above.

[0063] Still further, although Figure 6 6 shows a level shifter circuit 630 configured to provide control of the minimum / low level of the output voltage of the signal 616 as described above, but in other embodiments, the level shifter circuit 630 may be replaced with a level shifter circuit 630′ configured to provide control of the maximum / high level of the output voltage of the signal 616 ( Figure 6 In some such embodiments, to implement the level shifter circuit 630', Figure 6 The level shifter circuit 630 shown in FIG. 6 may be replaced with other examples of the level shifter circuit 300, or equivalently, Figure 6 The NMOS transistor of the level shifter circuit 630 shown in FIG. 6 can be replaced with a PMOS transistor, and the reference voltage 634 can be replaced with a reference voltage 634′ configured to accurately control the maximum / high level of the output voltage of the signal 616 (also not shown in FIG. 6 ). Figure 6 , but reference numbers are used here for ease of description).

[0064] The input to the level shifter circuit 630' may be applied / provided to a node Nin of the circuit 630', which is coupled to a first capacitor electrode of capacitor C1 and, in some embodiments, to an input of an inverter Inv, such as Figure 6 In some embodiments, the input to the level shifter circuit 630' may be based on the output signal 116 from the boost switch driver circuit 204, i.e., for Figure 6, based on a signal from 0V to 1.4V. The level shifter circuit 630' may generate an output signal from an output node Nout of the circuit 630', which is coupled to one or more of the second capacitor electrode of the capacitor C1, the drain terminal of the transistor m1, and the gate terminal of the transistor m2. The output signal 616 from the output node Nout of the level shifter circuit 630' may be a level-shifted version of the input signal (e.g., signal 116) provided at the input node Nin of the level shifter circuit 630', where the maximum / high value of the signal is carefully controlled based on the reference signal 634'. For example, if the input signal provided at the input node Nin of the level shifter circuit 630' is the signal 116 having a minimum voltage value of 0V and a maximum voltage value of 1.4V, respectively, as described above, the level shifter circuit 630' may shift these values ​​so that the maximum voltage value is 1.8V, which for this example would be the value of the reference voltage 634'. In particular, the level shifter circuit 630' is configured to carefully control the value to which the maximum voltage value is shifted based on the reference voltage 634', i.e., for the example shown, the maximum voltage value is shifted by 0.4V, from 1.4V to 1.8V. Ideally, the minimum switch voltage would be 0V+0.4V=0.4V. However, as described above with respect to the maximum voltage controller 300, due to capacitor charge redistribution, the capacitor-coupled signal swing at the output Nout of the level shifter circuit 630' may be attenuated by a ratio related to the size of the coupling capacitor C1 of the level shifter circuit 630' and the size of the capacitance on the gate of the transistor that may implement the switch 106 plus the wiring parasitic capacitance. Thus, the minimum voltage value at the output Nout of the level shifter circuit 630' may be 1.8V-1.3V=0.5V (rather than the ideal 0.4V, which would result in a 1.4V swing maintained from the input Nin of the level shifter circuit 630' to the output Nout of the level shifter circuit 630'), as shown in FIG. Figure 66. As shown in the signal 616 shown in . Therefore, the level shifter circuit 630' can carefully control the maximum / high value of the level-shifted clock signal 616 based on the reference signal 634', and the minimum / low voltage value of the level-shifted clock signal 616 can then be automatically adjusted based on the ratio between the capacitance of the coupling capacitor C1 of the level shifter circuit 630' and the capacitance of the load (including parasitic capacitance) for the level shifter circuit 630'. In other words, because the level shifter circuit 630' is a maximum level controller, the reference voltage 634' applied to the source terminals of the transistors m1 and m2 of the level shifter circuit 630' can accurately control the maximum / high level of the output voltage of the signal 616 (e.g., ensure that the level is approximately 1.8V). The minimum / low level of the output voltage of the signal 616 can then be automatically adjusted based on the ratio between the capacitor C1 of the level shifter circuit 630' and the load capacitance C1 for the level shifter circuit 630'. Load , which is based on the ratio of these capacitances. Therefore, the voltage swing of output signal 616 can be based on the value of reference voltage 234 provided to level shifter circuit 300, the value of reference voltage 634' provided to level shifter circuit 630', and the capacitor C1 of level shifter circuit 630' and the load capacitance C Load Charge redistribution between capacitors.

[0065] Similar to what is described above Figure 6 In other embodiments of the circuit 630′, the input to the inverter Inv of the level shifter circuit 630′ may be based on an inverted version of the input signal 114 provided to the input 222, rather than from the input signal 114 of the circuit 630′. Figure 6 . In such embodiments, the inverter of the level shifter circuit 630′ may be decoupled from the signal 116 and instead coupled to an inverted version of the signal 114, which may be advantageous in situations where driving the inverter of the level shifter circuit 630′ with a signal having a signal swing greater than about 1 V may be unreliable. In such embodiments, one of the capacitor electrodes of the capacitor C1 of the level shifter circuit 630′ is still driven by the signal 116, so that the level shifter circuit 630′ may then generate an output signal provided at an output node Nout of the level shifter circuit 630′ as a level-shifted version of the signal 116 provided at an input node Nin of the level shifter circuit 630′, wherein the maximum / high value of the signal is carefully controlled based on the reference signal 634′.

[0066] In other embodiments of circuit 600 , level shifter circuit 630 ′ may be implemented in any other manner than level shifter circuit 300 as long as it provides sufficiently accurate control of the maximum / high level of the output voltage of signal 616 , with the minimum / low level adjusted accordingly.

[0067] Example boost switch driver circuit with level shifting in the branch of the N-type transistor

[0068] Figure 7 A circuit diagram of an example circuit 700 is provided in which a boost switch driver with level shifting in the branch of an N-type transistor may be used according to some embodiments of the present disclosure. Figure 7 , circuit 700 may include a series of first inverters 702 and second inverters 704 coupled to switch 706. First inverter 702 may be substantially similar to first inverter 102, configured to receive signal 712 (similar to signal 112) as input and generate signal 714 (similar to signal 714) as output. The description provided above with reference to first inverter 102, input signal 112, and output signal 114 applies to inverter 702, input signal 712, and output signal 714, respectively, and therefore is not repeated for the sake of brevity.

[0069] The first inverter 702 may be configured to drive the second inverter 104, which may include any of the boost switch drivers described herein with level shifting performed in the branches of the N-type transistors. The second inverter 704 may be a boost switch driver that is powered up (i.e., configured to increase the output swing). This Figure 7 In FIG. 1 , the second inverter 704 receives a signal having an output swing of 1 V (ie, small graph 714) and outputs an inverted version of the signal having a larger output swing. Figure 7 7 is shown as a signal 716 (shown schematically within the dashed box labeled "716") still having a high voltage value of 1V, but now having a low voltage value of -0.4V. The output of the second inverter 704 may then be used to drive a switch 706, which in some embodiments may be implemented as Figure 7 The transistor shown in .

[0070] In various embodiments, the inverter may include any of the boost switch driver circuits with level shift in the branch of the N-type transistor presented herein. In various embodiments, the signals 712, 714, 716 may be different, for example, the signals may have different high values ​​and low values. Similarly, the low supply voltage and the high supply voltage coupled to each of the first inverter 702 and the second inverter 704 may be different in different embodiments in which any of the boost switch driver circuits with level shift in the branch of the N-type transistor presented herein is used to implement the second inverter 704. Moreover, in further embodiments, the inverter 704 including any of the boost switch driver circuits with level shift in the branch of the N-type transistor presented herein may be included in a circuit other than the circuit 700, and in particular, may but need not be implemented together with the first inverter 702, such as Figure 7 As shown in .

[0071] Figure 8 A circuit diagram of an example circuit 800 having a boost switch driver with a level shift on one side of an N-type transistor according to some embodiments of the present disclosure is provided. Circuit 800 can be considered an example of circuit 700, where the boost switch driver is used to Figure 7 The reference numbers of the circuit 700 are used to refer to the circuits 700 and 700 of the embodiment of Figure 8 Those elements shown in circuit 800 are identical or functionally similar elements, so the description of these elements provided with respect to one figure is not repeated with respect to the other figure, and only the differences are described.

[0072] like Figure 8 As shown in FIG. 1 , in some embodiments, the first inverter 702 may be implemented as a pair of complementary transistors m3, m4 (ie, one of the transistors is N-type and the other is P-type), similar to Figure 2 The implementation scheme of the first inverter 102 shown in FIG. Figure 2 The description of the first inverter shown in FIG. 7 is applicable to the first inverter 702 and is therefore not repeated for the sake of brevity. The output clock signal 714 of the first inverter 702 can be used as the basis for the input clock signal to the second inverter 704.

[0073] Figure 8 Further shown is a boost switch driver circuit 804, which may be, for example, an example of the second inverter 704 described above. Figure 8 As shown in FIG. 8 , circuit 804 may include an input 822, an output 824, and two branches 826 between input 822 and output 824. The first branch, at Figure 8 The second branch is schematically indicated by the dot-dash line 826-1, which may include transistor m5. Figure 8As schematically indicated by dashed line 826-2 in FIG. 8 , transistor m6 and level shifter circuit 830 may be included. Again, one of transistors m5 and m6 may be an N-type transistor and the other may be a P-type transistor. Figure 8 An embodiment is shown with level shifting done on one side of an N-type transistor, so transistor m6 is an N-type transistor (e.g., an NMOS transistor, as in Figure 8 ), while transistor m5 is a P-type transistor (e.g., a PMOS transistor, as shown in Figure 8 826-2). The circuit 804 may be configured to split an input clock signal (e.g., signal 714) between a first branch 826-1 and a second branch 826-2 such that a portion of the input clock signal 714 split into the first branch 826-1 is provided to the transistor m5 of the branch and a portion of the input clock signal split into the second branch 826-2 is level-shifted by the level shifter circuit 830 to generate a level-shifted signal 814-2, and the level-shifted signal 814-2 is provided to the transistor m6. Figure 8 814-1 is provided to transistor m5 (i.e., the gate terminal of transistor m5) and signal 814-2 is provided to transistor m6 (i.e., the gate terminal of transistor m6). Signal 814-1 is similar to signal 714 in its voltage swing (e.g., from about 0V to about 1V, as shown for Figure 8 ), while signal 814-2 may be substantially the same in terms of voltage swing from about -0.4V to about 0.5V compared to signal 714. Circuit 804 is further configured to combine the output of transistor m5 (e.g., the output from the drain terminal of transistor m5) with the output of transistor m6 (e.g., the output from the drain terminal of transistor m6) to generate output clock signal 716. Thus, the gate terminal of each of transistors m5 and m6 may be coupled to input 822, except that the gate terminal of transistor m6 is coupled to input 822 via a level shifter circuit 830 configured to perform level shifting before providing the signal to transistor m6. Similarly, the drain terminal of each of transistors m5 and m6 may be coupled to output 824, which may be coupled to switch 706 to be driven by switch driver circuit 804.

[0074] In some embodiments, the level shifter circuit 830 may include a voltage controller circuit 832 that may be configured to receive a reference signal 834 as an input and generate an output 836, such as Figure 8. In addition, the level shifter circuit 830 may further include a coupling capacitor 838 coupled to the voltage controller circuit 832. For example, a first capacitor electrode of the coupling capacitor 838 may be coupled to the input 822, and a second capacitor electrode of the coupling capacitor 838 may be coupled to each of the voltage controller circuit 832 and the gate terminal of the transistor m6. In other words, a portion of the input clock signal 714 split to the second branch 826-2 of the circuit 804 may be configured to be applied to the first capacitor electrode of the coupling capacitor 838, and a second capacitor electrode of the coupling capacitor 838 may be coupled to each of the output 836 of the voltage controller circuit 832 and the gate terminal of the transistor m6. The input 834 to the voltage controller circuit 832 may be a reference voltage or any other control signal configured to control the minimum voltage level set by the voltage controller circuit 832. The output 836 from the voltage controller circuit 832 may form the basis for the level-shifted input clock signal 814-2 to be provided to the gate terminal of the transistor m6.

[0075] When the transistor m6 is an N-type transistor, Figure 8 As shown in the embodiment of FIG. 8 , the voltage controller circuit 832 may be configured to control the minimum voltage value in the level-shifted input clock signal 814-2 provided to transistor m6, and thus in the output signal 716. To this end, the input to the PMOS transistor m5 may come directly from the 1V domain inverter output 114 (swinging 0V to 1V), as shown in FIG. Figure 8 814-1 shown in FIG. 814-1, and the input to the NMOS transistor m6 can be level-shifted via the coupling capacitor 838 and the voltage controller circuit 832 to provide, for example, a minimum switching voltage of -0.4V, and an ideal maximum switching voltage of -0.4V+1V=0.6V. Due to the capacitor charge redistribution, the capacitor-coupled signal swing at the output Nout of the level shifter circuit 830 can be attenuated by a ratio related to the size of the coupling capacitor 828 and the size of the capacitance on the gate of the NMOS transistor m6 plus the wiring parasitic capacitance. Thus, the signal at the output Nout of the level shifter circuit 830 can swing from -0.4V to -0.4V+0.9V=0.5V (rather than the ideal 0.6V, which would result in a 1V swing from the input Nin of the level shifter circuit 830 to the output Nout of the level shifter circuit 830), as shown in FIG. Figure 8 As shown in the signal 814-2 shown in FIG. Figure 8The voltage controller circuit 832 or level shifter circuit 830 shown in FIG. 8 may be referred to as a “minimum level controller” because the voltage controller circuit or the level shifter circuit is configured to set a maximum voltage value for the level-shifted input clock signal 814-2. The maximum voltage value for the level-shifted input clock signal 814-2 may then be automatically adjusted based on the ratio between the capacitance of the coupling capacitor 838 and the capacitance of the load for the voltage controller circuit 832.

[0076] In some embodiments of a level shifter circuit of an N-type transistor coupled to a boost switch driver circuit (e.g., as shown in FIG. N), a low supply voltage coupled to a source terminal of the N-type transistor (i.e., transistor m6 in this case) may be substantially the same as a minimum voltage value controlled by the voltage controller circuit 832 (e.g., both may be -0.4V), although in other embodiments, these voltages may be different. In general, the value of the supply voltage coupled to the source terminal of the N-type transistor of the branch that also includes the minimum level controller (i.e., transistor m6 in this case) may correspond to (e.g., substantially equal to) a low voltage in the level-shifted input clock signal 814-2. In some embodiments of circuit 804, a high supply voltage coupled to a source terminal of a P-type transistor of a branch that does not include a level shifter circuit (i.e., transistor m5 in this case) may be substantially the same as a maximum voltage value in the output signal 716 (e.g., both may be 1V), although in other embodiments, these voltages may be different (e.g., in the case of a second level shifter circuit, such as Fig.12 ).

[0077] In various embodiments, the level shifter circuit 830 may be implemented in any manner that allows careful control of the minimum value of the level-shifted input clock signal 814-2 to be provided to the N-type transistor m6. An example is shown in Fig. 9 However, in other embodiments of circuit 804, level shifter circuit 830 may be implemented differently. Fig. 9 A circuit diagram of an example level shifter circuit 900 is provided according to some embodiments of the present disclosure, which can be used with or in a boost switch driver, such as the level shifter circuit 830 of the boost switch driver 804, to perform level shifting in a situation where a minimum / high signal level is controlled.

[0078] like Fig. 9, the level shifter circuit 900 may include a pair of cross-coupled transistors m1 and m2, a pair of capacitors C1 and C2, and an inverter Inv. The arrangement of the level shifter circuit 900 is substantially the same as that of the level shifter circuit 300, except that the transistors m1 and m2 are N-type transistors in the level shifter circuit 900 because the level shifter circuit 900 is a minimum level controller. The description of the coupling between the various elements of the level shifter circuit 300 is applicable to the level shifter circuit 900, and therefore is not repeated for the sake of brevity.

[0079] When the level shifter circuit 900 is a minimum level controller, the value of the reference voltage 834 can be configured to correspond to a low voltage in the level-shifted input clock signal 814-2 output by the circuit. In some embodiments, the reference voltage 834 can be substantially the same as the supply voltage to which the source terminal of transistor m6 is coupled (e.g., for Figure 8 and 9 In the example shown in , both may be approximately -0.4V) and may come from the same voltage source.

[0080] Since the level shifter circuit 900 is a minimum level controller, the reference voltage 834 applied to the source terminals of the transistors m1 and m2 can accurately control the minimum / low level of the output voltage of the signal 814-2 (e.g., ensure that the level is approximately -0.4V). The maximum / high level of the output voltage of the signal 814-2 can then be determined based on the capacitor C1 and the load capacitance C Load The voltage swing of the output signal 814-2 can be based on the value of the reference voltage 834 provided to the level shifter circuit 900 and based on the capacitor C1 and the load capacitance C Load Charge redistribution between capacitors.

[0081] Fig.10 A circuit diagram is provided of an example circuit 1000 having a boost switch driver with a branch using an N-type transistor according to some embodiments of the present disclosure. Fig. 9 The circuit 1000 may be viewed as an example of the circuit 800, wherein the level shifter circuit 830 is implemented as the level shifter circuit 900 and thus (in Fig.10 ) is replaced by the level shifter circuit 900. Fig.10 In, used for Figures 7 to 9 The circuit reference numbers are used to refer to the Figures 7 to 9 The same or functionally similar elements as those shown in FIG. Fig.10 Repeat. In addition, Fig. 9 Various components of the level shifter circuit 900 shown in FIG. 1 and described above, such as transistors m1 and m2, capacitors C1 and C2, and inverter Inv are also shown in FIG. Fig.10 In order to clarify how the level shifter circuit 900 of this embodiment replaces Figure 8 The level shifter circuit 830 shown in FIG. Fig.10 In the embodiment of the present invention, the coupling capacitor 838 of the level shifter circuit 830 is implemented by the capacitor C1 of the level shifter circuit 900. In the context of the circuit 1000, Fig.10 . The input node Nin and the output node Nout of the level shifter circuit 900 are shown in FIG.

[0082] Fig.11 A circuit diagram is provided of an example circuit 1100 having a boost switch driver with level shifting in a branch of an N-type transistor (i.e., transistor m6 for the example shown) and having an additional transistor provided as a cascode transistor to a P-type transistor of another branch (i.e., transistor m5 for the example shown) according to some embodiments of the present disclosure. Circuit 1100 may be viewed as a further embodiment of circuit 1000, wherein, similar to circuit 1000, level shifter circuit 830 is implemented as level shifter circuit 900 and thus in Fig.11 In the schematic illustration of , the level shifter circuit 900 replaces the level shifter circuit 900. Fig.11 In, used for Figures 7 to 10 The circuit reference numbers are used to refer to the Figures 7 to 10 The same or functionally similar elements as those shown in FIG. Fig.11 1000 is different from the circuit 1000 in that the circuit 1100 further includes an additional transistor m7 provided to the transistor m5 as a cascode transistor as described above. To this end, the transistors m5 and m7 may be transistors of the same type (i.e., both are P-type transistors, as in Fig.11 ). The common-source common-gate transistor m7 can be considered as part of the first branch 826-1. Fig.11, the drain terminal of transistor m5 may be coupled to output 824 by coupling the drain terminal of transistor m5 to the source terminal of cascode transistor m7 and coupling the drain terminal of cascode transistor m7 to output 224. In various embodiments, the gate terminal of cascode transistor m7 may be coupled to a suitable reference voltage 1134. For example, for embodiments where cascode transistor m7 is a P-type transistor as shown (i.e., for embodiments where the level shifter circuit included in circuit 1100 is a minimum level controller), reference voltage 1134 may be substantially 0 V. However, in other embodiments, the value of reference voltage 1134 may be different.

[0083] although Fig.11 Only one cascode transistor m7 is shown in FIG. Fig.11 In other embodiments of the circuit shown in FIG. 8 , more than one cascode transistor m7 may be included in the first branch 826 - 1 . Fig.11 Combination Fig. 9 The level shifter circuit 900 shows a cascode transistor m7, but in Figure 8 In a further embodiment of the circuit 800 shown in FIG. 8 , the first branch 826-1 of the circuit 800 may include at least one such cascode transistor m7, wherein the level shifter circuit 830 may but need not be implemented as the level shifter circuit 900. In addition, any of the embodiments of the boost switch driver having a level shift in the branch of the N-type transistor (e.g., referring to FIG. 8 ) may include at least one such cascode transistor m7. Figures 7 to 12 In any of the described embodiments), one or more additional transistors m8 (not specifically shown in the figures) may be provided as cascode transistors to transistor m6 (i.e., as N-type transistors provided to the level shifter circuit as cascode transistors). To this end, transistors m6 and m8 may be transistors of the same type (e.g., both are N-type transistors), and the one or more cascode transistors m8 may be considered to be part of the second branch 826-2. For example, the source terminal of this cascode transistor m8 may be coupled to the drain terminal of transistor m6 and the drain terminal of cascode transistor m8 may be coupled to the output 224. The gate terminal of this cascode transistor m8 may be coupled to a suitable reference voltage, for example, for embodiments where cascode transistor m8 is an N-type transistor, the suitable reference voltage is substantially 1V (due to the fact that for Figures 7 to 12 100, the transistor m6 is an N-type transistor; that is, for an embodiment in which the level shifter circuit included in the circuit 1100 is a minimum level controller). However, in other embodiments, the value of the reference voltage coupled to the gate terminal of the additional cascode transistor m8 may be different.

[0084] Fig.12A circuit diagram of an example circuit 1200 having a boost switch driver with a level shift in the branch of the N-type transistor and having an additional level shifter circuit configured to control the minimum / low level of the final output signal 1216 according to some embodiments of the present disclosure is provided. The circuit 1200 can be viewed as a further embodiment of the circuit 1100, wherein, similar to the circuit 1100, the level shifter circuit 830 coupled to the input of the transistor m5 is implemented as the level shifter circuit 900, and thus (in Fig.12 ) is replaced by the level shifter circuit 900. Also similar to the circuit 1100, the circuit 1200 further includes a cascode transistor m7. Fig.12 In, used for Figures 7 to 11 The circuit reference numbers are used to refer to the Figures 7 to 11 The same or functionally similar elements as those shown in FIG. Fig.12 The circuit 1200 is different from the circuit 1100 in that the circuit 1200 further includes Fig. 9 Another example of the level shifter circuit 900, in Fig.12 12 is labeled as a level shifter circuit 1230 configured to control the minimum / low level of the output signal 1216 from the circuit 1200 based on the reference signal 1234. Since the operation of the level shifter circuit 900 has been described in detail above, this description is not repeated here with reference to the circuit 1230. The reference signal 1234 is similar to the reference signal 834 described above, except that its value may be different for the level shifter circuit 1230. For example, if the input signal provided at the input node Nin of the level shifter circuit 1230 is the signal 716 having a minimum voltage value of -0.4V and a maximum voltage value of 1V, respectively, as described above, then the level shifter circuit 1230 may shift these values ​​by approximately 0.9V (i.e., the value of the reference voltage 1234 may be 0.5V, as described above). Fig.12). In particular, the level shifter circuit 1230 may be configured to carefully control the value to which the minimum voltage value is shifted based on the reference voltage 1234, i.e., for the example shown, the minimum voltage value is shifted from -0.4V to 0.5V. Ideally, the maximum switch voltage would be 1V+0.9V=1.9V. However, as described above for circuit 900, due to capacitor charge redistribution, the capacitor-coupled signal swing at the output Nout of the level shifter circuit 1230 may be attenuated by the ratio of the size of the coupling capacitor C1 of the level shifter circuit 1230 to the size of the capacitance on the gate of the transistor that may implement switch 706 plus the wiring parasitic capacitance. Thus, the signal at the output Nout of the level shifter circuit 1230 may swing from 0.5V to 0.5V+1.3V=1.8V (rather than the ideal 1.9V, which would result in a 1.4V swing from the input Nin of the level shifter circuit 1230 to the output Nout of the level shifter circuit 1230), as shown in FIG. Fig.12 1234. Thus, the level shifter circuit 1230 can carefully control the minimum / low value of the level-shifted clock signal 1216 based on the reference signal 1234, while the maximum / high voltage value of the level-shifted clock signal 1216 can then be automatically adjusted based on the ratio between the capacitance of the coupling capacitor C1 of the level shifter circuit 1230 and the capacitance of the load for the level shifter circuit 1230 (including parasitic capacitance). In other words, since the level shifter circuit 1230 is a minimum level controller, the reference voltage 1234 applied to the source terminals of the transistors m1 and m2 of the level shifter circuit 630 can accurately control the minimum / low level of the output voltage of the signal 1216 (e.g., ensure that the level is approximately 0.5V). The maximum / high level of the output voltage of the signal 1216 can then be automatically adjusted based on the ratio between the capacitance of the coupling capacitor C1 of the level shifter circuit 1230 and the capacitance of the load for the level shifter circuit 1230 (including parasitic capacitance). Load The voltage swing of the output signal 1216 can be established based on the value of the reference voltage 834 provided to the level shifter circuit 900, the value of the reference voltage 1234 provided to the level shifter circuit 1230, and the capacitor C1 of the level shifter circuit 1230 and the load capacitance C of the level shifter circuit 1230. Load Charge redistribution between capacitors.

[0085] although Fig.12 1230, but in other embodiments of the circuit 1230, the input to the inverter Inv of the level shifter circuit 1230 may be based on an inverted version of the input signal 714 provided to the input 822, rather than from Fig.12824 shown in . In such embodiments, the inverter of the level shifter circuit 1230 may be decoupled from the signal 716 and instead coupled to an inverted version of the signal 714, which may be advantageous in situations where driving the inverter of the level shifter circuit 1230 with a signal having a signal swing greater than about 1 V may be unreliable. In such embodiments, one of the capacitor electrodes of the capacitor C1 of the level shifter circuit 1230 is still driven by the signal 716, so that the level shifter circuit 1230 may then generate an output signal provided at an output node Nout of the level shifter circuit 1230 as a level-shifted version of the signal 716 provided at an input node Nin of the level shifter circuit 1230, wherein the minimum / low value of the signal is carefully controlled based on the reference signal 1234.

[0086] Fig.12 One way of illustrating how the level shifter circuit 1230 may be implemented to provide control of the minimum / low level of the output voltage of the signal 1216 as described above is shown. In other embodiments of the circuit 1200, the level shifter circuit 1230 may be replaced by any circuit configured to provide sufficiently accurate control of the minimum / low level of the output voltage of the signal 1216, with the maximum / high level adjusted accordingly.

[0087] Although Fig.12 Combination Fig. 9 The level shifter circuit 900 shows an additional level shifter circuit 1230, but in Figure 8 In a further embodiment of the circuit 800 shown in FIG. 1 , an additional level shifter circuit 1230 may be included to receive the signal 716 as an input and generate an output 1216, as shown in FIG. Fig.12 As described above, the level shifter circuit 830 may, but need not, be implemented as the level shifter circuit 900. Fig.12 Combination Fig.11 The cascode transistor m7 shows an additional level shifter circuit 1230, but in Figure 8 In a further embodiment of the circuit 800 shown in FIG. 8 , the circuit 800 may include a circuit 800 as shown in FIG. Fig.12 The additional level shifter circuit 1230 is described without the cascode transistor m7. Figure 8 In a further embodiment of the circuit 800 shown in FIG. 8 , the circuit 800 may include a circuit 800 as shown in FIG. Fig.12 The additional level shifter circuit 1230 described herein does not have the cascode transistor m7 and wherein the level shifter circuit 830 is implemented differently from the level shifter circuit 900. In any of these embodiments, the level shifter circuit 1230 may be implemented in addition to the cascode transistor m7. Fig.12Any other implementation than that shown in will suffice as long as it provides sufficiently accurate control of the minimum / low level of the output voltage of signal 1216 as described above.

[0088] Still further, although Fig.12 The level shifter circuit 1230 is shown as being configured to provide control of the minimum / low level of the output voltage of the signal 1216 as described above, but in other embodiments, the level shifter circuit 1230 may use a level shifter circuit 1230′ (not shown) configured to provide control of the maximum / high level of the output voltage of the signal 1216. Fig.12 In some such embodiments, to implement the level shifter circuit 1230', Fig.12 The level shifter circuit 1230 shown in FIG. 1 may be replaced with the level shifter circuit 300, or equivalently, Fig.12 The NMOS transistor of the level shifter circuit 1230 shown in FIG. 1 may be replaced with a PMOS transistor, and the reference voltage 1234 may be configured to accurately control the maximum / high level of the output voltage of the signal 1216 using a reference voltage 1234′ ( Fig.12 , but the reference numbers are used here for convenience of explanation).

[0089] The input to the level shifter circuit 1230' may be applied / provided to a node Nin of the circuit 1230', which is coupled to a first capacitor electrode of capacitor C1 and, in some embodiments, to an input of an inverter Inv, such as Fig.12 In some embodiments, the input to the level shifter circuit 1230' may be based on the output signal 716 from the boost switch driver circuit 204, i.e., for Fig.12, based on a signal from -0.4V to 1V. The level shifter circuit 1230' may generate an output signal from an output node Nout of the circuit 1230', which is coupled to one or more of the second capacitor electrode of the capacitor C1, the drain terminal of the transistor m1, and the gate terminal of the transistor m2. The output signal 1216 from the output node Nout of the level shifter circuit 1230' may be a level-shifted version of the input signal (e.g., signal 716) provided at the input node Nin of the level shifter circuit 1230', where the maximum / high value of the signal is carefully controlled based on the reference signal 1234'. For example, if the input signal provided at the input node Nin of the level shifter circuit 1230' is the signal 716 having a minimum voltage value of -0.4V and a maximum voltage value of 1V, respectively, as described above, the level shifter circuit 1230' may shift these values ​​so that the maximum voltage value is 1.8V, which for this example would be the value of the reference voltage 1234'. In particular, the level shifter circuit 1230' is configured to carefully control the value by which the maximum voltage value is shifted based on the reference voltage 1234', i.e., for the example shown, the maximum voltage value is shifted by 0.8V, from 1V to 1.8V. Ideally, the minimum switch voltage would be -0.4V+0.8V=0.4V. However, as described above for the maximum voltage controller 300, due to capacitor charge redistribution, the capacitor-coupled signal swing at the output Nout of the level shifter circuit 1230' may be attenuated by the ratio of the size of the coupling capacitor C1 of the level shifter circuit 1230' to the size of the capacitance on the gate of the transistor that may implement the switch 706 plus the wiring parasitic capacitance. Thus, the minimum voltage value at the output Nout of the level shifter circuit 1230' may be 1.8V-1.3V=0.5V (instead of the ideal 0.4V, which would result in a 1.4V swing from the input Nin of the level shifter circuit 1230' to the output Nout of the level shifter circuit 1230'), as shown in FIG. Fig.12. Thus, the level shifter circuit 1230' can carefully control the maximum / high value of the level-shifted clock signal 1216 based on the reference signal 1234', and the minimum / low voltage value of the level-shifted clock signal 1216 can then be automatically adjusted based on the ratio between the capacitance of the coupling capacitor C1 of the level shifter circuit 1230' and the capacitance of the load (including parasitic capacitance) for the level shifter circuit 1230'. In other words, since the level shifter circuit 1230' is a maximum level controller, the reference voltage 1234' applied to the source terminals of the transistors m1 and m2 of the level shifter circuit 1230' can accurately control the maximum / high level of the output voltage of the signal 1216 (e.g., ensure that the level is approximately 1.8V). The minimum / low level of the output voltage of the signal 1216 can then be automatically adjusted based on the ratio between the capacitor C1 of the level shifter circuit 1230' and the capacitance C2 of the load for the level shifter circuit 1230'. Load The voltage swing of the output signal 1216 can be established based on the value of the reference voltage 834 provided to the level shifter circuit 900, the value of the reference voltage 1234' provided to the level shifter circuit 1230', and the capacitor C1 of the level shifter circuit 1230' and the load capacitance C Load Charge redistribution between capacitors.

[0090] Similar to what is described above Fig.12 In other embodiments of the circuit 1230′, the input to the inverter Inv of the level shifter circuit 1230′ may be based on an inverted version of the input signal 714 provided to the input 822, rather than from the input signal 714 of FIG. Fig.12 824 shown in . In such embodiments, the inverter of the level shifter circuit 1230′ may be decoupled from the signal 716 and instead coupled to an inverted version of the signal 714, which may be advantageous in situations where driving the inverter of the level shifter circuit 1230′ with a signal having a signal swing greater than about 1 V may be unreliable. In such embodiments, one of the capacitor electrodes of the capacitor C1 of the level shifter circuit 1230′ is still driven by the signal 716, so that the level shifter circuit 1230′ may then generate an output signal provided at an output node Nout of the level shifter circuit 1230′ as a level-shifted version of the signal 716 provided at the input node Nin of the level shifter circuit 1230′, wherein the maximum / high value of the signal is carefully controlled based on the reference signal 1234′.

[0091] In other embodiments of circuit 1200 , level shifter circuit 1230 ′ may be implemented in any other manner than level shifter circuit 300 as long as it provides sufficiently accurate control of the maximum / high level of the output voltage of signal 1216 , with the minimum / low level adjusted accordingly.

[0092] Example Systems and Apparatus

[0093] The boost switch driver circuits or portions thereof as described herein (e.g., only portions of the inverter circuits 104 and / or 704 as described herein) may be included in any suitable system, device, or apparatus. For example, in some embodiments, any of the boost switch drivers or portions thereof may be included in the Fig.13 In other embodiments, any of the boost switch drivers or portions thereof may be included in a larger system or device configured to perform analog-to-digital conversion. Some examples of such systems and devices are shown in Fig.14 and 15 Other examples of systems and devices incorporating one or more of the boost switch drivers described herein are possible and within the scope of the present disclosure.

[0094] Fig.13 A schematic illustration of an example component 1300 (e.g., an ADC) in which one or more boost switch drivers 1310 may be implemented according to some embodiments of the present disclosure is provided. The one or more boost switch drivers 1310 may include any of the boost switch driver circuits described above, for example, with reference to Figures 1 to 12 Any of the embodiments of the boost switch drivers described. One or more boost switch drivers 1310 may be configured to drive one or more switches 1320. In some embodiments, there may be a one-to-one correspondence between one or more boost switch drivers 1310 and one or more switches 1320 (i.e., each boost switch driver 1310 may be configured to drive only one of the switches 1320 and each of the switches 1320 may be configured to be driven by only one of the boost switch drivers 1310). In other embodiments, a single boost switch driver 1310 may drive more than one of the switches 1320 and / or a single switch of the switches 1320 may be driven by more than one of the boost switch drivers 1310.

[0095] Fig.14 is a block diagram of an example system 2100 (e.g., a computing device) that may include one or more boost switch drivers according to any of the embodiments disclosed herein. For example, any suitable one of the components of system 2100 may include one or more of the boost switch drivers disclosed herein. Fig.14Several components are shown as included in system 2100, but any one or more of these components may be omitted or duplicated depending on the application. In some embodiments, some or all of the components included in system 2100 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single system on chip (SoC) die.

[0096] Additionally, in various embodiments, the system 2100 may not include Fig.14 , but the system 2100 may include interface circuitry for coupling to the one or more components. For example, the system 2100 may not include the display device 2106, but may include display device interface circuitry (e.g., connector and driver circuitry) to which the display device 2106 can be coupled. In another set of examples, the system 2100 may not include an audio input device 2118 or an audio output device 2108, but may include audio input or output device interface circuitry (e.g., connector and supporting circuitry) to which the audio input device 2118 or the audio output device 2108 can be coupled.

[0097] The system 2100 may include a processing device 2102 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from a temporary register and / or memory to transform the electronic data into other electronic data that can be stored in the temporary register and / or memory. The processing device 2102 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The system 2100 may include a memory 2104, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic RAM (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the memory 2104 may include a memory that shares a die with the processing device 2102. This memory may be used as cache memory and may include embedded DRAM (eDRAM) or spin transfer torque magnetic RAM (STT-MRAM).

[0098] In some embodiments, the system 2100 may include a communication chip 2112 (e.g., one or more communication chips). For example, the communication chip 2112 may be configured to manage wireless communications for the transfer of data to and from the system 2100. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can use modulated electromagnetic radiation to communicate data through a non-solid medium. The term does not imply that the associated device does not contain any wires, although in some embodiments the associated device may not contain any wires.

[0099] The communication chip 2112 may implement any of a number of wireless standards or protocols, including but not limited to: Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE802.16-2005 amendments), Long Term Evolution (LTE) projects, together with any amendments, updates and / or revisions (e.g., Advanced LTE projects, Ultra Mobile Broadband (UMB) projects (also known as "3GPP2"), etc.). IEEE 802.16 compatible broadband wireless access (BWA) networks are commonly referred to as WiMAX networks - an acronym that stands for Worldwide Interoperability for Microwave Access, and is a certification mark for products that have passed conformance and interoperability testing for the IEEE802.16 standard. The communication chip 2112 may operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2112 may operate according to GSM Evolution Enhanced Data (EDGE), GSM Evolution Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2112 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), and derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G and above. In other embodiments, the communication chip 2112 may operate according to other wireless protocols. The system 2100 may include an antenna 2122 for facilitating wireless communications and / or receiving other wireless communications (such as AM or FM radio transmissions).

[0100] In some embodiments, the communication chip 2112 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 2112 can include multiple communication chips. For example, the first communication chip 2112 can be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and the second communication chip 2112 can be dedicated to longer-range wireless communications, such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO or others. In some embodiments, the first communication chip 2112 can be dedicated to wireless communications, and the second communication chip 2112 can be dedicated to wired communications.

[0101] System 2100 may include battery / power circuitry 2114. Battery / power circuitry 2114 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of system 2100 to an energy source separate from system 2100 (e.g., AC line power).

[0102] System 2100 may include a display device 2106 (or corresponding interface circuitry as discussed above). Display device 2106 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0103] The system 2100 may include an audio output device 2108 (or corresponding interface circuitry as discussed above). The audio output device 2108 may include any device that produces an audible indicator, such as a speaker, headphones, or earbuds.

[0104] The system 2100 may include an audio input device 2118 (or corresponding interface circuitry as discussed above). The audio input device 2118 may include any device that produces a signal representative of sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0105] The system 2100 may include a GPS device 2116 (or corresponding interface circuitry as discussed above). The GPS device 2116 may communicate with a satellite-based system and may receive the location of the system 2100, as is known in the art.

[0106] The system 2100 may include another output device 2110 (or corresponding interface circuitry as discussed above). Examples of other output devices 2110 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage.

[0107] The system 2100 may include another input device 2120 (or corresponding interface circuitry as discussed above). Examples of other input devices 2120 may include an accelerometer, a gyroscope, a compass, an image acquisition device, a keyboard, a cursor control device (such as a mouse), a stylus, a touch pad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0108] System 2100 may have any desired form factor, such as a handheld or mobile electronic device (e.g., a cell phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop electronic device, a server device or other network-connected computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electronic device. In some embodiments, system 2100 may be any other electronic device that processes data.

[0109] Fig.15 is a block diagram of an example RF device 2200 (e.g., an RF transceiver) that may include one or more components having one or more boost switch drivers according to any of the embodiments disclosed herein. For example, any suitable component of the components of the RF device 2200 may include a die that includes at least one boost switch driver or a portion thereof configured to drive one or more switches according to any of the embodiments disclosed herein. In some embodiments, the RF device 2200 may include a RF transceiver as described in reference to FIG. Fig.16 The RF device 2200 may be within any component of the described system 2100, or may be coupled to any of the components of the system 2100, for example, to the memory 2104 and / or the processing device 2102 of the system 2100. In still other embodiments, the RF device 2200 may further include a reference Fig.16 Any of the components described, such as, but not limited to, Fig.16 The battery / power circuit 2114, memory 2104 and various input and output devices are shown.

[0110] In general, the RF device 2200 may be any device or system that can support wireless transmission and / or reception of signals in the form of electromagnetic waves in the RF range of approximately 3 kilohertz (kHz) to approximately 300 gigahertz (GHz). In some embodiments, the RF device 2200 may be used for wireless communication, for example, in a base station (BS) or user equipment (UE) device suitable for any cellular wireless communication technology (such as GSM, WCDMA or LTE). In other examples, the RF device 2200 can be used as or for, for example, a BS or UE device of millimeter wave wireless technology (such as, for example, fifth generation (5G) wireless (i.e., high frequency / short wavelength spectrum, for example, having a frequency in a range between about 20 GHz and 60 GHz, corresponding to a wavelength in a range between about 5 mm and 15 mm). In yet another example, the RF device 2200 can be used for wireless communication using Wi-Fi technology (e.g., a frequency band of 2.4 GHz, corresponding to a wavelength of about 12 cm; or a frequency band, spectrum of 5.8 GHz, corresponding to a wavelength of about 5 cm), for example, in Wi-Fi enabled devices such as desktop computers, laptop computers, video The RF device 2200 may be used to transmit and / or receive RF signals for purposes other than communication, for example, in automotive radar systems, or in medical applications such as magnetic resonance imaging (MRI).

[0111] In various embodiments, the RF device 2200 may be included in a frequency division duplex (FDD) or time domain duplex (TDD) variant of frequency allocation that may be used in a cellular network. In an FDD system, the uplink (i.e., RF signals are transmitted from the UE device to the BS) and the downlink (i.e., RF signals are transmitted from the BS to the US device) may use separate frequency bands simultaneously. In a TDD system, the uplink and downlink may use the same frequency, but at different times.

[0112] exist Fig.152200, but any one or more of these components may be omitted or duplicated depending on the application. For example, in some embodiments, the RF device 2200 may be an RF device that supports both wireless transmission and reception of RF signals (e.g., an RF transceiver), in which case it may include both components referred to herein as a transmission (TX) path and components referred to herein as a reception (RX) path. However, in other embodiments, the RF device 2200 may be an RF device that only supports wireless reception (e.g., an RF receiver), in which case it may include components of the RX path but not components of the TX path, or the RF device 2200 may be an RF device that only supports wireless transmission (e.g., an RF transmitter), in which case it may include components of the TX path but not components of the RX path.

[0113] In some embodiments, some or all of the components included in the RF device 2200 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single die, such as a single SoC die.

[0114] In addition, in various embodiments, the RF device 2200 may not include Fig.15 2200, but the RF device 2200 may include interface circuitry for coupling to the one or more components. For example, the RF device 2200 may not include the antenna 2202, but may include antenna interface circuitry (e.g., matching circuitry, connector, and driver circuitry) to which the antenna 2202 may be coupled. In another set of examples, the RF device 2200 may not include the digital processing unit 2208 or the local oscillator 2206, but may include device interface circuitry (e.g., connector and supporting circuitry) to which the digital processing unit 2208 or the local oscillator 2206 may be coupled.

[0115] like Fig.15 As shown in FIG. 2 , the RF device 2200 may include an antenna 2202, a duplexer 2204, a local oscillator 2206, and a digital processing unit 2208. Fig.15 , RF device 2200 may include an RX path, which may include an RX path amplifier 2212, an RX path premix filter 2214, an RX path mixer 2216, an RX path postmix filter 2218, and an ADC 2220. Fig.15As further shown in FIG. 2 , the RF device 2200 may include a TX path, which may include a TX path amplifier 2222, a TX path postmix filter 2224, a TX path mixer 2226, a TX path premix filter 2228, and a DAC 2230. Still further, the RF device 2200 may further include an impedance tuner 2232, an RF switch 2234, and control logic 2236. In various embodiments, the RF device 2200 may include Fig.15 2200. In some embodiments, the RX path amplifier 2212, the TX path amplifier 2222, the duplexer 2204, and the RF switch 2234 may be considered to form or be part of the RF front end (FE) of the RF device 2200. In some embodiments, the RX path amplifier 2212, the TX path amplifier 2222, the duplexer 2204, and the RF switch 2234 may be considered to form or be part of the RF FE of the RF device 2200. In some embodiments, the RX path mixer 2216 and the TX path mixer 2226 (possibly with Fig.15 ) may be considered to form or be part of an RF transceiver of the RF device 2200 (if only the RX path or TX path components are included in the RF device 2200, then they may be considered to form or be part of an RF receiver or RF transmitter, respectively). In some embodiments, the RF device 2200 may further include Fig.15 2236, e.g., an RF FE control interface. In some embodiments, the control logic 2236 may be configured to control at least a portion of any of the boost switch drivers within any component of the RF device 2200 operating as described herein. In some embodiments, the control logic 2236 may be used to perform control of other functions within the RF device 2200, e.g., enhanced control of complex RF system environments, support for implementation of envelope tracking techniques, reduction of dissipated power, etc.

[0116] Antenna 2202 may be configured to wirelessly transmit and / or receive RF signals according to any wireless standard or protocol (e.g., Wi-Fi, LTE, or GSM), as well as any other wireless protocol designated as 3G, 4G, 5G, and above. If RF device 2200 is an FDD transceiver, antenna 2202 may be configured to simultaneously receive and transmit communication signals in separate (i.e., non-overlapping and non-contiguous) frequency bands (e.g., in frequency bands having a spacing of, for example, 20 MHz from each other). If RF device 2200 is a TDD transceiver, antenna 2202 may be configured to sequentially receive and transmit communication signals in frequency bands that may be the same or overlapping for the TX path and the RX path. In some embodiments, RF device 2200 may be a multi-band RF device, in which case antenna 2202 may be configured to simultaneously receive signals having multiple RF components in separate frequency bands and / or to simultaneously transmit signals having multiple RF components in separate frequency bands. In such embodiments, antenna 2202 may be a single broadband antenna or multiple band-specific antennas (i.e., multiple antennas each configured to receive and / or transmit signals in a specific frequency band). In various embodiments, antenna 2202 may include multiple antenna elements, for example, multiple antenna elements forming a phased antenna array (i.e., a communication system or any antenna array that can use multiple antenna elements and phase shifts to transmit and receive RF signals). Phased antenna arrays can provide advantages such as gain, directional steering capabilities, and increased simultaneous communications compared to single antenna systems. In some embodiments, RF device 2200 may include more than one antenna 2202 to implement antenna diversity. In some such embodiments, RF switch 2234 may be deployed to switch between different antennas.

[0117] The output of antenna 2202 may be coupled to the input of duplexer 2204. Duplexer 2204 may be any suitable component configured to filter multiple signals to allow bidirectional communication via a single path between duplexer 2204 and antenna 2202. Duplexer 2204 may be configured to provide RX signals to the RX path of RF device 2200 and receive TX signals from the TX path of RF device 2200.

[0118] The RF device 2200 may include one or more local oscillators 2206 configured to provide local oscillator signals that may be used for down-conversion of RF signals received by the antenna 2202 and / or up-conversion of signals to be transmitted by the antenna 2202 .

[0119] RF device 2200 may include a digital processing unit 2208, which may include one or more processing devices. In some embodiments, digital processing unit 2208 may be implemented as Fig.16, a description of which is provided above (when used as a digital processing unit 2208, the processing device 2102 may, but need not, implement any of the boost switch drivers described herein). The digital processing unit 2208 may be configured to perform various functions related to digital processing of RX and / or TX signals. Examples of such functions include, but are not limited to: decimation / downsampling, error correction, digital down-conversion or up-conversion, DC offset cancellation, automatic gain control, etc. Although Fig.15 2200, but in some embodiments, the RF device 2200 may further include a memory device, for example, configured to cooperate with the digital processing unit 2208 as described in reference Fig.16 Memory device 2104 described. When used within or coupled to RF device 2200, memory device 2104 may, but need not, implement any of the boost switch drivers described herein.

[0120] Returning to the details of the RX path that may be included in the RF device 2200, the RX path amplifier 2212 may include a low noise amplifier (LNA). The input of the RX path amplifier 2212 may be coupled to an antenna port (not shown) of the antenna 2202, for example, via the duplexer 2204. The RX path amplifier 2212 may amplify the RF signal received by the antenna 2202.

[0121] The output of the RX path amplifier 2212 may be coupled to the input of the RX path premix filter 2214 , which may be a harmonic or bandpass (eg, lowpass) filter configured to filter the received RF signal that has been amplified by the RX path amplifier 2212 .

[0122] The output of the RX path premix filter 2214 may be coupled to the input of the RX path mixer 2216 (also referred to as a down converter). The RX path mixer 2216 may include two inputs and one output. The first input may be configured to receive an RX signal, which may be a current signal indicating a signal received by the antenna 2202 (e.g., the first input may receive the output of the RX path premix filter 2214). The second input may be configured to receive a local oscillator signal from one of the local oscillators 2206. The RX path mixer 2216 may then mix the signals received at its two inputs to generate a down-converted RX signal provided at the output of the RX path mixer 2216. As used herein, down conversion refers to the process of mixing a received RF signal with a local oscillator signal to produce a signal of a lower frequency. In particular, when two input frequencies are provided at two input ports, the TX path mixer (e.g., down converter) 2216 may be configured to generate a sum frequency and / or a difference frequency at the output port. In some embodiments, the RF device 2200 may implement a direct conversion receiver (DCR), also known as a homodyne, synchronous or zero IF receiver, in which case the RX path mixer 2216 may be configured to demodulate the incoming radio signal using a local oscillator signal whose frequency is equal to or very close to the carrier frequency of the radio signal. In other embodiments, the RF device 2200 may utilize down-conversion to an intermediate frequency (IF). The IF may be used in a superheterodyne radio receiver, where the received RF signal is shifted to the IF before the final detection of the information in the received signal is completed. Conversion to the IF may be useful for several reasons. For example, when several filter stages are used, they may all be set to a fixed frequency, which makes them easier to build and tune. In some embodiments, the RX path mixer 2216 may include several such IF conversion stages.

[0123] Despite Fig.15A single RX path mixer 2216 is shown in the RX path of FIG. 2202 , but in some embodiments, the RX path mixer 2216 may be implemented as an orthogonal down-converter, in which case the RX path mixer will include a first RX path mixer and a second RX path mixer. The first RX path mixer may be configured to perform down-conversion to generate an in-phase (I) down-converted RX signal by mixing the RX signal received by the antenna 2202 with an in-phase component of a local oscillator signal provided by the local oscillator 2206. The second RX path mixer may be configured to perform down-conversion to generate a quadrature (Q) down-converted RX signal by mixing the RX signal received by the antenna 2202 with a quadrature component of a local oscillator signal provided by the local oscillator 2206 (the quadrature component is a component that is 90 degrees in phase with the in-phase component of the local oscillator signal). The output of the first RX path mixer may be provided to an I signal path, and the output of the second RX path mixer may be provided to a Q signal path, which may be substantially 90 degrees out of phase with the I signal path.

[0124] The output of the RX path mixer 2216 may optionally be coupled to an RX path post-mix filter 2218, which may be a low pass filter. In the case where the RX path mixer 2216 is a quadrature mixer implementing the first mixer and the second mixer as described above, the in-phase and quadrature components provided at the outputs of the first mixer and the second mixer, respectively, may be coupled to the respective first path post-mix filter and the second RX path post-mix filter included in the filter 2218.

[0125] ADC 2220 may be configured to convert the mixed RX signal from RX path mixer 2216 from the analog domain to the digital domain. ADC 2220 may be a quadrature ADC that, like RX path quadrature mixer 2216, may include two ADCs configured to digitize the down-converted RX path signal separated in in-phase and quadrature components. The output of ADC 2220 may be provided to digital processing unit 2208, which is configured to perform various functions related to digital processing of the RX signal so that information encoded in the RX signal may be extracted. One or more of any of the embodiments of the boost switch driver as described herein may be included within ADC 2220.

[0126] Returning to the details of the TX path that may be included in the RF device 2200, a digital signal (TX signal) to be later transmitted by the antenna 2202 may be provided from the digital processing unit 2208 to the DAC 2230. Like the ADC 2220, the DAC 2230 may include two DACs configured to convert the digital I path and Q path TX signal components into analog form, respectively.

[0127] Optionally, the output of the DAC 2230 may be coupled to a TX path premix filter 2228, which may be a bandpass (e.g., lowpass) filter (or, in the case of quadrature processing, a pair of bandpass (e.g., lowpass) filters) configured to filter out signal components beyond a desired frequency band from the analog TX signal output by the DAC 2230. The digital TX signal may then be provided to a TX path mixer 2226, which may also be referred to as an upconverter. Like the RX path mixer 2216, the TX path mixer 2226 may include a pair of TX path mixers for mixing in-phase and quadrature components. Like the first RX path mixer and the second RX path mixer that may be included in the RX path, each of the TX path mixers of the TX path mixer 2226 may include two inputs and one output. The first input may receive a TX signal component converted to analog form by the corresponding DAC 2230, which will be upconverted to produce an RF signal to be transmitted. The first TX path mixer can generate an in-phase (I) up-converted signal by mixing the TX signal component converted to analog form by the DAC 2230 with the in-phase component of the TX path local oscillator signal provided from the local oscillator 2206 (in various embodiments, the local oscillator 2206 can include multiple different local oscillators, or be configured to provide different local oscillator frequencies to the mixer 2216 in the RX path and the mixer 2226 in the TX path). The second TX path mixer can generate a quadrature phase (Q) up-converted signal by mixing the TX signal component converted to analog form by the DAC 2230 with the quadrature component of the TX path local oscillator signal. The output of the second TX path mixer can be added to the output of the first TX path mixer to generate a real RF signal. The second input of each of the TX path mixers can be coupled to the local oscillator 2206.

[0128] Optionally, the RF device 2200 may include a TX path postmix filter 2224 configured to filter the output of the TX path mixer 2226 .

[0129] The TX path amplifier 2222 may be a power amplifier (PA) configured to amplify the up-converted RF signal before providing it to the antenna 2202 for transmission.

[0130] In various embodiments, any of the RX path premix filter 2214, the RX path postmix filter 2218, the TX postmix filter 2224, and the TX premix filter 2228 may be implemented as an RF filter. In some embodiments, the RF filter may be implemented as a plurality of RF filters or a filter bank. The filter bank may include a plurality of RF filters that may be coupled to a switch (e.g., an RF switch 2234), the switch being configured to selectively turn on and off any of the plurality of RF filters (e.g., activate any of the plurality of RF filters) to achieve the desired filtering characteristics of the filter bank (i.e., to program the filter bank). For example, when the RF device 2200 is or is included in a BS or UE device, this filter bank may be used to switch between different RF frequency ranges. In another example, this filter bank may be programmable to suppress TX leakage at different duplex distances.

[0131] The impedance tuner 2232 may include any suitable circuitry configured to match input impedance and output impedance of different RF circuitry to minimize signal loss in the RF device 2200. For example, the impedance tuner 2232 may include an antenna impedance tuner. Being able to tune the impedance of the antenna 2202 may be particularly advantageous because the impedance of the antenna varies depending on the environment in which the RF device 2200 is located, for example, the impedance of the antenna changes depending on whether the antenna is held in a hand, placed on a roof of a car, etc.

[0132] As described above, the RF switch 2234 may be a device configured to route high frequency signals through a transmission path, for example, to Fig.15 2200, e.g., to achieve desired behavior and characteristics of the RF device 2200. For example, in some embodiments, the RF switch can be used to switch between different antennas 2202. In other embodiments, the RF switch can be used to switch between multiple RF filters of the RF device 2200 (e.g., by selectively turning the RF filters on and off). Typically, the RF system will include multiple such RF switches.

[0133] RF device 2200 provides a simplified version, and in other embodiments, may include Fig.152200 and 2210. For example, the RX path of the RF device 2200 may include a current-to-voltage amplifier between the RX path mixer 2216 and the ADC 2220, which may be configured to amplify and convert the down-converted signal into a voltage signal. In another example, the RX path of the RF device 2200 may include a balun transformer for generating a balanced signal. In yet another example, the RF device 2200 may further include a clock generator, which may, for example, include a suitable phase-locked loop (PLL) configured to receive a reference clock signal and use it to generate a different clock signal, which may then be used to clock the operation of the ADC 2220, the DAC 2230, and / or may also be used by the local oscillator 2206 to generate a local oscillator signal to be used in the RX path or the TX path.

[0134] Example Data Processing System

[0135] Fig.16 A block diagram is provided that illustrates an example data processing system 2300 that may be configured to control the operation of one or more boost switch drivers as described herein, according to some embodiments of the present disclosure. For example, the data processing system 2300 may be configured to implement or control portions of the boost switch driver 204, 804, or any other embodiment of the boost switch driver as described herein. In another example, the data processing system 2300 may be configured to implement Fig.15 At least a portion of the control logic 2236 shown in .

[0136] like Fig.16 , data processing system 2300 may include at least one processor 2302 (e.g., hardware processor 2302) coupled to memory element 2304 via system bus 2306. In this way, the data processing system may store program codes in memory element 2304. Further, processor 2302 may execute program codes accessed from memory element 2304 via system bus 2306. In one aspect, the data processing system may be implemented as a computer suitable for storing and / or executing program codes. However, it should be understood that data processing system 2300 may be implemented in the form of any system including a processor and a memory capable of performing the functions described in the present disclosure.

[0137] In some embodiments, the processor 2302 may execute software or algorithms to perform activities as discussed in the present disclosure, in particular, activities related to operating a boost switch driver as described herein. The processor 2302 may include any combination of hardware, software, or firmware that provides programmable logic, including, by way of non-limiting example, a microprocessor, a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic array (PLA), an application-specific IC (ASIC), or a virtual machine processor. The processor 2302 may be communicatively coupled to the memory element 2304, for example, in a direct memory access (DMA) configuration, such that the processor 2302 may read from or write to the memory element 2304.

[0138] In general, memory element 2304 may include any suitable volatile or non-volatile memory technology, including double data rate (DDR) random access memory (RAM), synchronous RAM (SRAM), dynamic RAM (DRAM), flash, read-only memory (ROM), optical media, virtual memory areas, magnetic or tape storage, or any other suitable technology. Unless otherwise specified, any of the memory elements discussed herein should be interpreted as being included within the broad term "memory". Information measured, processed, tracked, or sent to or from any of the components of data processing system 2300 may be provided in any database, register, control list, cache memory, or storage structure, all of which may be referenced at any suitable time frame. Any such storage option may be included within the broad term "memory" as used herein. Similarly, any of the potential processing elements, modules, and machines described herein should be interpreted as being included within the broad term "processor". Each of the elements shown in the figures of the present disclosure, for example, as shown in FIG. Figures 1 to 12 Any elements of the boost switch driver shown in may also include a suitable interface for receiving, transmitting and / or otherwise communicating data or information in a network environment so that it can communicate with, for example, the data processing system 2300.

[0139] In certain example embodiments, mechanisms for implementing one or more boost switch drivers as outlined herein may be implemented by logic encoded in one or more tangible media that may include non-transitory media, such as embedded logic provided in an ASIC, DSP instructions, software (possibly including object code and source code) for execution by a processor or other similar machine, etc. In some of these examples, memory elements, such as, for example, Fig.16The memory element 2304 shown in the figure can store data or information used for the operations described herein. This includes memory elements that can store software, logic, code, or processor instructions that are executed to implement the activities described herein. The processor can execute any type of instructions associated with the data or information used to implement the operations detailed herein. In one example, a processor, such as, for example, Fig.16 The processor 2302 shown in the figure can transform an element or item (e.g., data) from one state or thing to another state or thing. In another example, the activities outlined herein can be implemented using fixed logic or programmable logic (e.g., software / computer instructions executed by a processor), and the elements identified herein can be some type of programmable processor, programmable digital logic (e.g., FPGA, DSP, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)), or ASIC including digital logic, software, code, electronic instructions, or any suitable combination thereof.

[0140] Memory element 2304 may include one or more physical memory devices, such as, for example, local memory 2308 and one or more mass storage devices 2310. Local memory may refer to RAM or other non-permanent memory devices that are typically used during the actual execution of program code. Mass storage devices may be implemented as hard drives or other permanent data storage devices. Processing system 2300 may also include one or more cache memories (not shown) that provide temporary storage of at least some program code in order to reduce the number of times program code must be retrieved from mass storage device 2310 during execution.

[0141] like Fig.16 , memory element 2304 may store application 2318. In various embodiments, application 2318 may be stored in local memory 2308, one or more mass storage devices 2310, or separate from local memory and mass storage devices. It should be understood that data processing system 2300 may further execute an operating system (not shown) that may facilitate the execution of application 2318. Fig.16 23). Application 2318 implemented in the form of executable program code may be executed by data processing system 2300, for example, by processor 2302. In response to executing the application, data processing system 2300 may be configured to perform one or more operations or method steps described herein.

[0142] Input / output (I / O) devices, depicted as input devices 2312 and output devices 2314, may optionally be coupled to the data processing system. Examples of input devices may include, but are not limited to, keyboards, pointing devices such as mice, and the like. Examples of output devices may include, but are not limited to, monitors or displays, speakers, and the like. In some embodiments, output device 2314 may be any type of screen display, such as a plasma display, a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an electroluminescent (EL) display, or any other indicator, such as a dial, a barometer, or an LED. In some implementations, the system may include a driver (not shown) for output device 2314. Input and / or output devices 2312, 2314 may be coupled to the data processing system directly or through an intervening I / O controller.

[0143] In an embodiment, the input device and the output device may be implemented as a combined input / output device (in Fig.16 2312 and output device 2314). An example of such a combined device is a touch-sensitive display, sometimes referred to as a "touch screen display" or simply a "touch screen." In this embodiment, input to the device can be provided by the movement of a physical object, such as, for example, a stylus or a user's finger touching on or near the display screen.

[0144] Network adapter 2316 may also be optionally coupled to the data processing system to enable it to become coupled to other systems, computer systems, remote network devices, and / or remote storage devices through intervening private or public networks. The network adapter may include a data receiver for receiving data transmitted to the data processing system 2300 by the system, device, and / or network, and a data transmitter for transmitting data from the data processing system 2300 to the system, device, and / or network. Modems, cable modems, and Ethernet cards are examples of different types of network adapters that can be used with the data processing system 2300.

[0145] Select Instance

[0146] The following paragraphs provide various examples of the embodiments disclosed herein.

[0147] Example 1 provides a switch driver circuit, comprising: an input configured to receive an input clock signal; an output configured to provide an output clock signal; a first transistor (e.g., transistor m5 shown in the drawings of the present disclosure); a second transistor (e.g., transistor m6 shown in the drawings of the present disclosure), wherein each of the first transistor and the second transistor comprises a first terminal (e.g., a gate terminal) and a second terminal (e.g., a drain terminal), and wherein one of the first transistor and the second transistor is a P-type transistor (e.g., a PMOS transistor) and the other is an N-type transistor (e.g., an NMOS transistor); and a level shifter circuit configured to level shift the input clock signal to produce a level-shifted input clock signal. The first terminal of the first transistor is configured to receive a signal indicative of the input clock signal (e.g., the input clock signal itself or a version of the input clock signal that has been level-shifted in a manner complementary to the level shift of the signal to be provided to the second transistor), the first terminal of the second transistor is configured to receive a signal indicative of the level-shifted input clock signal, and each of the second terminal of the first transistor and the second terminal of the second transistor is coupled to the output (i.e., the second terminal of the first transistor is coupled to the second terminal of the second transistor, and both are coupled to the output).

[0148] Example 2 provides a switch driver circuit according to Example 1, wherein the input clock signal has a low voltage value and a high voltage value, and level shifting the input clock signal includes the level shifter circuit changing each of the low voltage value and the high voltage value of the input signal to produce the level-shifted input signal.

[0149] Example 3 provides a switch driver circuit according to Example 1 or 2, wherein the level shifter circuit includes a coupling capacitor and a voltage controller circuit, and the first terminal of the second transistor is configured to receive the signal indicative of the level-shifted input clock signal by coupling to the input via a first capacitor electrode and coupling to the voltage controller circuit and each of the first terminals of the second transistor via a second capacitor electrode.

[0150] Example 4 provides a switch driver circuit according to Example 3, wherein a voltage controller circuit is configured to control a high voltage value in the level-shifted input clock signal. This voltage controller circuit can be referred to as a "maximum level controller" because it sets a maximum voltage value for the level-shifted input clock signal. A minimum voltage value is then automatically adjusted based on a ratio between the capacitance of the coupling capacitor and the capacitance of a load for the voltage controller circuit.

[0151] Example 5 provides a switch driver circuit according to Example 4, wherein the third terminal of the second transistor is coupled to a supply voltage, and the value of the supply voltage corresponds to (e.g., is substantially equal to) the high voltage in the level-shifted input clock signal.

[0152] Example 6 provides a switch driver circuit according to Example 4 or 5, wherein the voltage controller circuit includes a pair of cross-coupled transistors, each of which includes a first terminal (e.g., a gate terminal), a second terminal (e.g., a drain terminal), and a third terminal (e.g., a source terminal), the first terminal of the first transistor of the pair of cross-coupled transistors is coupled to the second terminal of the second transistor of the pair of cross-coupled transistors, the first terminal of the second transistor of the pair of cross-coupled transistors is coupled to the second terminal of the first transistor of the pair of cross-coupled transistors, the third terminal of each of the first transistor of the pair of cross-coupled transistors and the second transistor of the pair of cross-coupled transistors is coupled to a reference voltage, and the value of the reference voltage corresponds to (e.g., is substantially equal to) the high voltage in the level-shifted input clock signal.

[0153] Example 7 provides the switch driver circuit of any of Examples 4 to 6, wherein the first transistor is an N-type transistor and the second transistor is a P-type transistor.

[0154] Example 8 provides a switch driver circuit according to any one of Examples 4 to 6, wherein the level shifter circuit is a first level shifter circuit, the switch driver circuit further includes a second level shifter circuit, and the second level shifter circuit is configured to control a low voltage level in the output clock signal.

[0155] Example 9 provides a switch driver circuit according to Example 3, wherein a voltage controller circuit is configured to control a low voltage value in the level-shifted input clock signal. This voltage controller circuit can be referred to as a "minimum level controller" because it sets a minimum voltage value for the level-shifted input clock signal. A maximum voltage value is then automatically adjusted based on a ratio between the capacitance of the coupling capacitor and the capacitance of a load for the voltage controller circuit.

[0156] Example 10 provides a switch driver circuit according to Example 9, wherein the third terminal of the second transistor is coupled to a supply voltage, and the value of the supply voltage corresponds to (e.g., is substantially equal to) a low voltage in the level-shifted input clock signal.

[0157] Example 11 provides a switch driver circuit according to Example 9 or 10, wherein the voltage controller circuit includes a pair of cross-coupled transistors, each of which includes a first terminal (e.g., a gate terminal), a second terminal (e.g., a drain terminal), and a third terminal (e.g., a source terminal). The first terminal of a first transistor of the pair of cross-coupled transistors is coupled to the second terminal of a second transistor of the pair of cross-coupled transistors, the first terminal of the second transistor of the pair of cross-coupled transistors is coupled to the second terminal of the first transistor of the pair of cross-coupled transistors, and the third terminal of each of the first transistor of the pair of cross-coupled transistors and the second transistor of the pair of cross-coupled transistors is coupled to a supply voltage, and the value of the supply voltage corresponds to (e.g., is substantially equal to) the low voltage in the level-shifted input clock signal.

[0158] Example 12 provides the switch driver circuit of any of Examples 9 to 11, wherein the first transistor is a P-type transistor and the second transistor is an N-type transistor.

[0159] Example 13 provides a switch driver circuit according to any one of Examples 9 to 12, wherein the level shifter circuit is a first level shifter circuit, the switch driver circuit further includes a second level shifter circuit, and the second level shifter circuit is configured to control a high voltage level in the output clock signal.

[0160] Example 14 provides a switch driver circuit according to any of the preceding examples, further comprising a third transistor coupled to the first transistor in a common-source common-gate arrangement, wherein the second terminal of the first transistor is coupled to the output by coupling the second terminal of the first transistor to a third terminal (e.g., a source terminal) of the third transistor and coupling the second terminal (e.g., a drain terminal) of the third transistor to the output.

[0161] In various embodiments, a first terminal (e.g., a gate terminal) of the third transistor may be coupled to a suitable reference voltage. For example, the reference voltage may be substantially 1V for embodiments where the third transistor is an N-type transistor, or substantially 0V (ground) for embodiments where the third transistor is a P-type transistor.

[0162] Example 15 provides a switch driver circuit according to any of the preceding examples, wherein each of the first transistor and the second transistor is a field effect transistor, and wherein the first terminal is a gate terminal, the second terminal is a drain terminal, and the third terminal is a source terminal.

[0163] Example 16 provides a switch driver circuit, comprising: a first branch, comprising a first transistor (e.g., transistor m5 shown in the drawings of the present disclosure); and a second branch, comprising a second transistor (e.g., transistor m6 shown in the drawings of the present disclosure) and a level shifter circuit. An input clock signal is split between the first branch and the second branch, so that a signal indicating a portion of the input clock signal split to the first branch is provided to the first transistor, and a portion of the input clock signal split to the second branch is level-shifted by the level shifter circuit to generate a level-shifted input clock signal and a signal indicating the level-shifted input clock signal is provided to the second transistor. One of the first transistor and the second transistor is an N-type transistor and the other is a P-type transistor. The output of the first transistor is combined with the output of the second transistor to generate an output clock signal.

[0164] Example 17 provides a switch driver circuit according to Example 16, wherein each of the first transistor and the second transistor includes a first terminal (e.g., a gate terminal), a second terminal (e.g., a drain terminal), and a third terminal (e.g., a source terminal), the signal indicating the portion of the input clock signal split into the first branch is provided to the first terminal of the first transistor, and the signal indicating the level-shifted input clock signal is provided to the first terminal of the second transistor.

[0165] Example 18 provides a switch driver circuit according to Example 17, wherein the level shifter circuit includes a capacitor and a voltage controller circuit, the portion of the input clock signal split into the second branch is configured to be applied to a first capacitor electrode of the capacitor, and the second capacitor electrode of the capacitor is coupled to the output of the voltage controller circuit and each of the first terminals of the second transistor.

[0166] Example 19 provides a switch driver circuit according to Example 17 or 18, wherein the second terminal of the first transistor is coupled to the second terminal of the second transistor, the third terminal of the first transistor is coupled to a first supply voltage, and the third terminal of the second transistor is coupled to a second supply voltage.

[0167] Example 20 provides a method for making a switch driver circuit, the method comprising: providing an input, the input being configured to receive an input clock signal; providing an output, the output being configured to provide an output clock signal; providing a first transistor (e.g., transistor m5 shown in the drawings of the present disclosure); providing a second transistor (e.g., transistor m6 shown in the drawings of the present disclosure), wherein each of the first transistor and the second transistor comprises a first terminal (e.g., a gate terminal) and a second terminal (e.g., a drain terminal), and wherein one of the first transistor and the second transistor is a P-type transistor (e.g., a PMOS transistor) and the other is an N-type transistor a first transistor (e.g., an NMOS transistor); and providing a level shifter circuit configured to level shift the input clock signal to generate a level-shifted input clock signal, wherein the first terminal of the first transistor is configured to receive a signal indicative of the input clock signal, the first terminal of the second transistor is configured to receive a signal indicative of the level-shifted input clock signal, and each of the second terminal of the first transistor and the second terminal of the second transistor is coupled to the output (i.e., the second terminal of the first transistor is coupled to the second terminal of the second transistor, and both are coupled to the output).

[0168] Example 21 provides the method of example 20, wherein the switch driver circuit is the switch driver circuit of any of examples 1-19.

[0169] Variations and implementations

[0170] Although the above reference Figures 1 to 16 The exemplary implementations shown in describe embodiments of the present disclosure, but those skilled in the art will appreciate that the various teachings described above are applicable to a wide variety of other implementations.

[0171] In the discussion of the above embodiments, components of the system, such as, for example, inverters, resistors, transistors and / or other components, may be easily replaced, substituted or otherwise modified to suit specific circuit system requirements. Moreover, it should be noted that the use of complementary electronics, hardware, software, etc. provides equally viable options for implementing the teachings of the present disclosure related to implementing one or more boost switch drivers.

[0172] Components of various systems for implementing one or more boost switch drivers as presented herein may include electronic circuitry that performs the functions described herein. In some cases, one or more components of the system may be provided by a processor specifically configured to perform the functions described herein. For example, the processor may include one or more application-specific components, or may include programmable logic gates configured to perform the functions described herein. The circuitry may operate in an analog domain, a digital domain, or a mixed signal domain. In some examples, the processor may be configured to perform the functions described herein by executing one or more instructions stored on a non-transitory computer-readable storage medium.

[0173] In some embodiments, any number of circuits of the accompanying drawings may be implemented on a board of an associated electronic device. The board may be a general-purpose circuit board that can hold various components of the internal electronic system of the electronic device and further provide connectors for other peripheral devices. More specifically, the board may provide an electrical connection through which other components of the system can communicate electrically. Any suitable processor (including DSP, microprocessor, supporting chipset, etc.), computer-readable non-transitory memory element, etc. may be appropriately coupled to the board based on configuration requirements, processing commands, computer design, etc. Other components (such as external storage devices, additional sensors, controllers for audio / video display, and peripheral devices) may be attached to the board as plug-in cards via cables, or integrated into the board itself. In various embodiments, the functionality described herein may be implemented in simulated form as software or firmware running in one or more configurable (e.g., programmable) elements arranged in a structure that supports these functions. The software or firmware providing the simulation may be provided on a non-transitory computer-readable storage medium that includes instructions that allow the processor to implement those functionalities.

[0174] In some embodiments, the circuits of the accompanying drawings may be implemented as stand-alone modules (e.g., devices having associated components and circuitry configured to perform a specific application or function) or as plug-in modules into application-specific hardware of an electronic device. It should be noted that embodiments of the present disclosure may be readily included in part or in whole in a system-on-chip (SOC) package. SOC refers to an IC that integrates the components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed signal, and typically RF functions: all of which may be provided on a single chip substrate. Other embodiments may include a multi-chip module (MCM), in which multiple individual ICs are located within a single electronic package and are configured to interact closely with each other through the electronic package.

[0175] All specifications, dimensions, and relationships outlined herein (e.g., the number of components or portions thereof of the boost switch driver shown in the drawings, etc.) are provided for purposes of example and instruction only. Such information may vary considerably without violating the spirit of the present disclosure or the scope of the appended claims. The specifications apply only to one non-limiting example, and therefore they should be interpreted as such. In the foregoing description, example embodiments have been described with reference to processors and / or component arrangements. Various modifications and changes may be made to such embodiments without violating the scope of the appended claims. Therefore, the description and drawings are to be regarded as having illustrative rather than restrictive meanings.

[0176] It should be noted that for the numerous examples provided herein, the interaction can be described in terms of two, three, four or more electrical components. However, this is done only for the purpose of clarity and example. It should be understood that the system can be combined in any suitable manner. According to similar design alternatives, any of the components, modules and elements shown in the drawings can be combined in various possible configurations, all of which are obviously within the broad scope of the present disclosure. In some cases, it may be easier to describe one or more of the functionality of a given set of processes by referring only to a limited number of electrical components. It should be understood that the circuits of the drawings and their teachings can be easily expanded and can accommodate many components, as well as more complex or more sophisticated arrangements and configurations. Therefore, the examples provided should not limit the scope of the circuit or suppress the extensive teachings of the circuit, because they may be applied to countless other architectures.

[0177] In addition, the functions associated with implementing one or more boost switch drivers as proposed herein illustrate only some of the possible functions that may be performed by or within the system shown in the accompanying drawings. Some of these operations may be deleted or removed where appropriate, or may be substantially modified or changed without violating the scope of the present disclosure. In addition, the timing of these operations may be substantially altered. The foregoing operational flows have been provided for purposes of example and discussion. The embodiments described herein provide significant flexibility in that any suitable arrangement, schedule, configuration, and timing mechanism may be provided without violating the teachings of the present disclosure.

[0178] It should be noted that all optional features of the apparatus described above may also be implemented with respect to the methods or processes described herein, and that the details in the examples may be used anywhere in one or more embodiments.

[0179] Numerous other changes, substitutions, variations, alterations, and modifications may be ascertained by those skilled in the art, and the disclosure is intended to embrace all such changes, substitutions, variations, alterations, and modifications that fall within the scope of the appended claims.

Claims

1. An electronic component comprising: one or more switches; and A switch driver circuit, for driving the one or more switches, the switch driver circuit comprising: input, for receiving an input clock signal; output, for providing an output clock signal; A first transistor and a second transistor, each comprising a first terminal and a second terminal; a third transistor coupled to the first transistor in a cascode arrangement; and a level shifter circuit for level-shifting the input clock signal to generate a level-shifted input clock signal, in: The first terminal of the first transistor is used to receive a signal indicating the input clock signal, The first terminal of the second transistor is used to receive a signal indicative of the level-shifted input clock signal, A second terminal of the first transistor is coupled to a third terminal of the third transistor, and a second terminal of the third transistor is coupled to the output, and A second terminal of the second transistor is coupled to the output.

2. The electronic assembly according to claim 1, wherein: The input clock signal has a low voltage value and a high voltage value, and Level shifting the input clock signal includes the level shifter circuit changing each of the low voltage value and the high voltage value of the input clock signal to generate the level shifted input clock signal.

3. The electronic component according to claim 1, wherein: The level shifter circuit includes a coupling capacitor and a voltage controller circuit, and the first terminal of the second transistor is used to receive a signal indicative of the level-shifted input clock signal by coupling a first capacitor electrode to the input and a second capacitor electrode to each of the voltage controller circuit and the first terminal of the second transistor.

4. The electronic assembly according to claim 3, wherein: The voltage controller circuit includes a pair of cross-coupled transistors, each transistor including a first terminal, a second terminal and a third terminal, a first terminal of a first transistor of the pair of cross-coupled transistors coupled to a second terminal of a second transistor of the pair of cross-coupled transistors, a first terminal of the second transistor of the pair of cross-coupled transistors coupled to a second terminal of the first transistor of the pair of cross-coupled transistors, A third terminal of each of the first transistor of the pair of cross-coupled transistors and the second transistor of the pair of cross-coupled transistors is coupled to a reference voltage, and The value of the reference voltage corresponds to a high voltage of the level-shifted input clock signal.

5. The electronic assembly according to claim 3, wherein: The level shifter circuit is a first level shifter circuit, The switch driver circuit further includes a second level shifter circuit, and The second level shifter circuit is used to control the low voltage level of the output clock signal.

6. The electronic assembly according to claim 3, wherein: The voltage controller circuit includes a pair of cross-coupled transistors, each transistor including a first terminal, a second terminal and a third terminal, a first terminal of a first transistor of the pair of cross-coupled transistors coupled to a second terminal of a second transistor of the pair of cross-coupled transistors, a first terminal of the second transistor of the pair of cross-coupled transistors coupled to a second terminal of the first transistor of the pair of cross-coupled transistors, A third terminal of each of the first transistor of the pair of cross-coupled transistors and the second transistor of the pair of cross-coupled transistors is coupled to a reference voltage, and The value of the reference voltage corresponds to a low voltage of the level-shifted input clock signal.

7. The electronic component according to claim 1, wherein: Each of the first transistor and the second transistor is a field effect transistor, and wherein the first terminal is a gate terminal, the second terminal is a drain terminal, and the third terminal is a source terminal.

8. The electronic component according to claim 1, wherein: The electronic component is an analog-to-digital converter.

9. An electronic component comprising: one or more switches; and A switch driver circuit, for driving the one or more switches, the switch driver circuit comprising: input, for receiving an input clock signal; output, for providing an output clock signal; A first transistor and a second transistor, each comprising a first terminal and a second terminal; a first level shifter circuit for level-shifting the input clock signal to generate a level-shifted input clock signal; and a second level shifter circuit; in: The first terminal of the first transistor is used to receive a signal indicating the input clock signal, The first terminal of the second transistor is used to receive a signal indicative of the level-shifted input clock signal, a second terminal of the second transistor coupled to the second level shifter circuit, each of a second terminal of the first transistor and a second terminal of the second transistor coupled to the output, The first level shifter circuit is used to control the high voltage value of the level-shifted input clock signal, and The second level shifter circuit is used to control a high voltage level of the output clock signal.

10. The electronic component of claim 9, further comprising a third transistor coupled to the first transistor in a cascode arrangement, wherein a second terminal of the first transistor is coupled to the output by coupling a second terminal of the first transistor to a third terminal of the third transistor and coupling a second terminal of the third transistor to the output.

11. The electronic component according to claim 9, wherein: The level shifter circuit includes a coupling capacitor and a voltage controller circuit, and the first terminal of the second transistor is used to receive a signal indicative of the level-shifted input clock signal by coupling a first capacitor electrode to the input and a second capacitor electrode to each of the voltage controller circuit and the first terminal of the second transistor.

12. The electronic component according to claim 11, wherein: A third terminal of the second transistor is coupled to a power supply voltage, and a value of the power supply voltage corresponds to a high voltage of the level-shifted input clock signal.

13. The electronic component according to claim 9, wherein: The electronic component is an analog-to-digital converter.

14. A switch driver circuit comprising: input, for receiving an input clock signal; output, for providing an output clock signal; A first transistor and a second transistor, each comprising a first terminal and a second terminal; a first level shifter circuit for level-shifting the input clock signal to generate a level-shifted input clock signal; as well as a second level shifter circuit; in: The first terminal of the first transistor is used to receive a signal indicating the input clock signal, The first terminal of the second transistor is used to receive a signal indicative of the level-shifted input clock signal, a second terminal of the second transistor coupled to the second level shifter circuit, Each of the second terminal of the first transistor and the second terminal of the second transistor is coupled to the output, and The second level shifter circuit is used to control a high voltage level or a low voltage level of the output clock signal.

15. The switch driver circuit of claim 14, wherein: The first level shifter circuit is used to control the high voltage value of the level-shifted input clock signal, and The second level shifter circuit is used to control the low voltage level of the output clock signal.

16. The switch driver circuit of claim 15, wherein: The first level shifter circuit includes a voltage controller circuit and a coupling capacitor having a first capacitor electrode and a second capacitor electrode, The first capacitor electrode is coupled to the input, and The second capacitor electrode is coupled to each of the voltage controller circuit and a first terminal of the second transistor.

17. The switch driver circuit of claim 14, wherein: The first level shifter circuit is used to control the high voltage value of the level-shifted input clock signal, and The second level shifter circuit is used to control the high voltage level of the output clock signal.

18. The switch driver circuit of claim 14, wherein: The first level shifter circuit is used to control the low voltage value of the level-shifted input clock signal, and The second level shifter circuit is used to control the high voltage level of the output clock signal.

19. The switch driver circuit of claim 14, wherein: The first level shifter circuit is used to control the low voltage value of the level-shifted input clock signal, and The second level shifter circuit is used to control the low voltage level of the output clock signal.

20. The switch driver circuit of claim 14, further comprising a third transistor coupled to the first transistor in a cascode arrangement, wherein a second terminal of the first transistor is coupled to the output by coupling a second terminal of the first transistor to a third terminal of the third transistor and coupling a second terminal of the third transistor to the output.

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