A common-source common-gate amplifier biasing method, device and biasing circuit

Abstract

The present invention discloses a bias method, device and bias circuit for a cascode amplifier. The bias method includes: obtaining a first minimum saturation drain-source voltage corresponding to the drain-source voltage of an input transistor in the cascode amplifier, and a second minimum saturation drain-source voltage corresponding to the drain-source voltage of the cascode transistor; setting the gate bias voltage of the cascode transistor according to the first minimum saturation drain-source voltage and the second minimum saturation drain-source voltage, so that the drain-source voltage of the input transistor is greater than or equal to the first minimum saturation drain-source voltage, and the drain-source voltage of the cascode transistor is greater than or equal to the second minimum saturation drain-source voltage. According to the values of the first minimum saturation drain-source voltage and the second minimum saturation drain-source voltage, the present invention sets the gate bias voltage of the cascode transistor, so that the drain-source voltage of the input transistor is greater than or equal to the first minimum saturation drain-source voltage, and the drain-source voltage of the cascode transistor is greater than or equal to the second minimum saturation drain-source voltage, thereby enabling the cascode amplifier to obtain stable gain.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular, to a cascode amplifier biasing method, device, and biasing circuit. Background Art

[0002] In order to increase the low-frequency gain of an operational amplifier without introducing new low-frequency poles, a cascode amplifier is usually used as the first-stage amplifier, and the second-stage amplifier uses a current-source-biased common-source amplifier or a push-pull structure. The first-stage cascode amplifier is used to provide a large gain, but only has a very small current driving ability; the second stage is usually used as a driving stage, which has a small gain but a large driving ability. The cascode amplifier is composed of an input transistor, a cascode transistor, and a cascode load. The input transistor and the cascode transistor are called the cascode stage. The second-stage amplifier is composed of a gain transistor and a load transistor. The gate-source voltage of the second-stage gain transistor is the sum of the drain-source voltages of the first-stage input transistor and the cascode transistor. In the current advanced process, in order to ensure speed, the threshold voltage of the core devices of the cascode amplifier is low, and in order to ensure sufficient driving ability, the overdrive voltage of the gain transistor in the second-stage amplifier is set to be small. Therefore, the gate-source voltage of the second-stage gain transistor is low. Worse still, the gate-source voltage decreases as the temperature increases. Therefore, it is difficult to ensure that both transistors in the first stage have sufficient drain-source voltages to operate in the saturation region at high temperatures. Generally, it is preferred to ensure that the first-stage input transistor operates in the saturation region, and then consider the operating state of the cascode transistor. In order to ensure that the cascode transistor is in the saturation region at high temperatures, the existing cascode amplifier biasing methods based on the single diode-connected MOS transistor structure adopt the following two methods: The first method is to increase the gate-source voltage of the second-stage gain transistor, but for a fixed output current, it is necessary to reduce its W / L, which will not only reduce the maximum driving ability of the operational amplifier, but also cause difficulties in Miller compensation of the operational amplifier; the second method is to reduce the drain-source voltage of the first-stage input transistor, but the drain-source voltage of the input transistor of the single-transistor biasing structure cascode stage increases as the temperature increases. Reducing the drain-source voltage at high temperatures will cause the drain-source voltage at low temperatures to be lower than its corresponding minimum drain-source saturation voltage, resulting in the input transistor being in the linear region at low temperatures and unable to stabilize the gain of the cascode amplifier. Summary of the Invention

[0003] The present invention provides a cascode amplifier biasing method, device, and biasing circuit to solve the technical problem that the existing cascode amplifier biasing methods cannot stabilize the gain of the cascode amplifier.

[0004] An embodiment of the present invention provides a cascode amplifier biasing method, including:

[0005] Obtain a first minimum saturation drain-source voltage corresponding to the drain-source voltage of the input transistor in the cascode amplifier, and a second minimum saturation drain-source voltage corresponding to the drain-source voltage of the cascode transistor;

[0006] According to the first minimum saturation drain-source voltage and the second minimum saturation drain-source voltage, set the gate bias voltage of the cascode transistor so that the drain-source voltage of the input transistor is greater than or equal to the first minimum saturation drain-source voltage, and the drain-source voltage of the cascode transistor is greater than or equal to the second minimum saturation drain-source voltage.

[0007] Further, the setting of the gate bias voltage of the cascode transistor is specifically:

[0008] Superimpose the gate-source voltage of a preset multiple of the gain transistor in the cascode amplifier on the gate voltage of the cascode transistor to obtain a superimposed voltage value, and use the superimposed voltage value as the gate bias voltage of the cascode transistor.

[0009] Further, the preset multiple is 0.4 - 0.6.

[0010] Further, the obtaining of the first minimum saturation drain-source voltage corresponding to the drain-source voltage of the input transistor in the cascode amplifier includes:

[0011] Take the difference between the gate-source voltage of the input transistor and the threshold voltage of the input transistor as the first minimum saturation drain-source voltage;

[0012] The obtaining of the second minimum saturation drain-source voltage corresponding to the drain-source voltage of the cascode transistor in the cascode amplifier includes:

[0013] Take the difference between the gate-source voltage of the cascode transistor and the threshold voltage of the cascode transistor as the second minimum saturation drain-source voltage.

[0014] Further, the cascode amplifier includes a first-stage amplifier and a second-stage amplifier. The first-stage amplifier includes the input transistor and the cascode transistor, and the second-stage amplifier includes the gain transistor; the input transistor is connected to the gain transistor through the cascode transistor.

[0015] An embodiment of the present invention provides a cascode amplifier biasing device, including:

[0016] A minimum saturation drain-source voltage acquisition module, configured to obtain a first minimum saturation drain-source voltage corresponding to the drain-source voltage of the input transistor in the cascode amplifier, and a second minimum saturation drain-source voltage corresponding to the drain-source voltage of the cascode transistor;

[0017] A gate bias voltage setting module is configured to set the gate bias voltage of the cascode transistor according to the first minimum saturation drain-source voltage and the second minimum saturation drain-source voltage, so that the drain-source voltage of the input transistor is greater than or equal to the first minimum saturation drain-source voltage, and the drain-source voltage of the cascode transistor is greater than or equal to the second minimum saturation drain-source voltage.

[0018] An embodiment of the present invention provides a computer-readable storage medium, which includes a stored computer program. When the computer program runs, it controls the device where the computer-readable storage medium is located to execute the cascode amplifier biasing method as described above.

[0019] An embodiment of the present invention provides a cascode amplifier biasing circuit, including:

[0020] A sampling circuit, a shifting circuit, and a cascode amplifier circuit;

[0021] The sampling circuit is connected to the shifting circuit, and the shifting circuit is connected to the cascode amplifier circuit;

[0022] The sampling circuit is configured to sample the gate-source voltage of the gain transistor in the cascode amplifier circuit, and mirror the gate-source voltage of the gain transistor to obtain the gate-source voltage of the gain transistor with a preset multiple;

[0023] The shifting circuit is configured to superimpose the gate-source voltage of the gain transistor with the preset multiple and the gate-source voltage of the cascode transistor, and use the result as the gate bias voltage of the cascode transistor in the cascode amplifier circuit, so that the drain-source voltages of the input transistor and the cascode transistor are both greater than or equal to their corresponding minimum saturation drain-source voltages.

[0024] Further, the sampling circuit includes a first MOS transistor 、 a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a first resistor, and a second resistor;

[0025] The gate and drain of the first MOS transistor are short-circuited and then connected to the source of the second MOS transistor, and the source of the first MOS transistor is grounded; the gate and drain of the second MOS transistor are short-circuited and then the drain is connected to the positive power supply voltage V dd connection, and the gate of the second MOS transistor is short-circuited with the third MOS transistor; the drain of the third MOS transistor is short-circuited with the fourth MOS transistor whose gate and drain are short-circuited, and the source of the third MOS transistor is short-circuited with the upper end of the first resistor; the source of the fourth MOS transistor is connected to the positive power supply voltage, and the drain of the fourth MOS transistor whose gate and drain are short-circuited is connected to the shifting circuit; the lower end of the first resistor is connected to the upper end of the second resistor and the shifting circuit; the lower end of the second resistor is connected to V ss connection;

[0026] The cascode amplifier circuit includes a fifth MOS transistor, a sixth MOS transistor, and a seventh MOS transistor. The gate terminal of the fifth MOS transistor is the input terminal of the cascode amplifier circuit. The drain terminal of the fifth MOS transistor is connected to the source terminal of the sixth MOS transistor. The source terminal of the fifth MOS transistor is connected to V ss ; The gate terminal of the sixth MOS transistor is connected to the shift circuit, and the gate terminal of the sixth MOS transistor is the gate terminal of the cascode transistor. The source terminal of the sixth MOS transistor is connected to the drain terminal of the fifth MOS transistor, and the node between the source terminal of the sixth MOS transistor and the drain terminal of the fifth MOS transistor is the source terminal node of the cascode transistor. The drain terminal of the sixth MOS transistor is connected to the gate terminal of the seventh MOS transistor, and the drain terminal of the sixth MOS transistor is the output node of the cascode stage. The gate terminal of the sixth MOS transistor is the gate terminal of the cascode transistor; The drain terminal of the seventh MOS transistor is connected to the output terminal of the cascode amplifier circuit. The source terminal of the seventh MOS transistor is connected to V ss ;

[0027] The fifth MOS transistor is an input transistor, the sixth MOS transistor is a cascode transistor, and the seventh MOS transistor is a gain transistor. V ss is ground or a negative power supply voltage.

[0028] Further, the shift circuit includes an eighth MOS transistor and a ninth MOS transistor. After the gate and drain of the eighth MOS transistor are short-circuited, they are respectively connected to the cascode amplifier circuit and the drain terminal of the ninth MOS transistor; The source terminal of the ninth MOS transistor is connected to the positive power supply voltage Vdd. The gate terminal of the ninth MOS transistor is connected to the sampling circuit. After the gate and drain of the ninth MOS transistor are short-circuited, the drain terminal is connected to the drain terminal after the gate and drain of the eighth MOS transistor are short-circuited.

[0029] Further, the cascode amplifier circuit further includes a tenth MOS transistor, an eleventh MOS transistor, and a twelfth MOS transistor;

[0030] The drain terminal of the tenth MOS transistor is connected to the output node of the cascode stage. The gate terminal of the tenth MOS transistor is connected to the second bias voltage input terminal. The source terminal of the tenth MOS transistor is connected to the drain terminal of the eleventh MOS transistor; The source terminal of the eleventh MOS transistor is connected to the positive power supply voltage. The gate terminal of the eleventh MOS transistor is connected to the first bias voltage input terminal; The gate terminal of the twelfth MOS transistor is connected to the first bias voltage input terminal. The source terminal of the twelfth MOS transistor is connected to the positive power supply voltage V dd ; The drain terminal of the twelfth MOS transistor is connected to the output terminal of the cascode amplifier circuit.

[0031] Further, the resistance value of the second resistor is 0.5 times that of the first resistor, the size of the second MOS transistor is the same as that of the third MOS transistor, and the size of the seventh MOS transistor is the same as that of the sixth MOS transistor.

[0032] Further, the sampling circuit includes a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, a sixteenth MOS transistor, a third resistor, and a fourth resistor; the gate and drain of the thirteenth MOS transistor are short-circuited and then connected to the source terminal of the fourteenth MOS transistor, and the source terminal of the thirteenth MOS transistor is grounded; the gate and drain of the fourteenth MOS transistor are short-circuited and then short-circuited to the input bias current and the gate terminal of the fifteenth MOS transistor; the drain terminal of the fifteenth MOS transistor is short-circuited to the sixteenth MOS transistor with its gate and drain short-circuited, and the source terminal of the fifteenth MOS transistor is short-circuited to the lower end of the third resistor; the source terminal of the sixteenth MOS transistor is connected to V ss , and the gate terminal of the sixteenth MOS transistor after its gate and drain are short-circuited is connected to the shift circuit; the upper end of the third resistor and the lower end of the fourth resistor are connected to the shift circuit, and the upper end of the fourth resistor is connected to the positive power supply voltage V dd connected;

[0033] The cascode amplifier circuit includes a seventeenth MOS transistor, an eighteenth MOS transistor, and a nineteenth MOS transistor. The gate terminal of the seventeenth MOS transistor is the input terminal of the cascode amplifier, and the source terminal of the seventeenth MOS transistor is connected to V dd ; the drain terminal of the seventeenth MOS transistor is connected to the source terminal of the eighteenth MOS transistor, and the node between the drain terminal of the seventeenth MOS transistor and the source terminal of the eighteenth MOS transistor M2 is the source terminal node of the cascode transistor, and the drain terminal of the eighteenth MOS transistor is the cascode stage output node; the gate terminal of the eighteenth MOS transistor is connected to the gate terminal of the nineteenth MOS transistor in the shift circuit, and the gate terminal of the eighteenth MOS transistor is the cascode transistor gate terminal; the drain terminal of the nineteenth MOS transistor is connected to V out , and the source terminal of the nineteenth MOS transistor is connected to V dd ; the seventeenth MOS transistor is the input transistor, the eighteenth MOS transistor is the cascode transistor, the nineteenth MOS transistor is the gain transistor, and V ss is ground or a negative power supply voltage.

[0034] Further, the shift circuit includes a twentieth MOS transistor and a twenty-first MOS transistor. The source terminal of the twentieth MOS transistor is connected to the third resistor R A1The upper end of the [component] is short-circuited with the lower end of the fourth resistor. After the gate and drain of the twentieth MOS transistor are short-circuited, they are respectively connected to the cascode amplifier circuit and the drain terminal of the MOS transistor; the gate terminal of the twenty-first MOS transistor is connected to the sampling circuit, the source terminal of the twenty-first MOS transistor is grounded, and the drain terminal of the twenty-first MOS transistor is short-circuited with the twentieth MOS transistor whose gate and drain are short-circuited.

[0035] Further, the cascode amplifier circuit further includes a twenty-second MOS transistor, a twenty-third MOS transistor, and a twenty-fourth MOS transistor;

[0036] The drain terminal of the twenty-second MOS transistor is connected to the cascode stage output node, the gate terminal of the twenty-second MOS transistor is connected to the second bias voltage input terminal, and the source terminal of the twenty-second MOS transistor is connected to the drain terminal of the twenty-third MOS transistor; the source terminal of the twenty-third MOS transistor is connected to V ss , the gate terminal of the twenty-third MOS transistor is connected to the first bias voltage input terminal; the gate terminal of the twenty-fourth MOS transistor is connected to the first bias voltage input terminal, the source terminal of the twenty-fourth MOS transistor is connected to V ss connection, and the drain terminal of the twenty-fourth MOS transistor is connected to the output terminal of the cascode amplifier circuit.

[0037] Further, the resistance value of the fourth resistor is 0.5 times that of the third resistor, the size of the fourteenth MOS transistor is the same as that of the fifteenth MOS transistor, and the size of the twenty-first MOS transistor is the same as that of the eighteenth MOS transistor.

[0038] In the embodiment of the present invention, according to the values of the first minimum saturation drain-source voltage and the second minimum saturation drain-source voltage, the gate bias voltage of the cascode transistor is set so that the drain-source voltage of the input transistor is greater than or equal to the first minimum saturation drain-source voltage, and the drain-source voltage of the cascode transistor is greater than or equal to the second minimum saturation drain-source voltage, so that the two MOS transistors of the cascode stage, the input transistor and the cascode transistor are in the saturation region at all temperatures and process corners, so that the cascode amplifier obtains a stable gain. Description of the Drawings

[0039] Figure 1 is a schematic flow chart of a method for biasing a cascode amplifier provided by an embodiment of the present invention;

[0040] Figure 2 is a circuit structure diagram of a cascode two-stage amplifier with an N-type cascode stage provided by an embodiment of the present invention;

[0041] Figure 3 is a circuit structure diagram of a cascode two-stage amplifier with a P-type cascode stage provided by an embodiment of the present invention;

[0042] Figure 4 It is a schematic diagram showing the relationship between the gate-source voltage of the gain tube, the drain-source voltage of the input tube, the drain-source voltage of the cascode tube and temperature provided by an embodiment of the present invention;

[0043] Figure 5 It is a schematic structural diagram of a cascode amplifier biasing device provided by an embodiment of the present invention;

[0044] Figure 6 It is a schematic structural diagram of a cascode amplifier biasing circuit provided by an embodiment of the present invention;

[0045] Figure 7 It is another schematic structural diagram of a cascode amplifier biasing circuit provided by an embodiment of the present invention;

[0046] Figure 8 It is another schematic structural diagram of a cascode amplifier biasing circuit provided by an embodiment of the present invention;

[0047] Figure 9 It is a schematic structural diagram of a fully transistor circuit of a single-ended output rail-to-rail output operational amplifier provided by an embodiment of the present invention;

[0048] Figure 10 It is another schematic diagram of a fully transistor circuit of a single-ended output rail-to-rail output operational amplifier provided by an embodiment of the present invention. Detailed implementation manners

[0049] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present application.

[0050] In the description of the present application, it should be understood that the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0051] In the description of the present application, it should be noted that unless otherwise clearly specified and defined, the terms "installation", "connection", and "coupling" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0052] It should be noted that the embodiments of the present invention are applicable to a cascode amplifier, including a cascode amplifier composed of two-stage amplifiers connected. The cascode amplifier may include a first-stage amplifier and a second-stage amplifier. The first-stage amplifier includes an input transistor, a cascode transistor, and a cascode load. The input transistor and the cascode transistor are called the cascode stage. The second-stage amplifier includes a gain transistor and a load transistor; the input transistor is connected to the gain transistor through the cascode transistor.

[0053] Please refer to Figure 1 , an embodiment of the present invention provides a cascode amplifier biasing method, including:

[0054] S1. Obtain a first minimum saturation drain-source voltage corresponding to the drain-source voltage of the input transistor in the cascode amplifier, and a second minimum saturation drain-source voltage corresponding to the drain-source voltage of the cascode transistor;

[0055] In the embodiments of the present invention, when the drain-source voltage of the input transistor is greater than or equal to the first minimum saturation drain-source voltage, and the drain-source voltage of the cascode transistor is greater than or equal to the second minimum saturation drain-source voltage, it can be ensured that the input transistor and the cascode transistor are in the saturation region.

[0056] The saturation drain-source voltage can be calculated by the difference between the gate-source voltage and the threshold voltage of the MOS transistor. In actual application scenarios, the saturation drain-source voltage fluctuates with process and temperature differences. In order to obtain a more accurate minimum saturation drain-source voltage, simulation is performed on the basis of obtaining the above difference, so as to be able to obtain an accurate saturation power fluctuation range, and further be able to accurately obtain the value of the minimum saturation drain-source voltage.

[0057] S2. Set the gate bias voltage of the cascode transistor according to the first minimum saturation drain-source voltage and the second minimum saturation drain-source voltage, so that the drain-source voltage of the input transistor is greater than or equal to the first minimum saturation drain-source voltage, and the drain-source voltage of the cascode transistor is greater than or equal to the second minimum saturation drain-source voltage.

[0058] In an embodiment of the present invention, according to the values of the first minimum saturation drain-source voltage and the second minimum saturation drain-source voltage, the gate bias voltage of the cascode transistor is set, so that the drain-source voltage of the input transistor is greater than or equal to the first minimum saturation drain-source voltage, and the drain-source voltage of the cascode transistor is greater than or equal to the second minimum saturation drain-source voltage, thereby enabling the two MOS transistors in the cascode stage, namely the input transistor and the cascode transistor, to be in the saturation region at all temperatures and process corners, so as to improve the performance of the cascode amplifier.

[0059] In one embodiment, setting the gate bias voltage of the cascode transistor specifically includes:

[0060] In the cascode amplifier, the gate-source voltage of a preset multiple of the gain transistor is superimposed on the gate voltage of the cascode transistor to obtain a superimposed voltage value, and the superimposed voltage value is used as the gate bias voltage of the cascode transistor.

[0061] In an embodiment of the present invention, after the gate-source voltage of a preset multiple of the gain transistor is superimposed on the gate voltage of the cascode transistor and used as the gate bias voltage of the cascode transistor, the drain-source voltage of the cascode transistor is the gate-source voltage of the gain transistor of this preset multiple. According to the voltage relationship among the cascode transistor, the input transistor, and the gain transistor, the voltage relationship between the drain-source voltage of the input transistor and the gate-source voltage of the gain transistor can be obtained. For example, in a specific implementation manner, the drain-source voltage of the input transistor is the product of (1 - the preset multiple) and the gate-source voltage of the gain transistor. Since the minimum saturation drain-source voltage of the MOS transistor is small, in a preferred implementation manner, when the preset multiple is set to 0.5, it can be ensured that the drain-source voltage of the input transistor is greater than or equal to the first minimum saturation drain-source voltage, and the drain-source voltage of the cascode transistor is greater than or equal to the second minimum saturation drain-source voltage.

[0062] In one embodiment, the preset multiple is 0.4 - 0.6.

[0063] In an embodiment of the present invention, the sum of the gate-source voltage superposition value of a gain tube with a preset multiple and the gate voltage of a cascode tube is used as the gate bias voltage of the cascode tube. According to the structure of the cascode amplifier in the embodiment of the present invention, the sum of the drain-source voltage of the input tube and the drain-source voltage of the cascode tube is equal to the gate-source voltage of the gain tube. That is, after setting the gate bias voltage of the cascode in the above manner, the drain-source voltage of the cascode tube is equal to the gate-source voltage of the gain tube with a preset multiple. According to the voltage relationship between the cascode tube, the input tube, and the gain tube, the relationship between the drain-source voltage of the input tube and the gate-source voltage of the gain tube after setting the bias voltage of the cascode tube can be obtained. For example, when the preset multiple is 0.4, the drain-source voltage of the cascode tube is 0.4 times the gate-source voltage of the gain tube, and the drain-source voltage of the input tube is 0.6 times the gate-source voltage of the gain tube; when the preset multiple is 0.5, the drain-source voltage of the cascode tube and the drain-source voltage of the input tube are both 0.5 times the gate-source voltage of the gain tube; when the preset multiple is 0.6, the drain-source voltage of the cascode tube is 0.6 times the gate-source voltage of the gain tube, and the drain-source voltage of the input tube is 0.4 times the gate-source voltage of the gain tube. Since the lowest saturation drain-source voltage is a relatively small value, the preset multiple in the embodiment of the present invention is in the range of 0.4 - 0.6. Within this numerical range, the drain-source voltages of the cascode tube and the input tube must be less than their corresponding lowest saturation drain-source voltages, that is, it can be ensured that both the cascode tube and the input tube are in the saturation region. The numerical range of 0.4 - 0.6 for the preset multiple in the embodiment of the present invention is a preferred implementation manner. Under the condition of satisfying the condition of "making the drain-source voltage of the input tube greater than or equal to the first lowest saturation drain-source voltage, and the drain-source voltage of the cascode tube greater than or equal to the second lowest saturation drain-source voltage", the preset multiple can be adjusted according to needs within the value range between 0 and 1.

[0064] In one embodiment, obtaining the first lowest saturation drain-source voltage corresponding to the drain-source voltage of the input tube in a cascode amplifier includes:

[0065] Taking the difference between the gate-source voltage of the input tube and the threshold voltage of the input tube as the first lowest saturation drain-source voltage;

[0066] Obtaining the second lowest saturation drain-source voltage corresponding to the drain-source voltage of the cascode tube in a cascode amplifier includes:

[0067] Taking the difference between the gate-source voltage of the cascode tube and the threshold voltage of the cascode tube as the second lowest saturation drain-source voltage.

[0068] In order to obtain an accurate lowest saturation drain-source voltage, the embodiment of the present invention can further determine the fluctuation range of the saturation drain-source voltage through simulation, so as to obtain an accurate lowest saturation drain-source voltage according to this fluctuation range.

[0069] In one embodiment, a cascode amplifier includes a first-stage amplifier and a second-stage amplifier. The first-stage amplifier includes an input transistor and a cascode transistor, and the second-stage amplifier includes a gain transistor. The input transistor is connected to the gain transistor through the cascode transistor.

[0070] Please refer to Figures 2-3 , which is the core circuit diagram of two cascode amplifiers provided by the embodiments of the present invention. Among them, Figure 2 is a two-stage amplifier composed of a cascode amplifier with an NMOS input, Figure 3 is a two-stage amplifier composed of a cascode amplifier with a P input. A cascode amplifier biasing method provided by the embodiments of the present invention is applicable to the above two cascode amplifiers.

[0071] Among them, in Figure 2 , V in is the input signal, V out is the output signal, V b1 and V b2 are the bias voltages of the PMOS transistors. MOS transistor M0 is the cascode input transistor, MOS transistor M2 is the cascode transistor, MOS transistor M3 is the input transistor of the second stage, also known as the common-source stage input transistor. A, B, and C are the output node of the cascode stage, the source node of the cascode transistor, and the gate node of the cascode transistor respectively. In order to obtain a higher gain, it is generally required that both MOS transistors in the cascode stage are in the saturation region, that is, MOS transistor M0 and MOS transistor M2 are in the saturation region. At this time, the impedance looking from point A to the ground is the largest, that is, the gain is the largest. It should be noted that the output node A of the first-stage amplifier is directly connected to the gate of the input NMOS transistor M3 of the second-stage amplifier. Therefore, at a specific load current, the DC level of node A is determined and determined by M3. In order to ensure that both MOS transistor M0 and MOS transistor M2 are in the saturation region, it is required that the drain-source voltage V DS0 of MOS transistor M0 and the drain-source voltage V DS2 of MOS transistor M2 must both be greater than their corresponding minimum saturation drain-source voltages V DSAT0 and V DSAT2 , that is:

[0072] V DS0 ≥V DSAT0 , V DS2 ≥V DSAT2

[0073] Generally speaking, at a relatively large width-to-length ratio W / L and a relatively small bias current, V DSAT can be reduced to as low as 100 mV. However, in circuit design, in order to obtain better robustness, it is still necessary to set V DS to be more than 50 mV larger than V DSAT . Please refer to Figure 2 ,, it can be seen that VDS0 The sum with V DS2 is the gate-source voltage V of M3, that is: GS3 That is:

[0074] V GS3 = V DS2 + V DS0

[0075] Similarly, in Figure 3 , in order to ensure that both the MOS transistor M0 and the MOS transistor M2 are in the saturation region, it is required that the drain-source voltage V of the MOS transistor M0 DS0 and the drain-source voltage V of the MOS transistor M2 DS2 must both be greater than their corresponding minimum saturation drain-source voltages V DSAT0 and V DSAT2 , that is: V DS0 ≥ V DSAT0 , V DS2 ≥ V DSAT2 , and Figure 3 the sum of V DS0 and V DS2 in is the gate-source voltage V of M3 GS3 , that is:

[0076] V GS3 = V DS2 + V DS0

[0077] Please refer to Figure 4 , when the preset multiple is set to 0.5, the schematic diagram of the relationship between the above three voltages and temperature, where the abscissa is temperature and the ordinate is voltage. Among them, L1 represents the gate-source voltage V of the common-source input transistor (gain transistor) GS , which decreases as the temperature increases and has a large slope; L2 represents the drain-source voltage V of the cascode input transistor DS , whose value is 0.5V GS , which also decreases as the temperature increases and the slope is half of V GS ; similarly, L3 represents the drain-source voltage V of the cascode transistor DS , whose value is also 0.5V GS , which also decreases as the temperature increases and the slope is half of V GS . It can be seen from Figure 3 that in the wide temperature range, the embodiments of the present invention can enable both the input transistor and the cascode transistor to be in the saturation region, thereby effectively improving the performance of the cascode amplifier.

[0078] Implementing the embodiments of the present invention has the following beneficial effects:

[0079] In an embodiment of the present invention, according to the values of the first minimum saturation drain-source voltage and the second minimum saturation drain-source voltage, the gate bias voltage of the cascode transistor is set such that the drain-source voltage of the input transistor is greater than or equal to the first minimum saturation drain-source voltage, and the drain-source voltage of the cascode transistor is greater than or equal to the second minimum saturation drain-source voltage, so that the two MOS transistors in the cascode stage, namely the input transistor and the cascode transistor, are in the saturation region at all temperatures and process corners, thereby ensuring that the bandwidth and gain of the cascode amplifier do not decay significantly, and improving the performance of the cascode amplifier.

[0080] Based on the same inventive concept as the above embodiment, an embodiment of the present invention provides a cascode amplifier biasing device as shown in Figure 5 and includes:

[0081] A minimum saturation drain-source voltage acquisition module 10, configured to acquire a first minimum saturation drain-source voltage corresponding to the drain-source voltage of the input transistor in the cascode amplifier, and a second minimum saturation drain-source voltage corresponding to the drain-source voltage of the cascode transistor;

[0082] A gate bias voltage setting module 20, configured to set the gate bias voltage of the cascode transistor according to the first minimum saturation drain-source voltage and the second minimum saturation drain-source voltage, such that the drain-source voltage of the input transistor is greater than or equal to the first minimum saturation drain-source voltage, and the drain-source voltage of the cascode transistor is greater than or equal to the second minimum saturation drain-source voltage.

[0083] In one embodiment, the gate bias voltage setting module 20 is specifically configured to:

[0084] Superimpose the gate-source voltage of the gain transistor in the cascode amplifier multiplied by a preset multiple on the gate voltage of the cascode transistor to obtain a superimposed voltage value, and use the superimposed voltage value as the gate bias voltage of the cascode transistor.

[0085] In one embodiment, the preset multiple is 0.4 - 0.6.

[0086] In one embodiment, acquiring the first minimum saturation drain-source voltage corresponding to the drain-source voltage of the input transistor in the cascode amplifier includes:

[0087] Taking the difference between the gate-source voltage of the input transistor and the threshold voltage of the input transistor as the first minimum saturation drain-source voltage;

[0088] Acquiring the second minimum saturation drain-source voltage corresponding to the drain-source voltage of the cascode transistor in the cascode amplifier includes:

[0089] Taking the difference between the cascode transistor voltage and the threshold voltage of the cascode transistor as the second minimum saturation drain-source voltage.

[0090] In one embodiment, a cascode amplifier includes a first-stage amplifier and a second-stage amplifier. The first-stage amplifier includes an input transistor and a cascode transistor, and the second-stage amplifier includes a gain transistor. The input transistor is connected to the gain transistor through the cascode transistor.

[0091] An embodiment of the present invention provides a computer-readable storage medium, which includes a stored computer program. When the computer program runs, it controls the device where the computer-readable storage medium is located to execute the cascode amplifier biasing method as described above.

[0092] Please refer to Figure 6 , an embodiment of the present invention provides a cascode amplifier biasing circuit, including:

[0093] a sampling circuit 101, a shift circuit 102, and a cascode amplifier circuit 103;

[0094] The sampling circuit 101 is connected to the shift circuit 102, and the shift circuit 102 is connected to the cascode amplifier circuit 103;

[0095] The sampling circuit 101 is configured to sample the gate-source voltage of the gain transistor in the cascode amplifier circuit 103, and mirror the gate-source voltage of the gain transistor to obtain the gate-source voltage of the gain transistor with a preset multiple.

[0096] In a specific embodiment, after sampling the gate-source voltage of the gain transistor in the cascode amplifier circuit 103, the voltage can also be buffered by a gain buffer, and 0.5 times of the voltage can be obtained through voltage division.

[0097] The shift circuit 102 is configured to superimpose the gate-source voltage of the gain transistor with a preset multiple on the gate-source voltage of the cascode transistor, and use it as the gate biasing voltage of the cascode transistor in the cascode amplifier circuit 103, so that the drain-source voltages of the input transistor and the cascode transistor are both greater than or equal to their corresponding minimum saturation drain-source voltages.

[0098] In an embodiment of the present invention, to ensure that both the cascode transistor and the input transistor operate in the saturation region, the gate-source voltage of a preset multiple of gain transistors is superimposed on the gate-source voltage of the cascode transistor to serve as the gate bias voltage of the cascode transistor. That is, the drain-source voltage of the cascode transistor is the gate-source voltage of the preset multiple of gain transistors, and the drain-source voltage of the input transistor is the product of (1 - the preset multiple) and the gate-source voltage of the gain transistor. Since the minimum saturation drain-source voltage of a MOS transistor is relatively small, in a preferred embodiment, when the preset multiple is set to 0.5, it can ensure that the drain-source voltage of the input transistor is greater than or equal to the first minimum saturation drain-source voltage, and the drain-source voltage of the cascode transistor is greater than or equal to the second minimum saturation drain-source voltage. Thus, both the cascode transistor and the input transistor operate in the saturation region, and further, the cascode amplifier can obtain stable gain. Under the condition of satisfying the requirement that "the drain-source voltage of the input transistor is greater than or equal to the first minimum saturation drain-source voltage, and the drain-source voltage of the cascode transistor is greater than or equal to the second minimum saturation drain-source voltage", the preset multiple can be adjusted within the range of 0 to 1 according to needs.

[0099] In a specific embodiment, the difference between the gate-source voltage and the threshold voltage of the input transistor is used as its saturation drain-source voltage; the difference between the gate-source voltage and the threshold voltage of the cascode transistor is used as its corresponding saturation drain-source voltage. To obtain an accurate minimum saturation drain-source voltage, the embodiment of the present invention can further determine the fluctuation range of the saturation drain-source voltage through simulation to obtain an accurate minimum saturation drain-source voltage.

[0100] Please refer to Figure 7 , in an embodiment, the sampling circuit 101 includes a first MOS transistor M A0、 a second MOS transistor M A1 , a third MOS transistor M A2 , a fourth MOS transistor M A4 , a first resistor R A1 and a second resistor R A2 ;

[0101] The gate and drain of the first MOS transistor M A0 are short-circuited and then connected to the source of the second MOS transistor M A1 , and the source of the first MOS transistor M A0 is grounded; the gate and drain of the second MOS transistor M A1 are short-circuited and then the drain is connected to the positive power supply voltage V dd , and the gate of the second MOS transistor M A1 is short-circuited to the third MOS M A2 transistor; the drain of the third MOS transistor M A2 is short-circuited to the fourth MOS transistor M A4 whose gate and drain are short-circuited, and the source of the third MOS M A2 transistor is connected to the first resistor RA1 is short-circuited at its upper end; the fourth MOS transistor M A4 has its source connected to the positive power supply voltage, and its drain is short-circuited to the fourth MOS transistor M A4 whose gate terminal is connected to the shift circuit 102; the first resistor R A1 has its lower end connected to the second resistor R A2 at its upper end and is connected to the shift circuit 102; the second resistor R A2 has its lower end connected to V ss is connected;

[0102] The cascode amplifier circuit 103 includes a fifth MOS transistor M0, a sixth MOS transistor M2, and a seventh MOS transistor M3. The gate terminal of the fifth MOS transistor M0 is the input terminal of the cascode amplifier circuit 103. The drain terminal of the fifth MOS transistor M0 is connected to the source terminal of the sixth MOS transistor M2. The source terminal of the fifth MOS transistor M0 is connected to V ss is connected; the gate terminal of the sixth MOS transistor M2 is connected to the shift circuit 102, and the gate terminal of the sixth MOS transistor M2 is the cascode transistor gate terminal. The source terminal of the sixth MOS transistor M2 is connected to the drain terminal of the fifth MOS transistor, and the node between the source terminal of the sixth MOS transistor M2 and the drain terminal of the fifth MOS transistor M0 is the cascode transistor source terminal node. The drain terminal of the sixth MOS transistor M2 is connected to the gate terminal of the seventh MOS transistor M3, and the drain terminal of the sixth MOS transistor M2 is the cascode stage output node. The gate terminal of the sixth MOS transistor M2 is the cascode transistor gate terminal; the drain terminal of the seventh MOS transistor M3 is connected to the output terminal of the cascode amplifier circuit 103, and the source terminal of the seventh MOS transistor M3 is connected to V ss is connected;

[0103] The fifth MOS transistor M0 is an input transistor, the sixth MOS transistor M2 is a cascode transistor, the seventh MOS transistor M3 is a gain transistor, and V ss is ground or a negative power supply voltage.

[0104] In the embodiment of the present invention, A, B, and C are respectively the cascode stage output node, the cascode transistor source terminal node, and the cascode transistor gate terminal. The MOS transistors M A0 ~M A3 , M0, and M2~M3 are NMOS transistors; the MOS transistors M A4 ~M A5 , M4~M6 are PMOS transistors.

[0105] Please continue to refer to Figure 7 , in one embodiment, the shift circuit 102 includes an eighth MOS transistor M A3 and a ninth MOS transistor M A5 . After the gate and drain of the eighth MOS transistor M A3 are short-circuited, they are respectively connected to the cascode amplifier circuit 103 and the drain terminal of the ninth MOS transistor M A5 ; the ninth MOS transistor MA5 The source terminal of the is connected to the positive power supply voltage Vdd, and the gate terminal of the ninth MOS transistor M A5 is connected to the sampling circuit 101. After the gate and drain of the ninth MOS transistor M A5 are short-circuited, the drain terminal is connected to the drain terminal after the gate and drain of the eighth MOS transistor M A3 are short-circuited.

[0106] Please continue to refer to Figure 7 , the cascode amplifier circuit 103 further includes a tenth MOS transistor M4, an eleventh MOS transistor M5, and a twelfth MOS transistor M6;

[0107] The drain terminal of the tenth MOS transistor M4 is connected to the cascode stage output node, the gate terminal of the tenth MOS transistor M4 is connected to the second bias voltage input terminal V b2 , and the source terminal of the tenth MOS transistor M4 is connected to the drain terminal of the eleventh MOS transistor M5; the source terminal of the eleventh MOS transistor M5 is connected to the positive power supply voltage, and the gate terminal of the eleventh MOS transistor M5 is connected to the first bias voltage input terminal V b1 ; the gate terminal of the twelfth MOS transistor M6 is connected to the first bias voltage input terminal V b1 , the source terminal of the twelfth MOS transistor M6 is connected to the positive power supply voltage V dd , and the drain terminal of the twelfth MOS transistor M6 is connected to the output terminal of the cascode amplifier circuit 103.

[0108] In one embodiment, the resistance value of the second resistor R A2 is 0.5 times the resistance value of the first resistor R A1 , the size of the second MOS transistor M A1 is the same as the size of the third MOS transistor M A2 , and the size of the eighth MOS transistor M A3 is the same as the size of the sixth MOS transistor M2.

[0109] In Figure 7 the shown embodiment, by adjusting the bias current I b it is possible to make the gate voltage of the first MOS transistor M A0 equal to the gate voltage V GS3 of the seventh MOS transistor M3, and since the second MOS transistor M A1 and the third MOS transistor M A2 have the same size and the same set current, the upper node voltage of the first resistor R A1 is also V GS3 . This voltage flows through the first resistor R A1 and the second resistor R A2 and generates a current, and this current is mirrored through the tenth MOS transistor M A4 and the eleventh MOS transistor M A5 and flows back to the second resistor R A2Above, by setting the second resistor R A2 = 0.5 times the first resistor R A1 . The current flowing through the second resistor R A2 is twice the current flowing through the first resistor R A1 . Therefore, the voltage across the first resistor R A1 is equal to the voltage across the second resistor R A2 . Thus, the source voltage of the eighth MOS transistor M A3 can be obtained as equal to 0.5V GS3 . By setting the size of the eighth MOS transistor M A3 to be substantially the same as the size of the sixth MOS transistor M2, and the current is also set to be substantially the same. Therefore, the gate-source voltage of the eighth MOS transistor M A3 is substantially equal to the gate-source voltage of the sixth MOS transistor M2. The gate terminal of the sixth MOS transistor M2, which is also the voltage at terminal C, is 0.5V GS3 +V GSA3 = 0.5V GS3 +V GS2 , where V GSA3 is the gate-source voltage of the eighth MOS transistor M A3 , and V GS2 is the gate-source voltage of the sixth MOS transistor M2. Thus, the voltage at terminal B can be obtained as 0.5V GS3 +V GS2 -V GS2 = 0.5V GS3 , thereby achieving that by setting the gate bias voltage of the cascode transistor, the drain-source voltage of the input transistor is greater than or equal to the first minimum saturation drain-source voltage, and the drain-source voltage of the cascode transistor is greater than or equal to the second minimum saturation drain-source voltage, to ensure that both the input transistor and the cascode transistor operate in the saturation region.

[0110] Please refer to Figure 8 . In one embodiment, the sampling circuit 101 includes a thirteenth MOS transistor M A0 , a fourteenth MOS transistor M A1 , a fifteenth MOS transistor M A2 , a sixteenth MOS transistor M A4 , a third resistor R A1 and a fourth resistor R A2 ; the gate and drain of the thirteenth MOS transistor M A0 are short-circuited and then connected to the source of the fourteenth MOS transistor M A1 , and the source of the thirteenth MOS transistor M A0 is grounded; the gate and drain of the fourteenth MOS transistor M A1 are short-circuited and then short-circuited to the input bias current and the gate of the fifteenth MOS transistor M A2 ; the drain of the fifteenth MOS transistor M A2 is connected to the sixteenth MOS transistor M with its gate and drain short-circuitedA4 Short - circuit the source terminal of the fifteenth MOS transistor M A2 to the lower end of the third resistor R A1 ; The source terminal of the sixteenth MOS transistor M A4 is connected to V ss , and the gate terminal of the sixteenth MOS transistor M A4 after the gate - drain short - circuit is connected to the shift circuit 102; The upper end of the third resistor R A1 is connected to the lower end of the fourth resistor R A2 , and the lower end of the fourth resistor R A2 is connected to the shift circuit 102, and the upper end of the fourth resistor R dd is connected to the positive power supply voltage V

[0111] The cascode amplifier circuit 103 includes the seventeenth MOS transistor M0, the eighteenth MOS transistor M2, and the nineteenth MOS transistor M3. The gate terminal of the seventeenth MOS transistor M0 is the input terminal of the cascode amplifier. The source terminal of the seventeenth MOS transistor M0 is connected to V dd ; The drain terminal of the seventeenth MOS transistor M0 is connected to the source terminal of the eighteenth MOS transistor M2, and the node between the drain terminal of the seventeenth MOS transistor M0 and the source terminal of the eighteenth MOS transistor M2 is the cascode transistor source - terminal node, and the drain terminal of the eighteenth MOS transistor M2 is the cascode - stage output node; The gate terminal of the eighteenth MOS transistor M2 is connected to the gate terminal of the nineteenth MOS transistor M3 in the shift circuit 102, and the gate terminal of the eighteenth MOS transistor M2 is the cascode transistor gate - terminal; The drain terminal of the nineteenth MOS transistor M3 is connected to V out , and the source terminal of the nineteenth MOS transistor M3 is connected to V dd ; The seventeenth MOS transistor M0 is the input transistor, the eighteenth MOS transistor M2 is the cascode transistor, the nineteenth MOS transistor M3 is the gain transistor, and V ss is ground or a negative power supply voltage.

[0112] In the embodiments of the present invention, A, B, and C are respectively the cascode - stage output node, the cascode transistor source - terminal node, and the cascode transistor gate - terminal; The MOS transistors M A0 ~M A3 , M0, and M2~M3 are PMOS transistors; The MOS transistors M A4 ~M A5 , M4~M6 are NMOS transistors.

[0113] Please continue to refer to Figure 8 , in one embodiment, the shift circuit 102 includes the twentieth MOS transistor M A3 and the twenty - first MOS transistor M A5 . The source terminal of the twentieth MOS transistor M A3 is short - circuited to the upper end of the third resistor R A1 and the lower end of the fourth resistor R A2 ; The source terminal of the twentieth MOS transistor MA3 After the gate-drain is shorted, it is respectively connected to the cascode amplifier circuit 103 and the drain terminal of the twenty-first MOS transistor M A5 ; The gate terminal of the twenty-first MOS transistor M A5 is connected to the sampling circuit 101, the source terminal of the twenty-first MOS transistor M A5 is grounded, and the drain terminal of the twenty-first MOS transistor M A5 is shorted to the drain terminal of the twentieth MOS transistor M A3 with the gate-drain shorted.

[0114] Please continue to refer to Figure 8 , in one embodiment, the cascode amplifier circuit 103 further includes a twenty-second MOS transistor M4, a twenty-third MOS transistor M5, and a twenty-fourth MOS transistor M6;

[0115] The drain terminal of the twenty-second MOS transistor M4 is connected to the cascode stage output node, the gate terminal of the twenty-second MOS transistor M4 is connected to the second bias voltage input terminal V b2 , and the source terminal of the twenty-second MOS transistor M4 is connected to the drain terminal of the twenty-third MOS transistor M5; The source terminal of the twenty-third MOS transistor M5 is connected to V ss , and the gate terminal of the twenty-third MOS transistor M5 is connected to the first bias voltage input terminal V b1 ; The gate terminal of the twenty-fourth MOS transistor M6 is connected to the first bias voltage input terminal V b1 , the source terminal of the twenty-fourth MOS transistor M6 is connected to V ss , and the drain terminal of the twenty-fourth MOS transistor M6 is connected to the output terminal of the cascode amplifier circuit 103.

[0116] In one embodiment, the resistance value of the fourth resistor R A2 is 0.5 times the resistance value of the third resistor R A1 , the size of the fourteenth MOS transistor M A1 is the same as the size of the fifteenth MOS transistor M A2 , and the size of the twentieth MOS transistor M A3 is the same as the size of the eighteenth MOS transistor M2.

[0117] In Figure 7 the illustrated embodiment, by adjusting the bias current I b the gate voltage of the thirteenth MOS transistor M A0 can be made equal to the gate voltage V dd -V GS3 of the nineteenth MOS transistor M3, the second MOS transistor M A1 has the same size as the third MOS transistor M A2 , the set currents are the same, and the voltage of the lower end node of the resistor R A1 is V dd -V GS3 . Vdd A voltage difference from this voltage flows through the third resistor R A1 and the fourth resistor R A2 and generates a current that passes through the sixteenth MOS transistor M A4 and the twenty - first MOS transistor M A5 for mirroring and then flows back to the fourth resistor R A2 Set R A2 = 0.5R A1 . The current flowing through the fourth resistor R A2 is twice the current flowing through the third R A1 . Thus, the voltage across the third R A1 is equal to the voltage across the fourth resistor R A2 . Therefore, the source voltage of the twentieth MOS transistor M A3 can be obtained as V dd - 0.5V GS3 . Set the size of the twentieth MOS transistor M A3 to be substantially the same as the size of the seventeenth MOS transistor M2, and the current is also set to be substantially the same. Thus, the gate - source voltage of the twentieth MOS transistor M A3 is substantially equal to the gate - source voltage of the eighteenth MOS transistor M2. The gate terminal of the eighteenth MOS transistor M2, which is also the voltage of endpoint C, is V dd - 0.5V GS3 - V GSA3 = V dd - 0.5V GS3 - V GS2 , where V GSA3 is the gate - source voltage of the twentieth MOS transistor M A3 , and V GS2 is the gate - source voltage of the eighteenth MOS transistor M2. Therefore, the voltage of endpoint B can be obtained as V dd - 0.5V GS3 - V GS2 + V GS2 = V dd - 0.5V GS3 , that is, the drain - source voltage of the seventeenth MOS M0 is 0.5V GS3 . Thus, by setting the gate - bias voltage of the cascode transistor, the drain - source voltage of the input transistor is greater than or equal to the first minimum saturation drain - source voltage, and the drain - source voltage of the cascode transistor is greater than or equal to the second minimum saturation drain - source voltage, so as to ensure that both the input transistor and the cascode transistor operate in the saturation region.

[0118] In one embodiment, refer to Figure 9 , for using the above - mentioned Figures 8-9A two-stage single-ended rail-to-rail output operational amplifier composed of a folded cascode first-stage amplifier and a common-source second-stage amplifier of the NMOS transistor input differential pair of the bias circuit. Among them, MOS transistors M2 to M5, M 10 ~M 13 are respectively P-type and N-type cascode stages, and MOS transistors M8 and M9 are the second-stage push-pull output amplifiers. This circuit can ensure that the drain-source voltages of MOS transistors M 10 ~M 13 are all half of the gate-source voltage of M9, and the drain-source voltages of M2 to M5 are all half of the gate-source voltage of MOS transistor M8.

[0119] In one embodiment, please refer to Figure 10 , which is a two-stage single-ended rail-to-rail output operational amplifier composed of a folded cascode first-stage amplifier and a common-source second-stage amplifier of the PMOS transistor input differential pair using the above Figures 8-9 bias circuit. Among them, MOS transistors M2 to M5, M 10 ~M 13 are respectively P-type and N-type cascode stages, and MOS transistors M8 and M9 are the second-stage push-pull output amplifiers. This circuit can ensure that the drain-source voltages of MOS transistors M 10 ~M 13 are all half of the gate-source voltage of MOS transistor M9, and the drain-source voltages of MOS transistors M2 to M5 are all half of the gate-source voltage of MOS transistor M8.

[0120] Implementing the embodiments of the present invention has the following beneficial effects:

[0121] In the embodiments of the present invention, the sampling circuit 101 samples the gate-source voltage of the gain transistor of the second-stage amplifier driven by the output end of the cascode stage, and mirrors this voltage to obtain a voltage value of a preset multiple of this voltage. The voltage equal to the gate-source voltage of the cascode transistor after mirroring is used as the gate bias voltage of the cascode transistor, so that the drain-source voltages of the cascode transistor and the cascode input transistor are both a certain multiple of the gate-source voltage of the input gain transistor of the second-stage amplifier, and the drain-source voltages of the cascode transistor and the cascode input transistor are both greater than or equal to their corresponding minimum saturation drain-source voltages. Furthermore, it can ensure that the cascode transistor and the cascode input transistor in the cascode amplifier can dynamically maintain working in the saturation region at all temperatures and process corners, ensuring the performance of the cascode amplifier.

[0122] Furthermore, the circuit structure of the embodiments of the present invention is simple, and the consumed area is relatively small, and it can be widely applied to the current advanced process and the SoC design with low power supply voltage.

[0123] The above are the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements are also regarded as the protection scope of the present invention.

Claims

1. A cascode amplifier biasing method, characterized in that, Comprising: Obtaining a first minimum saturation drain-source voltage corresponding to the drain-source voltage of an input transistor in a cascode amplifier, and a second minimum saturation drain-source voltage corresponding to the drain-source voltage of a cascode transistor; wherein, the cascode amplifier includes a first-stage amplifier and a second-stage amplifier, the first-stage amplifier includes the input transistor and the cascode transistor, the second-stage amplifier includes a gain transistor; the input transistor is connected to the gain transistor through the cascode transistor; Setting the gate bias voltage of the cascode transistor according to the first minimum saturation drain-source voltage and the second minimum saturation drain-source voltage, such that the drain-source voltage of the input transistor is greater than or equal to the first minimum saturation drain-source voltage, and the drain-source voltage of the cascode transistor is greater than or equal to the second minimum saturation drain-source voltage; wherein, the setting of the gate bias voltage of the cascode transistor is specifically: superimposing a gate-source voltage of a preset multiple of the gain transistor in the cascode amplifier on the gate-source voltage of the cascode transistor to obtain a superimposed voltage value, and taking the superimposed voltage value as the gate bias voltage of the cascode transistor.

2. The common-source and common-gate amplifier biasing method according to claim 1, wherein The preset multiple is 0.4 - 0.

6.

3. The cascode amplifier biasing method according to claim 1, wherein The obtaining of the first minimum saturation drain-source voltage corresponding to the drain-source voltage of the input transistor in the cascode amplifier includes: Taking the difference between the gate-source voltage of the input transistor and the threshold voltage of the input transistor as the first minimum saturation drain-source voltage; The obtaining of the second minimum saturation drain-source voltage corresponding to the drain-source voltage of the cascode transistor in the cascode amplifier includes: Taking the difference between the gate-source voltage of the cascode transistor and the threshold voltage of the cascode transistor as the second minimum saturation drain-source voltage.

4. A common source common gate amplifier biasing device, characterized in that Comprising: A minimum saturation drain-source voltage obtaining module, configured to obtain a first minimum saturation drain-source voltage corresponding to the drain-source voltage of an input transistor in a cascode amplifier, and a second minimum saturation drain-source voltage corresponding to the drain-source voltage of a cascode transistor; wherein, the cascode amplifier includes a first-stage amplifier and a second-stage amplifier, the first-stage amplifier includes the input transistor and the cascode transistor, the second-stage amplifier includes a gain transistor; the input transistor is connected to the gain transistor through the cascode transistor; A gate bias voltage setting module, configured to set the gate bias voltage of the cascode transistor according to the first minimum saturation drain-source voltage and the second minimum saturation drain-source voltage, such that the drain-source voltage of the input transistor is greater than or equal to the first minimum saturation drain-source voltage, and the drain-source voltage of the cascode transistor is greater than or equal to the second minimum saturation drain-source voltage; wherein, the setting of the gate bias voltage of the cascode transistor is specifically: superimposing a gate-source voltage of a preset multiple of the gain transistor in the cascode amplifier on the gate-source voltage of the cascode transistor to obtain a superimposed voltage value, and taking the superimposed voltage value as the gate bias voltage of the cascode transistor.

5. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored computer program, wherein, when the computer program runs, it controls the device where the computer-readable storage medium is located to execute the cascode amplifier biasing method according to any one of claims 1 to 3.

6. A common-source common-gate amplifier biasing circuit, characterized in that, Comprising: Sampling circuit, shift circuit and cascode amplifier circuit; The sampling circuit is connected to the shift circuit, and the shift circuit is connected to the cascode amplifier circuit; The sampling circuit is configured to sample the gate-source voltage of the gain transistor in the cascode amplifier circuit, and mirror the gate-source voltage of the gain transistor to obtain the gate-source voltage of the gain transistor with a preset multiple; The shift circuit is configured to superimpose the gate-source voltage of the gain transistor with the preset multiple and the gate-source voltage of the cascode transistor, and use it as the gate bias voltage of the cascode transistor in the cascode amplifier circuit, so that the drain-source voltages of the input transistor and the cascode transistor are both greater than or equal to their corresponding minimum saturation drain-source voltages; wherein, the drain end of the input transistor is connected to the source end of the cascode transistor, and the drain end of the cascode transistor is connected to the gate end of the gain transistor.

7. The cascode amplifier bias circuit according to claim 6, wherein The sampling circuit includes a first MOS transistor 、 a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a first resistor, and a second resistor; The gate and drain of the first MOS transistor are short-circuited and then connected to the source terminal of the second MOS transistor, and the source terminal of the first MOS transistor is grounded; the gate and drain of the second MOS transistor are short-circuited and then the drain terminal is connected to the positive power supply voltage V dd is connected, and the gate terminal of the second MOS transistor is short-circuited with the third MOS transistor; the drain terminal of the third MOS transistor is short-circuited with the fourth MOS transistor whose gate and drain are short-circuited, and the source terminal of the third MOS transistor is short-circuited with the upper end of the first resistor; the source electrode of the fourth MOS transistor is connected to the positive power supply voltage, and the gate terminal of the fourth MOS transistor whose drain is short-circuited is connected to the shift circuit; the lower end of the first resistor is connected to the upper end of the second resistor and the shift circuit; the lower end of the second resistor is connected to V ss is connected; The cascode amplifier circuit includes a fifth MOS transistor, a sixth MOS transistor, and a seventh MOS transistor. The gate terminal of the fifth MOS transistor is the input terminal of the cascode amplifier circuit. The drain terminal of the fifth MOS transistor is connected to the source terminal of the sixth MOS transistor. The source terminal of the fifth MOS transistor is connected to V ss ; The gate terminal of the sixth MOS transistor is connected to the shift circuit, and the gate terminal of the sixth MOS transistor is the gate terminal of the cascode transistor. The source terminal of the sixth MOS transistor is connected to the drain terminal of the fifth MOS transistor, and the node between the source terminal of the sixth MOS transistor and the drain terminal of the fifth MOS transistor is the source terminal node of the cascode transistor. The drain terminal of the sixth MOS transistor is connected to the gate terminal of the seventh MOS transistor, and the drain terminal of the sixth MOS transistor is the output node of the cascode stage. The gate terminal of the sixth MOS transistor is the gate terminal of the cascode transistor; The drain terminal of the seventh MOS transistor is connected to the output terminal of the cascode amplifier circuit. The source terminal of the seventh MOS transistor is connected to V ss ; The fifth MOS transistor is an input transistor, the sixth MOS transistor is a cascode transistor, and the seventh MOS transistor is a gain transistor. V ss is ground or a negative power supply voltage.

8. The cascode amplifier bias circuit according to claim 7, wherein The shift circuit includes an eighth MOS transistor and a ninth MOS transistor. After the gate and drain of the eighth MOS transistor are short-circuited, they are respectively connected to the cascode amplifier circuit and the drain end of the ninth MOS transistor; the source end of the ninth MOS transistor is connected to the positive power supply voltage Vdd, the gate end of the ninth MOS transistor is connected to the sampling circuit, and after the gate and drain of the ninth MOS transistor are short-circuited, the drain end is connected to the drain end after the gate and drain of the eighth MOS transistor are short-circuited.

9. The cascode amplifier bias circuit according to claim 6, wherein The cascode amplifier circuit further includes a tenth MOS transistor, an eleventh MOS transistor and a twelfth MOS transistor; The drain terminal of the tenth MOS transistor is connected to the cascode output node, the gate terminal of the tenth MOS transistor is connected to the second bias voltage input terminal, and the source terminal of the tenth MOS transistor is connected to the drain terminal of the eleventh MOS transistor; the source terminal of the eleventh MOS transistor is connected to the positive power supply voltage, the gate terminal of the eleventh MOS transistor is connected to the first bias voltage input terminal; the gate terminal of the twelfth MOS transistor is connected to the first bias voltage input terminal, and the source terminal of the twelfth MOS transistor is connected to the positive power supply voltage V dd is connected, and the drain terminal of the twelfth MOS transistor is connected to the output terminal of the cascode amplifier circuit.

10. The cascode amplifier bias circuit according to claim 8, characterized in that, The resistance value of the second resistor is 0.5 times that of the first resistor, the size of the second MOS transistor is the same as that of the third MOS transistor, and the size of the eighth MOS transistor is the same as that of the sixth MOS transistor.

11. The cascode amplifier bias circuit according to claim 6, wherein The sampling circuit includes a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, a sixteenth MOS transistor, a third resistor, and a fourth resistor; the gate and drain of the thirteenth MOS transistor are short-circuited and then connected to the source terminal of the fourteenth MOS transistor, and the source terminal of the thirteenth MOS transistor is grounded; the gate and drain of the fourteenth MOS transistor are short-circuited and then short-circuited to the input bias current and the gate terminal of the fifteenth MOS transistor; the drain terminal of the fifteenth MOS transistor is short-circuited to the sixteenth MOS transistor with its gate and drain short-circuited, and the source terminal of the fifteenth MOS transistor is short-circuited to the lower end of the third resistor; the source terminal of the sixteenth MOS transistor is connected to V ss , and the gate terminal of the sixteenth MOS transistor after its gate and drain are short-circuited is connected to the shift circuit; the upper end of the third resistor and the lower end of the fourth resistor are connected to the shift circuit, and the upper end of the fourth resistor is connected to the positive power supply voltage V dd connection; The cascode amplifier circuit includes a seventeenth MOS transistor, an eighteenth MOS transistor, and a nineteenth MOS transistor. The gate terminal of the seventeenth MOS transistor is the input terminal of the cascode amplifier, and the source terminal of the seventeenth MOS transistor is connected to V dd ; the drain terminal of the seventeenth MOS transistor is connected to the source terminal of the eighteenth MOS transistor, and the node between the drain terminal of the seventeenth MOS transistor and the source terminal of the eighteenth MOS transistor M2 is the source terminal node of the cascode transistor. The drain terminal of the eighteenth MOS transistor is the output node of the cascode stage; the gate terminal of the eighteenth MOS transistor is connected to the gate terminal of the nineteenth MOS transistor in the shift circuit, and the gate terminal of the eighteenth MOS transistor is the gate terminal of the cascode transistor; the drain terminal of the nineteenth MOS transistor is connected to V out , and the source terminal of the nineteenth MOS transistor is connected to V dd ; the seventeenth MOS transistor is the input transistor, the eighteenth MOS transistor is the cascode transistor, the nineteenth MOS transistor is the gain transistor, and V ss is ground or a negative power supply voltage.

12. The cascode amplifier bias circuit according to claim 11, wherein The said shift circuit includes a twentieth MOS transistor and a twenty-first MOS transistor. The source terminal of the twentieth MOS transistor is short-circuited with the upper end of the said third resistor R A1 and the lower end of the fourth resistor. After the gate and drain of the twentieth MOS transistor are short-circuited, they are respectively connected to the cascode amplifier circuit and the drain terminal of the MOS transistor. The gate terminal of the twenty-first MOS transistor is connected to the sampling circuit. The source terminal of the twenty-first MOS transistor is grounded. The drain terminal of the twenty-first MOS transistor is short-circuited with the twentieth MOS transistor whose gate and drain are short-circuited.

13. The cascode amplifier bias circuit according to claim 6, wherein The cascode amplifier circuit further includes a twenty-second MOS transistor, a twenty-third MOS transistor and a twenty-fourth MOS transistor; The drain terminal of the twenty-second MOS transistor is connected to the cascode output node, the gate terminal of the twenty-second MOS transistor is connected to the second bias voltage input terminal, and the source terminal of the twenty-second MOS transistor is connected to the drain terminal of the twenty-third MOS transistor; the source terminal of the twenty-third MOS transistor is connected to V ss , the gate terminal of the twenty-third MOS transistor is connected to the first bias voltage input terminal; the gate terminal of the twenty-fourth MOS transistor is connected to the first bias voltage input terminal, the source terminal of the twenty-fourth MOS transistor is connected to V ss is connected, and the drain terminal of the twenty-fourth MOS transistor is connected to the output terminal of the cascode amplifier circuit.

14. The cascode amplifier bias circuit according to claim 12, wherein The resistance value of the fourth resistor is 0.5 times that of the third resistor, the size of the fourteenth MOS transistor is the same as that of the fifteenth MOS transistor, and the size of the twentieth MOS transistor is the same as that of the eighteenth MOS transistor.

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