A split pipeline successive approximation analog-to-digital converter with selectable sampling modes

Abstract

The present invention belongs to the technical field of integrated circuits, and specifically relates to a split pipeline successive approximation analog-to-digital converter with selectable sampling modes. The circuit of the present invention consists of two symmetrical half channels, and each half channel includes: a first-stage ADC with selectable sampling modes, a ringing operational amplifier using level shifting technology, a second-stage ADC, and related digital circuits for controlling the selection of sampling modes. The present invention selects the sampling mode of the first-stage ADC according to an externally input sampling mode control signal, so that the actual sampled value of the system is the input signal or its positive and negative level offsets or its scaled value; the four modes provide a circuit implementation for more stringent criteria based on the digital background correction algorithm of the Split architecture, avoiding mis-convergence. The level shifting technology reduces the power consumption of the operational amplifier, and the closed-loop amplification reduces the gain error. The two-stage ADC works in a pipeline manner, making the circuit more suitable for the application scenarios of low-power, high-speed, and high-precision ADCs.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a split pipeline - successive approximation analog - to - digital converter with selectable sampling modes. Background Art

[0002] With the increasing requirements for data, high - speed and high - resolution analog - to - digital converters are indispensable. Pipeline analog - to - digital converters (Pipeline ADCs) have good advantages in terms of high speed and high precision, but have high power consumption; combining successive approximation analog - to - digital converters (SAR ADCs), which have medium precision and speed but low power consumption, with Pipeline ADCs, the resulting pipelined - successive approximation analog - to - digital converters (Pipelined - SAR ADCs) are more energy - efficient than traditional Pipeline ADCs and are superior to SAR ADCs in terms of speed, resolution, and linearity. Therefore, they have great advantages in the field of high - performance high - speed high - resolution ADCs.

[0003] Traditional Pipelined - SAR ADCs rely on high - performance operational transconductance amplifiers (OTAs) in switched - capacitor circuits to accurately amplify the residue, resulting in high power consumption. If a dynamic amplifier with extremely low power consumption is used, fluctuations in process, power supply voltage, and temperature (PVT) will bring large gain errors, thus introducing significant non - linearity into the system. Using a ringing amplifier for residue amplification, the closed - loop operation improves the accuracy of the gain. Since there is no static power consumption, the circuit also has good power efficiency. Therefore, it has advantages in the design of high - precision high - speed ADCs.

[0004] According to Moore's law, the process nodes of integrated circuit design and manufacturing are constantly advancing. In advanced processes (such as 28nm CMOS process), the design of high - performance ADCs relies more on various front - end or back - end calibration techniques to correct errors and improve performance compared to designs in traditional processes (such as 0.18μm CMOS process). Front - end calibration techniques refer to extracting and correcting errors in the ADC before it officially operates, and they cannot achieve good calibration effects for new errors and error variations generated during actual operation. Therefore, back - end calibration techniques are often more favored. The split - ADC (Split - ADC) architecture is a physical architecture with small hardware overhead, low power - consumption cost, easy digital modeling, and can achieve good digital back - end calibration.

[0005] Figure 1The schematic diagram of the Split-ADC architecture is given, that is, the normal single-channel ADC is split into two, obtaining two half-channel ADCs that sample the same signal. Among them, each half-channel has half the size of the passive part capacitance and half the size of the active part transconductance of the original ADC. Therefore, in terms of area and power consumption overhead, each half-channel is half of the original ADC, making the total area and power consumption basically the same as the original ADC. The final output result of the Split-ADC is obtained by averaging the quantization results of the two half-channels respectively. Therefore, the noise performance is also the same as that of the original ADC.

[0006] In the calibration method based on the Split-ADC, both half-channels need to be calibrated. The core idea of the calibration is based on the basic mathematical property of linearity, that is, an approximate expression of translational invariance:

[0007] h(x + Δ) = h(x) + c, (1)

[0008] As the criterion for determining whether the quantization transfer function of the channel is a straight line.

[0009] In the above formula, h(·) is the overall transfer function of the ADC after calibration, x is the input signal, Δ is a fixed offset added to the input signal, and c is a constant. That is to say, for a given ADC, the quantization result of its input x after calibration is h(x), and the quantization result of the input (x + Δ) after calibration is h(x + Δ). If for any input x and (x + Δ), the difference between the quantization results h(x) and h(x + Δ) after calibration is a constant c, then it can be determined that its overall quantization transfer function after calibration is linear.

[0010] For the two half-channels of the Split-ADC, each has an overall transfer function h A (·) and h B (·). Then the formula (1) can be indirectly realized through the following relationship:

[0011] h A (x) - h B (x) = a, (2)

[0012] h A (x + Δ) - h B (x) = b, (3)

[0013] It can be seen that if (2) and (3) can be satisfied simultaneously, it is equivalent to satisfying (1). What these two equations represent is that in the two half-channels A and B of the split-ADC, if channel A operates in two modes, mode I is to normally sample x, and in mode II, a fixed bias is first added to the input signal and then sampled (x + Δ); while channel B always samples normally. According to the error extraction method described above, if the quantization differences of the two channels are two constants independent of the input signal in mode I and mode II respectively, it can be shown that channel A is linear, and it can be immediately obtained from (2) that channel B is also linear. Obviously, this determination condition is independent of the specific structure of the ADC, so this method is universal and can be extended to various different ADC designs and calibration structures, having good promotional significance.

[0014] However, the above Split-ADC non-linearity detection method has defects. Theoretically, there should be another condition satisfied in (1 - 3), that is, Δ is an infinitesimal quantity, or (1 - 3) holds for any Δ. But in the actual circuit implementation, Δ is a fixed value. Therefore, for a step with Δ as the width and a constant c as the step height, such a transfer function can still satisfy (1 - 3), but it is not linear. Therefore, to ensure the universality of this method, the linear determination condition of the Split-ADC needs to be more stringent, for example, introducing a proportional scaling condition of the input signal.

[0015] h A (kx) - kh B (x) = 0, k ≠ 0, (4)

[0016] That is, channel A samples the proportional signal of the input signal in mode three, channel B samples normally, and the digital code values output by the two channels also have the same value after being scaled by the same ratio. Proving the linearity of the circuit using (1 - 4) requires the ADC to have at least three different sampling modes. Summary of the Invention

[0017] The object of the present invention is to propose a split pipelined - successive approximation analog - to - digital converter with selectable sampling modes.

[0018] The split pipelined - successive approximation analog - to - digital converter with selectable sampling modes proposed by the present invention is based on the Split - ADC architecture. The overall circuit consists of two symmetric half - channels. Each half - channel circuit includes: a first - stage successive approximation analog - to - digital converter (SAR ADC) with selectable sampling modes, a ringing operational amplifier using level - shifting technology, a second - stage successive approximation analog - to - digital converter (SAR ADC), and related digital circuits for controlling the sampling mode selection; where:

[0019] The relevant digital circuit for controlling the sampling mode selection generates a signal for controlling the sampling mode selection according to the externally input digital signal; the first-stage SAR-ADC with selectable sampling mode samples and quantizes the input signal on the bottom plate according to this mode selection signal, and generates the first-stage quantization digital code and the quantized analog residue; the ringing operational amplifier using the level shift technology amplifies this analog residue signal, and the amplified signal is sampled and quantized by the second-stage SAR-ADC, and generates the second-stage quantization digital code; the two-stage SAR-ADC works in a pipelined manner, and the digital code values of the first stage and the second stage are output after synchronization processing.

[0020] In the present invention, the relevant digital circuit for controlling the sampling mode selection includes a plurality of digital combinational logics. First, it synchronizes the externally input mode selection signal, and then generates a series of internal control codes and control signals through logic to control the first-stage SAR-ADC with selectable sampling mode, generating four different sampling modes; among them,

[0021] The first sampling mode is normal sampling, that is, the input signal VIN is fully loaded on the sampling capacitor array, so that the first-stage SAR-ADC with selectable sampling mode quantizes the input signal VIN;

[0022] The second sampling mode is proportional sampling, that is, a signal kVIN proportional to the input signal is loaded on the sampling capacitor array, so that the first-stage SAR-ADC with selectable sampling mode quantizes the signal kVIN proportional to the input signal, where k is a non-zero proportionality coefficient;

[0023] The third sampling mode is positive offset sampling, that is, after the signal kVIN proportional to the input signal is positively offset, it is loaded on the capacitor array, so that the first-stage SAR-ADC with selectable sampling mode quantizes the signal kVIN+△ proportional to the input signal, where k is a non-zero proportionality coefficient;

[0024] The fourth sampling mode is negative offset sampling, that is, after the signal kVIN proportional to the input signal is negatively offset, it is loaded on the capacitor array, so that the first-stage SAR-ADC with selectable sampling mode quantizes the signal kVIN-△ proportional to the input signal, where k is a non-zero proportionality coefficient.

[0025] In the present invention, the first-stage SAR-ADC with selectable sampling mode includes a gate voltage bootstrap circuit with selectable sampling mode, a sampling capacitor array, a dynamic comparator circuit, and a successive approximation digital logic; among them:

[0026] The sampling-mode selectable bootstrap circuit is used to generate the gate voltage of the NMOS sampling switch corresponding to each sampling capacitor, and control the on / off of the sampling switch in different sampling modes; the signal is loaded on the sampling capacitor array after passing through the NMOS sampling switch, and the dynamic comparator circuit compares the sampled value with the reference voltage, and the comparison result controls the successive approximation digital logic to work, so that the reference voltage of the capacitor plate changes sequentially, and finally the first-stage digital code output and the analog margin are obtained.

[0027] In the present invention, the sampling-mode selectable bootstrap circuit, such as Figure 2 shown, includes a bootstrap voltage generation module (201), a controllable on / off bootstrap voltage output module (202), a main bootstrap voltage output module (203), and a virtual matching module (204); wherein:

[0028] The bootstrap voltage generation module (201) includes: 4 PMOS transistors P1, P2, P3, P4, 6 NMOS transistors N1, N2, N3, N4, N5, N6, and a bootstrap capacitor C boost , and is used to receive the input signal and bootstrap it under the control of the sampling phase control clocks CK and CKN, and generate a bootstrap signal that is higher than the input signal by VDD;

[0029] The controllable on / off bootstrap voltage output module (202) includes 4 PMOS transistors P5, P6, P7, P8 and 4 NMOS transistors N7, N8, N9, N10, where P6 and P7 have the same size and are conduction switches to control whether the module works; its input is the bootstrap voltage signal generated by the bootstrap voltage generation module, and according to the different control codes PN and control signals CON in the four sampling modes, the output is controlled so that the gate voltage of the sampling NMOS switch it controls is the bootstrap voltage signal generated by the bootstrap voltage generation module or GND;

[0030] The main bootstrap voltage output module (203) includes 3 PMOS transistors P9, P10, P11 and 3 NMOS transistors N11, N12, N13, and the input is the bootstrap voltage signal generated by the bootstrap voltage generation module; P9 and P10 are constantly conducting, so the output signal makes the gate terminal voltage of the sampling NMOS switch it controls still the bootstrap voltage generated by the bootstrap voltage generation module;

[0031] If instead of adding a main bootstrap voltage output module, the bootstrap voltage signal generated by the bootstrap voltage generation module is directly loaded onto the gate terminal of the NMOS sampling switch, then compared to the NMOS sampling switch controlled by the controllable on / off bootstrap voltage output module, the voltage signal at the gate will arrive earlier, and there will also be no voltage loss due to the drain-source voltage of P6 and P7 and the circuit noise introduced by other transistors. As a result, the gate signals of the two NMOS sampling switches under the same input signal will be inconsistent, introducing sampling non-linearity. In order to ensure that the gate signals loaded onto the NMOS sampling switch have the same delay, signal bandwidth, and voltage loss, and to minimize the introduction of sampling non-linearity as much as possible, the sizes of P9, P10, P11, N11, N12, and N13 are proportional to the sizes of P6, P7, P8, N8, N9, and N10 in the controllable on / off bootstrap voltage output module respectively, with the same proportionality coefficient, and equal to the ratio of the capacitances driven by the two modules.

[0032] The virtual matching module includes 4 PMOS transistors P12, P13, P14, P15 and 4 NMOS transistors N14, N15, N16, N17, and the device sizes and connection relationships are exactly the same as those of P5, P6, P7, P8 and N7, N8, N9, N10 in the controllable on / off bootstrap voltage output module. This module does not control any sampling NMOS switches, and its control signals PNN and CONN are opposite to PN and CON described above. When the output of the controllable on / off bootstrap voltage output module is a bootstrap signal higher than the input signal by VDD, P13 and P14 are not conducting, and the virtual matching module does not work. When the output voltage of the controllable on / off bootstrap voltage output module is GND (i.e., P6 and P7 are not conducting), P13 and P14 conduct, and the virtual matching module is connected to the circuit to ensure that the load at the output terminal of the bootstrap voltage generation module does not change, so that the output voltage of the main bootstrap voltage output module remains unchanged, improving the sampling linearity.

[0033] In the present invention, the ringing operational amplifier using the level-shifting technique amplifies differential signals using a pseudo-differential structure, and includes two symmetric ringing operational amplifier circuits using the level-shifting technique. Each operational amplifier circuit operates in a closed-loop circuit and achieves precise amplification by means of capacitor reallocation.

[0034] In the present invention, the open-loop circuit of the ringing operational amplifier circuit using the level-shifting technique is as Figure 3 shown, and includes: a bias-enhanced ringing operational amplifier (301), a nulling capacitor C Z (302), level-shifting capacitors C S1 , C S2 (303), a reset and level-shifting control circuit (304), and a common-mode feedback circuit (305); where:

[0035] The offset-enhanced ring oscillator operational amplifier (301) is composed of three cascaded inverters. The signal is input from the gates of the input transistors MP1 and MN1 of the first-stage inverter. Two equal-value resistors R1P and R1N are connected in series between the drain terminals of MP1 and MN1 to achieve self-bias enhancement of the second-stage inverter. The drain terminal of MP1 (the upper end of R1P) is connected to the gate of the input transistor MN2 of the second-stage inverter, and the drain terminal of MN1 (the lower end of R1N) is connected to the gate of the input transistor MP2 of the second-stage inverter. A resistor R2 is connected in series between the drain terminals of MP2 and MN2 to achieve self-bias of the third-stage inverter. The drain terminal of MP2 (the upper end of R2) is connected to the gate of the input transistor MP3 of the third-stage inverter, and the drain terminal of MN2 (the lower end of R2) is connected to the gate of the input transistor MN3 of the third-stage inverter. The amplified signal is output from the drain terminals of MP3 and MN3.

[0036] In the present invention, the reset and level-shifting control circuit (304) includes six control switches S, S1, S2, S3, S4, and S5 and includes two working phases and As Figure 4 shown, a high level indicates that the switch is closed; among them:

[0037] In phase (401), the input terminal (the top plate of the zero-adjustment capacitor C Z ) and the output terminal (the drain terminals of MP3 and MN3) of the ring oscillator operational amplifier circuit using the level-shifting technology are reset to the common mode. First, the zero-adjustment switch S is opened The two ends of the zero-adjustment capacitor C Z are connected to the common-mode signal for capacitor reset. The bias voltages VBP and VBN are respectively loaded on the top plates of the level-shifting capacitors C S1 , C S2 . Subsequently, the zero-adjustment switch S is closed Under the bias condition, the circuit offset error is extracted and stored on the zero-adjustment capacitor C Z to complete the self-zero calibration of the circuit;

[0038] In phase (402), the zero-adjustment switch S, the reset voltage, and the bias voltage are disconnected. The input signal passes through the zero-adjustment capacitor C Z and the level-shifting capacitors C S1 , C S2 . After canceling and shifting the DC level offset of the input signal, it is input to the gates of the input transistors MP1 and MN1 of the first-stage inverter for signal amplification.

[0039] The foregoing has generally described the features and technical advantages of the present invention. Below, a Pipelined-SAR ADC based on the Split-ADC architecture with a sampling rate of 200 MS / s and a resolution of 12 bits will be used as an example to more clearly illustrate the idea of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a schematic diagram of a split-type analog-to-digital converter architecture.

[0041] Figure 2 It is a schematic diagram of a gate voltage bootstrap circuit with selectable sampling modes.

[0042] Figure 3 It is an open-loop schematic diagram of a ringing operational amplifier circuit using level-shifting technology.

[0043] Figure 4 It is a schematic diagram of the switch working timing in a ringing operational amplifier circuit using level-shifting technology.

[0044] Figure 5 It is a schematic diagram of an example of a split two-stage Pipelined-SAR ADC with a sampling rate of 200 MS / s and a resolution of 12 bits.

[0045] Figure 6 It is a schematic diagram of the single-channel working timing of an example of a split two-stage Pipelined-SAR ADC with a sampling rate of 200 MS / s and a resolution of 12 bits.

[0046] Reference numerals in the figure: 201 is a bootstrap voltage generation module, 202 is a controllable on / off bootstrap voltage output module, 203 is a main bootstrap voltage output module, 204 is a virtual matching module, 301 is a bias-enhanced ringing operational amplifier, 302 is a zero-adjusting capacitor C Z , 303 is a level-shifting capacitor C S1 、C S2 , 304 is a reset and level-shifting control circuit, 305 is a common-mode feedback circuit, 401 is a working phase 402 is a working phase 501 is a related digital circuit for controlling sampling mode selection, 502 is a sampling controllable capacitor, 503 is an uncontrollable normal sampling capacitor. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0047] The split pipelined - successive approximation type analog - to - digital converter with selectable sampling mode designed by the present invention will be further described below in conjunction with the accompanying drawings. It should be noted that the pipelined - successive approximation type analog - to - digital converter provided by the present invention can have many different specifications and performance implementation methods, and the sampling - mode - selectable gate - voltage - bootstrap circuit and the ringing operational amplifier using level - shifting technology in the present invention can also have various application scenarios. The following implementation only provides a typical implementation circuit for the present invention, which is only used to illustrate the formation and use of the present invention, and is not used to limit the present invention.

[0048] The split pipelined - successive approximation type analog - to - digital converter with selectable sampling mode and its internal module circuit provided by the present invention. One implementation example is a two - stage Pipelined - SAR ADC with a sampling rate of 200 MS / s and a 12 - bit resolution. According to the requirements of the Split - ADC architecture, the single channel of this ADC is split into two half - channels A and B, and the front and rear two stages work in a pipelined manner. The specific implementation method is as Figure 5 shown. In this example, the power supply voltage is 0.9 V, VBP is 0.36 V, and VBN is 0.54 V.

[0049] In this example, the relevant digital circuit (501) for controlling the sampling mode selection receives the externally input sampling mode selection signal, generates an internal sampling mode control signal, and controls the working states of the bootstrap voltage output module (202) and the virtual matching module (204) that can be controlled to turn on and off, as well as the first - stage sampling capacitor array. To ensure the sampling linearity, channels A and B share the same sampling - mode - selectable gate - voltage - bootstrap circuit of the present invention. Therefore Figure 5 there are two bootstrap voltage output modules that can be controlled to turn on and off in the gate - voltage - bootstrap circuit, which respectively correspond to channel A and channel B, and there are two virtual matching modules that work alternately with them. Inside a single channel, the inter - stage margin is amplified in a pseudo - differential manner. Therefore, for the convenience of demonstration, the sampling capacitors of the first - stage SAR ADC are also shown in a differential form. For the convenience of distinction, the modules and signal flow directions related to channel B are represented by shading and dashed lines.

[0050] In this example, the first-stage SAR ADC is 4-bit, and the capacitance ratio corresponding to its MSB to LSB is 8C:4C:2C:C:C. Different residue curves need to be generated. Therefore, half of the LSB capacitance, i.e., 0.5C (502), is taken as the sampling controllable capacitance. Then, the load of the bootstrap voltage output module (202) with controllable on / off is 0.5C, and the load of the main bootstrap voltage output module (203) is (8C + 4C + 2C + C + 0.5C) * 2, i.e., 31C (503) (because channels A and B share a main bootstrap voltage output module). Also, the corresponding MOS transistor size ratio is 1:62 to ensure the matching of voltage loss, noise introduction, signal bandwidth, etc. at the two bootstrap voltage output terminals; the virtual matching module (204) is exactly the same as the bootstrap voltage output module (202) with controllable on / off to ensure that when the bootstrap voltage output module with controllable on / off is turned off, the load of the bootstrap voltage generation module (201) remains unchanged, thereby improving the sampling linearity.

[0051] Since the working modes and circuit connections of channels A and B are exactly the same, the subsequent description takes channel A as an example; the specific implementation methods of the four sampling methods and the working states of the sampling-mode selectable bootstrap circuit are as follows:

[0052] Normal sampling: In the sampling-mode selectable bootstrap circuit, the bootstrap voltage output module (202) with controllable on / off works, and the virtual matching module (204) does not work. The system sampling value is (Vip - Vin).

[0053] Proportional sampling: In the sampling-mode selectable bootstrap circuit, the bootstrap voltage output module (202) with controllable on / off does not work. At the sampling phase, the bottom plate of the sampling controllable capacitance 0.5C is connected to the common-mode voltage Vcm, and the bottom plates of the other capacitances are connected to the input signal. The virtual matching module (204) works, so that the system sampling value is 31 / 32 (Vip - Vin).

[0054] Positive offset sampling: In the sampling-mode selectable bootstrap circuit, the bootstrap voltage output module (202) with controllable on / off does not work. At the sampling phase, the bottom plate of the sampling controllable capacitance 0.5C is connected to (Vrefp - Vrefn), and the bottom plates of the other capacitances are connected to the input signal. The virtual matching module (204) works, and the system sampling value is 31 / 32 (Vip - Vin) + 1 / 32 (Vrefp - Vrefn).

[0055] In negative-offset sampling, when the controllable bootstrap voltage output module (202) in the sampling-mode selectable gate bootstrap circuit is not working, the bottom plate of the controllable capacitor 0.5C is connected to (Vrefn - Vrefp) during the sampling phase, the bottom plates of the remaining capacitors are connected to the input signal, the virtual matching module (204) is working, and the system sampling value is 31 / 32(Vip - Vin) - 1 / 32(Vrefp - Vrefn).

[0056] Four different sampling modes enable the system to generate four different margin curves, providing a circuit implementation for a more stringent split-architecture-based digital back-end calibration using Equation (1-4) as the calibration criterion.

[0057] After quantization by the first-stage ADC, the corresponding margin with 4-bit accuracy is generated, and the feedback capacitor C FB is 1 / 8 of the sampling capacitor. The principle of charge redistribution is used to achieve closed-loop amplification of the margin with an amplification factor of 8, thereby generating one-bit inter-stage redundancy to reduce the bit error rate of the ADC. The disconnection of switch S4 at the output end of the amplifier and the closing of amplifier selection switch S0 should be as synchronous as possible. After S0 is closed, the ringing operational amplifier circuit using level-shifting technology starts to operate according to the Figure 4 shown timing sequence. The output signal of the amplifier is sampled and quantized by the second-stage ADC, generating a 10-bit output code that includes one-bit intra-stage redundancy to reduce errors.

[0058] The working timing relationship of a single half-channel is as follows: during the phase described above the first-stage ADC performs sampling and quantization, the amplifier performs reset and bias voltage injection, and the second-stage ADC performs quantization; during which phase, the first-stage ADC performs sampling, phase, the first-stage ADC performs quantization; during the phase described above the first-stage ADC and the amplifier perform margin amplification, and the second-stage ADC performs sampling. Among them, during the phase, before the first-stage ADC starts formal sampling, the sampling mode selection will be performed first. The two half-channels A and B sample and work synchronously. Since the front and rear stages in each channel work in a pipelined manner, a high speed can be achieved.

[0059] Although the content and advantages of the present invention have been disclosed in detail above, it must be noted that the scope of the present invention is not limited to the specific embodiments such as the methods and steps described in the specification. Without departing from the spirit and scope of the present invention, any person of ordinary skill in the art can make many deformations and modifications according to the content disclosed in the present invention, and these should also be regarded as the protection scope of the present invention.

Claims

1. A split pipeline - successive approximation analog - to - digital converter with selectable sampling mode, characterized in that, Based on a split - type analog - to - digital converter architecture, its overall circuit consists of two symmetric half - channels. Each half - channel circuit includes: a first - stage successive - approximation analog - to - digital converter with selectable sampling mode, a ringing operational amplifier using level - shifting technology, a second - stage successive - approximation analog - to - digital converter, and related digital circuits for controlling the sampling mode selection; where: The related digital circuits for controlling the sampling mode selection generate a control code for controlling the sampling mode selection according to the externally input digital signal. The first - stage successive - approximation analog - to - digital converter with selectable sampling mode samples and quantizes the input signal on the bottom plate according to this mode control code, and generates a first - stage quantization digital code and the quantized analog residue. The ringing operational amplifier using level - shifting technology amplifies this analog residue signal, and the amplified signal is sampled and quantized by the second - stage successive - approximation analog - to - digital converter, and a second - stage quantization digital code is generated; where: The two - stage successive - approximation analog - to - digital converters work in a pipelined manner, and the digital code values of the first stage and the second stage are output after synchronization processing.

2. The split - type pipelined - successive - approximation analog - to - digital converter according to claim 1, wherein: The first - stage successive - approximation analog - to - digital converter with selectable sampling mode has a circuit including a gate - bootstrapping circuit with selectable sampling mode, a sampling capacitor array, a dynamic comparator circuit, and successive - approximation digital logic. Among them, the gate - bootstrapping circuit with selectable sampling mode is used to generate the gate voltage of the sampling NMOS switch corresponding to each sampling capacitor, and control the on - off of the sampling switch in different sampling modes. The signal is loaded on the sampling capacitor array after passing through the sampling NMOS switch, and the dynamic comparator circuit compares the sampled value with the reference voltage. The comparison result controls the operation of the successive - approximation digital logic, so that the reference voltage of the capacitor plate changes sequentially, and finally a first - stage digital code output and an analog residue are obtained; The ringing operational amplifier using level - shifting technology uses a pseudo - differential structure to amplify the differential signal, and includes two symmetric ringing operational amplifier circuits using level - shifting technology. Among them, each operational amplifier circuit works in a closed - loop circuit and realizes precise amplification by means of capacitor re - distribution; The related digital circuits for controlling the sampling mode selection include multiple digital combinational logics. After synchronizing the externally input sampling mode selection signal, a series of internal control codes are generated through logic to control the gate - bootstrapping circuit with selectable sampling mode and the sampling capacitor array, and four different sampling modes are generated; where: The first sampling mode is normal sampling, that is, the input signal VIN is fully loaded on the sampling capacitor array, so that the first - stage successive - approximation analog - to - digital converter with selectable sampling mode quantizes the input signal VIN; The second sampling mode is proportional sampling, that is, a signal kVIN proportional to the input signal is loaded on the sampling capacitor array, so that the first - stage successive - approximation analog - to - digital converter with selectable sampling mode quantizes the signal kVIN proportional to the input signal, where k is a non - zero proportionality coefficient; The third sampling mode is positive offset sampling, that is, after offsetting the signal kVIN proportional to the input signal in the positive direction, it is loaded on the capacitor array, so that the first-stage successive approximation analog-to-digital converter of the selectable sampling mode quantifies the signal kVIN+△ proportional to the input signal, where k is a non-zero proportionality coefficient; The fourth sampling mode is negative offset sampling, that is, after offsetting the signal kVIN proportional to the input signal in the negative direction, it is loaded on the capacitor array, so that the first-stage successive approximation analog-to-digital converter of the selectable sampling mode quantifies the signal kVIN-△ proportional to the input signal, where k is a non-zero proportionality coefficient.

3. The split pipeline - successive approximation analog - to - digital converter according to claim 2, wherein, The bootstrapped gate voltage circuit with selectable sampling modes includes a bootstrap voltage generation module, a main bootstrap voltage output module, a controllable on-off bootstrap voltage output module, and a virtual matching module; where: The bootstrap voltage generation module receives the input signal and bootstraps it under clock control to generate a bootstrap signal that is higher than the input signal by VDD; The main bootstrap voltage output module outputs the bootstrap voltage generated by the bootstrap voltage generation module, so that the gate terminal voltage of the sampling NMOS switch it controls is a bootstrap signal that is higher than the input signal by VDD; The controllable on-off bootstrap voltage output module controls the output of the bootstrap voltage according to the four sampling modes, so that the gate voltage of the sampling NMOS switch it controls is a bootstrap signal that is higher than the input signal by VDD or GND; The virtual matching module does not control any sampling NMOS switches. When the output of the controllable on-off bootstrap voltage output module is a bootstrap signal that is higher than the input signal by VDD, the virtual matching module does not work. When the output voltage of the controllable on-off bootstrap voltage output module is GND, the virtual matching module works to ensure that the output voltage of the main bootstrap voltage output module remains unchanged and improve the sampling linearity.

4. The split pipeline - successive approximation analog - to - digital converter according to claim 3, wherein, The bootstrap voltage generation module includes four PMOS transistors P1, P2, P3, P4, six NMOS transistors N1, N2, N3, N4, N5, N6, and a bootstrap capacitor C boost ; where: The source terminal of N1 is connected to the input signal, the gate terminal of N1 is the output of the bootstrap voltage, and is connected to the drain terminal of P1, the gate terminal of P2, the gate terminal of N2, and the drain terminal of N5. The drain terminal of N1 is connected to the source terminal of N2, the drain terminal of N3, the source terminal of N4, and the boost bottom plate of C boost The top plate is connected to the source terminal of P1 and the drain terminal of P2. The gate terminal of P1 is connected to the drain terminal of P3, the drain terminal of N2, and the drain terminal of N4. The source terminal of N5 is connected to the drain terminal of P4 and the drain terminal of N6. The gate terminal of N4 and the gate terminal of P3 are connected to the sampling phase control clock CK. The gate terminals of N3 and N6 and the gate terminal of P4 are connected to the control clock CKN; The source terminals of P2, P3, and P4 and the gate terminal of N5 are connected to VDD, and the source terminal of N3 is grounded.

5. The split pipeline - successive approximation analog - to - digital converter according to claim 4, wherein The controllable on-off bootstrap voltage output module includes 4 PMOS transistors P5, P6, P7, P8 and 4 NMOS transistors N7, N8, N9, N10; where: The source terminals of N7 and N8 are connected to the input signal. The drain terminals of N7 and N8 are connected to the drain terminal of P5, the gate terminals of P6 and P7. The output of the bootstrap voltage generation module is connected to the source terminal of P6. The drain terminal of P6 is connected to the source terminal of P7. The drain terminal of P7 is connected to the gate terminal of N8 and the drain terminal of N9, and outputs a controllable on-off bootstrap voltage signal. The source terminal of N9 is connected to the drain terminal of N10 and the drain terminal of P8. The gate terminals of P8 and N10 are connected to the control signal CON. The gate terminals of P5 and N7 are connected to the internal control code PN; The source terminals of P5 and P8 and the gate terminal of N9 are connected to VDD, and the source terminal of N10 is grounded; The PMOS transistors P6 and P7 have the same size and are on switches to control whether the module works. The control signal CON is generated by the control signal CKN and the internal control code PN.

6. The split pipeline - successive approximation analog - to - digital converter according to claim 5, wherein The main bootstrap voltage output module includes three PMOS transistors P9, P10, P11 and three NMOS transistors N11, N12, N13. Among them: The gate terminals of P9, P10, the source terminal and the drain terminal of N11 are connected to the input signal. The source terminal of P9 is connected to the output of the bootstrap voltage generation module. The drain terminal of P9 is connected to the source terminal of P10. The drain terminal of P10 is connected to the gate terminal of N11 and the drain terminal of N12, and outputs a bootstrap voltage signal. The source terminal of N12 is connected to the drain terminal of N13 and the drain terminal of P11. The gate terminals of P11 and N13 are connected to the control signal CONT. The source terminal of P11 and the gate terminal of N12 are connected to VDD. The source terminal of N13 is grounded. The PMOS transistors P9 and P10 have the same size and are constantly-conducting switching devices. The control signal CONT is generated by controlling the control signal CKN. The sizes of the PMOS transistors P9, P10, P11 and the NMOS transistors N11, N12, N13 are respectively proportional to the sizes of P6, P7, P8, N8, N9, N10 in the controllable on-off bootstrap voltage output module, with the same proportionality coefficient, which is equal to the ratio of the capacitance arrays driven by the two modules.

7. The split pipeline - successive approximation analog - to - digital converter according to claim 5, wherein, The virtual matching module includes four PMOS transistors P12, P13, P14, P15 and four NMOS transistors N14, N15, N16, N17. Among them, the device sizes and connection relationships are exactly the same as those of P5, P6, P7, P8 and N7, N8, N9, N10 in the controllable on-off bootstrap voltage output module: The source terminals of N14 and N15 are connected to the input signal. The drain terminals of N14 and N15, the drain terminal of P12, the gate terminals of P13 and P14 are connected. The output of the bootstrap voltage generation module is connected to the source terminal of P13. The drain terminal of P13 is connected to the source terminal of P14. The drain terminal of P14 is connected to the gate terminal of N15 and the drain terminal of N16, and outputs a controllable on-off bootstrap voltage signal. The source terminal of N16 is connected to the drain terminal of N17 and the drain terminal of P15. The gate terminals of P15 and N17 are connected to the control signal CONN. The gate terminals of P12 and N14 are connected to the internal control code PNN. The source terminals of P12 and P15 and the gate terminal of N16 are connected to VDD. The source terminal of N17 is grounded. Its control signals PNN and CONN are opposite to PN and CON. When the controllable on-off bootstrap voltage output module outputs a bootstrap signal that is VDD higher than the input signal, the virtual matching module does not work. When the output voltage of the controllable on-off bootstrap voltage output module is GND, the virtual matching module works, and the output voltage of the main bootstrap voltage output module remains unchanged, improving the sampling linearity.

8. The split pipeline - successive approximation analog - to - digital converter according to claim 3, wherein, The ringing operational amplifier circuit using the level shifting technique includes: a bias-enhanced ringing operational amplifier, a zero-adjusting capacitor C Z , a level shifting capacitor C S1 , C S2 , a reset and level shifting control circuit, and a common mode feedback circuit; wherein: The offset-enhanced ringing operational amplifier has a circuit composed of three cascaded inverters. The signal is input from the gates of the input transistors MP1 and MN1 of the first-stage inverter. Two equal-value resistors R1P and R1N are connected in series between the drain terminals of MP1 and MN1 to achieve self-bias enhancement of the second-stage inverter. The upper end of R1P, which is the drain terminal of MP1, is connected to the gate of the input transistor MN2 of the second-stage inverter, and the lower end of R1N, which is the drain terminal of MN1, is connected to the gate of the input transistor MP2 of the second-stage inverter. A resistor R2 is connected in series between the drain terminals of MP2 and MN2 to achieve self-bias of the third-stage inverter. The upper end of R2, which is the drain terminal of MP2, is connected to the gate of the input transistor MP3 of the third-stage inverter, and the lower end of R2, which is the drain terminal of MN2, is connected to the gate of the input transistor MN3 of the third-stage inverter. The amplified signal is output from the drain terminals of MP3 and MN3.

9. The split pipeline - successive approximation analog - to - digital converter according to claim 8, characterized in that, In the ringing operational amplifier circuit using the level shifting technique, the input signal is input from the top plate of the zero-adjusting capacitor C Z The top plates of the level shifting capacitors C S1 and C S2 are respectively connected to the gates of MP1 and MN1. The bottom plates of C S1 and C S2 are connected to the bottom plate of the zero-adjusting capacitor Cz and are connected to the lower end of R1P (i.e., the upper end of R1N) through the zero-adjusting switch S.

10. The split pipeline - successive approximation analog - to - digital converter according to claim 9, characterized in that, In the reset and level-shifting control circuit, there are two phases φ1 and φ2; among them: At phase φ1, the input and output terminals of the ringing operational amplifier circuit using the level shifting technique as described are reset to the common mode. First, the zero adjustment switch S is opened, and the zero adjustment capacitor C Z is connected across the common mode signal for capacitor reset. The bias voltages VBP and VBN are respectively applied to the top plates of the level shifting capacitors C S1 and C S2 . Subsequently, the zero adjustment switch S is closed, and the circuit offset error is extracted under bias conditions and stored in the zero adjustment capacitor C Z . At phase φ2, the zero-adjustment switch S, the reset voltage, and the bias voltage are disconnected, and the input signal passes through the zero-adjustment capacitor C Z and the level-shifting capacitor C S1 , C S2 . After canceling and shifting the DC level offset of the input signal, it is input to the gates of the input transistors MP1 and MN1 of the first-stage inverter.

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