Hall integrated sensor and corresponding manufacturing process

Abstract

An integrated Hall sensor is provided, the integrated Hall sensor comprising: a main wafer (10) of semiconductor material, the main wafer having a substrate (101), the substrate having a first surface (101a) and a second surface (101b), the second surface (101b) being opposite to the first surface (101a) along a vertical axis (y); Hall sensor terminals (1, 2, 3, 4; 1', 2', 3', 4'), the Hall sensor terminals being arranged at at least one of the first surface (101a) and the second surface (101b) of the substrate (101); and an isolation structure (109) in the substrate (101), the isolation structure defining a Hall sensor plate (103) of the integrated Hall sensor, the Hall sensor terminals being arranged in the isolation structure (109). Furthermore, the integrated Hall sensor has a test or calibration coil integrated in the wafer (10), the test or calibration coil having a plurality of windings formed at least in part by metal parts (130b, 170b; 130a, 170a) arranged above the first surface (101a) and the second surface (101b) of the substrate (101) and defining an inner volume (1001) completely surrounding the Hall sensor plate (103).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the priority of European patent application with application number 19185046.0 filed on July 8, 2019, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a Hall integrated sensor, in particular a Hall integrated sensor having at least an integrated coil for final testing and calibration, and to a corresponding manufacturing process. Background Art

[0004] Magnetic sensor ICs (integrated circuits) typically use silicon-based Hall sensor elements that are monolithically integrated with the circuits required for signal conditioning and amplification. Typical commercial products with monolithic integrated Hall sensors are Hall switch ICs, Hall ICs for linear position measurement, angular position sensor Hall ICs, Hall ICs for current sensing, and 3D Hall sensor ICs. Depending on the product type, the Hall integrated sensor may include horizontal Hall elements, vertical Hall elements, or both. Horizontal Hall elements sense the magnetic field strength perpendicular to the silicon surface. They are used in many applications where it is sufficient to determine the magnetic field strength in only one spatial dimension. For example, unipolar and bipolar Hall switch ICs and Hall sensor ICs for linear position measurement along one axis. Vertical Hall elements that sense magnetic field strength in the direction of the plane of the silicon surface are used in angular position sensor Hall ICs, and in 3D Hall sensor ICs together with horizontal Hall elements.

[0005] The Hall sensor can be manufactured using standard CMOS manufacturing processes so that the Hall sensor and the electronics for operation and readout can be integrated on the same chip. Alternatively, a dedicated Hall sensor wafer can be stacked on a second wafer containing the required circuitry. In WO2020 / 104998 A1, applied for in the name of the applicant, a method of stacking two wafers to form such a Hall sensor IC product is disclosed.

[0006] The magnetic sensitivity of a Hall sensor depends on stress, temperature, aging, and thermal shock. Manufacturing defects such as photoalignment errors, uneven dopant density, or defects can cause Hall voltage shifts. Even more seriously, the plastic package used for the Hall sensor IC causes stress in the silicon, which also causes Hall voltage shifts. Therefore, Hall sensor ICs need to undergo a lot of testing. For many products, such as linear Hall ICs, each Hall sensor is calibrated and the calibration data obtained is stored in the IC. In order to characterize the magnetic response of the Hall sensor, the packaged chip is placed in an external Helmholtz coil. Of course, 3D Hall sensor ICs need to be characterized in all three spatial dimensions. As understood above, the final testing and calibration work for the Hall sensor IC is very important, and the associated costs account for a large part of the total manufacturing cost.

[0007] It has been proposed to equip Hall sensor ICs with integrated coil testing and calibration, see for example:

[0008] -PLCSimon,PHSde Vries,S.Middelhoek,Autocalibration of siliconHall devices,Transducers 95,291-A12,pp.237-240,1995

[0009] -RS Popovic, TJAFlanagan, PABesse, The future of magnetic sensors, Sensors and Actuators A56, pp.39-55, 1996.

[0010] The integrated coils used for final testing and calibration of horizontal and / or vertical Hall sensors are required to induce a sufficiently large magnetic field, at least in the range of several mT. Coil efficiency is defined as the ratio of the induced magnetic field strength divided by the coil current. The maximum coil current applied to the integrated coil during the final test or calibration procedure may be limited by the electromigration performance of the CMOS metal layer used for the coil. More importantly, self-heating of the Hall sensor element during testing must be considered. For these reasons, it is critical to achieve high coil efficiency for the integrated coil.

[0011] Furthermore, the magnetic field induced by the integrated coil should be uniform across the area of ​​the Hall sensor element being tested. While this can be achieved to some extent for horizontal Hall sensors (by using standard metal layers to form the coil), there is no known way to form the induction coil for a vertical Hall sensor such that a uniform and homogeneous magnetic field is induced in the Hall plate of the vertical Hall sensor. Summary of the invention

[0012] It is therefore an object of the present invention to provide an improved Hall integrated sensor, in particular a Hall integrated sensor having at least an integrated coil for final testing and calibration.

[0013] According to the present invention, a Hall integrated sensor according to the embodiments of the present application is provided.

[0014] According to an embodiment of the present application, an integrated Hall sensor may include: a main wafer of semiconductor material, the main wafer having a substrate, the substrate having a first surface and a second surface, the second surface being opposite to the first surface along a vertical axis; Hall sensor terminals, the Hall sensor terminals being arranged at least at one of the first surface and the second surface of the substrate; an isolation structure in the substrate, the isolation structure defining a Hall sensor board of the integrated Hall sensor, the Hall sensor terminals being arranged inside the isolation structure, the integrated Hall sensor also including at least one test or calibration coil integrated in the main wafer, the at least one test or calibration coil having a plurality of windings at least partially formed by metal parts arranged above the first surface and the second surface of the substrate. group and defines an inner volume that completely surrounds the Hall sensor plate; and wherein the test or calibration coil includes: at least a first metal portion defined in a metal layer, the metal layer is formed on a first dielectric layer structure arranged on the first surface of the substrate; at least a second metal portion defined in a corresponding metal layer, the corresponding metal layer is formed on a second dielectric layer structure arranged on the second surface of the substrate; and at least through-silicon vias, the through-silicon vias extending from the second surface of the substrate to the first surface of the substrate; and wherein a first outer dielectric layer is arranged on the first dielectric layer structure, the main wafer is attached to the second wafer together with the top surface of the outer dielectric layer, and the second wafer is configured to thin the main wafer from the second surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] For a better understanding of the present invention, preferred embodiments of the present invention will now be described by way of non-limiting example only and with reference to the accompanying drawings, in which:

[0016] - Figure 1A is a plan view of a Hall integrated sensor according to an embodiment of the present solution;

[0017] - Figure 1B yes Figure 1A The cross section of the Hall integrated sensor;

[0018] - Figure 1C and Figure 2 is another plan view of a Hall-integrated sensor according to an embodiment of the present solution;

[0019] - Figure 3A is a cross section of a Hall integrated sensor according to another embodiment of the present solution;

[0020] - Figure 3B and Figure 3C yes Figure 3A A plan view of the Hall integrated sensor;

[0021] - Figure 4A is a plan view of a Hall integrated sensor according to another embodiment of the present solution;

[0022] - Figure 4B yes Figure 4A The cross section of the Hall integrated sensor;

[0023] - Figure 5A is a plan view of a Hall integrated sensor according to another embodiment of the present solution;

[0024] - Figure 5B yes Figure 5A The cross section of the Hall integrated sensor;

[0025] - Figure 6 is a cross section of a Hall integrated sensor according to yet another embodiment of the present solution;

[0026] - Figure 7 is a plan view of a Hall integrated sensor according to another embodiment of the present solution;

[0027] - Fig. 8A is a plan view of a Hall integrated sensor according to another embodiment of the present solution;

[0028] - Figure 8B yes Fig. 8A The cross section of the Hall integrated sensor;

[0029] - Fig. 9A is a plan view of a Hall integrated sensor according to another embodiment of the present solution;

[0030] - Fig. 9B yes Fig. 9A The cross section of the Hall integrated sensor;

[0031] - Fig. 10Ais a plan view of a Hall integrated sensor according to another embodiment of the present solution;

[0032] - Fig. 10B yes Fig. 10A The cross section of the Hall integrated sensor;

[0033] - FIG. 11A to FIG. 14 is a plan view of a Hall integrated sensor according to other embodiments of the present solution;

[0034] - Fig.15A is a cross section of a Hall integrated sensor according to yet another embodiment of the present solution;

[0035] - FIG. 15B to FIG. 15D yes Fig.15A A plan view of the Hall integrated sensor;

[0036] - Figures 16 to 18 is a plan view of a Hall integrated sensor according to another embodiment of the present solution;

[0037] - Figure 19 to Figure 20 is a cross section of a Hall-integrated sensor according to another embodiment of the present solution; and

[0038] - FIG. 21A to FIG. 21M is a cross section of an integrated Hall sensor in consecutive steps of the corresponding manufacturing process. DETAILED DESCRIPTION

[0039] As will be discussed in detail below, the present solution envisions the use of fully CMOS-compatible process steps and materials to fabricate the integrated Hall sensor.

[0040] Figure 1A , Figure 1B and Figure 1C A first embodiment of the present solution is shown.The Hall sensor product 100 comprises a vertical Hall sensor equipped with a coil for calibration and testing. Figure 1A A projection diagram of the Hall sensor product 100 in the xz plane is given. A section parallel to the x direction from 1B to 1B' is indicated and represented by 1B-1B'. Figure 1B A cross section of the Hall sensor product 100 along the cut line 1B-1B' is shown. Figure 1B Two cuts are indicated in FIG. A first cut from 1A to 1A' is denoted by 1A-1A', and a second cut from 1C to 1C' is denoted by 1C-1C'. Each of the two cuts corresponds to a plane parallel to the xz plane offset from the origin in the y direction. Figure 1A The Hall sensor product 100 is shown in a cut plane 1A- 1A′. Figure 1C1 is another projection diagram of the Hall sensor product 100, this time shown in the plane of the cut 1C-1C'. The Hall sensor product 100 includes a vertical Hall element and an on-chip coil dedicated to the testing and calibration of the vertical Hall element. Figure 1B The vertical Hall element is formed on a wafer 10 having a semiconductor substrate 101. The semiconductor substrate 101 is preferably a silicon substrate, but other semiconductor materials may also be considered. The semiconductor substrate 101 has a first conductivity type, which is preferably an n-type. Figure 2 , the semiconductor substrate has a first surface represented by 101a. Two highly doped regions 1 and 2 with a first conductivity type are formed at the first surface 101a. The two highly doped regions 1 and 2 extend from the surface 101a into the semiconductor substrate 101. The highly doped regions 1 and 2 can be formed by common CMOS manufacturing techniques (such as photomask ion implantation and subsequent rapid thermal annealing). A dielectric layer 104 is disposed on the first surface 101a. The dielectric layer 104 constitutes a pre-metal dielectric layer and can contain silicon nitride, silicon oxide, phosphosilicate glass, borophosphosilicate glass or other suitable dielectric materials. The dielectric layer 104 can also include a stack of dielectric layers having a material composition as given above. In a portion of the surface 101a occupied by the highly doped region 1, the dielectric layer 104 has an opening extending downward to the substrate surface 101a. In the same manner, a second opening is provided in the dielectric layer 104, which is located in a portion of the semiconductor surface 101a occupied by the highly doped region 2. The second opening also extends to the substrate surface 101a. The first metal layer 110 is disposed on the dielectric layer 104. The first metal layer 110 may be an aluminum-based metal layer commonly used in many CMOS manufacturing processes. Figure 2 As shown, the aluminum-based metal layer fills the two openings in the dielectric layer 104. Alternatively, the two openings can also be filled with a tungsten-based layer, and the metal layer 110 is aluminum-based, or alternatively copper-based. The metal layer 110 can adopt different metallization schemes known in the art. Figure 1BAs shown, the metal layer 110 is configured to leave portions 110b, 112, 111 and 111b. The metal portions 111 and 112 are in contact with the high doping regions 1 and 2, respectively. The high doping regions 1 and 2 define two terminals of the vertical Hall sensor, both of which are formed at the first surface 101a of the substrate 101. The metal portions 111 and 112 provide electrical contact and wiring to access the Hall terminals 1 and 2, respectively. The metal wiring for each of the two Hall terminals disposed on the dielectric layer 104 is oriented in the x direction within the region of the vertical Hall sensor and also near the vertical Hall sensor. The metal portions 110b and 111b are portions of the metal coil surrounding the vertical Hall sensor, which will become clearer below. The metal layer 110 is embedded in the second dielectric layer 105 forming the first intermetallic dielectric. Suitable materials for the dielectric layer 105 are silicon oxide or high-k dielectric materials. A through hole 121b is formed in the dielectric layer 105. The second metal layer 130 is disposed on the dielectric layer 105 and is configured to leave a metal portion 130b. The second metal layer may adopt a common metallization scheme. The via 121b may be filled with a tungsten-based layer, and the metal layer 130 may be aluminum-based or copper-based. The via 121b may also be filled with an aluminum-based metal layer 130 disposed on the intermetallic dielectric 105. Common manufacturing processes may be applied to form Figure 1BThe metal structure shown. The second metal layer is embedded in the dielectric layer 106, which may include silicon oxide or a stack with a high-k dielectric and silicon oxide. The through hole 121b contacts the metal portion 111b. The metal portion 110b, the metal portion 111b, the through hole 121b and the metal portion 130b constitute a part of a coil surrounding the vertical Hall element at the first surface of the substrate 101. The wafer 10 is attached to the second wafer 20 through the top surface of the dielectric layer 106. The second wafer 20 may be a carrier wafer, for example, the second wafer 20 may be a cheap silicon wafer. Alternatively, the second wafer 20 may be a CMOS wafer containing an integrated circuit required to operate the vertical Hall element. In this case, the wafer 20 includes a silicon substrate and a metallized stack, wherein the CMOS device is formed in the silicon substrate. The metallized stack on the wafer 20 may include a plurality of metal layers embedded in the dielectric layer. In this case, the wafer 10 is attached to the top surface of the dielectric layer provided on the silicon wafer 20 via the top surface of the dielectric layer 106. In addition, electrical contact is provided between the metal layer formed on the wafer 20 and on the first surface of the wafer 10. Such electrical contact can be achieved by hybrid bonding or other methods known in the art. Using the wafer 20 as a carrier, the wafer 10 is thinned from the back side, i.e. from the side opposite to the first surface 101a. Most of the wafer material is removed so that only a thin layer of the semiconductor substrate 101 remains. The resulting second substrate surface opposite to the first surface 101a is Figure 1B 101a. The second surface 101b of the substrate layer 101 is parallel to the first surface 101a. The thickness of the remaining semiconductor substrate 101 can preferably be in the range of 10 microns to 50 microns, but lower or higher thickness values ​​can also be envisioned. Two highly doped regions 3 and 4 are arranged at the second surface 101b extending into the substrate 101. The highly doped regions 3 and 4 have a first conductivity type that is the conductivity type of the substrate layer 101. For the vertical Hall element in the product 100, the highly doped region 3 can be formed opposite to the highly doped region 2 at the first surface 101a, and the highly doped region 4 can be formed opposite to the highly doped region 1 at the first surface 101a. Figure 1A The Hall sensor product 100 is shown in the xz plane of the second surface 100b along the cut line 1A-1A'. Figure 1AAs can be seen in the figure, the highly doped regions 3 and 4 form strips along the z-direction. For the vertical Hall element of the product 100, the highly doped regions 1 and 2 on the first surface 100a also form strips oriented in the z-direction. The highly doped regions 1, 2, 3 and 4 may all have the same lateral dimensions. The highly doped regions 3 and 4 at the second surface 100b may be formed by photomask ion implantation and subsequent laser thermal annealing. Laser thermal annealing allows activation of the doping at the second surface without causing any damage to the metallization on the first surface. The highly doped regions 3 and 4 and the highly doped regions 1 and 2 are surrounded by a dielectric structure 109. The dielectric structure 109 extends from the second surface 101b of the substrate layer 101 to the first surface 101a. In Figure 1A In FIG. 1 , it is depicted that the highly doped regions 3 and 4 are laterally surrounded by the dielectric structure 109. The portion of the substrate layer 101 that is laterally surrounded by the dielectric structure 109 is Figure 1A and 1B 103 in the figure. The portion 103 of the substrate layer 101 is the Hall sensor region (Hall plate) of the vertical Hall element of the product 100. The dielectric structure 109 can be established by a deep trench isolation process. The dielectric material of the dielectric structure 109 can be silicon oxide. The deep trench isolation process is known in the art. Again referring to Figure 1B , the first dielectric layer 107 is disposed on the second surface 101b. The dielectric layer 107 provides a pre-metal dielectric layer on the second side of the substrate layer 101. Similar materials or material compositions as used for the pre-metal dielectric layer 104 on the first side can be considered for the dielectric layer 107. A first through silicon via 140b is formed to extend from the top surface of the dielectric layer 107 through the layer 107, through the substrate layer 101 and through the dielectric layer 104 on the first surface 101a to reach a metal portion 110b of the first metal layer disposed on the layer 104. The through silicon via 140b is filled with a metal layer, which can be a tungsten-based metal layer, or more preferably a copper-based metal layer. The metal filling of the through silicon via is electrically isolated from the semiconductor substrate 101 by a dielectric liner 181. The dielectric liner can include silicon oxide or other suitable insulating materials. A second through-silicon via 141b is formed extending from the top surface of the dielectric layer 107 through the substrate to the metal portion 111b of the metal layer 110. The formation of through-silicon vias is known to those skilled in the art. Similar to the first side, two contact openings are formed in the dielectric layer 107, which extend to the surface 101b and provide access to the highly doped regions 3 and 4, respectively. Figure 1BAs described above, the first metal layer 150 is disposed on the pre-metal dielectric layer 107 on the second substrate surface 101b. The two trenches are filled with the metal layer 150. Similar processes and materials as the metal layer 110 on the first surface may be applied. Figure 1B Four metal portions 150b, 153, 154 and 151b are shown in FIG. Metal portion 150b contacts the metal filling of through-type silicon via 140b. Metal portion 151b contacts the metal filling of through-type silicon via 141b. Metal portion 153 contacts the high doping region 3, which defines one of the two Hall terminals disposed on the second surface 101b. Metal portion 154 contacts the high doping region 4, which defines the other of the two Hall terminals disposed on the second surface 101b. Metal portions 153 and 154 also include wiring for two Hall terminals 3 and 4. The wiring is oriented in the z direction. Metal layer 150 is embedded in the first intermetallic dielectric layer 108. Processes and materials similar to the first intermetallic dielectric 105 on the first side of substrate 101 can be applied. A through hole 160b formed through the intermetallic dielectric 108 provides contact with metal portion 150b. The second via 161b passing through the dielectric layer 108 provides contact with the metal portion 151b. The second metal layer 170 is disposed on the intermetallic dielectric 108 and is configured to electrically connect the via 160b with the via 161b. The electrical connection is established by the metal portion 170b. Figure 1C , metal portion 107b and vias 160b and 161b are depicted in the xz plane along section 1C-1C'. The process and materials for filling the via with metal and forming metal portion 170b can be similar to the process and materials used for the second metal layer on the first side of the substrate. Finally, dielectric layer 182 is disposed on second metal layer 170 and on intermetallic dielectric layer 108. Dielectric layer 182 serves as a final passivation layer and can include a silicon nitride or silicon oxynitride layer.

[0041] The vertical Hall element has four terminals, which are arranged on two opposite surfaces of the semiconductor substrate layer 101 in a manner to obtain four-fold symmetry. In operation, the driving current can be forced to go from terminal 1 to terminal 3. The current flows through the semiconductor layer 101 in the diagonal direction, where the current flow is limited by the dielectric structure 109. The Hall voltage can be captured between terminals 2 and 4. The measured Hall voltage represents the component of the magnetic field in the z direction. Similarly, the driving current can be forced to go from terminal 2 to terminal 4, and the Hall voltage can be captured between Hall terminals 3 and 1. Similarly, the measured Hall voltage represents the component of the magnetic field in the z direction. In addition, the driving current can be reversed so that a total of four different operating phases can be established, thereby determining all the same components of the magnetic field in the z direction. The operation of the vertical Hall sensor requires a complex circuit system for adjusting and amplifying the voltage signal. The required integrated circuit can be formed on the first surface 101a of the semiconductor wafer 10 or can be arranged on the second semiconductor wafer 20. In any case, additional through-silicon vias may be required to access the Hall terminals 3 and 4 arranged on the second surface 101b from the first side. These vertical connections and the required integrated circuits are not included in the Figure 1A and Figure 1B Shown in.

[0042] like Figure 1B As shown, a rectangular coil is formed in the wafer 10 around the vertical Hall element. The coil includes a metal wire and pad 110b, a through-silicon via 140b, a metal pad 150b, a through hole 160b, a metal wire 170b, a through hole 161b, a metal pad 151b, a through-silicon via 141b, a metal pad 111b, a through hole 121b and a metal wire 130b. The rectangular coil is in the xy plane. If a current is fed into the coil to flow counterclockwise through the coil, a magnetic field directed in the z direction is induced - inside the coil. The strength of the induced magnetic field depends on the feed current and the geometry of the induction coil. The magnetic field induced by the coil can be measured by a vertical Hall element, which is sensitive to the magnetic field component in the z direction.

[0043] from Figure 1BIt can be clearly seen that the coil can be arranged in the xy plane so that an almost uniform magnetic field is induced within the Hall plate 103 of the vertical Hall element. The thickness of the dielectric layers 107 and 108 on the second surface can be selected to have the same thickness value as the dielectric layers 104 and 105, respectively. In this way, the vertical distance of the metal portion 170b to the Hall plate 103 is the same as the vertical distance of the metal portion 130b to the Hall plate 103. In addition, the through-silicon vias 140b and 141b can be placed so that their lateral distances to the Hall plate 103 are equal. In addition, the distance of the through-silicon vias 140b and 141b to the Hall plate can be such that the distance is equal to the combined layer thickness of 104 and 105.

[0044] like Figure 1A As shown, the vertical Hall element of product 100 can be equipped with - as an example - seven induction coils arranged in a row in the z direction. Each coil is in a plane parallel to the xy plane, such as Figure 1B As shown. Figure 1A In FIG. 1 , it is given a representation of a vertical Hall element with a coil in the xz plane along the cut 1A-1A′, showing the through-silicon vias belonging to the coil. Figure 1B As described above, the through-type silicon vias 140b and 141b belong to a coil ( Figure 1B ). Through-silicon vias 140a and 141a belong to another coil, through-silicon vias 140c and 141c belong to yet another coil, and the same is true for through-silicon vias 140d and 141d, through-silicon vias 140e and 141e, through-silicon vias 140f and 140f, and through-silicon vias 140g and 141g. The seven coils can be connected in series so that the direction of current in the xy plane is the same for all seven individual coils (i.e., counterclockwise or clockwise). In this way, the seven individual coils form a winding of a combined coil. In addition, the magnetic fields induced by the individual coils or windings have the same direction. Each individual coil or winding is arranged parallel to the xy plane, and a series connection of the individual coils is established at a certain distance from the vertical Hall element. The technician will understand how to provide a series connection between the individual coils. The series connection can be formed by the first metal layer 110 and the second metal layer 130 and the corresponding through holes. As Figure 1A As shown, the seven windings are equidistant. The windings may be arranged so that a nearly uniform magnetic field is induced in the z-direction over the area occupied by the Hall plate 103 .

[0045] In the Hall sensor product 100, the Hall plate 103 of the vertical Hall element is located inside the multi-winding coil. The interior (internal volume) of the coil is understood as the volume of the space surrounded by the coil windings. Figure 1B, the interior of the coil as seen in this cutaway parallel to the xy plane is indicated and represented by 1001. As shown, the Hall plate 103 is completely placed within the inner volume 1001 of the coil. Figure 1A The same is true for the section parallel to the xz plane given in . The Hall plate 103 is placed completely within the inner volume (again indicated as 1001) of the (multi-winding) coil.

[0046] Figure 2 Another Hall sensor product, generally designated 200, is shown having a vertical Hall element equipped with a coil for testing and calibration. Figure 2 A two-dimensional cross-section of the Hall sensor product along the second surface 101b of the substrate 101 parallel to the xz plane is provided (similar to the cross-section of the Hall sensor product 100). Figure 1B ). Highly doped regions 3 and 4 defining the two terminals of the vertical Hall sensor are indicated. The Hall sensor region 103 is laterally limited by a dielectric structure 109. Compared to the vertical Hall sensor of product 100, the vertical Hall sensor of product 200 has a smaller width in the z direction. Figure 2 Two pairs of through-silicon vias are shown in FIG. The first pair, including through-silicon vias 140a and 141a, belongs to the first winding. The second pair, including through-silicon vias 140b and 141b, belongs to the second winding of the coil. The first winding and the second winding are both in the xy plane. As in the Hall sensor product 100, the windings are connected so that the current fed into the coil flows through each winding in the same direction (i.e., clockwise or counterclockwise in the xy plane).

[0047] exist Figure 2 In FIG. 1 , the spacing between the through-silicon vias 140a and 141a is represented by a. The length a is the inner length of the rectangular induction coil in the x direction. The spacing between the two rectangular windings in the z direction is Figure 2 In the diagram, d is used to represent the distance d. If the spacing d is selected to be close to a / 2, a Helmholtz configuration is approximately obtained. As known to those skilled in the art, for a secondary winding of length a, if the distance d between the two windings is selected to be 0.544*a, the Helmholtz characteristic is almost obtained. As is also known, if a current is fed through the Helmholtz coil, a uniform and constant magnetic field will be induced inside any Helmholtz coil. Figure 2 As shown, the Hall plate 103 of the vertical Hall element of the product 200 is completely located inside 1001 of the two coils.

[0048] Figure 3A , Figure 3B and Figure 3CAnother Hall sensor product 300 is shown in FIG. The Hall sensor product 300 includes a horizontal Hall sensor equipped with a coil for calibration and testing. Figure 3A A cross-sectional view of the Hall sensor product 300 parallel to the xy plane is provided.

[0049] Figure 3B and Figure 3C 3 are projection diagrams of the Hall sensor product 300 at two different positions along the y direction. Figure 3B The product 300 is shown in the xz plane at the second surface 101b of the substrate. This section is indicated by 3C-3C' and is Figure 3A Instructed. Figure 3C A second section parallel to the xz plane is shown and is indicated by 3B-3B'. Figure 3B and Figure 3C In the figure, the section line from 3A to 3A' is indicated. Figure 3A The section 3A-3A' is shown in FIG. Figure 3C , four highly doped regions 1, 2, 3 and 4 are formed at the second surface 101b of the substrate 101. Similarly, four highly doped regions 1', 2', 3' and 4' are formed at the first surface 101a of the substrate 101. Figure 3A It can be seen that the high doping regions 1 and 1' formed at two opposite surfaces of the substrate 101 have the same position in the xy plane. It can also be seen that the high doping regions 2 and 2' have the same position in the xz plane. The high doping regions 3 and 3' also have the same position in the xz plane and the same is true for the high doping regions 4 and 4'. Figure 3A , electrical contacts and wiring portions 151, 111', 152 and 112' are established to access the highly doped regions 1, 1', 2 and 2' respectively. Similar electrical contacts and wiring portions are also provided for the highly doped regions 3, 3', 4 and 4'. The dielectric structure 109 is arranged to extend from the second surface 101b to the first surface 101a of the substrate. Figure 3C As shown, the dielectric structure surrounds a portion 103 of the substrate 101, which defines the Hall plate of the horizontal Hall element. All highly doped regions are formed in the Hall plate 103. The highly doped regions 1 and 1' are electrically connected by means of wiring portions 151 and 111' and by means of through-silicon vias, which are Figure 3A , Figure 3B and Figure 3C By looking at Figure 1B, a person skilled in the art will easily understand how to establish a vertical electrical connection between the highly doped regions 1 and 1'. In the same manner, the highly doped regions 2 and 2' are also electrically connected. At the same time, the highly doped regions 3 and 3' are also electrically connected; the highly doped regions 4 and 4' are also electrically connected in this manner. The four required through-silicon vias are located on the outside of the Hall plate 103 limited by the dielectric structure 109. The pair (1, 1') constitutes the first Hall terminal of the horizontal Hall element. The pair (2, 2') constitutes the second Hall terminal of the horizontal Hall element. The pair (3, 3') constitutes the third Hall terminal of the horizontal Hall element, and the pair (4, 4') constitutes the fourth Hall terminal of the horizontal Hall element. Also refer to Figure 3C , the Hall plate 103 of the horizontal Hall element has a square shape. The highly doped regions 1, 2, 3 and 4 are located at the four corners of the square-shaped Hall plate 103. Different layouts of the horizontal Hall element can be considered. In particular, the Hall plate can have the shape of a Greek cross, where the four terminals are placed at the four ends of the cross.

[0050] In operation, a drive current can be fed from Hall terminal (1, 1') to Hall terminal (3, 3'). In the xz plane, the drive current flows diagonally through the square-shaped Hall plate 103. The Hall voltage is then captured between Hall terminals (2, 2') and (4, 4'). The Hall voltage represents the magnetic field in the y direction. In another operating mode, a drive current can be fed from Hall terminal (2, 2') to Hall terminal (4, 4'), and a Hall voltage can be detected between terminals (1, 1') and (3, 3'). Similarly, the measured Hall voltage represents a magnetic field oriented in the y direction. The reversed current direction in the above operating mode gives two other operating modes.

[0051] Back to Figure 3A , at least two metal layers are applied on a first side of the substrate 101 facing the carrier wafer 20. The first metal layer 110 is used to provide an electrical connection to the Hall terminals formed at the first surface 101a as described above. In addition, at least two metal layers are applied on the second side 101b of the substrate 101. The first metal layer 150 is used to provide an electrical connection to the Hall terminals formed at the second surface 101b. Two coils are formed around the area occupied by the Hall plate 103. The first coil 130a is formed by the second metal layer 130 on the first side of the wafer 10. The second coil 170a is formed by the second metal layer 170 on the second side of the wafer 10. Figure 3B , coil 170a is shown in the xz plane (section 3B-3B'). The coil may have Figure 3B A square shape is shown, however, other shapes are possible, such as a hexagonal shape or a circular shape. Figure 3BThe coil 170a in has only one winding, however, the coil may have more than one winding. Preferably, the first coil 130a and the second coil 170a are formed in the same manner. In detail, the first induction coil 130a and the second coil 170a may preferably be formed so that they face each other, have the same number of windings, the same line width, the same inner diameter and the same outer diameter. In addition, preferably, the second metal layers 130 and 170 are formed using the same process and material on both sides of the substrate layer 101, so that the series resistance of the two induction coils is approximately the same. In addition, preferably, the combined thickness of the dielectric layers 104 and 105 is the same as the combined thickness of the dielectric layers 107 and 108. With the help of a through-silicon via (not shown), the two coils are connected in series, thereby forming two windings of one coil. The connection is established in this way so that the current direction of the two windings in the xz plane is the same. If the current passes through the coil in a counterclockwise direction, a magnetic field oriented in the y direction is induced. In this way, the coil creates a magnetic field, which is measured by a horizontal Hall element. The Hall plate 103 of the horizontal Hall element is again inside the coil including windings 130a and 170a. For reference, the inner volume of the coil is Figure 3A and Figure 3B Indicated by 1001.

[0052] like Figure 4A and Figure 4B As shown, the Hall sensor product 400 includes a vertical Hall element equipped with an on-chip coil for testing and calibration. Figure 4A It is a projection diagram of the Hall sensor product, and Figure 4B is a cross-sectional view. The cutting position for the projection view is this time along the first surface 101a of the substrate 101 (cut 4A-4A'). The cutting position for the cross-sectional view is Figure 4A Indicated in. The Hall sensor product 400 is preferably formed on a substrate having a second conductivity type (p-type). A well 701 extending from the first surface 101a into the substrate is formed. The well 701 has a conductivity type opposite to that of the substrate, that is, the well has a first conductivity type (n-type). A plurality of highly doped regions 1, 2, 3, 4 and 5 having the first conductivity type are formed at the first surface 101a extending into the substrate. The highly doped regions 1, 2, 3, 4 and 5 are completely disposed within the region of the well 701. Electrical contacts and wiring portions (111, 112, 113, 114, 115) are formed using the first metal layer 110. The well 701 constitutes a Hall plate (previously indicated by 103) of a vertical Hall element, and the highly doped regions 1, 2, 3, 4 and 5 define the Hall terminals of the vertical Hall element. As shown Figure 4AAs shown, Hall terminals 1, 2, 3, 4 and 5 are formed in a row along the x-axis. Such vertical Hall elements are known in the art. There is no need to discuss their operation here. As is known, such vertical Hall elements can have different numbers of Hall elements, such as 3, 4 or more than 5. In any case, Figure 4B The vertical Hall element depicted in FIG. 1 is sensitive to magnetic fields in the z direction. The coil for testing and calibration of the vertical Hall element is built in the same manner as for the Hall sensor product 100. Likewise, the Hall plate of the Hall element (here the well 701) is completely within the inner volume 1001 of the coil.

[0053] Another Hall sensor product represented by 500 is Figure 5A and Figure 5B As shown. The Hall sensor product 500 includes a horizontal Hall element equipped with an on-chip coil for testing and calibration. The Hall sensor product 500 is formed on a substrate 101 having a second conductivity type (p-type). A well 701 having a first conductivity type is formed in the substrate extending from a first surface 101a. Four highly doped regions 1, 2, 3, and 4 having a first conductivity type are formed at the first surface 101a extending into the well 701. In the xz plane, the well 701 may have a Figure 5A In addition, the four highly doped regions 1, 2, 3 and 4 defining the Hall terminals may be located at the four corners of the square-shaped well 701. Other layouts are known in the art, for example, the well 701 may have the shape of a Greek cross and the four Hall terminals may be located at the four corners of the cross. Figure 5A and Figure 5B The horizontal Hall element depicted in is sensitive to magnetic fields oriented in the z direction. The coil dedicated to the testing and calibration of the horizontal Hall element of the Hall sensor product 500 is formed in the same manner as in the Hall sensor product 300. The Hall plate of the horizontal Hall sensor is completely placed within the inner volume 1001 of the coil.

[0054] Figure 6 A Hall sensor product 600 is shown including a vertical Hall element, which may be the same as the vertical Hall element of the Hall sensor product 100 . Figure 6 A cross-sectional representation of a Hall sensor product is given. A vertical Hall element having a Hall plate 103 and Hall terminals 1, 2, 3, and 4 is surrounded by two coils, an inner coil and an outer coil. The inner coil is formed by a metal portion 110b, a through-silicon via 140b, a metal portion 150, a via 160b, a metal line 170a, a via 161b, a metal portion 151b, a through-silicon via 141b, a metal portion 111b, a via 121b, and a metal line 130b. The inner coil is similar to the reference Hall sensor product 100. Figure 1B The same coil as depicted in FIG. Figure 6 As shown, the outer coil is formed by metal structures 114b, 142b, 155b, 162b, 171b, 192b, 270b, 193b, 172b, 163b, 156b, 143b, 115b, 123b, 123b and 123b. To form the outer coil, an additional metal layer 230 is added on the first side of the substrate facing the carrier wafer 20. The metal layer 230 is arranged on the top surface of the dielectric layer 106 and is itself embedded in the dielectric layer 206. Vertical connections to the metal layer 130 are provided, such as vias 223b. Along the same line, an additional metal layer 270 is added on the second side of the substrate 101. The metal layer 270 is arranged on the dielectric layer 182 and provides vias such as 192b and 193b. The metal layer 270 is embedded in the final passivation layer 193. The inner coil and the outer coil are connected in series in such a way that if current is fed to them, the current flows in the same direction (clockwise or counterclockwise in the xy plane) in the inner coil and the outer coil. Figure 6 The required electrical connections between the inner and outer coils are not shown in FIG. As a result, a coil having one inner winding and one outer winding is created. Similar to the Hall sensor product 100, multiple such coils can be arranged in the z direction, each coil comprising an inner winding and an outer winding both in the xy plane. If multiple coils are connected in series, a multi-winding coil having an inner winding loop and an outer winding loop is established. The Hall plate 103 of the vertical Hall element is located inside the resulting coil, inside Figure 6 Again represented by 1001.

[0055] Figure 7 700 is a projection diagram of the Hall sensor product 700. The Hall sensor product 700 is different from the Hall sensor product 300 in that the coil winding 130a (not shown here) disposed on the dielectric layer 105 is established as a spiral coil having multiple windings, and the coil winding 170a disposed on the dielectric layer 108 is established as a spiral coil having multiple windings. Figure 7 . The spiral coil 170a is depicted in . The spiral coil 130a can have the same or similar layout and number of windings. Similar to the Hall sensor product 300, the two coils 130a and 170a are connected in series so that the current direction in the xz plane is the same for both spirals. The series connection requires through-silicon vias and possible underpasses for the internal ports or ends of the spiral coils 130a and 170a. The underpasses can be formed by the first metal layers 110 and 150, respectively. Those skilled in the art will readily understand how to establish a series connection. In Figure 7The horizontal Hall element is also indicated in FIG. The horizontal Hall element is shown by a cut along the second surface 101 b. Figure 7 In FIG. 1 , the spiral coil 170 a and the horizontal Hall element belong to two different cutaway positions along the y-axis. 1001 denotes a volume enclosed by the spiral coils 130 a and 170 a. The Hall plate 103 is completely inside the inner volume 1001 .

[0056] Fig. 8A and Figure 8B The Hall sensor product 800 shown is another product having a horizontal Hall element, for example, similar to the one in the Hall sensor product 300. An on-chip coil for testing and calibration is formed by means of through-silicon vias 140 that laterally surround the horizontal Hall element. Figure 8B A cross-sectional view of a horizontal Hall element and surrounding coil is given. A cut 8A-8A' is indicated, which is in the plane of the second surface 101b. Fig. 8A In FIG. 8A , the horizontal Hall element and surrounding coils are depicted in the xz plane of section 8A-8A′. Figure 8B As shown, the coil includes a metal portion 114 of a metal layer 110 on a first side of a substrate, a through-silicon via 140 passing through the substrate 101, and a metal portion 154 of a metal layer 150 on a second side of the same substrate. The through-silicon via 140 is isolated from the substrate 101 by a dielectric liner 181. Fig. 8A In , a through-silicon via 140 is shown as laterally surrounding a horizontal Hall element with a Hall plate 103. If a current is fed into the coil, a uniform magnetic field is induced inside the coil. Inside the coil, the direction of the induced magnetic field is perpendicular to the xz plane. The coil has a square shape; however, other shapes are also possible, such as a circular shape, an octagonal shape, or a hexagonal shape. Since the coil extends from a first metal layer 110 on a first side of the substrate to a first metal layer 150 on a second side of the substrate, and since the additional coil laterally surrounds the Hall element, a second metal layer on the first side of the substrate and a second metal layer on the second side are required to access the Hall terminals from the outside of the coil. In Figure 8B, metal line 171 and via 161 provide access to metal portion 151 and therefore to Hall terminal 1. Similarly, metal line 172 and via 162 provide access to metal portion 152 and therefore to Hall terminal 2. On the first side of substrate 101 facing carrier wafer 20, metal line 131' and via 121' provide access to metal portion 111' and therefore to Hall terminal 1'. Similarly, metal line 132' and via 112' provide access to metal portion 112' and therefore to Hall terminal 2'. The coil of the Hall sensor product 800 may also have more than one winding, i.e., a spiral coil may be established with the aid of metal portion 154, through-silicon via 140 and metal portion 114. In this case, at least one down-through channel is required. From Figure 8B It can be clearly seen that such a down-through channel can be completed by the metal layer 130 and the corresponding through hole. The down-through channel can also be formed by the metal 170 and the corresponding through hole. Fig. 8A and Figure 8B As can be seen in FIG. 1 , the Hall plate 103 of the horizontal Hall element is completely within the volume 1001 enclosed by the coil integrated in the same wafer 10 .

[0057] Fig. 9A and Fig. 9B The Hall sensor product 900 shown in includes a horizontal Hall element equipped with a coil for testing and calibration, and the coil includes three coil windings oriented in the xz plane. The first coil winding is formed by a metal portion 130a. The coil winding may be the same as the coil winding 130a of the Hall sensor product 300. The second coil winding includes a metal portion 110a, a through-type silicon via 140a and a metal portion 150a. The coil winding may be the same as the coil of the Hall sensor product 800. The third coil winding is formed by a metal portion 170a. The coil winding may also be the same as the coil winding 170a of the Hall sensor product 300. The first coil winding, the second coil winding and the third coil winding are connected in series so that if current is fed into these coil windings, the current direction is the same in the xz plane.

[0058] Fig. 10A and Fig. 10BA Hall sensor product 1000 is shown, which has a vertical Hall element and a coil for testing and calibrating the Hall element. It differs from the Hall sensor product 100 only in that the through-silicon vias 140a-g, 141a-g are placed away from the Hall plate 103 (i.e., at a greater distance). This is indicated by symbol 777. Therefore, if a current is fed into a multi-winding coil, the magnetic field induced in the Hall plate 103 is largely created only by the lateral sections of the coil windings, i.e., the metal parts 130a, 170a, 130b, 170b, etc. As is known in the art, also with this configuration, a uniform magnetic field can be created inside the coil, provided that the sum of the thicknesses of the dielectric layers 107 and 108 on the second side of the substrate 101 is equal to the sum of the thicknesses of the dielectric layers 104 and 105 on the first side of the substrate facing the carrier wafer 20. In other words, if the vertical distance between the metal wire 170 b and the Hall plate 103 is equal to the vertical distance between the Hall plate 103 and the metal wire 130 b , a uniform magnetic field can be induced in the Hall plate 103 .

[0059] Fig.11A The Hall sensor product 1100 shown in FIG. 1 is equipped with the same coil configuration as the Hall sensor product 1000 , however, more than one vertical Hall element is placed inside the coil. Fig.11A , three vertical Hall elements, represented by H1, H2 and H3, are shown as being placed within a volume 1001 representing the interior of a multi-winding coil. Fig.11A A cut along the second surface 101b of the substrate 101 is shown. The vertical Hall elements H1, H2 and H3 are all placed so that their distance to the through-silicon vias 140a-g, 141a-g is large. The large spacing is indicated by symbol 777. The vertical Hall elements H1, H2 and H3 are oriented so that they are sensitive to the magnetic field component in the z-direction. The Hall plates of the vertical Hall elements H1, H2 and H3 are completely inside the multi-winding coil. The multi-winding coil is oriented so that a uniform magnetic field directed in the z-direction can be induced inside the coil. Fig.11AIn , three vertical Hall elements are shown. This is just an example. In general, multiple vertical Hall elements oriented so that they are sensitive to magnetic field components in the z direction can be placed in the interior 1001 of a multi-winding coil, which itself is oriented so that a magnetic field is induced inside it and points in the z direction. Similarly, multiple vertical Hall elements oriented so that they are sensitive to magnetic field components in the x direction can be placed in the interior 1001 of a multi-winding coil, which itself is oriented so that a magnetic field is induced inside it and points in the x direction. In this way, for each of the two directions, multiple vertical Hall elements can be tested and calibrated by a single multi-winding coil. This approach can be extended to the case of horizontal Hall elements. Hall sensor product 300( Figure 3A ) The inner radius of the coil windings 130a and 170a in can be set large enough so that multiple horizontal Hall elements can be placed within the two coil windings.

[0060] This is Fig. 11B , where, as an example, four horizontal Hall elements, denoted by H1, H2, H3 and H4, are placed in the interior 1001 of the test and calibration coil. The coil for testing and calibration has a winding 170a and a winding 130a (not shown).

[0061] In this way, multiple horizontal Hall elements can also be tested and calibrated with a single coil.

[0062] exist Fig. 12A In the Hall sensor product 1200, four vertical Hall elements represented by H1, H2, H3 and H4 are placed in the interior 1001 of the multi-winding coil so that they are at a large distance from any through-silicon vias 140a-g, 141a-g. The four Hall elements H1, H2, H3 and H4 are orthogonally coupled. Fig. 12A In the figure, the orthogonal coupling of the Hall elements H1, H2, H3 and H4 is represented by OC. The orthogonal coupling produces a new Hall element or Hall sensor H. The orthogonal coupling of the four Hall elements H1, H2, H3 and H4 requires various electrical connections, including electrical connections between the metal layer on the first side of the substrate facing the carrier 20 and the metal layer on the second side of the substrate. Part of the electrical connection can be formed on the outside of the multi-winding coil. However, the Hall plates 103 of all four Hall elements are placed inside the interior 1001 of the multi-winding coil. The Hall sensor H is tested and calibrated with the multi-winding coil. In the figure, the orthogonal coupling of the Hall elements H1, H2, H3 and H4 requires various electrical connections, including electrical connections between the metal layer on the first side of the substrate facing the carrier 20 and the metal layer on the second side of the substrate. Fig. 12A In FIG, the vertical Hall element is depicted as being sensitive to the magnetic field component in the z direction. This is for example only. Fig. 12AIn the embodiment, four Hall elements are orthogonally coupled, however, only two Hall elements may be orthogonally coupled to produce a new Hall element or Hall sensor H. In addition, two or four horizontal Hall elements may be orthogonally coupled and tested and calibrated by suitable coils as described above. Fig. 12B is shown in .

[0063] exist Fig.13 In the Hall sensor product 1300, other devices are placed in the multi-winding coil together with the Hall element H. As an example, Fig.13 A vertical Hall element H is depicted in the figure, which is oriented so that the Hall element is sensitive to the magnetic field component along the z-axis. The through-type silicon vias 140a-g, 141a-g belong to a multi-winding coil, which is suitable for inducing a uniform constant magnetic field in the z-direction inside it. The Hall plate of the Hall element H is in the inner volume 1001 of the multi-winding coil. D1 and D2 represent other semiconductor devices besides the Hall element. In the Hall sensor product 1300, the space within the large multi-winding coil dedicated to the testing and calibration of the Hall element is also used for other devices.

[0064] exist Fig.14 In the Hall sensor product 1400, the entire Hall IC is placed inside the multi-winding coil. Fig.14 In the figure, the Hall IC represented by IC includes a vertical Hall element H, which is oriented so that the vertical Hall element is sensitive to the z component of the magnetic field. The Hall IC and the Hall element H are placed in the interior 1001 of a multi-winding coil, which is oriented so that a uniform magnetic field in the z direction is induced inside it. The Hall IC may include more than one vertical Hall element that is sensitive to the z component of the magnetic field. The basic idea of ​​the Hall sensor product can also be extended to the case of a Hall IC, which includes a horizontal Hall element and a coil for testing and calibration.

[0065] Another Hall sensor product 1500 in Fig.15A , Fig. 15B , Fig. 15C and Fig.15D is shown in Fig.15A middle, Fig.15A1 is a cross-sectional view of the Hall sensor product 1500 parallel to the xy plane, showing a vertical Hall element having a Hall plate 103 disposed in a substrate 101, and Hall terminals 1, 2, 3, and 4. The depicted vertical Hall element is sensitive to the z component of the external magnetic field. A winding loop of the first coil is shown, which is formed by metal portions 115 (left and right), through-silicon vias 145 (left and right), metal portions 155 (left and right), through-holes 165 (left and right), through-holes 125, and metal strips 175 and 135. As shown by 777, the vertical section of the first coil is connected to the Fig.15A The vertical Hall elements depicted in are spaced a large distance apart, i.e. far from each other. If a current passes through the coil, as shown in the figure, the windings of the coil are parallel to the xy plane, a magnetic field in the z direction is induced inside the coil. In addition, at the position of the depicted vertical Hall elements, i.e. far away from the through-silicon vias 145, a magnetic field is mainly induced by the current flowing through the metal strips 135 and 175. A third metal layer 230 is arranged on a first side of the substrate 101 facing the carrier 20, and a third metal layer 270 is also arranged on a second side of the substrate. With the help of the metal layers 230 and 270, a second multi-winding coil is formed, the orientation of which in the xz plane is rotated by 90 degrees relative to the first coil. Fig. 15B is a projection diagram showing the orientation of the metal strip 175 parallel to the xz plane (cut 15B- 15B′). Fig. 15C is a projection showing the orientation of the metal strip 275 parallel to the xz plane (section 15C-15C'). The vertical section of the second coil is not shown in any of the figures, but Figure 6 It is clear how these vertical sections can be established. Fig.15A , 1001 represents an inner volume shared by a first (inner) multi-winding coil and a second (outer) multi-winding coil. If a current I1 is fed into the first coil, a magnetic field in the z direction is induced in the volume 1001. If a current I2 is fed into the second coil, a magnetic field in the x direction is induced in the volume 1001. By appropriately adjusting the currents I1 and I2, the absolute value of the magnetic field in the z direction can be made equal to the absolute value of the magnetic field in the x direction. Fig.15D Another cutaway of the Hall sensor product 1500 parallel to the xz plane is given, this time along the second surface 101b (cutaway 15D-15D'). Two vertical Hall elements H1 and H2 are placed inside 1001 of the two multi-winding coils, one oriented so as to be sensitive to magnetic fields in the z direction (H1) and the other oriented so as to be sensitive to magnetic fields in the x direction (H2). The vertical Hall element H1 is tested and calibrated by the first (inner) coil, and the vertical Hall element H2 is tested and calibrated by the second (outer) coil.

[0066] The coil configuration of the Hall sensor product 1500 is used in the Hall sensor product 1600, see Fig.16 , to test and calibrate circular vertical Hall elements. Fig.16 A cutaway of the Hall sensor product 1600 along the second surface 101b is shown. 145 represents a plurality of through-type silicon vias belonging to the first (inner) multi-winding coil and the second (outer) multi-winding coil. The inner volume shared by the two coils is represented by 1001. The circular vertical Hall element CVH is placed within the two coils so that the Hall plate 103 is completely within the volume 1001. The Hall plate 103 has an annular shape and is laterally limited by two dielectric structures, each represented by 109. As shown, a plurality of n Hall terminals 1, 2, 3, ..., n are formed in the Hall plate on the second surface 101b of the substrate 101. A second plurality of Hall terminals 1', 2', 3', ..., n' can be formed on the first surface 101a of the substrate. The circular vertical Hall element CVH is sensitive to external magnetic fields in the xz plane, i.e., parallel to the surfaces 101a and 101b of the substrate. This type of vertical Hall element is particularly useful for angular position measurement applications. The circular vertical Hall element CVH is tested and calibrated by the combined operation of the first (inner) multi-winding coil and the second (outer) multi-winding coil.

[0067] exist Fig.17 In the Hall sensor product 1700, two coils are placed in series for testing and calibration of the Hall element. Fig.17 , a first coil represented by C1 is shown. The vertical Hall element H1 C1 is placed in the interior 1001 of the coil C1. The vertical Hall element is oriented so as to be sensitive to an external magnetic field in the z direction. The coil C1 is dedicated to testing and calibrating the vertical Hall element. Therefore, the coil winding of the coil C1 is oriented so that a magnetic field in the z direction is induced in the interior 1001 of the coil winding. C2 represents the second coil. A second vertical Hall element H2 is depicted, which is placed in the interior 1001 of the coil C2. The vertical Hall element H2 is oriented so as to be sensitive to an external magnetic field in the x direction. The coil C2 dedicated to testing and calibrating the vertical Hall element H2 is oriented accordingly. The two coils C1 and C2 are connected in series, and the Hall elements H1 and H2 can be tested or calibrated at the same time. The basic idea of ​​the Hall sensor product 1700 is applicable to situations where three or more coils are connected in series for testing and calibration. In particular, it can be considered to have three coils C1, C2 and C3, where C1 and C2 are used for testing and calibrating such as Fig.17The two vertical Hall elements are shown, while C3 is used to test and calibrate the horizontal Hall element. In this way, a 3D Hall sensor can be tested and calibrated by a coil setup consisting of a series connection of three coils C1, C2 and C3, one coil for each direction in space.

[0068] Fig.18 The Hall sensor product 18 shown includes a plurality of identical Hall elements, wherein only a subset of the identical Hall elements are equipped with an on-chip coil for testing and calibration. Fig.18 , four vertical Hall elements H1, H2, H3 and H4 are shown by way of example. Only the vertical Hall element H3 is placed in the interior 1001 of the multi-winding coil. The basic concept also applies to multiple identical horizontal Hall elements.

[0069] Another Hall sensor product 1900 in Fig.19 It is shown in Fig.19 is a cross-sectional view. A vertical Hall element is formed on a substrate 101 belonging to a wafer 10. A Hall plate 103 is disposed in the substrate 101. A dielectric structure 109 laterally limits the Hall plate. Hall terminals 1 and 2 are formed at a first surface 101a of the substrate 101, while Hall terminals 3 and 4 are formed on a second surface 101b of the substrate. The wafer 10 is attached to a wafer 20, the first surface 101a of the wafer 10 facing the carrier 20. In the Hall sensor product 1900, the carrier 20 is also a structured wafer, for example, 20 is a CMOS wafer. Fig.19 In the embodiment, wafer 20 includes substrate 201 and at least one metal layer 230 disposed in dielectric layer 206. Electrical connection between metal layer 130 of substrate 101 and metal layer 230 of substrate 201 can be established by hybrid bonding. By this technique known in the art, direct bonding between dielectric layers (oxide) 106 and 206 is achieved, while electrical connection is established by copper-to-copper bonding. Fig.19 2313b and 1323b represent such copper-to-copper bonding. Other techniques for wafer stacking are known in the art and may also be used in the Hall sensor product 1900. A third wafer 30 is provided, which has a substrate 301 and at least one metal layer 370 embedded in a dielectric layer 306. Wafer 30 is attached to wafer 10, wherein dielectric layer 306 faces dielectric layer 182 of wafer 20. The electrical connection between wafer 30 and wafer 20 is preferably established in the same manner as the electrical connection between wafer 20 and wafer 10, for example again by Fig.19 1737b and 3717b represent the copper-to-copper bonding between substrates 101 and 301. Fig.19Also shown, a coil for testing and calibrating a vertical Hall element is formed, which extends over all three wafers 10, 20 and 30. In particular, the lateral sections 370b and 230b of the coil are formed by the metal layers of wafers 30 and 20, respectively. The Hall plate 103 of the vertical Hall element is located inside 1001 of the multi-winding coil extending over the three wafers 10, 20 and 30. The basic concept of the Hall sensor product 1900 also applies to the case of horizontal Hall elements. In this case, the first spiral coil will be formed by the metal layer 230 of the substrate 201. The second spiral coil will be formed by the metal layer 370 of the substrate 301. In order to connect the two spiral coils in series, electrical connections between the wafers and through-silicon vias are required. It can be combined with Fig.19 The same type of structure shown and discussed.

[0070] Fig. 20 The Hall sensor product 2000 is another Hall sensor product in which the coils for testing and calibration of the Hall element extend over three substrates. However, compared with the Hall sensor product 1900, the three substrates are not stacked at the wafer level but at the die level. In other words, the connection is completed after separation during the assembly process. Fig. 20 , a vertical Hall element is formed on a substrate 101. A Hall plate 103 is disposed in the substrate 101. A dielectric structure 109 laterally limits the Hall plate. Hall terminals 1 and 2 are formed at a first surface 101a of the substrate 101, while Hall terminals 3 and 4 are formed on a second surface 101b of the substrate. Processing on the second side of the substrate 201 requires a carrier wafer. However, the carrier wafer is a temporary carrier and is therefore not part of the final Hall sensor product. Fig. 20 After the manufacturing process of the substrate 101 is completed, the substrate 101 is separated into dies. Fig. 20 10 represents a single die including at least one vertical Hall element. Another die 20 is provided, which includes a substrate 201 and at least two metal layers 230 and 250 embedded in a dielectric layer 206. In addition, another die 30 is provided, which includes a substrate 201 and at least two metal layers 370 and 350 embedded in a dielectric layer 306. The electrical connection between the die 10 and the die 20 is made by copper or solder bumps (such as Fig. 20 Similarly, the electrical connection between die 30 and die 20 is established by copper or solder bumps (such as Fig. 20 Such assembly processes are known in the art and may deviate from the foregoing discussion in several aspects and details. Fig. 20, forming a coil for testing and calibrating the vertical Hall element, which extends on tube core 30, tube core 10 and tube core 20. In particular, the lateral sections of coils 230b and 370b are formed by the metal layers of substrates 201 and 301, respectively. Similar to Hall sensor product 1900, the basic concept of Hall sensor product 2000 can also be applied to the case of horizontal Hall elements. In this case, the first spiral coil will be formed by metal layer 230 of substrate 201 (tube core 20). The second spiral coil will be formed by metal layer 370 of substrate 301 (tube core 30). The electrical series connection of the spiral coils will have the same Fig. 20 The vertical sections of the coils shown in FIG.

[0071] Reference now FIG. 21A to FIG. 21M Public by example Figures 1A to 1C The manufacturing process steps of the Hall sensor product 100 are shown in FIG.

[0072] like Fig.21A As shown, a wafer 10 including a semiconductor substrate 101 is provided, the semiconductor substrate having a first surface 101a and a second surface 101c. The substrate 101 is preferably a silicon substrate of a first conductivity type (preferably n-type). Two shallow and highly doped regions 1 and 2 of the first conductivity type are formed at the first surface 101a. The two highly doped regions 1 and 2 extend from the surface 101a into the semiconductor substrate 101. The highly doped regions 1 and 2 are created by photomask implantation, subsequent removal of the resist and laser thermal annealing. The highly doped regions 1 and 2 have n-type conductivity and extend to the surface 10b. The doping concentration may be 1020atoms / cm 3 Up to 1022atoms / cm 3 In laser thermal annealing, the wafer is subjected to very short heat pulses so that the heat can only penetrate to a limited depth in the silicon, depending on the pulse time, energy dose and wavelength. The depth of the highly doped region may be in the range of 50 nanometers to 200 nanometers.

[0073] like Fig.21B As shown, a dielectric layer 104 is deposited on the surface 10b. The dielectric layer may be tetraethyl orthosilicate (TEOS) deposited by plasma enhanced chemical vapor deposition (PECVD). The first opening and the second opening are etched through the oxide layer 104 by a photomask etching process, so that the highly doped region 1 is exposed. A first metal layer 110 is deposited on the dielectric layer 104. The first metal layer 110 is deposited by Fig.21BThe photomask etching step shown is configured to leave portions 110b, 112, 111 and 111b and fill the two openings below portions 111 and 112 so that the metal contacts the exposed highly doped silicon regions 1 and 2. The metal layer is preferably an aluminum-based metal stack, which typically includes a titanium adhesion layer, a titanium nitride barrier layer, an aluminum layer and a titanium nitride capping layer. A second dielectric layer 105 is deposited on top of the metal structure 110 and the exposed oxide layer 104. The second dielectric layer 105 is planarized by chemical mechanical polishing (CMP). Through silicon vias 121b are etched through the dielectric layer 105 by anisotropic dry etching, selectively stopping at the titanium nitride barrier layer of the metal structure 111b. The through silicon vias are filled with a tungsten-based layer. A second metal layer 130, preferably an aluminum-based or copper-based layer, is deposited on the dielectric layer 105 and is configured to leave portions 130b. The third dielectric layer 106 is then deposited on top of the second metal layer 130b and the exposed second dielectric layer 105. The third dielectric layer 106 is planarized by chemical mechanical polishing (CMP).

[0074] Steering Fig. 21C and Fig.21D , the wafer 10 is flipped and attached to the surface of the second wafer 20 with the third dielectric layer surface 106a. The second wafer 20 can be a carrier wafer or a CMOS wafer containing integrated circuits required to operate the vertical Hall element. Permanent bonding is achieved between wafer 10 and wafer 20. There are several methods for permanent wafer bonding known in the art. An example of a bonding process is described in the above-mentioned international application WO 2020 / 104998 A1 in the name of the present applicant. Using the CMOS wafer 20 as a carrier wafer, the Hall sensor wafer 10 is processed from the rear surface 101c of the Hall sensor wafer.

[0075] like Fig.21E As shown, the wafer 10 is thinned by removing most of the silicon material from the back side. The second substrate surface of the wafer 10 obtained after thinning is indicated by 101b. The thickness of the remaining semiconductor substrate 101 may preferably be in the range of 10 to 50 micrometers.

[0076] continue Fig.21F, shallow and highly doped regions 3 and 4 with n-type conductivity are formed on the second surface 101b in the same manner as the highly doped regions 1 and 2 on the first surface. In particular, the doped regions 1 and 2 are created using the same implantation species, implantation dose and energy as used on the first surface. More particularly, the same laser thermal annealing conditions as those applied on the first surface for activating the doped regions 1 and 2 are applied after the resist is removed. Those skilled in the art will appreciate that by activating the dopants on the second surface using laser thermal annealing, compared to other activation methods such as furnace annealing or rapid thermal processing, the aluminum-based metallization on the first surface of the Hall sensor wafer 10 can be prevented from being damaged by the heat treatment. In addition, the laser thermal annealing does not increase the thermal budget of the devices formed on the CMOS wafer 20.

[0077] like Figure 21G As shown, a dielectric structure 19 is created that extends from the second surface 101b to the first surface 101a of the substrate layer 101, laterally surrounding a portion of the substrate layer 101 containing the Hall sensor region (Hall plate) 103. The dielectric structure is created by a deep trench isolation process known in the art.

[0078] refer to Fig.21H A first dielectric layer 107 is deposited on the second surface 101b using the same process and materials as used for the first dielectric layer 104 on the first side.

[0079] refer to Fig.21I , a deep silicon etching process is performed using the silicon nitride layer as a hard mask to form a through hole opening 11. The deep silicon etching is first selectively stopped on the oxide layer 104. A thin oxide layer 181 is deposited. More specifically, layer 181 can be tetraethyl orthosilicate (TEOS) deposited by plasma enhanced chemical vapor deposition (PECVD) at a temperature not higher than 400° C. The oxide layer 181 serves as a dielectric liner on the silicon sidewalls exposed by the previous deep silicon etching. The thickness of the oxide layer 181 can be, for example, 3000 angstroms, but is not limited to this value.

[0080] The thin oxide 181 is then etched through at the bottom of the deep through silicon via opening 11. The dry etching stops selectively in the titanium nitride barrier layer of the metal structure 110. The via opening 11 is filled with a metal layer, which may be a tungsten based metal layer, or more preferably, a copper based metal layer.

[0081] Steering Figure 21K, a contact trench or hole 17 is formed through the dielectric layer 107 by a photomask etching process, so that the highly doped regions 3 and 4 are exposed. Due to the high selectivity to silicon, the etching can stop in the shallow highly doped regions 3 and 4, thereby ensuring that the doping concentration at the silicon surface within the trench or hole 17 is 1020atoms / cm 3 Up to 1022atoms / cm 3 in the range of.

[0082] A first metal layer 150 is deposited on the dielectric layer 107 and fills the contact trenches or holes 17. Similar processes and materials are applied as for the metal layer 110 on the first surface. After deposition, the metal layer is formed by Figure 21L As shown in the figure, the metal structure 150 completely covers the top surface of the through-silicon vias 140b and 141b, thereby achieving electrical connection between the two through-silicon vias.

[0083] Then the intermetallic dielectric layer 108 is deposited on top of the metal structure 150. Similar processes and materials are used for the first side intermetallic dielectric 105. Figure 21M As shown, the via structure is etched through the intermetallic dielectric layer 108 and filled with metal layers 160b and 161b. Then the second metal layer 170 is deposited on top of the intermetallic dielectric layer 108 and is configured to electrically connect the vias 160b and 161b through the metal portion 170b. The process and materials for filling the vias with metal and forming the metal layer portion 170b are similar to the process and materials for the second metal layer 130 on the first side of the substrate. Finally, a dielectric layer 182 is deposited on top of the metal structure 170 and on the exposed intermetallic dielectric layer 108.

[0084] From the foregoing description it is clear that the advantages of the proposed solution can be seen.

[0085] In particular, the Hall sensor is configured such that the n induction coils for testing and calibration induce a uniform and constant magnetic field in the Hall plate of the vertical or horizontal Hall sensor element.

[0086] Finally, it will be evident that modifications and variations may be made to what has been described and illustrated herein without departing from the scope of the present invention as defined in the appended claims.

Claims

1. An integrated Hall sensor, comprising: A main wafer (10) of semiconductor material, the main wafer having a substrate (101), the substrate having a first surface (101a) and a second surface (101b), the second surface (101b) being opposite to the first surface (101a) along a vertical axis (y); Hall sensor terminals (1, 2, 3, 4; 1', 2', 3', 4'), the Hall sensor terminals (1, 2, 3, 4; 1', 2', 3', 4') are arranged at at least one of the first surface (101a) and the second surface (101b) of the substrate (101); an isolation structure in the substrate (101), the isolation structure defining a Hall sensor plate (103) of the integrated Hall sensor, the Hall sensor terminals being arranged inside the isolation structure, The integrated Hall sensor further comprises at least one test or calibration coil (C1) integrated in the main wafer (10), wherein the at least one test or calibration coil (C1) has a metal portion (130b, 170b) at least partially arranged above the first surface (101a) and the second surface (101b) of the substrate (101); 130a, 170a) and define an inner volume (1001) that completely surrounds the Hall sensor plate (103); and Wherein, the test or calibration coil comprises: at least a first metal portion (130b; 130a) defined in a metal layer (130), the metal layer (130) being formed on a first dielectric layer structure (104, 105) arranged on the first surface (101a) of the substrate (101); at least a second metal portion (170b; 170a) defined in a corresponding metal layer (170), the corresponding metal layer (170) being formed on a second dielectric layer structure (107, 108) arranged on the second surface (101b) of the substrate (101); and at least a through-silicon via (140b), the through-silicon via (140b) extending from the second surface (101b) of the substrate (101) to the first surface (101a) of the substrate (101); and A first outer dielectric layer (106) is arranged on the first dielectric layer structure (104, 105), the main wafer (10) is attached to a second wafer (20) together with the top surface of the outer dielectric layer (106), and the second wafer (20) is configured to thin the main wafer (10) from the second surface (101b).

2. The integrated Hall sensor according to claim 1, wherein: The second wafer (20) is configured to thin the main wafer (10) from the second surface (101b) to a thickness in the range of 10 micrometers to 50 micrometers.

3. The integrated Hall sensor according to claim 1 or 2, comprising at least one Hall sensor element (H1), the at least one Hall sensor element (H1) having: Hall sensor terminals (1, 2) formed at the first surface (101a) of the substrate (101); 1'、2'、3'、4')； and Hall sensor terminals (3, 4; 1, 2, 3, 4) formed at a second surface (101b) of the substrate (101) opposite to the Hall sensor terminals at the first surface (101a); wherein the isolation structure comprises a dielectric structure (109) extending from the second surface (101b) of the substrate (101) to the first surface (101a) and laterally surrounding a portion of the substrate (101) defining the Hall sensor plate (103); and wherein the test or calibration coil comprises : a first metal portion (130a), the first metal portion (130a) is formed on a first dielectric layer structure (104, 105), the first dielectric layer structure (104, 105) is arranged on the first surface (101a) of the substrate (101); and a second metal portion (170a), the second metal portion (170a) is formed on a second dielectric layer structure (107, 108), the second dielectric layer structure (107, 108) is arranged on the second surface (101b) of the substrate (101).

4. The integrated Hall sensor according to claim 3, wherein: The first dielectric layer structure (104, 105) has the same thickness as the second dielectric layer structure (107, 108).

5. The integrated Hall sensor according to claim 3, comprising: A further Hall sensor element (H2, H3, H4) is completely surrounded by the inner volume (1001) defined by the test or calibration coil.

6. The integrated Hall sensor according to claim 5, wherein: At least some of the Hall sensor elements are orthogonally coupled elements which together form a Hall sensor (H) designed to be tested and calibrated by the test or calibration coil.

7. The integrated Hall sensor according to claim 3, further comprising an integrated circuit (IC) arranged in the inner volume (1001) defined by the test or calibration coil.

8. The integrated Hall sensor according to claim 3, wherein: The second wafer (20) has a corresponding substrate (201) and at least one metal layer (230), the at least one metal layer (230) being arranged in a dielectric layer (206) formed on the substrate (201), the second wafer (20) being attached to the main wafer (10) above the first surface (101a) of the substrate (101), wherein the dielectric layer (206) faces the same first surface (101a); and The integrated Hall sensor further comprises a third wafer (30), the third wafer (30) having a corresponding substrate (301) and at least one metal layer (370), the at least one metal layer (370) being arranged in a dielectric layer (306) formed on the substrate (301), the third wafer (30) being attached to the main wafer (10) above the second surface (101b) of the substrate (101), wherein the dielectric layer (306) faces the same second surface (101b), Parts of the metal layer (230, 370) of the second wafer (20) and the third wafer (30) help to define the winding of the test or calibration coil and the inner volume (1001) of the test or calibration coil of the Hall sensor plate (103) surrounding the Hall sensor element, and the test or calibration coil extends across the main wafer (10) and the second wafer (20) and the third wafer (30).

9. The integrated Hall sensor according to claim 8, wherein: At least one of the second wafer (20) and the third wafer (30) is a CMOS wafer integrated circuit for operating the Hall sensor element.

10. The integrated Hall sensor according to claim 3, further comprising: At least one additional Hall sensor element (H2); and an additional test or calibration coil (C2) integrated in the main wafer (10), the additional test or calibration coil (C2) defining a corresponding inner volume (1001) of the Hall sensor plate that completely surrounds the additional Hall sensor element (H2); wherein the at least one test or calibration coil (C1) and the additional test or calibration coil (C2) are connected in series so that the at least one Hall sensor element (H1) and the additional Hall sensor element (H2) can be tested or calibrated simultaneously.

11. The integrated Hall sensor according to claim 3, comprising at least one vertical Hall sensor element (H1), wherein the at least one vertical Hall sensor element (H1) has: first coupled Hall sensor terminals (1, 2) formed at the first surface (101a) of the substrate (101); and second coupled Hall sensor terminals (3, 4) formed at the second surface (101b) of the substrate (101) and opposite to the first coupled Hall sensor terminals; wherein, Each winding of the test or calibration coil comprises: a first metal portion (130b), the first metal portion (130b) being formed on the first dielectric layer structure (104, 105), the first dielectric layer structure (104, 105) being arranged on the first surface (101a) of the substrate (101); a second metal portion (170b), the second metal portion (170b) being formed on the second dielectric layer structure (107, 108), the second dielectric layer structure (107, 108) being arranged on the second surface (101b) of the substrate (101); and through-silicon vias (140b, 141b), the through-silicon vias (140b, 141b) extending through the substrate (101) and being coupled to the first metal portion (130b) and the second metal portion (170b).

12. The integrated Hall sensor according to claim 11, wherein: The Hall sensor terminals (1, 2, 3, 4) extend along a first horizontal axis (z) of a plane parallel to the first surface (101a) and the second surface (101b) of the substrate (101), and the first metal part (130b) and the second metal part (170b) extend along a second horizontal axis (x) of the plane transverse to the first horizontal axis (z); and wherein the windings of the test or calibration coil each have a rectangular cross-section in a plane defined by the second horizontal axis (x) and by the vertical axis (y), and the windings of the test or calibration coil are connected in series and arranged along the first horizontal axis (z).

13. The integrated Hall sensor according to claim 11, wherein: The through-silicon vias (140b, 141b) have the same lateral distance from the Hall sensor plate (103).

14. The integrated Hall sensor according to claim 11, wherein: The through-silicon vias (140b, 141b) defining the windings of the test or calibration coil are spaced apart from the Hall sensor plate (103) so as not to affect the magnetic field induced in the Hall sensor plate (103).

15. The integrated Hall sensor according to claim 11, further comprising an external coil formed in the main wafer (10), the external coil having a plurality of windings, each winding comprising: a corresponding first metal portion (230b), the corresponding first metal portion (230b) being formed on the first outer dielectric layer (106), the first outer dielectric layer (106) being arranged on the first dielectric layer structure (104, 105); a corresponding second metal portion (270b), the corresponding second metal portion (270b) being formed on the second outer dielectric layer (182), the second outer dielectric layer (182) being arranged on the second dielectric layer structure (107, 108); and corresponding through-silicon vias (142b, 143b), the corresponding through-silicon vias (142b, 143b) extending through the substrate (101) and being coupled to the corresponding first metal portion (230b) and the second metal portion (270b); wherein the external coil is connected in series to the test or calibration coil.

16. The integrated Hall sensor according to claim 11, further comprising an external coil formed in the main wafer (10), the external coil having a plurality of windings, each winding comprising: A corresponding first metal portion (234), the corresponding first metal portion (234) is formed on a first outer dielectric layer (106), the first outer dielectric layer (106) is arranged on the first dielectric layer structure (104, 105); a corresponding second metal portion (275), the corresponding second metal portion (275) is formed on a second outer dielectric layer (182), the second outer dielectric layer (182) is arranged on the second dielectric layer structure (107, 108); wherein the orientation of the outer coil is rotated 90 degrees relative to the test or calibration coil.

17. The integrated Hall sensor according to claim 16, wherein: The vertical Hall sensor element is a circular vertical Hall element (CVH), wherein a Hall sensor plate (103) having a ring shape is completely arranged in the inner volume (1001) defined by the outer coil and the test or calibration coil.

18. The integrated Hall sensor according to claim 3, comprising at least one horizontal Hall sensor element, wherein the horizontal Hall sensor element has: a first group of doped regions (1', 2', 3', 4') formed at the first surface (101a) of the substrate (101); and a second group of doped regions (1, 2', 3', 4') formed at the second surface (101b) of the substrate (101). 2, 3, 4), the second group of doped regions (1, 2, 3, 4) are opposite to the first group of doped regions (1', 2', 3', 4') and the second group of doped regions (1, 2, 3, 4) and the first group of doped regions (1', 2', 3', 4') define corresponding Hall sensor terminals of the horizontal Hall sensor element.

19. The integrated Hall sensor according to claim 18, wherein: The test or calibration coil comprises: at least a first winding, the at least first winding being defined in a metal layer (130), the metal layer (130) being formed on a first dielectric layer structure (104, 105) arranged on the first surface (101a) of the substrate (101); and at least a second winding, the at least second winding being defined in a corresponding metal layer (170), the corresponding metal layer being formed on a second dielectric layer structure (107, 108) arranged on the second surface (101b) of the substrate (101); the first winding and the second winding being arranged to face each other and surround the Hall sensor plate (103).

20. The integrated Hall sensor according to claim 18, wherein: The test or calibration coil is at least partially formed by a through-silicon via (140b) laterally surrounding the horizontal Hall element and surrounding the dielectric structure (109).

21. The integrated Hall sensor according to claim 18, wherein: The test or calibration coil has a spiral configuration.

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