Integrated circuit and testing method thereof

Abstract

The present application relates to an integrated circuit and a test method thereof. The integrated circuit includes a test control circuit, a drive circuit and a test detection circuit. The test control circuit generates a test address signal and a test command signal corresponding to a test operation. The drive circuit performs a test operation by using a test internal voltage generated based on the test command signal. The test detection circuit compares the test address signal with target address information to output a test internal voltage.

Description

Technical Field

[0001] Various embodiments generally relate to an integrated circuit and a test method thereof, and more particularly, to an integrated circuit capable of detecting a test result according to a test operation and a test method thereof. Background Art

[0002] Typically, various tests are performed on an integrated circuit such as a semiconductor memory device before it is released to the market. Traditionally, the integrated circuit is tested using automatic test equipment (ATE). Automatic test equipment is a single product developed to determine whether the integrated circuit is well designed. Because the cost of automatic test equipment is relatively high, the cost of the integrated circuit depends on whether the integrated circuit is tested by the automatic test equipment. As the time spent testing the integrated circuit with the automatic test equipment increases, the cost of the integrated circuit increases.

[0003] In order to solve the above problems, more attention is paid to built-in self-test circuits. The built-in self-test circuits are installed in the integrated circuits and perform test operations on the integrated circuits instead of automatic test equipment. The built-in self-test circuits reduce the time that the automatic test equipment would otherwise use, thereby reducing the final cost of the integrated circuits.

[0004] However, the built-in self-test circuit generally has a complicated configuration and requires a large amount of space. The complicated configuration makes the built-in self-test circuit susceptible to noise and may cause the built-in self-test circuit to output an erroneous test result value due to noise. The need for increased space is a disadvantage of installing the built-in self-test circuit within the integrated circuit. Summary of the invention

[0005] According to an embodiment, an integrated circuit capable of detecting a test result according to a test operation with a minimum configuration and a test method of the integrated circuit are provided.

[0006] According to an embodiment, an integrated circuit capable of detecting an intermediate test result value occurring during a test operation on the integrated circuit and a test method of the integrated circuit are provided.

[0007] In an embodiment, the integrated circuit may include a test control circuit, a drive circuit, and a test detection circuit. The test control circuit may be configured to generate a test address signal and a test command signal corresponding to a test operation. The drive circuit may be configured to perform a test operation by using a test internal voltage generated based on the test command signal. The test detection circuit may be configured to compare the test address signal with the target address information to output a test internal voltage.

[0008] In an embodiment, the integrated circuit may include a test control circuit, a drive circuit, and a test detection circuit. The test control circuit may be configured to generate a test address signal and a test command signal corresponding to a test operation. The drive circuit may be configured to perform a test operation by utilizing a plurality of test internal voltages generated based on the test command signal. The test detection circuit may be configured to compare the test address signal with the target address information to output a test internal voltage corresponding to the target voltage information among the plurality of test internal voltages.

[0009] In an embodiment, a testing method for an integrated circuit may include: storing a test address signal and a test command signal for performing a test operation; setting target address information corresponding to the test address signal so as to select a specific test operation among the test operations; setting target voltage information corresponding to each of a plurality of test internal voltages so as to select a specific test internal voltage among a plurality of test internal voltages utilized during the specific test operation; and detecting at least one test internal voltage among the plurality of test internal voltages based on the target address information and the target voltage information.

[0010] According to the embodiment, a test result can be detected without using automatic test equipment, and thus the cost of the integrated circuit can be reduced.

[0011] According to an embodiment, an intermediate test result value occurring during a test operation may be detected, and thus, the test operation may be deeply analyzed, and the reliability of the test result may be improved.

[0012] The objects of the present disclosure are not limited to the above objects, and other objects not described above may be clearly understood by those skilled in the art to which the present disclosure belongs from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a block diagram illustrating a configuration of an integrated circuit according to an embodiment.

[0014] Figure 2 is an example Figure 1 A block diagram of the configuration of the test control circuit is shown.

[0015] Figure 3 is stored in Figure 2 A table showing the relationship between a test address signal and a test command signal in a test storage circuit is shown.

[0016] Figure 4 is a block diagram illustrating a configuration of an integrated circuit according to an embodiment.

[0017] Figure 5 is an example Figure 4 A block diagram of the configuration of the test detection circuit is shown.

[0018] Figure 6 is an example Figure 4 A flow chart of a method for testing an integrated circuit is shown.

[0019] Figure 7 is an example Figure 4 A block diagram of the configuration of the test detection circuit is shown. DETAILED DESCRIPTION

[0020] The description of the present disclosure is only an embodiment for structural description and / or functional description. The scope of rights of the present disclosure should not be interpreted as being limited to the embodiments described in the specification. That is, because the embodiments can be modified in various ways and the embodiments can have various forms, the scope of rights of the present disclosure should be understood to include equivalent forms that can realize the technical spirit. In addition, the purpose or effect proposed in the present disclosure does not mean that a specific embodiment should include all purposes or effects or only include such effects. Therefore, the scope of rights of the present disclosure should not be understood to be limited thereto.

[0021] The meanings of the terms described in the present application should be understood as follows.

[0022] Terms such as "first" and "second" are used to distinguish one element from another element, and the scope of the present disclosure should not be limited by these terms. For example, the first element can be named as the second element. Similarly, the second element can be named as the first element.

[0023] Unless otherwise clearly indicated in the context, singular expressions should be understood to include plural expressions. Terms such as "including" or "having" should be understood to indicate the presence of set characteristics, quantities, steps, operations, elements, components or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other characteristics, quantities, steps, operations, elements, components or combinations thereof.

[0024] In each step, symbols (e.g., a, b, and c) are used for ease of description, and these symbols do not describe the order of the steps. Unless a specific order is clearly described in the context, the steps may be performed in an order different from the order described in the context. That is, the steps may be performed in the order described, may be performed substantially simultaneously with the order described, or may be performed in an order opposite to the order described.

[0025] Unless otherwise defined, all terms (including technical or scientific terms) used in this article have the same meaning as those generally understood by those skilled in the art. Unless explicitly defined in this application, terms defined in commonly used dictionaries should be interpreted as having the same meaning as in the context of the relevant technology, and should not be interpreted as having an ideal or excessive form of meaning.

[0026] Figure 1 is a block diagram illustrating a configuration of an integrated circuit according to an embodiment.

[0027] Reference Figure 1 The integrated circuit may include a test control circuit 100 , a drive circuit 200 and a test detection circuit 300 .

[0028] The test control circuit 100 may be configured to generate a test command signal T_CMD and a test address signal T_ADD corresponding to a test operation. For some embodiments, the test operation is a preset test operation. The test command signal T_CMD may be a signal corresponding to one of the various test operations performed in the driving circuit 200. The test address signal T_ADD may be a flag signal indicating one of the various test operations. Figure 3 The test command signal T_CMD and the test address signal T_ADD are described.

[0029] The driving circuit 200 may be configured to perform a test operation based on the test command signal T_CMD. During the test operation, the driving circuit 200 may generate a test internal voltage V_INN, and may perform the test operation by utilizing the test internal voltage V_INN. The test operation may be a main operation of the semiconductor memory device, such as an operation of storing data, reading stored data, etc.

[0030] The test detection circuit 300 may compare the test address signal T_ADD with the target address information INF_ADD to output a test internal voltage V_INN as a test result value V_KR.

[0031] By configuring as described above, the integrated circuit according to the embodiment can perform a test operation on the driving circuit 200 based on the test command signal T_CMD. In addition, the integrated circuit according to the embodiment can detect the test internal voltage V_INN generated by the driving circuit 200 as the test result value V_KR based on the target address information INF_ADD.

[0032] Figure 2 is an example Figure 1 FIG. 1 is a block diagram of the configuration of the test control circuit 100 shown in FIG.

[0033] Reference Figure 2, the test control circuit 100 may include a signal generating circuit 110 and a test storage circuit 120 .

[0034] The signal generation circuit 110 may be configured to generate a control signal CTR_D for controlling a test operation. The test storage circuit 120 may be configured to store a test command signal T_CMD and a test address signal T_ADD. The test storage circuit 120 may be implemented with a read-only memory (ROM). The test storage circuit 120 may store the test command signal T_CMD and the test address signal T_ADD before the test operation. The test storage circuit 120 may output the test command signal T_CMD and the test address signal T_ADD based on the control signal CTR_D output from the signal generation circuit 110.

[0035] Figure 3 is stored in Figure 2 A table showing the relationship between the test address signal T_ADD and the test command signal T_CMD in the test storage circuit 120 is shown.

[0036] According to an embodiment, the integrated circuit may be a NAND flash memory device. The NAND flash memory device may perform a program operation to store data in a memory cell, and may perform a read operation to read out data stored in the memory cell. The NAND flash memory device may perform an erase operation to erase data stored in the memory cell before performing a program operation on the memory cell.

[0037] Figure 2 The test storage circuit 120 shown can generate a test command signal T_CMD and a test address signal T_ADD for each of the erase operation, program operation, and read operation of the NAND flash memory device. The test storage circuit 120 can provide the test command signal T_CMD to the drive circuit 200. The test storage circuit 120 can provide the test address signal T_ADD to the test detection circuit 300. Hereinafter, for the convenience of description, the number of test address signals T_ADD may be defined as 15, and the number of test command signals T_CMD may be defined as 15. The number of test command signals T_CMD and test address signals T_ADD may depend on the test operation to be set.

[0038] Reference Figure 3, the test command signal T_CMD corresponding to the test address signal T_ADD of "0" may indicate an "erase" operation. In addition, the test command signal T_CMD corresponding to the test address signal T_ADD of "1" to "13" may indicate a "program" operation. In addition, the test command signal T_CMD corresponding to the test address signal T_ADD of "14" may indicate a "read" operation. The "erase" operation may correspond to a single test address signal T_ADD of "0", and the "read" operation may correspond to a single test address signal T_ADD of "14". That is, a single test operation may correspond to a single test address signal T_ADD. The "program" operation may correspond to 13 test address signals, namely T_ADD of "1" to "13". That is, a single test operation may correspond to multiple test address signals T_ADD.

[0039] Specifically, the "program" operation may correspond to a plurality of test address signals T_ADD. A test address signal T_ADD of "1" may correspond to a "program initialization" operation within a "program" operation. A test address signal T_ADD of "2" may correspond to a "first programming pulse application" operation within a "program" operation. A test address signal T_ADD of "3" may correspond to a "second programming pulse application" operation within a "program" operation. Although not shown, test address signals T_ADD of "4" to "12" may correspond to specific operations within a "program" operation. A test address signal T_ADD of "13" may correspond to a "program completion" operation within a "program" operation. A "program completion" operation may correspond to a "verification" operation.

[0040] Return to reference Figure 2 , the test storage circuit 120 may store a test address signal T_ADD and a test command signal T_CMD corresponding to each test operation. The test storage circuit 120 may sequentially output the test command signal T_CMD and the test address signal T_ADD based on the control signal CTR_D. Therefore, Figure 1 The driving circuit 200 shown in FIG. 2 can generate a test internal voltage V_INN during a test operation corresponding to each of the test address signals T_ADD of "0" to "14" to perform a test operation. Specifically, the driving circuit 200 can generate a test internal voltage V_INN corresponding to a "programming" operation based on the test address signals T_ADD of "1" to "12". In addition, the test detection circuit 300 can detect the test internal voltage V_INN as an intermediate test result value for the "programming" operation based on each of the test address signals T_ADD of "1" to "12".

[0041] According to an embodiment, the integrated circuit can detect a test internal voltage V_INN corresponding to the test address signal T_ADD. Therefore, the test operator can analyze the internal operation of the integrated circuit by himself through the test internal voltage V_INN. According to an embodiment, the integrated circuit can detect an intermediate test result value. Therefore, the test operator can analyze the integrated circuit more deeply.

[0042] Figure 4 is a block diagram illustrating a configuration of an integrated circuit according to an embodiment.

[0043] Reference Figure 4 , the integrated circuit may include a test control circuit 100A, a drive circuit 200A and a test detection circuit 300A.

[0044] The test control circuit 100A may be configured to generate a test command signal T_CMD and a test address signal T_ADD corresponding to a test operation. For some embodiments, the test operation is a preset test operation.

[0045] The driving circuit 200A may be configured to perform a test operation by using a plurality of test internal voltages (e.g., a first test internal voltage V1, a second test internal voltage V2, and a third test internal voltage V3) generated based on a test command signal T_CMD. The first test internal voltage V1, the second test internal voltage V2, and the third test internal voltage V3 may include at least one test internal voltage used during an erase operation, a program operation, and a read operation.

[0046] The test detection circuit 300A may compare the test address signal T_ADD with the target address information INF_ADD to output a test internal voltage corresponding to the target voltage information INF_V among a plurality of test internal voltages (ie, a first test internal voltage V1 , a second test internal voltage V2 , and a third test internal voltage V3 ).

[0047] Through the configuration as described above, the integrated circuit according to the embodiment can selectively detect a specific test internal voltage among a plurality of test internal voltages utilized during a specific test operation based on the target address information INF_ADD and the target voltage information INF_V.

[0048] Figure 5 is an example Figure 4 2 is a block diagram of the configuration of a test detection circuit 300A.

[0049] Reference Figure 5 The test detection circuit 300A may include a test target storage circuit 510 , an activation circuit 520 , a voltage selection circuit 530 , and an analog-to-digital conversion circuit 540 .

[0050] The test target storage circuit 510 may receive and store therein target address information INF_ADD and target voltage information INF_V. The target address information INF_ADD may be information corresponding to a specific test operation. The target voltage information INF_V may be information corresponding to a specific test internal voltage among a plurality of test internal voltages utilized during a specific test operation. The test target storage circuit 510 may output the stored target address information S_ADD corresponding to the target address information INF_ADD, and may output the stored target voltage information S_V corresponding to the target voltage information INF_V.

[0051] The activation circuit 520 may be configured to compare the stored target address information S_ADD output from the test target storage circuit 510 with the test address signal T_ADD to generate an activation signal EN. When the stored target address information S_ADD and the test address signal T_ADD are identical to each other, the activation circuit 520 may enable the activation signal EN. The activation signal EN may be provided to the analog-to-digital conversion circuit 540 to be described later.

[0052] The voltage selection circuit 530 may be configured to selectively output at least one of the first test internal voltage V1, the second test internal voltage V2, and the third test internal voltage V3 based on the stored target voltage information S_V output from the test target storage circuit 510. The stored target voltage information S_V may be a code type signal corresponding to each of the first test internal voltage V1, the second test internal voltage V2, and the third test internal voltage V3.

[0053] The analog-to-digital conversion circuit 540 may receive the output voltage V_O of the voltage selection circuit 530 and may convert the output voltage V_O into a digital signal based on the activation signal EN. That is, the analog-to-digital conversion circuit 540 may convert the output voltage V_O input therein as an analog signal into a digital signal to output a digital signal.

[0054] According to an embodiment, the integrated circuit may selectively detect a test internal voltage corresponding to the target voltage information INF_V among the test internal voltages generated during a specific test operation corresponding to the target address information INF_ADD.

[0055] The test detection circuit 300A may further include a result storage circuit 550. The result storage circuit 550 may be configured to store the voltage value output from the analog-to-digital conversion circuit 540. That is, the result storage circuit 550 may store the digital value of the test internal voltage corresponding to the target address information INF_ADD and the target voltage information INF_V. Therefore, the test operator may analyze the integrated circuit through the voltage value of the test internal voltage stored in the result storage circuit 550.

[0056] Figure 6 is an example Figure 4 A flow chart of a method for testing an integrated circuit is shown.

[0057] Reference Figures 4 to 6 , the test method of the integrated circuit may include the following steps: storing a test address / command signal (S610), setting target address information (S620), setting target voltage information (S630), converting a test internal voltage (S640), and detecting a test internal voltage (S650).

[0058] The step S610 of storing the test address / command signal may be a step of storing the test address signal T_ADD and the test command signal T_CMD for performing various test operations. The step S610 of storing the test address / command signal may include storing the test address signal T_ADD and the test command signal T_CMD in Figure 2 The steps in testing storage circuit 120 are shown.

[0059] The step S620 of setting the target address information may be a step of setting the target address information INF_ADD corresponding to the test address signal T_ADD so as to select a specific test operation among the test operations. The step S620 of setting the target address information may include storing the target address information INF_ADD in Figure 5 The steps in the test target storage circuit 510 are shown.

[0060] The step S630 of setting the target voltage information may be a step of setting the target voltage information INF_V corresponding to each of the plurality of test internal voltages so as to select a specific test internal voltage among the plurality of test internal voltages utilized during a specific test operation. The step S630 of setting the target voltage information may include storing the target voltage information INF_V in Figure 5 The test target storage circuit 510 is shown. Figure 5The first test internal voltage V1, the second test internal voltage V2, and the third test internal voltage V3 are illustrated as examples of the plurality of test internal voltages. For example, the test target storage circuit 510 may store target voltage information INF_V including one of the first test internal voltage V1, the second test internal voltage V2, and the third test internal voltage V3. Although the example of selecting one of the plurality of test internal voltages V1, V2, and V3, which are three, is illustrated, according to the embodiment, one test internal voltage may be selected from the different plurality of test internal voltages.

[0061] The step S640 of converting the test internal voltage may be a step of converting the test internal voltage corresponding to the target voltage information INF_V. The step S640 of converting the test internal voltage may include: Figure 5 The analog-to-digital conversion circuit 540 shown in FIG. 5 is a step of converting an analog output voltage V_O into a digital signal.

[0062] The step S650 of detecting the test internal voltage may be a step of detecting at least one test internal voltage among a plurality of test internal voltages based on the target address information INF_ADD and the target voltage information INF_V. The step S650 of detecting the test internal voltage may include: a step of outputting at least one test internal voltage among the first test internal voltage V1, the second test internal voltage V2, and the third test internal voltage V3 as a test result value V_KR based on the target address information INF_ADD and the target voltage information INF_V, the step being performed by Figure 4 The test detection circuit 300A shown is implemented.

[0063] According to an embodiment, the integrated circuit may selectively detect a test internal voltage corresponding to the target voltage information INF_V among a plurality of test internal voltages generated during a specific test operation corresponding to the target address information INF_ADD.

[0064] Figure 7 is an example Figure 4 2 is a block diagram of the configuration of a test detection circuit 300A.

[0065] Reference Figure 7 The test detection circuit 300A may include an address storage circuit 710 , a selection control circuit 720 , an analog-to-digital conversion circuit 730 , and a voltage value storage circuit 740 .

[0066] The address storage circuit 710 may be configured to store the test address signal T_ADD. The address storage circuit 710 may be configured with a plurality of registers. The plurality of registers may store the respective test address signals T_ADD inputted sequentially.

[0067] The selection control circuit 720 may be configured to compare the output address signal ADD_O output from the address storage circuit 710 with the target address information INF_ADD to generate the selection control signal CTR_S. When the target address information INF_ADD is identical to one of the test address signals T_ADD stored in the address storage circuit 710, the selection control circuit 720 may output information corresponding to the register storing the test address signal T_ADD identical to the target address information INF_ADD as the selection control signal CTR_S. For example, when the target address information INF_ADD is identical to the test address signal T_ADD stored in the third register within the address storage circuit 710, the selection control signal CTR_S may have information corresponding to the third register.

[0068] The analog-to-digital conversion circuit 730 may be configured to convert the first test internal voltage V1, the second test internal voltage V2, and the third test internal voltage V3, which are a plurality of test internal voltages, into digital signals. Figure 4 The first test internal voltage V1, the second test internal voltage V2, and the third test internal voltage V3 output by the driving circuit 200A shown in the figure may be analog signals. Therefore, the analog-to-digital conversion circuit 730 may convert the first test internal voltage V1, the second test internal voltage V2, and the third test internal voltage V3 input as analog signals into digital signals to output digital signals.

[0069] The voltage value storage circuit 740 may be configured to store output values ​​from the analog-to-digital conversion circuit 730. The voltage value storage circuit 740 may be configured by a plurality of registers, similar to the address storage circuit 710. The plurality of registers may store respective output values ​​sequentially input from the analog-to-digital conversion circuit 730. Based on the selection control signal CTR_S and the target voltage information INF_V, the voltage value storage circuit 740 may be configured to output at least one of the stored output values ​​as a test result value V_KR.

[0070] In the following, reference will be made to Figure 7 Describe testing methods for integrated circuits.

[0071] Figure 4 The driving circuit 200A shown can perform a test operation based on the test command signal T_CMD. The driving circuit 200A can generate a first test internal voltage V1, a second test internal voltage V2, and a third test internal voltage V3, and Figure 7The analog-to-digital conversion circuit 730 shown provides a first test internal voltage V1, a second test internal voltage V2, and a third test internal voltage V3. The analog-to-digital conversion circuit 730 can convert the first test internal voltage V1, the second test internal voltage V2, and the third test internal voltage V3 into digital signals. The voltage value storage circuit 740 can store the first test internal voltage V1, the second test internal voltage V2, and the third test internal voltage V3 converted into digital signals in a plurality of registers, respectively. A plurality of registers can be set to be logically distinguished arrays. The rows in the array can indicate any one of the first test internal voltage V1, the second test internal voltage V2, and the third test internal voltage V3. The columns in the array can indicate each test operation. Therefore, the voltage value storage circuit 740 can select the columns in the array based on the target address information INF_ADD, and can select the rows in the array based on the target voltage information INF_V.

[0072] Hereinafter, for ease of description, it is assumed that the target address information INF_ADD is identical to the test address signal T_ADD stored in the third register within the address storage circuit 710. In this case, according to the test operation corresponding to the third register within the address storage circuit 710, the first test internal voltage V1, the second test internal voltage V2, and the third test internal voltage V3 may be stored in the third register within the voltage value storage circuit 740. Therefore, the voltage value storage circuit 740 may output a test internal voltage among the first test internal voltage V1, the second test internal voltage V2, and the third test internal voltage V3 as a test result value V_KR based on the selection control signal CTR_S corresponding to the target address information INF_ADD and the target voltage information INF_V.

[0073] As mentioned above, according to Figure 7 implementation method, and Figure 5 The same as the implementation of the embodiment, the test result value V_KR can be output based on the target address information INF_ADD and the target voltage information INF_V. The test operator can analyze the integrated circuit through the test result value V_KR.

[0074] Although some embodiments have been described above, it will be understood by those skilled in the art that the described embodiments are only examples. Therefore, the integrated circuit and the test method thereof should not be limited based on the described embodiments. Instead, the integrated circuit and the test method thereof described herein should only be limited according to the attached claims in combination with the above description and the accompanying drawings.

[0075] CROSS-REFERENCE TO RELATED APPLICATIONS

[0076] This application claims the Korean Patent Application No. 10-2020-0107399 filed on August 25, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. An integrated circuit, comprising: a test control circuit configured to generate a test address signal and a test command signal corresponding to a test operation; a driving circuit configured to perform the test operation by using a test internal voltage generated based on the test command signal; as well as A test detection circuit is configured to compare the test address signal with target address information to output the test internal voltage as a test result.

2. The integrated circuit according to claim 1, wherein: The test control circuit comprises: a signal generating circuit configured to generate a control signal for controlling the test operation; and A test storage circuit is configured to store the test command signal and the test address signal and is configured to output the test command signal and the test address signal based on the control signal.

3. The integrated circuit according to claim 2, wherein: The test storage circuit is configured to store at least one test address signal corresponding to at least one test operation.

4. An integrated circuit, comprising: a test control circuit configured to generate a test address signal and a test command signal corresponding to a test operation; a driving circuit configured to perform the test operation by using a plurality of test internal voltages generated based on the test command signal; as well as A test detection circuit is configured to compare the test address signal with target address information to output a test internal voltage corresponding to the target voltage information among the plurality of test internal voltages as a test result.

5. The integrated circuit according to claim 4, wherein: The test control circuit comprises: a signal generating circuit configured to generate a control signal for controlling the test operation; and A test storage circuit is configured to store the test command signal and the test address signal and is configured to output the test command signal and the test address signal based on the control signal.

6. The integrated circuit according to claim 5, wherein: The test storage circuit is configured to store at least one test address signal corresponding to at least one test operation.

7. The integrated circuit according to claim 4, wherein: The test detection circuit comprises: a test target storage circuit configured to receive and store the target address information and the target voltage information; an activation circuit configured to compare the stored target address information output from the test target storage circuit with the test address signal to generate an activation signal; a voltage selection circuit configured to selectively output at least one test internal voltage among the plurality of test internal voltages based on the stored target voltage information output from the test target storage circuit; and The analog-to-digital conversion circuit is configured to receive the output voltage of the voltage selection circuit and convert the output voltage into a digital signal based on the activation signal.

8. The integrated circuit of claim 7, further comprising: A result storage circuit is configured to store a voltage value output from the analog-to-digital conversion circuit as the digital signal.

9. The integrated circuit of claim 4, wherein: The test detection circuit comprises: an address storage circuit, the address storage circuit being configured to store the test address signal; a selection control circuit configured to compare an output address signal output from the address storage circuit with the target address information to generate a selection control signal; an analog-to-digital conversion circuit configured to convert the plurality of test internal voltages into digital signals; and A voltage value storage circuit is configured to store output values ​​from the analog-to-digital conversion circuit and output at least one output value among the stored output values ​​as a test result value based on the selection control signal and the target voltage information.

10. A method for testing an integrated circuit, the method comprising the following steps: storing a test address signal and a test command signal for executing a test operation; setting target address information corresponding to the test address signal so as to select a specific test operation among the test operations; setting target voltage information corresponding to each of a plurality of test internal voltages so as to select a specific test internal voltage among the plurality of test internal voltages utilized during the specific test operation; as well as At least one test internal voltage corresponding to the target voltage information among the plurality of test internal voltages is output as a test result based on comparing the test address signal and the target address information.

11. The test method according to claim 10, further comprising the following steps: The test internal voltage corresponding to the target voltage information is converted into a digital signal.

12. The testing method according to claim 10, wherein: The step of storing the test address signal includes the step of storing at least one test address signal corresponding to at least one test operation.

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