High-throughput linear feedback shift register

Abstract

Embodiments of the present disclosure relate to a high-throughput linear feedback shift register. An N-bit linear feedback shift register includes P parallel flip-flop chains, each flip-flop chain having an input and an output. The input is coupled to the output of an exclusive-OR circuit of the flip-flop chain. The input of the exclusive-OR circuit of the flip-flop chain is coupled to the outputs of different flip-flops of the P flip-flop chains according to the exponent of an N-1 order primitive polynomial. The flip-flops of the P flip-flop chains are clocked by a second clock. At each rising edge of the second clock, P LFSR pre-outputs are generated from the output of the last flip-flop of each flip-flop chain in the P parallel flip-flop chains. A readout circuit device clocked by a first clock having a frequency P times that of the first clock passes a different one of the P pre-LFSR outputs as the LFSR output in each clock cycle.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 072,376, filed on August 31, 2020, the contents of which are incorporated by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates to the field of linear feedback shift registers (LFSRs), and in particular to a parallelized design for LFSRs with high throughput capabilities. Background Art

[0004] A linear feedback shift register (LFSR) is a shift register whose input bits are a linear function of its previous state. These input bits are typically generated from certain taps of the LFSR as an exclusive-OR of bits. The operation of an LFSR is deterministic, as the stream of values generated is determined by its current or previous state. Since an LFSR has a finite number of possible states, it will eventually enter a repeating loop. However, because LFSRs include feedback, they can produce seemingly random sequences of bits with very long repeat periods. Consequently, LFSRs are widely used in applications that generate pseudorandom numbers.

[0005] A typical LFSR 10 is as follows Figure 1 , and is formed as a chain of flip-flops that are synchronously clocked by a clock signal CLK. Here, the LFSR 10 is an N-bit LFSR, so there are N flip-flops, labeled from D[0] to D[N-1]. Flip-flop D[0] receives input from the XOR tree 11 and provides an output to the subsequent flip-flop D[1] in the chain, which in turn provides an output to the next flip-flop in the chain, and so on, until the last flip-flop in the chain, D[N-1], receives input from the previous flip-flop D[N-2].

[0006] A primitive polynomial function of order N-1 (where N is the same as the number of bits in the LFSR) (the generation of which is known to those skilled in the art) is used to determine the inputs to the XOR tree 11. Specifically, the outputs of the flip-flops corresponding to the exponents of the primitive polynomial function become the inputs to the XOR tree 11. In the illustrated example, the exponents of the primitive polynomial function of order N are i, j, and N-1. Thus, as illustrated, the inputs to the XOR tree 11 are the outputs of the flip-flops D[i], D[j], and D[N-1].

[0007] Such as Figure 1LFSRs 10 of the design illustrated in FIG are very useful and widely used. However, such LFSRs 10 encounter problems when it is desired to operate them at high speeds (i.e., when the clock CLK has a high frequency), despite the fact that they are formed in slower technologies. In particular, individual flip-flops are limited by their setup time, limiting the speed at which such LFSRs 10 can operate when implemented in certain technologies.

[0008] Therefore, there remains a need for a LFSR 10 capable of high-speed operation, even when implementing slower techniques. Summary of the Invention

[0009] Disclosed herein is an N-bit linear feedback shift register (LFSR), comprising: P parallel flip-flop chains, each flip-flop chain having an output; a counter clocked by a fast clock and configured to output N different output words, wherein a different one of the N different output words is generated at each pulse of the fast clock, and the counter is configured to reset after each of the N different output words is output; a multiplexer having a single output, having inputs coupled to the outputs of the P parallel flip-flop chains, having a select input coupled to the counter, and configured to pass different inputs to the single output depending on which of the N different output words is received from the counter; and a flip-flop having an input coupled to the single output of the multiplexer, the flip-flop being clocked by the fast clock such that the flip-flop passes the current state of its input to its output at each pulse of the fast clock.

[0010] Each parallel chain of flip-flops is formed by: a chain of flip-flops clocked by a slow clock, the slow clock being equal to the fast clock divided by P, each flip-flop except the last flip-flop of the chain having an index calculated as x+yP, where x indicates to which of the P parallel flip-flop chains the flip-flop chain belongs, and where y indicates the position within the flip-flop chain occupied by the flip-flop, wherein the last flip-flop of the chain has an index calculated as x+yP, where y is equal to the smallest integer greater than or equal to (N-1-x) / P; and an exclusive-OR (XOR) circuit for the parallel chain of flip-flops, receiving as input the outputs of those flip-flops from the flip-flop chains of the parallel chain of flip-flops having an index equal to the exponent of a primitive polynomial of order N-1, wherein the exclusive-OR circuit of the parallel chain of flip-flops provides its output as input to the first flip-flop chain of the parallel chain of flip-flops.

[0011] This document also discloses an N-bit linear feedback shift register (LFSR), comprising: P parallel flip-flop chains, each flip-flop chain having an input and an output, wherein the input is coupled to the output of a combinational logic circuit for the parallel flip-flop chain, wherein the input of the combinational logic circuit for the parallel flip-flop chain is coupled to the outputs of different flip-flops of the P parallel flip-flop chains according to the exponent of an N-1 order primitive polynomial, wherein the flip-flops of the P parallel flip-flop chains are clocked by a second clock; wherein at each rising edge of the second clock, P LFSR outputs are generated from the output of the last flip-flop of each of the P parallel flip-flop chains, respectively.

[0012] The controller may be configured to, in the startup mode, reset all but one flip-flop in each of the parallel flip-flop chains, but set the one flip-flop in each of the parallel flip-flop chains that is not reset.

[0013] The multiplexer may have a single output and have inputs coupled to the outputs of the P parallel flip-flop chains, and the multiplexer is configured to pass different inputs to the single output depending on which of the N different output words is received at a select input of the multiplexer.

[0014] A flip-flop may have an input coupled to a single output of the multiplexer, and the flip-flop is clocked by a first clock such that the flip-flop transfers the current state of its input to its output on each pulse of the first clock, where the frequency of the first clock is P times the frequency of the second clock.

[0015] The counter may be clocked by a first clock and configured to output N different output words, wherein a different output word of the N different output words is generated at each pulse of the first clock, and the counter is configured to reset after each of the N different output words is output.

[0016] The combinational logic circuit may be an exclusive OR (XOR) circuit.

[0017] Also disclosed herein is an N-bit linear feedback shift register (LFSR), comprising: P parallel flip-flop chains, each flip-flop chain having an output; a counter clocked by a first clock and configured to output N different output words, wherein a different one of the N different output words is generated at each pulse of the first clock, and the counter is configured to reset after each of the N different output words is output; a multiplexer having a single output and having an input coupled to the outputs of the P parallel flip-flop chains, having a select input coupled to the counter to receive the N different output words from the counter, and the multiplexer being configured to pass different inputs to the single output depending on which of the N different output words is received from the counter; and a flip-flop having an input coupled to the single output of the multiplexer, the flip-flop being clocked by the first clock such that the flip-flop passes the current state of its input to its output at each pulse of the first clock. Each parallel flip-flop chain includes: a flip-flop chain clocked by a second clock, the second clock being equal to the first clock divided by P; and a combinational logic circuit for the parallel flip-flop chain, which receives outputs from selected flip-flops of other flip-flop chains in the P parallel flip-flop chains as inputs, wherein the combinational logic circuit for the parallel flip-flop chain provides its output as input to the first flip-flop chain for the parallel flip-flop chain.

[0018] The combinational logic circuit may be an exclusive OR (XOR) circuit.

[0019] The controller may be configured to, in the startup mode, reset all but one flip-flop in each of the parallel flip-flop chains and set the one flip-flop in each of the parallel flip-flop chains that is not reset. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a block diagram of a prior art linear feedback shift register (LFSR).

[0021] Figure 2 is a block diagram of the LFSR described in this paper.

[0022] Figure 3 It shows Figure 2 A generalized schematic block diagram of a parallel logic block.

[0023] Figure 4 It shows Figure 2 A schematic block diagram of a specific example of a parallel logic block.

[0024] Figure 5 is a graph showing the relationship between the high-speed clock FSTCLK and the low-speed clock CLK.

[0025] Figure 6 Comparison is made under the same input conditions. Figure 2 The output of the LFSR is Figure 1 A diagram of the output of an LFSR. DETAILED DESCRIPTION

[0026] The following disclosure enables one skilled in the art to make and use the subject matter disclosed herein. The general principles described herein can be applied to embodiments and applications other than those described in detail above without departing from the spirit and scope of the present disclosure. The present disclosure is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed or suggested herein.

[0027] Initial reference Figure 2 Disclosed herein is a linear feedback shift register (LFSR) 20. LFSR 20 is an N-bit LFSR comprised of parallel logic blocks 21-24 that provide outputs to output flip-flops 27 via multiplexer 25. Output flip-flops 27 are clocked by a fast or high-speed clock, FSTCLK, and parallel logic blocks 21-24 are each comprised of a chain of flip-flops clocked by a slow clock, CLK, which is equal to the fast clock, FSTCLK, divided by a divisor, P. The specific frequencies of FSTCLK and CLK depend on the technology used in the LFSR design.

[0028] With the numbers N and P now understood in more detail, the LFSR 20 includes P parallel logic blocks (illustrated as parallel logic blocks 21-24, referred to as parallel logic blocks 0 to P-1, where it is understood that there can be any number of P parallel logic blocks) interconnected with each other, and each parallel logic block provides an output to a multiplexer 25. As explained, each parallel logic block 21-24 is composed of a chain of flip-flops clocked by a slow clock CLK. Multiplexer 25 has a select input that receives an input from a counter 26 clocked by a high-speed clock FSTCLK. Counter 26 counts from 0 to P-1, providing its output to the select input of multiplexer 25 at each increment, and overflowing (thereby effectively resetting) once its count reaches P-1. The output of multiplexer 25 is fed to the input of a flip-flop 27, which, as described above, is clocked by the high-speed clock FSTCLK to provide the LFSR output bit stream as an output. Note that controller 28 generates set and reset signals for flip-flop 27 and all flip-flops within parallel logic blocks 21-24.

[0029] Now additional reference Figure 321 - 24. Each of parallel logic blocks 21 - 24 includes a plurality of flip-flops connected in a chain and indexed according to the expression D[x+yP], where x indicates to which parallel logic block the individual flip-flop belongs (so, x=0 indicates the flip-flop belongs to parallel logic block 21; x=1 indicates the flip-flop belongs to parallel logic block 22, and so on), where y indicates the position of the individual flip-flop in its respective parallel logic block (so, y=0 indicates the flip-flop is the first in its parallel logic block; y=1 indicates the flip-flop is the second in its parallel logic block, and so on), and where P indicates a divisor applied to the high-speed clock FSTCLK.

[0030] However, note that the value of y for the last flip-flop in each parallel logic block is equal to the smallest integer greater than or equal to (N-1-x) / P, remembering that N represents the number of bits in the LFSR 20. Mathematically, this is called the smallest integer function, and therefore, the value of y for the last flip-flop in each parallel logic block can be mathematically expressed as:

[0031]

[0032] Mathematically, this equation can be derived from the fact that the y value of the last flip-flop in each parallel logic block is greater than or equal to N-1. Therefore, we can derive the above equation as follows:

[0033] x+yP≥N-1 (2)

[0034] Rearranging this equation yields:

[0035]

[0036] Since y is an integer, the above equation (1) is obtained using the minimum integer function.

[0037] The input of each first flip-flop of each parallel logic block 21 to 24 is the output of the corresponding XOR circuit 31 to 34. The input of each XOR circuit 31 to 34 is as follows.

[0038] The inputs to the XOR circuit 31 of the parallel logic block 21 are the exponents of a primitive polynomial of order N-1. Primitive polynomials are well known to those skilled in the art and therefore need not be described in detail here, as one skilled in the art can calculate primitive polynomials of any order. To maintain the generality of this example, assume that the exponents of the primitive polynomial of order N-1 are i, j, and N-1. Therefore, the inputs to the XOR circuit 31 are the outputs of flip-flops D[N-1], D[i], and D[j], remembering that the indices (the numbers in parentheses after D) are calculated as described above. Therefore, any flip-flop with an index calculated to be equal to N-1, i, and j provides an output to the input of the XOR circuit 31. These flip-flops with the noted indices can be present in any of the parallel logic blocks 21-24.

[0039] For each successive parallel logic block, the index calculated for the immediately preceding parallel logic block is incremented by 1. Thus, since the indices calculated for the inputs to XOR circuit 31 are N-1, i, and j, the indices for the inputs to XOR circuit 32 are N, i+1, and j+1. Therefore, the outputs of flip-flops D[N], D[i+1], and D[j+1] are the inputs to XOR circuit 32.

[0040] Continuing from this, since the indices calculated for the inputs to XOR circuit 32 are N, i+1, and j+1, the indices for the inputs to XOR circuit 33 are N+1, i+2, and j+2. Therefore, the outputs of flip-flops D[N+1], D[i+2], and D[j+2] are the inputs to XOR circuit 33.

[0041] Similarly, since the indices calculated for the inputs to XOR circuit 33 are N+1, i+2, and j+2, the indices for the inputs to XOR circuit 34 are N+P-1 (since the last parallel logic block is the P-1 logic parallel logic block), i+P-1, and j+P-1. Therefore, the outputs of flip-flops D[N+P-1], D[i+P-1], and D[j+P-1] are the inputs to XOR circuit 34.

[0042] Those skilled in the art will appreciate that there may be any given number of primitive polynomials of order N-1. This means that for a LFSR 20 having a given number of bits N, there may be a plurality of possible different input combinations that may be provided to the P XOR circuit.

[0043] Figure 4An example is shown in . Here, N=25 and P=4. Therefore: the first parallel logic block 21 has flip-flops D[0], D[4], D[8], D

[12] , D

[16] , D

[20] , and D

[24] ; the second parallel logic block 22 has flip-flops D[1], D[5], D[9], D

[13] , D

[17] , D

[21] , and D

[25] ; the third parallel logic block 23 has flip-flops D[2], D[6], D

[10] , D

[14] , D

[18] , D

[22] , and D

[26] ; and the fourth parallel logic block 24 has flip-flops D[3], D[7], D

[11] , D

[15] , D

[19] , D

[23] , and D

[27] . The exponents of the 24th-order primitive polynomial used here are 24 and 21. Therefore: the input to XOR circuit 31 is the output of D

[21] and D

[24] ; the input to XOR circuit 32 is the output of D

[22] and D

[25] ; the input to XOR circuit 33 is the output of D

[23] and D

[26] ; and the input to XOR circuit 34 is the output of D

[24] and D

[27] .

[0044] The startup state of LFSR 20 will now be described. At the start of operation, in addition to the one flip-flop per parallel logic block set by controller 28, controller 28 may reset each flip-flop per parallel logic block by asserting a reset signal (which may be a logic low signal) to these flip-flops. Which flip-flops per parallel logic block are set may vary from iteration to iteration, with different flip-flop settings resulting in different LFSR output words. In some examples, at the start of operation, in addition to the two or more flip-flops per parallel logic block set by controller 28, controller 28 may reset these flip-flops by asserting a reset signal to each flip-flop per parallel logic block. Which flip-flop settings per parallel logic block may vary from iteration to iteration, with different flip-flop settings resulting in different LFSR output words.

[0045] As mentioned above, the slow clock CLK is a version of the high-speed clock FSTCLK divided by P. This can be Figure 5 As seen in FIG, where P=4, it can also be observed that the output completion of the N-bit LFSR output word occurs at each rising edge of the slow CLK (because different sub-words of the LFSR output word are output at each rising edge of the high-speed clock FSTCLK).

[0046] Given the same input states for the parallel logic blocks, the sample outputs are shown by Figure 2 The LFSR20 generates an N-bit LFSR output word that is composed of Figure 1 The LFSR 10 produces the same N-bit output word as the LDSR and can be Figure 6In the figure above, observe how the flip-flop is operated when the high-speed clock FSTCLK is used to generate the LFSR output value ( Figure 1 ), the first four LFSR output values generated are 105D7C4, 01D7C49, 1D7C490, and 0BC490F; Now, observe directly below it, when the low-speed clock CLK is used to operate the flip-flop ( Figure 2 ), these exact same values are produced. The difference is that for Figure 1 In the embodiment, the LFSR output value is generated at each rising edge of the high-speed clock FSTCLK, and for Figure 2 In the embodiment, four LFSR output values are generated in parallel at each rising edge of the low-speed clock CLK. Therefore, it can be considered that Figure 2 The embodiment has the Figure 1 The same throughput as the example, Figure 1 The embodiment will not erroneously operate in the case Figure 2 The embodiment can use the high-speed clock FSTCLK to compare Figure 1 The embodiment operates at a higher frequency. Therefore, Figure 2 The LFSR 20 is actually able to Figure 1 The LFSR 10 has higher throughput.

[0047] While the present invention has been described with respect to a limited number of embodiments, those skilled in the art having benefit of this disclosure will appreciate that other embodiments can be conceived without departing from the scope of the invention disclosed herein. Accordingly, the scope of the present disclosure is limited only by the appended claims.

Claims

1. An N-bit linear feedback shift register, comprising: P parallel flip-flop chains, each with an output; a counter circuit clocked by a first clock and configured to output N different output words, wherein a different one of the N different output words is generated at each pulse of the first clock, and the counter circuit is configured to reset once each of the N different output words has been output; a multiplexer having a single output and having an input coupled to the output of the P parallel flip-flop chains, the multiplexer having a select input coupled to the counter circuit to receive the N different output words from the counter circuit, and the multiplexer being configured to pass a different input to the single output depending on receipt of one of the N different output words from the counter circuit; as well as a flip-flop having an input coupled to the single output of the multiplexer, the flip-flop being clocked by the first clock such that the flip-flop transfers a current state of the input of the flip-flop to an output of the flip-flop on each pulse of the first clock; Each parallel trigger chain includes: a chain of flip-flops clocked by a second clock, the second clock being equal to the first clock divided by P, each flip-flop of the chain except for a last flip-flop of the chain having an index calculated as x+yP, wherein x represents one of the P parallel flip-flop chains to which the flip-flop chain belongs, and wherein y represents a position within the flip-flop chain occupied by the flip-flop, wherein the last flip-flop of the chain has an index calculated as x+yP, wherein y is equal to a smallest integer greater than or equal to (N-1-x) / P; as well as a combinational logic circuit for the parallel chain of flip-flops, receiving as input the outputs of those flip-flops of the chain of flip-flops of the parallel chain of flip-flops having an index equal to the exponent of a primitive polynomial of order N-1, wherein the combinational logic circuit for the parallel chain of flip-flops provides the output of the combinational logic circuit as input to a first flip-flop in the chain of flip-flops of the parallel chain of flip-flops.

2. The N-bit linear feedback shift register according to claim 1 , further comprising a controller, wherein the controller is configured to: in a startup mode, reset all flip-flops except one flip-flop in each of the parallel flip-flop chains, and set the one flip-flop in each of the parallel flip-flop chains that is not reset.

3. The N-bit linear feedback shift register according to claim 1, wherein the combinational logic circuit comprises an exclusive OR (XOR) logic circuit.

4. An N-bit linear feedback shift register, comprising: P parallel flip-flop chains, each having an output, wherein each parallel flip-flop chain comprises: a chain of flip-flops clocked by a second clock, the second clock being equal to the first clock divided by P, each flip-flop in the chain except for a last flip-flop in the chain having an index calculated as x+yP, where x represents one of the P parallel flip-flop chains to which the flip-flop chain belongs, and where y represents a position within the flip-flop chain occupied by the flip-flop, wherein the last flip-flop in the chain has an index calculated as x+yP, where y is equal to a smallest integer greater than or equal to (N-1-x) / P; and an exclusive-OR (XOR) circuit for the parallel chain of flip-flops that receives as inputs outputs of those flip-flops of the chain of flip-flops of the parallel chain of flip-flops that have indices equal to the exponent of the primitive polynomial of order N-1, wherein the exclusive-OR circuit for the parallel chain of flip-flops provides as input an output of the exclusive-OR circuit to a first flip-flop in the chain of flip-flops of the parallel chain of flip-flops; Wherein, at each rising edge of the second clock, P linear feedback shift register outputs are generated from the output of the last flip-flop of each of the P parallel flip-flop chains.

5. The N-bit linear feedback shift register according to claim 4 , further comprising a controller configured to: in a startup mode, reset all flip-flops except one flip-flop in each of the parallel flip-flop chains, but set the one flip-flop in each of the parallel flip-flop chains that is not reset.

6. The N-bit linear feedback shift register of claim 4 , further comprising a multiplexer having a single output, the multiplexer having inputs coupled to the outputs of the P parallel flip-flop chains, and the multiplexer being configured to pass different inputs to the single output depending on whether one of the N different output words is received at a select input of the multiplexer.

7. The N-bit linear feedback shift register of claim 6 , further comprising a flip-flop having an input coupled to the single output of the multiplexer, and the flip-flop being clocked by the first clock such that the flip-flop transfers a current state of the input of the flip-flop to an output of the flip-flop on each pulse of the first clock.

8. The N-bit linear feedback shift register of claim 6 , further comprising a counter circuit, the counter circuit being clocked by the first clock and configured to output the N different output words, wherein a different output word of the N different output words is generated at each pulse of the first clock, and the counter circuit being configured to reset once each of the N different output words has been output.

9. An N-bit linear feedback shift register, comprising: P parallel flip-flop chains, each having an input and an output, wherein the input is coupled to an output of a combinational logic circuit for the parallel flip-flop chain, wherein the input of the combinational logic circuit for the parallel flip-flop chain is coupled to an output of a flip-flop of the P parallel flip-flop chains having an index equal to an exponent of an N-1 order primitive polynomial, wherein the flip-flops of the P parallel flip-flop chains are clocked by a second clock; Wherein, at each rising edge of the second clock, P linear feedback shift register outputs are generated from the output of the last flip-flop of each flip-flop chain in the P parallel flip-flop chains.

10. The N-bit linear feedback shift register according to claim 9, further comprising a controller, wherein the controller is configured to: in a startup mode, reset all flip-flops except one flip-flop in each of the parallel flip-flop chains, but set the one flip-flop in each of the parallel flip-flop chains that is not reset.

11. The N-bit linear feedback shift register of claim 9 , further comprising a multiplexer having a single output, the multiplexer having inputs coupled to the outputs of the P parallel flip-flop chains, and the multiplexer being configured to pass different inputs to the single output depending on whether one of the N different output words is received at a select input of the multiplexer.

12. The N-bit linear feedback shift register of claim 11 , further comprising a flip-flop having an input coupled to the single output of the multiplexer, and the flip-flop being clocked by a first clock such that the flip-flop transfers a current state of the input of the flip-flop to an output of the flip-flop on each pulse of the first clock, wherein the first clock has a frequency that is P times the frequency of the second clock.

13. The N-bit linear feedback shift register of claim 11 , further comprising a counter circuit clocked by a first clock and configured to output the N different output words, wherein a different output word of the N different output words is generated at each pulse of the first clock, and the counter circuit is configured to reset once each of the N different output words has been output.

14. The N-bit linear feedback shift register according to claim 9, wherein the combinational logic circuit comprises an exclusive OR (XOR) circuit.

15. An N-bit linear feedback shift register, comprising: P parallel flip-flop chains, each with an output; a counter circuit clocked by a first clock and configured to output N different output words, wherein a different one of the N different output words is generated at each pulse of the first clock, and the counter circuit is configured to reset once each of the N different output words has been output; a multiplexer having a single output and having an input coupled to the output of the P parallel flip-flop chains, the multiplexer having a select input coupled to the counter to receive the N different output words from the counter circuit, and the multiplexer being configured to pass a different input to the single output depending on receipt of one of the N different output words from the counter circuit; as well as a flip-flop having an input coupled to the single output of the multiplexer, the flip-flop being clocked by the first clock such that the flip-flop transfers a current state of the input of the flip-flop to an output of the flip-flop on each pulse of the first clock; Each parallel trigger chain includes: a chain of flip-flops, clocked by a second clock, the second clock being equal to the first clock divided by P; as well as A combinational logic circuit for the parallel chain of flip-flops receives as input an output of a flip-flop having an index equal to an exponent of an N-1 order primitive polynomial from one of the P parallel chains of flip-flops, wherein the combinational logic circuit for the parallel chain of flip-flops provides as input an output of the combinational logic circuit to a first flip-flop in the chain of flip-flops in the parallel chain of flip-flops.

16. The N-bit linear feedback shift register of claim 15, wherein the combinational logic circuit comprises an exclusive OR (XOR) circuit.

17. The N-bit linear feedback shift register according to claim 15 , further comprising a controller configured to, in a startup mode, reset all flip-flops except one flip-flop in each of the parallel flip-flop chains and set the one flip-flop that is not reset in each of the parallel flip-flop chains.

18. An N-bit linear feedback shift register, comprising: a plurality of parallel flip-flop chains, each having an input and an output, wherein the input is coupled to an output of a combinational logic circuit for the parallel flip-flop chain, wherein the input of the combinational logic circuit for the parallel flip-flop chain is coupled to an output of a flip-flop of the parallel flip-flop chain having an index equal to the exponent of the primitive polynomial of order N-1 according to an exponent of a primitive polynomial, wherein the flip-flops of the parallel flip-flop chain are clocked by a second clock; Wherein, at each rising edge of the second clock, a linear feedback shift register output is generated from the output of the last flip-flop of each flip-flop chain of the parallel flip-flop chain.

19. The N-bit linear feedback shift register of claim 18 , further comprising a controller configured to, in a startup mode, reset all but one flip-flop in each of the parallel flip-flop chains but set the one flip-flop in each of the parallel flip-flop chains that is not reset.

20. The N-bit linear feedback shift register of claim 18 , further comprising a multiplexer having a single output, the multiplexer having an input coupled to the output of the parallel flip-flop chain, and the multiplexer being configured to pass different inputs to the single output depending on whether one of the different output words is received at a select input of the multiplexer.

21. The N-bit linear feedback shift register of claim 20 , further comprising a flip-flop having an input coupled to the single output of the multiplexer, and the flip-flop being clocked by a first clock such that the flip-flop transfers a current state of the input of the flip-flop to an output of the flip-flop on each pulse of the first clock, wherein the first clock has a frequency that is a multiple of a frequency of the second clock.

22. The N-bit linear feedback shift register of claim 20 , further comprising a counter circuit clocked by a first clock and configured to output the different output words, wherein a different one of the different output words is generated at each pulse of the first clock, and the counter circuit is configured to reset once each of the different output words has been output.

23. The N-bit linear feedback shift register of claim 19, wherein the combinational logic circuit comprises an exclusive OR (XOR) circuit.

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