Status register power outage protection

Abstract

This application relates to state register power interrupt protection. The disclosure provides techniques for improved restart of a system. In an example, a system can alternately store state register values or state to two or more non-volatile memory locations. After a power interrupt and restart, the values of the state register can be restored to a state very close or comparable to the last occurring state, even if a write operation to one of the non-volatile memory locations resulted in an inaccurate save of that state of the state register.

Description

TECHNICAL FIELD

[0001] Embodiments described herein generally relate to systems and methods for improving system restart after unexpected power interruption. BACKGROUND

[0002] Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory needs power to maintain its data and includes a variety of random access memory (RAM), such as static RAM (SRAM), dynamic random access memory (DRAM) or synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can retain stored data when not powered and can include one or more storage technologies, such as flash memory (e.g., NAND or NOR flash memory), electrically erasable programmable ROM (EEPROM), ferroelectric RAM (FeRAM), erasable programmable ROM (EPROM), resistive variable memory, such as phase change random access memory (PCRAM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM) or 3D XPoint memory, among others. TM Memory, among others.

[0003] Flash memory is used as non-volatile memory for a wide range of electronic applications. Flash memory devices typically include one or more groups of single transistor, floating gate or charge trap memory cells that allow for high memory density, high reliability and low power consumption. Two common types of flash memory array architectures include NAND and NOR architectures, named in logical form of the basic memory cell configuration for each architecture arranged. The memory cells of a memory array are typically arranged in a matrix. In an example, the gates of each floating gate memory cell in a row of the array are coupled to an access line (e.g., a word line). In a NOR architecture, the drains of each memory cell in a column of the array are coupled to a data line (e.g., a bit line). In a NAND architecture, the drains of each memory cell in a string of the array are coupled together in series (source to drain) between a source line and a bit line.

[0004] Reducing the amount of time required for a system to start from a power outage event can provide a significant advantage over competitors. Some delay between recovering power from a power interruption and providing the desired functionality of the system can be due to some portion of the system retrieving or evaluating the last state of the system and preparing the system functionality in view of the last known state. SUMMARY

[0005] In one aspect, the present application provides a system comprising: a status register configured to change value to track the progress of a process of the system; a first location within a non-volatile memory; a second location within the non-volatile memory; and a controller configured to perform an operation comprising saving a representation of the value of the status register in the first location or the second location, including saving a first representation of the first value of the status register in the first location in response to a change in the first value of the status register, and saving a second representation of the second value of the status register in the second location in response to a change in the second value of the status register.

[0006] On the other hand, the present application provides a method comprising: incrementing a register of a system based on an event of a first event type; copying the value of the register to a first non-volatile memory location in response to a first event of the first event type; copying the value of the register to a second non-volatile memory location in response to a second event of the first event type; interrupting power to the system; after restarting the system, determining the validity of the value of the first non-volatile memory location and the validity of the value of the second non-volatile memory location; and resetting the value of the register based on the validity of the values ​​of the first and second non-volatile memory locations. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the accompanying drawings, which are not necessarily drawn to scale, like numbers may describe similar components in different views. Like numbers with different letter suffixes may represent different instances of similar components. The accompanying drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0008] Figure 1 An example of an environment 100 including a host device 105 and a memory device 110 configured to communicate through a communication interface 111 is illustrated.

[0009] Figure 2 An example mechanism is described for ensuring reliable and accurate refreshing of system state values ​​following an unexpected power outage to the system.

[0010] Figure 3 An example method 300 of preserving the state of a status register in accordance with the present subject matter is generally described.

[0011] Figure 4 Generally speaking, restart includes the above Figures 1 to 3 Example methods of systems with status registers are discussed.

[0012] Figure 5A block diagram illustrating an example machine 500 upon which any one or more of the techniques (eg, methodologies) discussed herein may be performed. DETAILED DESCRIPTION

[0013] A memory device includes individual memory dies, which may, for example, include a storage area comprising one or more memory cell arrays implementing one (or more) selected storage technologies. Such a memory die will typically include support circuitry for operating the memory array. Other examples, sometimes often referred to as "managed memory devices," include an assembly of one or more memory dies associated with a memory controller functionality configured to control the operation of the one or more memory dies. This memory controller functionality can simplify interoperability with external devices, such as a "host" as discussed later herein, and further facilitate the management of (typically) multiple discrete memory devices. In such managed memory devices, the controller functionality can be implemented on one or more dies that are also incorporated into the memory array, or on a separate die. In other memory devices, one or more memory devices can be combined with the memory controller functionality to form a solid-state drive (SSD) storage volume.

[0014] Example embodiments of the present disclosure are described in the context of examples of non-volatile memory devices, such as flash memory devices (in NAND or NOR configurations) or ferroelectric RAM (FeRAM); and in assemblies, such as managed memory devices implementing NAND flash memory cells (referred to as "managed NAND" devices) or SSDs, both as discussed above. However, these examples do not limit the scope of the present disclosure, and the present disclosure may be implemented using memory devices implementing other memory storage technologies, such as the non-limiting examples previously discussed herein. Managed memory devices may be used as primary or secondary memory in various forms of electronic devices and are commonly used in mobile devices. FeRAM may use a similar device architecture to DRAM, but may have non-volatile properties due to the use of ferroelectric capacitors as the storage device. In some applications, FeRAM devices may have more flexible performance compared to other non-volatile and volatile memory devices.

[0015] Some non-volatile architecture semiconductor memory arrays can be programmed into two or more programmed states. For example, a single-level cell (SLC) can represent one of two programmed states (e.g., 1 or 0), which represents one bit of data. Flash memory cells can also represent more than two programmed states, allowing for the manufacture of higher density memories without increasing the number of memory cells, since each cell can represent more than one binary digit (e.g., more than one bit). Such cells may be referred to as multi-state memory cells, multi-digit cells, or multi-level cells (MLC). In some examples, MLC may refer to a memory cell that can store two bits of data per cell (e.g., one of four programmed states), TLC may refer to a memory cell that can store three bits of data per cell (e.g., one of eight programmed states), and QLC may store four bits of data per cell. MLC is used herein in its broader context to refer to any memory cell(s) that can store more than one bit of data per cell (i.e., they can represent more than two programmed states; thus, the term MLC is used herein in its broader context to refer generically to memory cells that store 2, 3, 4, or more bits of data per cell).

[0016] Various non-volatile memory devices may be configured and operated according to recognized industry standards. For example, a managed NAND device may be, as a non-limiting example, a Universal Flash (UFS) TM ) device, embedded MMC device (eMMC TM ), etc. For example, in the case of the above example, the UFS device may be configured according to a Joint Electronic Device Engineering Council (JEDEC) standard (e.g., JEDEC standard JESD223D entitled "JEDEC UFS Flash Memory 3.0," and / or an updated or subsequent version of this standard). Similarly, the identified eMMC device may be configured according to JEDEC standard JESD84-A51 entitled "JEDEC eMMC Standard 5.1," and / or an updated or subsequent version of this standard. The identified standards are provided merely as example environments in which the described methods and structures may be utilized, but such methods and structures may be utilized in a variety of environments outside of the identified standards (or any other actual or proposed standards), unless expressly indicated herein.

[0017] SSDs are particularly useful as primary storage devices for computers and offer advantages over traditional hard disk drives with moving parts in terms of, for example, performance, size, weight, ruggedness, operating temperature range, and power consumption. For example, SSDs can have reduced seek times, latency, or other delays relative to conventional magnetic disk drives. SSDs use non-volatile memory cells, such as flash memory cells, thus allowing the drives to be more versatile and compact.

[0018] Both SSDs and managed memory devices may include several memory devices, including several dies or logical units (e.g., logical unit numbers or LUNs), and typically a memory controller, including processing circuitry that will typically include one or more processors that perform logic functions to operate the memory devices or interface with external systems. Such SSDs and managed memory devices may include one or more flash memory dies that include several memory arrays and peripheral circuitry thereon. A flash memory array may include several blocks of memory cells organized into several physical pages or blocks. In some examples, an SSD may also include DRAM or SRAM (or other forms of memory dies or other memory structures), for example, as part of the controller. Similarly, a managed NAND device may include one or more volatile and / or non-volatile memory arrays separate from the NAND storage array and within or separate from the controller. Both SSDs and managed NAND devices can receive commands from the host associated with memory operations, such as read or write operations to transfer data (e.g., user data and associated integrity data, such as error data and address data, etc.) between the memory device and the host, or erase operations to erase data from one or more memory devices.

[0019] Figure 1 An example of an environment 100 is illustrated that includes a host device 105 and a memory device 110 configured to communicate via a communication interface 111. The host device 105 or the memory device 110 may be included in various products 150, such as Internet of Things (IoT) devices (e.g., refrigerators or other appliances, sensors, motors or actuators, mobile communication devices, automobiles, drones, etc.) to support processing, communication, or control of the product 150.

[0020] Memory device 110 includes a memory controller 115 and a memory array 120, which includes, for example, several individual memory dies (e.g., a stack of 3D NAND dies). In one example, memory device 110 may be a discrete memory or storage device component of host device 105. In other examples, memory device 110 may be part of an integrated circuit (e.g., a system on a chip (SOC)), stacked or otherwise included with one or more other components of host device 105. Each memory die may include a local controller 165 for controlling operations on the memory die. This local controller 165 may include processing circuitry for controlling the die, which may include processor(s). The control die may include a processor that implements the power-off protection functionality described herein. In other examples, the power-off protection functionality may be implemented in memory controller 115.

[0021] In the depicted example, memory device 110 communicates with host device 105 components via communication interface 111. Thus, as described herein, host or host device 105 operates distinct from memory device 110, even when memory device 110 is integrated into host device 105.

[0022] Various forms of communication interfaces may be used to transfer data between the memory device 110 and one or more other components of the host device 105, such as a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Universal Flash Storage (UFS) interface, an eMMC interface, or a SATA-based interface. TM interface or one or more other connectors or interfaces. Host device 105 may include a host system, an electronic device, a processor, a memory card reader, or one or more other electronic devices external to memory device 110. In some examples, host 105 may be a host computer with a reference Figure 5 The machine 500 may include some or all of the components discussed above.

[0023] The memory controller 115 may receive instructions from the host 105 and may communicate with the memory array 120, for example, to transfer (e.g., write) data to, read data from (e.g., erase) one or more of the memory cells, planes, sub-blocks, blocks, or pages of the memory array 120. For example, the memory controller 115 includes processing circuitry that may include one or more processors that, when present, operate to execute instructions stored in the memory device. For purposes of this example, the instructions will be discussed as firmware, although the instructions may also exist as software; and all or some portion of the described functionality may also be implemented in circuitry including one or more components or integrated circuits.

[0024] For example, the memory controller 115 may include one or more memory control units, circuits, or components configured to control access across the memory array 120 and provide a translation layer between the host 105 and the memory device 110. In addition, the memory controller may include a memory interface for interfacing with an associated memory device. In some examples, the memory interface may be an Open NAND Flash Interface (ONFI). Although the memory controller 115 is described herein as being part of the memory device 110 package, other configurations may be employed, such as the memory controller 115 being a component of the host 105 (e.g., being a discrete package on a system-on-chip of the host 105 that is separate from the memory device 110), or even being implemented via the host 105's central processing unit (CPU).

[0025] The memory manager 125 may include, among other things, a plurality of components or integrated circuits associated with various memory management functions and / or instructions for performing them. In some embodiments, the functions of the memory manager 125 are implemented by a controller (or processor) executing instructions of firmware, which in some instances will be stored within the memory controller 115. In other instances, the memory manager 125 may be implemented at least in part by one or more processors within the memory controller 115, which may execute instructions stored in the memory array 120. Similarly, management tables 130, such as mapping tables or logical block to physical address (L2P) tables, may be stored on the memory controller 115 or in the memory array 120. In such instances, the instructions and / or management tables 130 may be stored in certain blocks of the non-volatile memory die stack and loaded into the working memory of the memory controller 115 during operation.

[0026] For the purposes of this description, example memory operations and management functions may be described in the context of a particular form of memory architecture (e.g., ferromagnetic, NAND, etc.). Those skilled in the art will recognize that other forms of non-volatile memory may have similar memory operations or management functions. Such non-volatile management functions may include wear leveling, garbage collection, fatigue monitoring, reclamation, error detection or correction, block retirement, or one or more other memory management functions. Memory manager 125 may parse or format host commands (e.g., commands received from a host) into device commands (e.g., commands associated with operation of memory array 120, etc.), or generate device commands for array controller 135 or one or more other components of memory device 110 (e.g., to perform various memory management functions). Such internally generated operations, such as garbage collection, wear leveling, etc., may result in the ongoing operation providing an opportunity for power management operations as described herein in the same manner as externally directed memory operations.

[0027] The memory manager 125 may include a set of management tables 130 configured to maintain various information associated with one or more components of the memory device 110 (e.g., various information associated with a memory array or one or more memory cells coupled to the memory controller 115). For example, the management tables 130 may include information regarding block age, block erase count, error history, or one or more error counts (e.g., write operation error count, read bit error count, read operation error count, erase error count, etc.) for one or more blocks of memory cells coupled to the memory controller 115. In certain examples, a bit error may be referred to as an uncorrectable bit error if the number of detected errors in one or more of the error counts is above a threshold. The management tables 130 may, in particular, maintain counts of correctable or uncorrectable bit errors. In an example, the management tables 130 may include a translation table or a logical-to-physical (L2P) table, or a portion thereof.

[0028] The array controller 135 may further include, among other things, circuitry or components configured to control memory operations associated with writing data to, reading data from, or erasing one or more memory cells of the memory device 110 coupled to the memory controller 115. The memory operations may be based on host commands (e.g., associated with wear leveling, error detection or correction, etc.), for example, received from the host 105 or generated internally by the memory manager 125.

[0029] The array controller 135 may further include an error correction code (ECC) component 140, which may include, among other things, an ECC engine or other circuitry configured to detect or correct errors associated with writing data to or reading data from one or more memory cells of the memory device 110 coupled to the memory controller 115. The memory controller 115 may be configured to proactively detect and recover from error occurrences (e.g., bit errors, operational errors, etc.) associated with various operations or data storage based on the ECC data maintained by the array controller 135. This enables the memory controller 115 to maintain the integrity of data transferred between the host 105 and the memory device 110 or to maintain the integrity of stored data. Part of this integrity maintenance may include removing (e.g., retiring) failed memory resources (e.g., memory cells, memory arrays, pages, blocks, etc.) to prevent future errors.

[0030] The memory array 120 can include a number of memory cells arranged in, for example, devices, planes, sub-blocks, blocks, or pages. As one example, a 48 GB TLC NAND memory device can include 18,592 bytes (B) of data per page (16,384 + 2208 bytes), 1536 pages per block, 548 blocks per plane, and 4 or more planes per device. As another example, a 32 GB MLC memory device (storing two bits of data per cell (i.e., 4 programmable states)) can include 18,592 bytes (B) of data per page (16,384 + 2208 bytes), 1024 pages per block, 548 blocks per plane, and 4 planes per device, but the write time required is half that of the corresponding TLC memory device and the program / erase (P / E) cycles are twice that of the corresponding TLC memory device. Other examples can include other numbers or arrangements. In some examples, a memory device or a portion thereof can be selectively operated in SLC mode or in a desired MLC mode (e.g., TLC, QLC, etc.).

[0031] In operation, data is typically written to or read from the non-volatile memory device 110 in pages and erased in blocks. However, one or more memory operations (e.g., read, write, erase, etc.) can be performed on larger or smaller groups of memory cells as desired. The data transfer size of the non-volatile memory device 110 is typically referred to as a page, while the data transfer size of the host is typically referred to as a sector.

[0032] In some examples, a memory array can include a number of non-volatile memory dies and one or more functions of the memory controller 115 for a particular memory die can be implemented on-die on a die controller on that particular die. Other organizations and divisions of control functionality can also be utilized, such as one controller per die, plane, super-block, block, page, etc.

[0033] While a page of data can include a number of bytes of user data (e.g., a data payload including data for a number of sectors) and its corresponding metadata, the size of the page typically only refers to the number of bytes used to store user data. As an example, a page of data having a page size of 4 KB can include 4 KB of user data (e.g., 8 sectors having a sector size of 512 B) and a number of bytes (e.g., 32 B, 54 B, 224 B, etc.) of metadata corresponding to the user data, such as integrity data (e.g., error detection or correction code data), address data (e.g., logical address data, etc.), or other metadata associated with the user data.

[0034] Different types of memory cells or memory arrays 120 may provide different page sizes or may require different amounts of metadata associated therewith. For example, different memory device types may have different bit error rates, which may result in different amounts of metadata required to ensure the integrity of a data page (e.g., a memory device with a higher bit error rate may require more bytes of error correction code data than a memory device with a lower bit error rate). As an example, an MLC NAND flash memory device may have a higher bit error rate than a corresponding SLC NAND flash memory device. Thus, an MLC device may require more bytes of metadata for error data than a corresponding SLC device. In some examples, the memory array may include a complete mapping table or L2P table 161.

[0035] Figure 2 An example power-off protection mechanism 260 is illustrated for ensuring reliable and accurate refreshing of a status register 261 after an unexpected power outage to the overall system. The mechanism 260 may include a status register 261, a controller circuitry 262, and two or more non-volatile memory locations 263-1, 263-2, ..., 263-N. The control circuitry 262 may include a comparator 264, a flip evaluation circuit 265, a checksum generation circuit 266, a checksum verification circuit 267, and control logic 268. In some examples, the control circuitry 262 may be part of a non-volatile memory, such as part of a memory controller of a non-volatile memory device (e.g., Figure 1 , 161). In some examples, the control circuitry 262 may be implemented in a controller (e.g., Figure 1 , 115).

[0036] Status register 261 can be a volatile memory location within a larger system, within a nonvolatile memory system, or within a nonvolatile memory device. In an example, status register 261 can be a counter, such as one used to track a variable of a system or nonvolatile memory. Such a variable can include a counter for wear leveling, a counter for waste item collection, a counter for fatigue detection (e.g., a fatigue threshold) for FeRAM, or a status register used to track the progress of a process that can continue without having to be restarted if unexpectedly interrupted due to a power outage. Nonvolatile memory locations 263-1, 263-2, ..., 263-N can be used to store the value of status register 261 so that after a power outage and subsequent startup, status register 261 can be refreshed to the last known state before the power outage. The present inventors have recognized that even when the value of the status register is stored in nonvolatile memory, a power outage during the process of writing the value to the nonvolatile memory can disrupt the write process, thereby negating the benefit of storing the value of the status register. Thus, the present subject matter uses multiple non-volatile memory locations 263 - 1 , 263 - 2 , . . . , 263 -N to better ensure that one of the locations contains a valid, recent value for the status register 261 .

[0037] Control logic 268 can save the value of status register 261 to one of a plurality of non-volatile memory locations 263-1, 263-2, ..., 263-N and can refresh the value of status register 261 upon system restart. Control logic 268 can save the value of status register 261 to non-volatile locations 263-1, 263-2, ..., 263-N when the value changes or at regular intervals. Control logic 268 can save the current value of status register 261 to a non-volatile location 263-1, 263-2, ..., 263-N that is different from the last time the value of status register 261 was saved to non-volatile location 263-1, 263-2, ..., 263-N. This technique ensures that the most recent valid value of status register 261 is saved to non-volatile memory if the current save is interrupted or corrupted, such as due to an unexpected power outage.

[0038] After a system restart, control logic 268 can evaluate the contents of the multiple non-volatile memory locations 263-1, 263-2,..., 263-N to obtain the most recent value and can refresh the status register 261 with that value. For example, at a system restart that uses two non-volatile memory locations 263-1, 263-2 and a count-up counter as the status register 261, control circuitry 262 can include a comparator 264 to evaluate the values of the two memory locations 263-1, 263-2 and reset the status register 261 to the higher of the two stored values. If the system allows the counter / status register 261 to roll over, control circuitry 262 can include a rollover evaluation circuit 265 and control logic 268 can initiate the rollover evaluation circuit 265 to evaluate the values of the two non-volatile locations 263-1, 263-2 based on a particular rollover value and can refresh the counter / status register 261 with the later occurring value. In some examples that use a counter as the status register 261, after the accumulated count of the counter / status register 261 is refreshed, control logic 268 can cause the counter / status register 261 to increment.

[0039] When saving the value of the status register 261 to one of the non-volatile locations 263-1, 263-2,..., 263-N, a checksum generator circuit 266 can compute a checksum of the value of the status register 261. The checksum can be saved with the value of the status register 261. After a restart, the checksum can be used to indicate the validity of the value stored at each of the non-volatile memory locations 263-1, 263-2,..., 263-N. For example, after a restart, control logic 268 can initiate a checksum verification circuit 267 to separately compute a checksum of the value that is assumed to have been saved in the non-volatile memory location 263 to provide a retrieved checksum. The checksum verification circuit 267 can then compare the retrieved checksum to the checksum that is assumed to be stored at the non-volatile memory location 263. If the checksums match, the checksum verification circuit 267 can indicate to the control logic 268 that the value stored at that non-volatile memory location 263 is valid. If the checksums do not match, the checksum verification circuit 267 can indicate to the control logic 268 that the value stored at that non-volatile memory location 263 is invalid. An invalid checksum result can indicate that the value stored at that non-volatile memory location 263 was corrupted when the value was written to the non-volatile memory location 263.

[0040] Thus, after system startup, checksum verification circuit 267 may receive the value of each nonvolatile memory location 263-1, 263-2, ..., 263-N and the corresponding stored checksum. Checksum verification circuit 267 may calculate a new checksum for each value. The new checksum may be compared to the stored checksum, and checksum verification circuit 267 may provide an indication of the validity of each nonvolatile memory location 263-1, 263-2, ..., 263-N to control logic 268 of control circuitry 262. Upset evaluation circuit 265 of controller circuitry 262 may also receive the value of each nonvolatile memory location 263-1, 263-2, ..., 263-N and may pass upset information for each nonvolatile memory location 263-1, 263-2, ..., 263-N to control logic 268. Control logic 268 of controller circuitry 262 may receive the validity information and upset information and may pass a reset value to status register 261.

[0041] If only a single location in the plurality of nonvolatile memory locations 263-1, 263-2, ..., 263-N contains a value and a checksum indicating that the value is valid, then the control logic 268 may refresh the status register 261 with that valid value. In certain examples, such as when the status register 261 is a counter, the control logic 268 may increment the valid value and refresh the status register 261 with the incremented value. If the valid value is at a rolled-over value, then the control logic 268 may refresh the status register with the rolled-over value.

[0042] If more than one of the nonvolatile locations 263-1, 263-2, ..., 263-N includes a valid value (e.g., a value with an appropriately corresponding checksum), the values ​​may be compensated based on the rollover, the rollover compensation values ​​may be compared to determine the last valid value that occurred, and the control logic 268 may refresh the status register 261 with the last valid value that occurred. In some examples, such as when the status register 261 is a counter, the control logic 268 may increment the last valid value that occurred and refresh the status register 261 with the incremented value.

[0043] If none of the non-volatile memory locations can be verified as valid, then the control logic 268 may refresh the status register 261 with a predetermined default refresh value.

[0044] Figure 3An example method 300 for saving the state of a status register according to the present subject matter is generally described. At 301, the value of a status register may be retrieved or read. At 303, a checksum of the value of the status register may be determined. At 305, the register value and the checksum may be stored or programmed into a non-volatile memory location identified by an index or pointer. In some examples, the index or pointer may be initialized at system startup. At 307, the index may be incremented and rollover compensation may be performed, if necessary. In some examples, at least two non-volatile memory locations are used to save the state of the status register. Method 300 may be repeated continuously from 301. The method ensures that the state of the status register is saved in more than one non-volatile memory location. This method allows for efficient recovery from power outages even if a power outage occurs during programming of the non-volatile memory and corrupts the saved data. After power is restored, the last saved valid state may be verified by the checksum, and the status register may be refreshed with the verified data. Restarting the system may include a step of redoing the process that was in progress at the time of the power outage. If the state register is a counter, the refresh process may increment the last valid accumulated count to possibly avoid redoing previously completed tasks. In some examples, the method may not retrieve the next state of the state register until the state of the state register changes to a state different from the last saved state.

[0045] Figure 4 Generally speaking, restart includes the above Figures 1 to 3 At 401, the system including the status register may be restarted. At 403, data from a non-volatile memory location may be retrieved. The non-volatile memory location may be a location for storing information such as information about the status register. Figures 1 to 3 At least two or more nonvolatile memory locations may be checked for a valid value of a status register as discussed in the examples of FIG. At 405, a checksum of the value sensed from the first nonvolatile memory location may be verified to be valid or invalid. In some examples, the verification may include calculating a new checksum based on a value within the data received from the nonvolatile memory location and comparing the new checksum to the checksum of the data received from the nonvolatile memory location. If the checksums match, the value is valid. If the checksums do not match, the value is invalid. At 407, one or more additional nonvolatile memory locations may be checked for a valid value of the status register. At 409, a determination may be made as to whether any of the nonvolatile memory locations contains a valid status register value. If all values ​​for all relevant nonvolatile memory locations are invalid, at 411, the value of the status register may be set to a default value.

[0046] If one or more values ​​at the associated nonvolatile memory location are determined to be valid, then at 413, rollover compensation may be performed on each valid value, if necessary. For example, if the state register is an up-counter and the up-counter rolls over to zero at a specified cumulative count, then a valid value of zero may actually represent the specified cumulative count. Rollover compensation may track rollover values ​​to determine which of the valid values ​​represents the last-occurring state of the state register. At 415, the valid values, including the rollover-compensated valid values, may be compared to determine which valid value represents the last known or last-occurring state of the state register. For example, if the state register is an up-counter, then the last value of the last-occurring state may be the highest rollover compensation value. In some examples, the last-occurring value may be determined by comparing the rollover compensation value to a lookup table indicating a sequence of state register values.

[0047] At 417, the status register may be set to the value represented by the last-occurred value determined at 415. In some instances, the last-occurred value may not have been subjected to a compensating rollover before being written to the status register. At 419, the status register may optionally be incremented to the next sequential value. Incrementing the status register may be performed on systems where one of the values ​​in the associated non-volatile memory location is corrupted or invalid. This corruption may indicate a power outage that occurred when the next state of the status register was programmed into the non-volatile memory location.

[0048] Figure 5 A block diagram illustrating an example machine 500 on which any one or more of the techniques (e.g., methodologies) discussed herein may be performed. For example, any of the memory systems within the machine 500 (main memory 504, static memory 506, and mass storage 521) may implement a method as described herein with respect to Figures 1 to 4The discussed improves memory access command execution. In alternative embodiments, machine 500 can operate as a standalone device or can be connected (e.g., networked) to other machines. In a networked deployment, the machine 500 can operate in the capacity of a server machine, a client machine, or both in server-client network environments. In an example, the machine 500 can act as a peer machine in peer-to-peer (P2P) (or other distributed) network environment. The machine 500 can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile telephone, a web appliance, an IoT device, an automotive system, or any machine capable of executing instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein, such as cloud computing, software as a service (SaaS), other computer cluster configurations.

[0049] As described herein, examples can include, or can operate by, logic, a component, device, package, or mechanism in which a set (e.g., a group) of operations are performed. A circuit system is a collection (e.g., set) of circuits implemented in tangible entities that include hardware (e.g., simple circuits, gates, logic, etc.). Circuit system membership can change over time as hardware is removed, added, and / or modified, e.g., often with the addition of new hardware in response to changing user demand. Circuit system(s) include members that may, alone or in combination, perform specified tasks when operating in a circuit system context. In an example, hardware of the circuit system can be immutably designed to carry out a specific operation (e.g., hardwired). In an example, the hardware of the circuit system can include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) including a physical machine-readable medium with instructions to modify the physical arrangement and / or activation state of the physical component members (e.g., conesponding to a set of logic gates for a finite state machine). Such physical components can be

[0050] A machine (e.g., a computer system) 500 (e.g., host device 105, memory device 110, etc.) may include a hardware processor 502 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof, such as memory controller 115, etc.), a main memory 504, and a static memory 506, some or all of which may communicate with each other via an interconnection link (e.g., a bus) 530. The machine 500 may further include a display unit 510, an alphanumeric input device 512 (e.g., a keyboard), and a user interface (UI) navigation device 514 (e.g., a mouse). In an example, the display unit 510, the input device 512, and the UI navigation device 514 may be a touch screen display. The machine 500 may also include a mass storage device (e.g., a drive unit) 508, a signal generating device 518 (e.g., a speaker), a network interface device 520, and one or more sensors 516, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors. The machine 500 may include an output controller 528, such as a serial (e.g., Universal Serial Bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0051] The mass storage device 508 may include a machine-readable medium 522 having stored thereon one or more sets of data structures or instructions 524 (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. The instructions 524 may also reside, completely or at least partially, within the main memory 504, static storage 506, or the hardware processor 502 during execution by the machine 500. In an example, one or any combination of the hardware processor 502, the main memory 504, the static storage 506, or the storage device 508 may constitute the machine-readable medium 522.

[0052] Although machine-readable medium 522 is illustrated as a single medium, the term "machine-readable medium" may include a single medium or multiple media (eg, a centralized or distributed database, or associated caches and servers) configured to store one or more instructions 524.

[0053] The term "machine-readable medium" may include any medium capable of storing, encoding, or carrying instructions for execution by machine 500 and causing machine 500 to perform any one or more of the techniques of this disclosure, or capable of storing, encoding, or carrying data structures used by or associated with such instructions. Non-limiting examples of machine-readable media include solid-state memory, and optical and magnetic media. In an example, aggregate machine-readable media includes a machine-readable medium with a plurality of particles having a constant (e.g., stationary) mass. Thus, aggregate machine-readable media is not a transitory propagating signal. Specific examples of aggregate machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)), and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0054] Instructions 524 (e.g., software, programs, operating system (OS), etc.) or other data are stored on storage device 521 and can be accessed by memory 504 for use by processor 502. Memory 504 (e.g., DRAM) is typically fast but volatile, and therefore, unlike storage devices 521 (e.g., SSDs), which are suitable for long-term storage, including when in an "off" state. Instructions 524 or data used by a user or machine 500 are typically loaded into memory 504 for use by processor 502. When memory 504 is full, virtual space from storage device 521 can be allocated to supplement memory 504. However, because storage device 521 is typically slower than memory 504, with write speeds typically at most half the read speed, the use of virtual memory significantly reduces the user experience due to storage device latency (compared to memory 504, such as DRAM). Furthermore, using storage device 521 for virtual memory can significantly reduce the useful life of storage device 521.

[0055] Compared to virtual memory, virtual memory compression (e.g. A kernel feature ("ZRAM") uses portions of memory as compressed block storage to avoid paging to storage 521. Paging occurs in compressed blocks until the data must be written to storage 521. Virtual memory compression increases the available size of memory 504 while reducing the wear and tear on storage 521.

[0056] Storage devices optimized for mobile electronic devices or mobile storage devices traditionally include MMC solid-state storage devices (e.g., micro Secure Digital (microSD) TM) card, etc.). An MMC device includes several parallel interfaces (e.g., 8-bit parallel interfaces) with a host device and is typically a removable component that is separate from the host device. In contrast, an eMMC TM The device is attached to the circuit board and is considered a component of the host device, and its read speed can be comparable to that of Serial ATA-based TM The speed of SSDs is comparable to that of SSDs based on Serial AT (Advanced Technology) Attachment (SATA). However, the demand for performance in mobile devices continues to increase, for example to fully enable virtual or augmented reality devices and take advantage of increasing network speeds. In response to this demand, storage devices have transitioned from parallel to serial communication interfaces. Universal Flash Storage (UFS) devices, including controllers and firmware, communicate with host devices using a low-voltage differential signaling (LVDS) serial interface with dedicated read / write paths, further improving read / write speeds.

[0057] The instructions 524 may further be transmitted or received over a communication network 526 using a transmission medium via a network interface device 520 that utilizes any of a number of transmission protocols, such as frame relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc. Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), a mobile telephone network (e.g., a cellular network), a plain old telephone (POTS) network, and a wireless data network (e.g., the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series of standards, known as IEEE 802.16 series of standards, known as IEEE 802.15.4 family of standards), peer-to-peer (P2P) networks, and the like. In an example, network interface device 520 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connecting to communications network 526. In an example, network interface device 520 may include multiple antennas for wireless communication using at least one of single-input, multiple-output (SIMO), multiple-input, multiple-output (MIMO), or multiple-input, single-output (MISO) technology. The term "transmission media" should be understood to include any intangible medium capable of storing, encoding, or carrying instructions for execution by machine 500, including digital or analog communication signals or other intangible media used to facilitate communication of such software.

[0058] Additional examples:

[0059] In a first example, Example 1 is a system that may include: a status register configured to change value to track the progress of a process of the system; a first location within a non-volatile memory; a second location within the non-volatile memory; and a controller configured to perform an operation, the operation including saving a representation of the value of the status register in the first location or the second location, including: in response to a change in the first value of the status register, saving a first representation of the first value of the status register in the first location; and in response to a change in the second value of the status register, saving a second representation of the second value of the status register in the second location.

[0060] In Example 2, the subject matter of Example 1 includes, wherein the controller is configured to restore the status register with the value of the first location or the value of the second location in response to startup of the system.

[0061] In example 3, the subject matter of examples 1-2 includes, wherein the first representation includes a first checksum based on the first value of the status register.

[0062] In example 4, the subject matter of examples 1-3 includes, wherein the second representation includes a second checksum based on the second value of the status register.

[0063] In Example 5, the subject matter of Examples 1-4 includes, wherein in response to startup of the system, the controller is configured to determine whether a third representation within the first location includes a first valid value for the status register based on a third checksum within the third representation.

[0064] In Example 6, the subject matter of Example 5 includes, wherein in response to startup of the system, the controller is configured to determine whether a fourth representation within the second location includes a second valid value for the status register based on a fourth checksum within the fourth representation within the second location.

[0065] In Example 7, the subject matter of Example 6 includes, wherein in response to a determination that the third representation and the fourth representation include valid values ​​for the status register, the controller is configured to determine whether the third representation or the fourth representation is a most recently saved representation of the status register and to restore the status register with a value corresponding to the most recently saved representation.

[0066] In Example 8, the subject matter of Examples 6-7 includes, wherein in response to a determination that only one of the third representation or the fourth representation includes a valid value for the status register, the controller is configured to restore the status register with a value corresponding to an immediately sequential valid value based on the valid value.

[0067] In Example 9, the subject matter from Examples 6-8 includes, wherein in response to a determination that neither the third representation nor the fourth representation includes a valid value of the status register, the controller is configured to restore the status register with a value corresponding to a predetermined default value.

[0068] In Example 10, the subject matter from Examples 1-9 includes, wherein the status register is an accumulation register of a counter.

[0069] In Example 11, the subject matter from Example 10 includes, wherein the accumulation counter tracks a characteristic of the non-volatile memory.

[0070] In Example 12, the subject matter from Examples 10-11 includes, wherein the accumulation counter tracks wear leveling statistics of non-volatile memory including the first location and the second location.

[0071] In Example 13, the subject matter from Examples 1-12 includes, wherein the non-volatile memory includes ferroelectric random access memory (FeRAM).

[0072] Example 14 is a method comprising: incrementing a register of a system based on an event of a first event type; copying a value of the register to a first non-volatile memory location in response to a first event of the first event type; copying the value of the register to a second non-volatile memory location in response to a second event of the first event type; interrupting power to the system; after restarting the system, determining a validity of the value of the first non-volatile memory location and a validity of the value of the second non-volatile memory location; and resetting the value of the register based on the validity of the values of the first and second non-volatile memory locations.

[0073] In Example 15, the subject matter from Example 14 includes, wherein the copying the value of the register to the first non-volatile memory location includes determining a first checksum based on the value.

[0074] In Example 16, the subject matter from Example 15 includes, wherein the copying the value of the register to the first non-volatile memory location includes storing the first checksum in non-volatile memory.

[0075] In Example 17, the subject matter from Examples 15-16 includes, wherein the copying the value of the register to the first non-volatile memory location includes storing the first checksum with the value in a first non-volatile memory location.

[0076] In Example 18, the subject matter of Examples 15-17 includes, wherein the determining the validity of the value of the first nonvolatile memory location includes determining a second checksum based on the value of the first nonvolatile memory location and comparing the second checksum to the first checksum.

[0077] In Example 19, the subject matter of Example 18 includes, wherein the value of the first nonvolatile memory location is determined to be valid in response to the second checksum matching the first checksum.

[0078] In Example 20, the subject matter of Examples 14-19 includes, wherein the determining the validity includes: determining whether the value of the first nonvolatile memory is valid based on a first checksum, and determining whether the value of the second nonvolatile memory is valid based on a second checksum; and wherein the resetting includes resetting the value of the register with a later-occurring incremented value of the register of the system, wherein the later-occurring value is the value of the first nonvolatile memory location or the value of the second nonvolatile memory location.

[0079] In example 21, the subject matter of examples 14-20 includes, wherein the determining the validity includes: determining that the value of the first nonvolatile memory is valid based on a first checksum, and determining that the value of the second nonvolatile memory is invalid based on a second checksum; and wherein the resetting includes resetting the value of the register with the value of the first nonvolatile memory location.

[0080] In Example 22, the subject matter of Examples 14-21 includes, wherein the determining the validity includes: determining that the value of the first nonvolatile memory is invalid based on a first checksum, and determining that the value of the second nonvolatile memory is invalid based on a second checksum; and wherein the resetting includes resetting the value of the register with a default value.

[0081] In example 23, the subject matter of examples 14-22 includes wherein the register of the system is a fatigue threshold register for a nonvolatile memory device including the first nonvolatile memory location and the second nonvolatile memory location.

[0082] In example 24, the subject matter of examples 14-23 includes wherein one of the first nonvolatile memory location or the second nonvolatile memory location is a ferroelectric random access memory (FeRAM) location.

[0083] Example 25 is at least one machine-readable medium comprising instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations to implement any of Examples 1-24.

[0084] Example 26 is an apparatus comprising components for implementing any of Examples 1-24.

[0085] Example 27 is a system for implementing any one of Examples 1 to 24.

[0086] Example 28 is a method for implementing any one of Examples 1 to 24.

[0087] The above detailed description includes reference to the accompanying drawings, which form a part of the detailed description. The accompanying drawings show, by way of illustration, specific embodiments in which the present invention may be practiced. These embodiments are also referred to herein as "examples." Such examples may include elements other than those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. In addition, the present inventors also contemplate examples using any combination or arrangement of those elements (or one or more aspects thereof) shown or described with respect to a specific example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0088] In this document, as is common in patent literature, the terms "a / an" are used to include one or more than one, independent of any other examples or usages of "at least one" or "one or more". In this document, unless otherwise indicated, the term "or" is used to refer to a non-exclusive or, such that "A or B" may include "A but not B", "B but not A", and "A and B". In the appended claims, the terms "including" and "in which" are used as the plain English equivalents of the corresponding terms "comprising" and "wherein". Moreover, in the appended claims, the terms "including" and "comprising" are open-ended, that is, a system, device, object, or process that includes elements other than those listed after the term in the claim is still deemed to fall within the scope of that claim. In addition, in the appended claims, the terms "first", "second", and "third", etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0089] In various examples, the components, controllers, processors, units, engines, or tables described herein may include, among other things, physical circuitry or firmware stored on a physical device. As used herein, "processor" refers to any type of computing circuitry, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuitry, including groups of processors or multi-core devices.

[0090] As used in this document, the term "horizontal" is defined as a plane parallel to a conventional plane or surface of a substrate, such as the plane underlying a wafer or die, regardless of the actual orientation of the substrate at any point in time. The term "vertical" refers to a direction perpendicular to the horizontal plane as defined above. Prepositions such as "on," "above," and "below" are defined relative to a conventional plane or surface on the top or exposed surface of a substrate, regardless of the orientation of the substrate; while "on" is intended to imply direct contact of one structure relative to another structure that it is "above" (in the absence of an explicit indication to the contrary); the terms "above" and "below" are expressly intended to identify the relative positions of structures (or layers, features, etc.), which expressly includes—but is not limited to—direct contact between the identified structures unless specifically identified as such. Similarly, the terms "above" and "below" are not limited to a horizontal orientation, as a structure may be "above" a referenced structure if it is the outermost portion of the structure being discussed at a certain point in time, even if such structure extends vertically rather than horizontally relative to the referenced structure.

[0091] The terms "wafer" and "substrate" are used herein to generally refer to any structure on which an integrated circuit is formed, and to refer to such a structure during the various stages of integrated circuit fabrication. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the various embodiments is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0092] Various embodiments according to the present disclosure and described herein include memories utilizing a vertical structure of memory cells (e.g., a NAND string of memory cells). As used herein, directional adjectives are to be understood relative to the surface of the substrate on which the memory cells are formed (i.e., a vertical structure is to be considered to extend away from the substrate surface, a bottom end of the vertical structure is to be considered to be the end closest to the substrate surface, and a top end of the vertical structure is to be considered to be the end farthest from the substrate surface).

[0093] As used herein, directional adjectives such as horizontal, vertical, normal, parallel, perpendicular, etc. may refer to relative orientations and are not intended to require strict adherence to specific geometric properties unless otherwise indicated. For example, as used herein, a vertical structure need not be strictly perpendicular to the surface of the substrate, but may instead be substantially perpendicular to the surface of the substrate and may form an acute angle (e.g., between 60 and 120 degrees, etc.) with the surface of the substrate.

[0094] As used herein, operating a memory cell includes reading from the memory cell, writing to the memory cell, or erasing the memory cell. The operation of placing a memory cell in a desired state is referred to herein as "programming" and can include both writing to the memory cell and erasing from the memory cell (e.g., a memory cell can be programmed to an erased state).

[0095] According to one or more embodiments of the present disclosure, a memory controller (e.g., a processor, controller, firmware, etc.) located inside or outside a memory device is capable of determining (e.g., selecting, setting, adjusting, calculating, changing, clearing, communicating, adapting, deriving, defining, utilizing, modifying, applying, etc.) a certain number of wear cycles or wear states (e.g., recording wear cycles, counting operations of the memory device as they occur, tracking the operations of the memory device from which they originate, evaluating memory device characteristics corresponding to the wear states, etc.).

[0096] According to one or more embodiments of the present disclosure, a memory access device may be configured to provide wear cycle information to a memory device with each memory operation. Memory device control circuitry (e.g., control logic) may be programmed to compensate for memory device performance variations corresponding to the wear cycle information. The memory device may receive the wear cycle information and determine one or more operating parameters (e.g., values, characteristics) in response to the wear cycle information.

[0097] It will be understood that when an element is referred to as being "on," "connected to," or "coupled to" another element, it can be directly on, connected to, or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements or layers present. If two elements are shown in a drawing as having a line connecting them, the two elements may be coupled or directly coupled unless otherwise indicated.

[0098] The method examples described herein may be at least partially machine or computer implemented. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform the methods described in the above examples. Implementations of such methods may include code, such as microcode, assembly language code, high-level language code, etc. This code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. In addition, the code may be tangibly stored on one or more volatile or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, a hard disk, a removable magnetic disk, a removable optical disk (e.g., an optical disk and a digital video disk), a magnetic tape cartridge, a memory card or stick, random access memory (RAM), read-only memory (ROM), a solid-state drive (SSD), a universal flash storage (UFS) device, an embedded MMC (eMMC) device, etc.

[0099] The above description is intended to be illustrative and non-restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. After reviewing the above description, for example, a person of ordinary skill in the art may use other embodiments. The above description should be submitted with the understanding that the above description will not be used to interpret or limit the scope or meaning of the claims. Moreover, in the above detailed description, various features may be grouped together to simplify the present disclosure. This should not be interpreted as unclaimed disclosed features being intended to be essential to any claim. Rather, the subject matter of the invention may be less than all the features of a particular disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim is independently a separate embodiment, and it is considered that such embodiments can be combined with each other in various combinations or arrangements. The scope of the present invention should be determined with reference to the appended claims together with the full scope of equivalents to which these claims are given.

Claims

1. A system for improving system restart, comprising: a status register configured to change a value to track the progress of a process of the system; a first location in the non-volatile memory; a second location within the non-volatile memory; and A controller configured to perform operations comprising: Saving a representation of the value of the status register in the first location or the second location comprises: In response to a change in a first value of the status register, saving a first representation of the first value of the status register in the first location, and In response to a change in a second value of the status register, saving a second representation of the second value of the status register in the second location; In response to a subsequent startup of the system: determining the validity of the value read from the first location and the validity of the value read from the second location by comparing the respective stored checksums with corresponding new checksums based on the value read from the first location or the second location; as well as The value of the status register is reset based on the validity of the values ​​of the first location and the second location. 2 . The system of claim 1 , wherein the first representation comprises a first checksum based on the first value of the status register. 3 . The system of claim 1 , wherein the second representation comprises a second checksum based on the second value of the status register. 4 . The system of claim 1 , wherein determining the validity of the value read from the first location comprises comparing a stored checksum of the first representation to a second checksum of the value read from the first location. 5 . The system of claim 4 , wherein determining the validity of the value read from the second location comprises comparing a second stored checksum of the second representation to a third checksum of the value read from the second location. 6 . The system of claim 5 , wherein in response to determining that both values ​​are valid values, resetting the value of the status register comprises resetting the value of the status register to a most recently saved value between the values ​​of the first location and the second location.

7. The system of claim 5, wherein in response to determining that only one of the value read from the first location and the value read from the second location is a valid value, resetting the value of the status register comprises resetting the value of the status register to the valid value.

8. The system of claim 5, wherein in response to determining that neither the value read from the first location nor the value read from the second location is a valid value, resetting the value of the status register to a predetermined default value.

9. The system of claim 1, wherein the status register is an accumulation register of a counter.

10. The system of claim 9, wherein the accumulator register tracks a characteristic of the non-volatile memory.

11. The system of claim 9, wherein the accumulator register tracks wear leveling statistics for a non-volatile memory comprising the first location and the second location.

12. The system of claim 1, wherein the non-volatile memory comprises ferroelectric random access memory (FeRAM).

13. A method for improving system restart, comprising: incrementing a register of the system based on an event of the first event type; copying the value of the register to a first non-volatile memory location in response to a first event of the first event type; copying the value of the register to a second non-volatile memory location in response to a second event of the first event type; interrupting power to said system; determining, after restarting the system, the validity of the value at the first non-volatile memory location and the validity of the value at the second non-volatile memory location by comparing the respective stored checksums to corresponding new checksums based on the value at the first non-volatile memory location or the second non-volatile memory location; and The value of the register is reset based on the validity of the values ​​of the first and second nonvolatile memory locations.

14. The method of claim 13, wherein the copying the value of the register to the first non-volatile memory location comprises determining a first checksum based on the value.

15. The method of claim 14, wherein the copying the value of the register to the first non-volatile memory location comprises storing the first checksum in non-volatile memory.

16. The method of claim 14, wherein the copying the value of the register to the first non-volatile memory location comprises storing the first checksum with the value in a first non-volatile memory location.

17. The method of claim 14, wherein the determining the validity of the value of the first nonvolatile memory location comprises determining a second checksum based on the value of the first nonvolatile memory location and comparing the second checksum to the first checksum.

18. The method of claim 17, wherein the value of the first non-volatile memory location is determined to be valid in response to the second checksum matching the first checksum.

19. The method of claim 13, wherein said determining said validity comprises: determining whether the value of the first nonvolatile memory location is valid based on a first checksum, and determining whether the value of the second nonvolatile memory location is valid based on a second checksum; and wherein the resetting comprises resetting the value of the register of the system with a later occurring incremented value of the register, wherein the later occurring value is the value of the first non-volatile memory location or the value of the second non-volatile memory location.

20. The method of claim 13, wherein said determining said validity comprises: determining that the value at the first non-volatile memory location is valid based on a first checksum, and determining, based on a second checksum, that the value at the second non-volatile memory location is invalid; and Wherein the resetting comprises resetting the value of the register with the value of the first non-volatile memory location.

21. The method of claim 13, wherein said determining said validity comprises: determining that the value at the first non-volatile memory location is invalid based on a first checksum, and determining, based on a second checksum, that the value at the second non-volatile memory location is invalid; and wherein the resetting comprises resetting the value of the register with a default value.

22. The method of claim 13, wherein the register of the system is a fatigue threshold register for a nonvolatile memory device including the first nonvolatile memory location and the second nonvolatile memory location.

23. The method of claim 13, wherein one of the first nonvolatile memory location or the second nonvolatile memory location is a ferroelectric random access memory (FeRAM) location.

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