Method for determining physical address and chip system

Abstract

The present application provides a method for determining a physical address and a chip system, which relates to the field of operating systems. The method includes: when obtaining a first virtual address in a first virtual address space, determining a first table entry index address corresponding to the first virtual address; and determining a first target physical address corresponding to the first virtual address from a first page table according to the first table entry index address. The second table entry index address corresponding to the starting virtual address of the first virtual address space is greater than or equal to the base address of the first page table and less than the sum of the quotient of the starting virtual address divided by the size of the second virtual address space and the base address of the first page table. The maximum table entry index address of the first page table is less than the sum of the quotient of the maximum virtual address of the first virtual address space divided by the size of the second virtual address space and the base address of the first page table. The second virtual address space is associated with any table entry in the first page table. The technical solution provided by the present application can save the memory occupied by the page table and improve the memory utilization rate.

Description

Technical Field

[0001] This application relates to the field of operating systems, and in particular, to a method for determining a physical address and a chip system. Background Art

[0002] A chip system in an electronic device usually includes a central processing unit (CPU), a memory, and a coprocessor. The CPU accesses the memory during operation to obtain or store data, and the coprocessor is used to perform operations that the CPU cannot or does not need to perform. Currently, the access address for the CPU to access the memory is a virtual address, and a memory management unit (MMU) in the coprocessor can convert this virtual address into a corresponding physical address. Therefore, how to determine the physical address has also attracted more and more extensive attention.

[0003] In the prior art, when the MMU receives a virtual address access request from the CPU for a certain virtual address space, the MMU can obtain a first-level page table corresponding to the virtual address space from the memory. The first-level page table includes multiple table entries, and each table entry includes the association relationship between the table entry index address and the physical address. The MMU obtains the corresponding table entry index address from the first-level page table based on the virtual address, and then determines the physical address corresponding to the virtual address from the first-level page table based on the table entry index address.

[0004] However, since the starting virtual address of the virtual address space may not start from 0, and the table entries included in the first-level page table are usually allocated according to the virtual address from 0 to the maximum virtual address of the virtual address space, the number of table entries in the first-level page table is greater than the number of table entries actually required by the virtual address space. The table entries with lower addresses in the first-level page table will not be utilized, and the memory space occupied by these table entries will be wasted, resulting in low memory utilization. Summary of the Invention

[0005] In view of this, this application provides a method for determining a physical address and a chip system to save the memory occupied by the page table and improve memory utilization.

[0006] To achieve the above object, a first aspect provides a method for determining a physical address, including: when obtaining a first virtual address in a first virtual address space, determining a first table entry index address corresponding to the first virtual address; according to the first table entry index address, determining a first target physical address corresponding to the first virtual address from a first page table; wherein, the first page table is used to determine the physical address corresponding to each virtual address in the first virtual address space, the starting virtual address of the first virtual address space corresponds to a second table entry index address in the first page table, the second table entry index address is greater than or equal to the base address of the first page table and less than the sum of the quotient of the starting virtual address divided by the size of a second virtual address space and the base address of the first page table, the maximum table entry index address of the first page table is less than the sum of the quotient of the maximum virtual address of the first virtual address space divided by the size of the second virtual address space and the base address of the first page table, and the second virtual address space is a virtual address space associated with any table entry in the first page table, that is, the second virtual address space may be a subset of the first virtual address space.

[0007] It should be noted that a page table is a special data structure stored in memory. The page table can be used as an index for a virtual address space and may include multiple table entries. Each table entry includes the association relationship between the table entry index address and the physical address. Among them, the physical address can be carried in the page table descriptor of the table entry, and the page table descriptor can be used to indicate the base address of the next-level page table or the base address of the physical address corresponding to the virtual address.

[0008] In the embodiment of the present application, when the MMU obtains a first virtual address in a first virtual address space, it can determine a first table entry index address corresponding to the first virtual address in the first page table, and according to the first table entry index address, determine a first target physical address corresponding to the first virtual address from the first page table. Since the first page table can be used to determine the physical address corresponding to each virtual address in the first virtual address space, the starting virtual address of the first virtual address space corresponds to a second table entry index address in the first page table, the second table entry index address is greater than or equal to the base address of the first page table and less than the sum of the quotient of the starting virtual address divided by the size of the second virtual address space and the base address of the first page table, the maximum table entry index address of the first page table is less than the sum of the quotient of the maximum virtual address of the first virtual address space divided by the size of the second virtual address space and the base address of the first page table, and the second virtual address space is a virtual address space associated with any table entry in the first page table, the first page table can at least only include the table entries actually required by the first virtual address space, thereby saving memory and improving the utilization rate of memory.

[0009] Optionally, it can be obtained in advance (for example, before determining the first table entry index address corresponding to the first virtual address when obtaining the first virtual address of the first virtual address space), the second page table corresponding to the first virtual address space is obtained. If the fourth table entry index address is greater than the base address of the second page table, it can be determined that there are unused table entries in the second page table. The page table descriptors in the second page table can be sequentially offset downward by the number of the first table entries, and the first number of table entries in the high-address part of the second page table are deleted, so as to obtain the first page table corresponding to the first virtual address space.

[0010] Wherein, the fourth table entry index address is the table entry index address corresponding to the starting virtual address of the first virtual address space in the second page table. When the page table descriptors in the second page table are sequentially offset downward by the number of the first table entries, the fourth table entry index address is the same as the second table entry index address.

[0011] Optionally, the number of the first table entries can be greater than 0 and less than or equal to the number of the second table entries.

[0012] Wherein, the number of the second table entries can be the maximum value that the page table descriptor in the second page table can be offset downward. There can be multiple calculation methods for the number of the second table entries, but the calculation results under multiple calculation methods can be the same. For example, the number of the second table entries = the starting virtual address of the first virtual address space / the size of the second virtual address space, or the number of the second table entries = the number of table entries in the second page table - the size of the first virtual address space / the size of the second virtual address space.

[0013] It should be noted that the larger the number of the first table entries, the greater the offset amplitude of the table entries and the more memory is saved. Taking the second page table and the first page table as an example, the memory saved by the first page table compared to the second page table = the number of the first table entries * the memory size occupied by each table entry in the second page table (or the first page table).

[0014] Of course, in practical applications, the first virtual address space can also be obtained first. If the starting virtual address of the first virtual address space is greater than 0, the fourth table entry index address in the second page table may be greater than the base address of the second page table. Therefore, the page table descriptors of the second page table can be sequentially offset downward by the number of the first table entries corresponding to the second page table to obtain the first page table.

[0015] Optionally, the determining the first entry index address corresponding to the first virtual address includes: determining a second virtual address based on the first virtual address and a first offset value, where the first virtual address is greater than the second virtual address, and the first offset value is less than or equal to the starting virtual address of the first virtual address space; determining the first entry index address based on the second virtual address. Wherein, the first offset value = the number of entries in the first page table * the size of the second virtual address space associated with each entry in the first page table.

[0016] When the arithmetic logic unit (ALU) has completed offsetting the first virtual address and determined the second virtual address, the MMU can determine the base address of the first page table, and determine the first entry index address based on the base address of the first page table and the second virtual address. And since when determining the first target physical address corresponding to the first virtual address, it is searched sequentially from the first-level page table, the second-level page table, the third-level page table... until the corresponding first target physical address is found. Therefore, the first entry index address can be determined based on the base address of the first page table and the second virtual address through the following two possible implementation manners:

[0017] In a possible implementation manner, when the first page table is a first-level page table, the first virtual address can be compared with the virtual address spaces corresponding to each translation table base register (TTBR). If the first virtual address belongs to the virtual address space corresponding to a certain TTBR (the first virtual space can be a subset of the virtual address space corresponding to the TTBR), the base address of the first page table is obtained from the TTBR corresponding to the virtual address space. The sum of the base address of the first page table and the first-level page table index bits in the second virtual address is determined as the first entry index address.

[0018] In another possible implementation manner, when the first page table is a secondary page table, the base address of the first page table can be determined based on the third page table, and the first entry index address can be determined based on the base address of the first page table and the second virtual address, where the third page table is the previous-level page table adjacent to the first page table.

[0019] Optionally, the determining the first entry index address corresponding to the first virtual address includes: determining a third entry index address to be offset based on the first virtual address; determining the first entry index address based on the third entry index address and a second offset value, where the third entry index address is greater than the first entry index address, and the second offset value = the number of entries.

[0020] As can be seen from the foregoing, in the process of the MMU determining the first target physical address corresponding to the first virtual address, it may be necessary to search for page tables at multiple levels. The first page table may be any level page table, that is, any page table may be offset. Then, if the MMU first offsets the first virtual address through the ALU to obtain a second virtual address, and then determines the corresponding first table entry index address from the first page table based on the second virtual address, no matter which page tables in the multiple levels of page tables are offset, at least as long as the first virtual address is offset once, the obtained second virtual address can match the offset page table. If the MMU first determines the third table entry index address to be offset from the first virtual address, and then offsets the third table entry index address to obtain the first table entry index address, then when determining the first table entry index address in each level of offset page table, the third table entry index address can be offset separately for this page table to obtain the first table entry index address.

[0021] Optionally, before determining the first table entry index address corresponding to the first virtual address, the method further includes: obtaining page table offset flag information, where the page table offset flag information is used to indicate determining the first target physical address corresponding to the first virtual address based on the first page table.

[0022] Optionally, the page table offset flag information is indicated by an offset indication bit in a translation table base control register (TTBCR). Obtaining the page table offset flag information includes: when the value of the offset indication bit in the TTBCR is a first indicator, determining that the page table offset flag information is obtained.

[0023] Optionally, the method further includes:

[0024] Setting the value of the offset indication bit in the TTBCR to the first indicator.

[0025] Optionally, the first page table is a first-level page table or a second-level page table.

[0026] Optionally, the first virtual address space is a kernel-mode address space.

[0027] Among them, the address range of the kernel-mode address space can be 0x80000000 - 0xFFFFFFFF.

[0028] A second aspect provides a chip system, which includes: at least one CPU, at least one memory, and at least one coprocessor, where at least one MMU is included in the at least one coprocessor; the at least one MMU is configured to: when receiving an access request initiated by the at least one CPU for the at least one memory, and the access request carries a first virtual address in a first virtual address space, determine a first table entry index address corresponding to the first virtual address; according to the first table entry index address, determine a first target physical address corresponding to the first virtual address from a first page table; where the first page table is used to determine a physical address corresponding to each virtual address in the first virtual address space, a starting virtual address of the first virtual address space corresponds to a second table entry index address in the first page table, the second table entry index address is greater than or equal to a base address of the first page table and less than a sum of a quotient of the starting virtual address divided by a size of a second virtual address space and the base address of the first page table, a maximum table entry index address of the first page table is less than a sum of a quotient of a maximum virtual address of the first virtual address space divided by the size of the second virtual address space and the base address of the first page table, and the second virtual address space is a virtual address space associated with any table entry in the first page table.

[0029] Optionally, the at least one MMU includes at least one ALU:

[0030] The at least one ALU is configured to determine a second virtual address based on the first virtual address and a first offset value, where the first virtual address is greater than the second virtual address;

[0031] The at least one MMU is further configured to: determine the first table entry index address based on the second virtual address.

[0032] Optionally, the at least one MMU is further configured to: determine a third table entry index address to be offset based on the first virtual address; determine the first table entry index address based on the third table entry index address and a second offset value, where the third table entry index address is greater than the first table entry index address.

[0033] Optionally, the at least one MMU further includes at least one TTBCR, and the at least one MMU is further configured to: obtain page table offset flag information, where the page table offset flag information is indicated by an offset indication bit in the at least one TTBCR.

[0034] Optionally, the MMU further includes at least one TTBR, and the base address of a first-level page table can be stored in each TTBR. Correspondingly, the TTBCR can be used to indicate the TTBR selected when determining the physical address corresponding to a virtual address in different virtual address spaces, that is, to determine the TTBR corresponding to different virtual address spaces.

[0035] Optionally, the at least one coprocessor can be integrated in the at least one CPU.

[0036] A third aspect provides an electronic device, and the electronic device includes the chip system according to any one of the second aspects.

[0037] A fourth aspect provides a computer program product, and when the computer program product runs on an electronic device, the electronic device is enabled to execute the method according to any one of the first aspects.

[0038] It can be understood that for the beneficial effects of the second aspect to the fourth aspect, reference can be made to the relevant descriptions in the first aspect above, and details are not described herein again. Description of Drawings

[0039] Figure 1 A schematic structural diagram of an electronic device provided by an embodiment of the present application;

[0040] Figure 2 A schematic diagram of the logical relationship between a virtual address space, a page table, and a physical address space provided by an embodiment of the present application;

[0041] Figure 3 A schematic structural diagram of a page table descriptor of a first-level page table provided by an embodiment of the present application;

[0042] Figure 4 A schematic structural diagram of a page table descriptor of a second-level page table provided by an embodiment of the present application;

[0043] Figure 5 A schematic diagram of another logical relationship between a virtual address space, a page table, and a physical address space provided by an embodiment of the present application;

[0044] Figure 6 A flowchart of a mapping initialization setting provided by an embodiment of the present application;

[0045] Figure 7 A schematic diagram of the logical relationship between a virtual address space and a page table provided by an embodiment of the present application;

[0046] Figure 8 A schematic diagram of a page table provided by an embodiment of the present application;

[0047] Figure 9Flowchart of a method for determining a physical address provided by an embodiment of the present application;

[0048] Figure 10 Schematic diagram of another logical relationship among a virtual address space, a page table, and a physical address space provided by an embodiment of the present application;

[0049] Figure 11 Schematic diagram of another logical relationship among a virtual address space, a page table, and a physical address space provided by an embodiment of the present application;

[0050] Figure 12 Schematic diagram of the structure of a chip system provided by an embodiment of the present application;

[0051] Figure 13 Schematic diagram of the structure of another chip system provided by an embodiment of the present application. Detailed implementation manners

[0052] The method for determining a physical address provided by the embodiments of the present application can be applied to electronic devices such as mobile phones, tablet computers, wearable devices, in-vehicle devices, augmented reality (AR) / virtual reality (VR) devices, laptop computers, ultra-mobile personal computers (UMPCs), netbooks, personal digital assistants (PDAs), servers, etc. The embodiments of the present application do not impose any restrictions on the specific types of electronic devices.

[0053] Please refer to Figure 1, is a schematic structural diagram of the electronic device 100 provided in the embodiments of the present application. The electronic device 100 may include a CPU 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a headphone jack 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor L, a bone conduction sensor, etc.

[0054] It can be understood that the structure schematically shown in the embodiments of the present application does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may include more or fewer components than shown in the figure, or combine certain components, or split certain components, or have different component arrangements. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0055] The CPU 110 may include one or more processing units. For example, the CPU 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Among them, different processing units may be independent devices or integrated in one or more processors.

[0056] Among them, the controller may be the nerve center and command center of the electronic device 100. The controller may generate operation control signals according to the instruction operation code and timing signals to complete the control of fetching instructions and executing instructions.

[0057] In some embodiments, the CPU 110 may include one or more interfaces. The interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0058] The I2C interface is a bidirectional synchronous serial bus, including a serial data line (SDA) and a serial clock line (SCL). In some embodiments, the CPU 110 may include multiple groups of I2C buses. The CPU 110 may be respectively coupled to a touch sensor, a charger, a flash, a camera 193, etc. through different I2C bus interfaces. For example: The CPU 110 may be coupled to the touch sensor through the I2C interface, enabling the CPU 110 to communicate with the touch sensor through the I2C bus interface to implement the touch function of the electronic device 100.

[0059] The I2S interface may be used for audio communication. In some embodiments, the CPU 110 may include multiple groups of I2S buses. The CPU 110 may be coupled to the audio module 170 through the I2S bus to implement communication between the CPU 110 and the audio module 170. In some embodiments, the audio module 170 may transmit an audio signal to the wireless communication module 160 through the I2S interface to implement the function of answering a call through a Bluetooth headset.

[0060] The PCM interface may also be used for audio communication to sample, quantize, and encode analog signals. In some embodiments, the audio module 170 and the wireless communication module 160 may be coupled through the PCM bus interface. In some embodiments, the audio module 170 may also transmit an audio signal to the wireless communication module 160 through the PCM interface to implement the function of answering a call through a Bluetooth headset. Both the I2S interface and the PCM interface may be used for audio communication.

[0061] The UART interface is a general-purpose serial data bus for asynchronous communication. This bus can be a two-way communication bus. It converts the data to be transmitted between serial communication and parallel communication. In some embodiments, the UART interface is typically used to connect the CPU 110 and the wireless communication module 160. For example, the CPU 110 communicates with the Bluetooth module in the wireless communication module 160 through the UART interface to implement the Bluetooth function. In some embodiments, the audio module 170 can transmit audio signals to the wireless communication module 160 through the UART interface to implement the function of playing music through a Bluetooth headset.

[0062] The MIPI interface can be used to connect the CPU 110 with peripheral devices such as the display screen 194 and the camera 193. The MIPI interface includes a camera serial interface (CSI), a display serial interface (DSI), etc. In some embodiments, the CPU 110 and the camera 193 communicate through the CSI interface to implement the shooting function of the electronic device 100. The CPU 110 and the display screen 194 communicate through the DSI interface to implement the display function of the electronic device 100.

[0063] The GPIO interface can be configured by software. The GPIO interface can be configured as a control signal or as a data signal. In some embodiments, the GPIO interface can be used to connect the CPU 110 with the camera 193, the display screen 194, the wireless communication module 160, the audio module 170, the sensor module 180, etc. The GPIO interface can also be configured as an I2C interface, an I2S interface, a UART interface, a MIPI interface, etc.

[0064] The USB interface 130 is an interface that complies with the USB standard specification, and can specifically be a Mini USB interface, a Micro USB interface, a USB Type C interface, etc. The USB interface 130 can be used to connect a charger to charge the electronic device 100, and can also be used for data transmission between the electronic device 100 and peripheral devices. It can also be used to connect a headset to play audio through the headset. This interface can also be used to connect other electronic devices 100, such as AR devices, etc.

[0065] It can be understood that the interface connection relationships between the modules illustrated in the embodiments of the present application are only illustrative descriptions and do not constitute a structural limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 can also adopt different interface connection methods in the above embodiments, or a combination of multiple interface connection methods.

[0066] The charging management module 140 is used to receive a charging input from a charger. Herein, the charger may be a wireless charger or a wired charger. In some embodiments of wired charging, the charging management module 140 may receive the charging input from a wired charger through the USB interface 130. In some embodiments of wireless charging, the charging management module 140 may receive the wireless charging input through the wireless charging coil of the electronic device 100. While charging the battery 142, the charging management module 140 may also supply power to the electronic device 100 through the power management module 141.

[0067] The power management module 141 is used to connect the battery 142, the charging management module 140, and the CPU 110. The power management module 141 receives the inputs from the battery 142 and / or the charging management module 140 and supplies power to the CPU 110, the internal memory 121, the external memory, the display screen 194, the camera 193, the wireless communication module 160, etc. The power management module 141 may also be used to monitor parameters such as the battery capacity, the number of battery charge cycles, and the battery health status (leakage, impedance). In some other embodiments, the power management module 141 may also be disposed in the CPU 110. In some other embodiments, the power management module 141 and the charging management module 140 may also be disposed in the same device.

[0068] The wireless communication function of the electronic device 100 may be implemented by the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, the modulation and demodulation processor, and the baseband processor, etc.

[0069] The antenna 1 and the antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in the electronic device 100 may be used to cover a single or multiple communication frequency bands. Different antennas may also be multiplexed to improve the utilization rate of the antennas. For example, the antenna 1 may be multiplexed as the diversity antenna of the wireless local area network. In some other embodiments, the antenna may be used in combination with a tuning switch.

[0070] The mobile communication module 150 may provide solutions for wireless communications such as 2G / 3G / 4G / 5G applied to the electronic device 100. The mobile communication module 150 may include at least one filter, switch, power amplifier, low noise amplifier (LNA), etc. The mobile communication module 150 may receive electromagnetic waves through the antenna 1, filter and amplify the received electromagnetic waves, and then transmit them to the modulation and demodulation processor for demodulation. The mobile communication module 150 may also amplify the signal modulated by the modulation and demodulation processor and convert it into electromagnetic waves through the antenna 1 for radiation. In some embodiments, at least some functional modules of the mobile communication module 150 may be provided in the CPU 110. In some embodiments, at least some functional modules of the mobile communication module 150 and at least some modules of the CPU 110 may be provided in the same device.

[0071] The modulation and demodulation processor may include a modulator and a demodulator. Among them, the modulator is used to modulate the low-frequency baseband signal to be transmitted into a medium-high frequency signal. The demodulator is used to demodulate the received electromagnetic wave signal into a low-frequency baseband signal. Subsequently, the demodulator transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After being processed by the baseband processor, the low-frequency baseband signal is transmitted to the application processor. The application processor outputs a sound signal through an audio device (not limited to the speaker 170A, receiver 170B, etc.), or displays an image or video through the display screen 194. In some embodiments, the modulation and demodulation processor may be an independent device. In other embodiments, the modulation and demodulation processor may be independent of the CPU 110 and be provided in the same device as the mobile communication module 150 or other functional modules.

[0072] The wireless communication module 160 may provide solutions for wireless communications applied to the electronic device 100, including wireless local area networks (WLANs) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite systems (GNSSs), frequency modulation (FM), near field communication (NFC), infrared (IR), and the like. The wireless communication module 160 may be one or more devices integrating at least one communication MMU. The wireless communication module 160 receives electromagnetic waves via the antenna 2, performs frequency modulation and filtering processing on the electromagnetic wave signals, and sends the processed signals to the CPU 110. The wireless communication module 160 may also receive signals to be sent from the CPU 110, perform frequency modulation and amplification on them, and convert them into electromagnetic waves through the antenna 2 for radiation.

[0073] In some embodiments, antenna 1 of electronic device 100 is coupled to mobile communication module 150, and antenna 2 is coupled to wireless communication module 160, such that electronic device 100 can communicate with a network and other devices through wireless communication technologies. The wireless communication technologies may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), BT, GNSS, WLAN, NFC, FM, and / or IR technology, etc. The GNSS may include global positioning system (GPS), global navigation satellite system (GLONASS), beidou navigation satellite system (BDS), quasi-zenith satellite system (QZSS), and / or satellite based augmentation systems (SBAS).

[0074] Electronic device 100 implements a display function through a GPU, display screen 194, and an application processor, etc. The GPU is a microprocessor for image processing, and is connected to display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. CPU 110 may include one or more GPUs, which execute program instructions to generate or change display information.

[0075] The display screen 194 is used to display images, videos, etc. The display screen 194 includes a display panel. The display panel can adopt a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a Miniled, a MicroLed, a Micro-oLed, a quantum dot light-emitting diode (QLED), etc. In some embodiments, the electronic device 100 may include one or N display screens 194, where N is a positive integer greater than 1.

[0076] The electronic device 100 can implement the shooting function through the ISP, the camera 193, the video codec, the GPU, the display screen 194, and the application processor, etc.

[0077] The ISP is used to process the data fed back by the camera 193. For example, when taking a photo, the shutter is opened, and the light passes through the lens and is transmitted to the camera photosensitive element. The optical signal is converted into an electrical signal, and the camera photosensitive element transmits the electrical signal to the ISP for processing and converts it into an image visible to the naked eye. The ISP can also perform algorithm optimization on the noise, brightness, and skin color of the image. The ISP can also optimize parameters such as the exposure and color temperature of the shooting scene. In some embodiments, the ISP can be set in the camera 193.

[0078] The camera 193 is used to capture static images or videos. An object generates an optical image through the lens and projects it onto the photosensitive element. The photosensitive element can be a charge-coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the optical signal into an electrical signal, and then transmits the electrical signal to the ISP to convert it into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in standard RGB, YUV, etc. formats. In some embodiments, the electronic device 100 may include one or N cameras 193, where N is a positive integer greater than 1.

[0079] The digital signal processor is used to process digital signals. In addition to processing digital image signals, it can also process other digital signals. For example, when the electronic device 100 selects a frequency point, the digital signal processor is used to perform Fourier transform on the frequency point energy, etc.

[0080] The video codec is used to compress or decompress digital videos. The electronic device 100 can support one or more video codecs. In this way, the electronic device 100 can play or record videos in multiple coding formats, such as: Moving Picture Experts Group (MPEG) 1, MPEG2, MPEG3, MPEG4, etc.

[0081] The NPU is a neural-network (NN) computing processor. By drawing on the structure of biological neural networks, such as the transmission pattern between human brain neurons, it can quickly process input information and can also continuously self-learn. Through the NPU, applications such as intelligent cognition of the electronic device 100 can be realized, such as: image recognition, face recognition, voice recognition, text understanding, etc.

[0082] The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 100. The external memory card communicates with the CPU 110 through the external memory interface 120 to implement the data storage function. For example, files such as music and videos are saved in the external memory card.

[0083] The internal memory 121 can be used to store computer-executable program code, and the executable program code includes instructions. The CPU 110 executes various functional applications and data processing of the electronic device 100 by running the instructions stored in the internal memory 121. The internal memory 121 can include a program storage area and a data storage area. Among them, the program storage area can store the operating system, application programs required for at least one function (such as the sound playback function, the image playback function, etc.). The data storage area can store the data created during the use of the electronic device 100 (such as audio data, phone book, etc.). In addition, the internal memory 121 can include high-speed random access memory and can also include non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS), etc.

[0084] The MMU 111 can be set in the coprocessor ( Figure 1In (not shown in the figure), the coprocessor can be set between the bus of the CPU 110, the internal memory 121, and the external memory interface 120. When the CPU 110 needs to access the internal memory 121 (i.e., the memory mentioned above), a virtual address can be provided, and the MMU maps this virtual address to a physical address, so that the CPU 110 can read or write data to the internal memory 121 based on this physical address.

[0085] The virtual address is an address in the address space that can be recognized or generated by the operating system in the electronic device, and its size range can be determined by the number of bits of the operating system running in the CPU 110. For example, if the operating system running in the CPU 110 is 32 bits, the virtual address is also 32 bits, and its address range is 0 - 0xFFFFFFFF (4GB); if the operating system running in the CPU 110 is 64 bits, the virtual address is also 64 bits, and its address space is 0 - 0xFFFFFFFFFFFFFFFF (16EB).

[0086] Among them, the virtual address can be divided into multiple virtual address spaces according to actual needs, such as the user mode address space and the kernel mode address space. The user mode address space can be accessed by user mode programs (such as reading, writing, opening, closing, or drawing) and kernel mode programs (such as process management, storage management, file management, or device management), and the kernel mode address space can only be accessed by kernel mode programs during operation.

[0087] The physical address can be an address in the address space actually possessed by a hardware storage device such as the internal memory 121. The address space of the physical address can be smaller than the address space of the virtual address. For example, when the size of the address space of the virtual address can be 4GB, the size of the address space of the physical address can be 256MB.

[0088] The MMU 111 can include several ALUs 112 ( Figure 1 only 1 is shown in the figure), a TTBCR 113, and several TTBRs 114 ( Figure 1 only 2 are shown in the figure).

[0089] The TTBCR 113 can be used to store relevant control information of the TTBR, such as specifying the TTBR 114 corresponding to the kernel mode address space and the user mode address space. In the embodiments of the present application, the reserved bits in the TTBCR 113 can also be used to indicate whether to offset the virtual address before mapping the virtual address.

[0090] The TTBR 114 can be used to indicate the base address of the first-level page table (i.e., the table entry index address of the first table entry in this first-level page table). The ALU 112 can be used to perform logical operations, such as offsetting the virtual address up or down.

[0091] The electronic device 100 can implement audio functions through the audio module 170, speaker 170A, receiver 170B, microphone 170C, headphone jack 170D, and application processor, etc. For example, music playback, recording, etc.

[0092] The audio module 170 is used to convert digital audio information into an analog audio signal for output, and is also used to convert analog audio input into a digital audio signal. The audio module 170 can also be used for encoding and decoding audio signals. In some embodiments, the audio module 170 can be disposed in the CPU 110, or some functional modules of the audio module 170 can be disposed in the CPU 110.

[0093] The speaker 170A, also known as the "loudspeaker", is used to convert an audio electrical signal into a sound signal. The electronic device 100 can listen to music or hands-free calls through the speaker 170A.

[0094] The receiver 170B, also known as the "earpiece", is used to convert an audio electrical signal into a sound signal. When the electronic device 100 answers a call or a voice message, the voice can be listened to by placing the receiver 170B close to the human ear.

[0095] The microphone 170C, also known as the "microphone" or "transmitter", is used to convert a sound signal into an electrical signal. When making a call or sending a voice message, the user can speak by bringing the mouth close to the microphone 170C to input the sound signal into the microphone 170C. The electronic device 100 can be provided with at least one microphone 170C. In some other embodiments, the electronic device 100 can be provided with two microphones 170C, which can not only collect sound signals but also implement a noise reduction function. In some other embodiments, the electronic device 100 can also be provided with three, four or more microphones 170C to implement sound signal collection, noise reduction, and can also identify the sound source to implement functions such as directional recording.

[0096] The headphone jack 170D is used to connect a wired headphone. The headphone jack 170D can be a USB interface 130, or a 3.5 mm open mobile terminal platform (OMTP) standard interface, or a cellular telecommunications industry association of the USA (CTIA) standard interface.

[0097] The button 190 includes a power-on button, volume buttons, etc. The button 190 can be a mechanical button or a touch button. The electronic device 100 can receive button inputs and generate key signal inputs related to the user settings and function controls of the electronic device 100.

[0098] The motor 191 can generate vibration prompts. The motor 191 can be used for incoming call vibration prompts and also for touch vibration feedback. For example, touch operations on different applications (such as taking pictures, audio playing, etc.) can correspond to different vibration feedback effects. For touch operations on different areas of the display screen 194, the motor 191 can also correspond to different vibration feedback effects. Different application scenarios (such as time reminder, receiving messages, alarm clock, games, etc.) can also correspond to different vibration feedback effects. The touch vibration feedback effect can also support customization.

[0099] The indicator 192 can be an indicator light and can be used to indicate the charging state, power change, and can also be used to indicate messages, missed calls, notifications, etc.

[0100] The SIM card interface 195 is used to connect the SIM card. The SIM card can be in contact with and separated from the electronic device 100 by inserting or removing it from the SIM card interface 195. The electronic device 100 can support 1 or N SIM card interfaces, where N is a positive integer greater than 1. The SIM card interface 195 can support Nano SIM cards, Micro SIM cards, SIM cards, etc. Multiple cards can be inserted into the same SIM card interface 195 at the same time. The types of the multiple cards can be the same or different. The SIM card interface 195 can also be compatible with different types of SIM cards. The SIM card interface 195 can also be compatible with external memory cards. The electronic device 100 interacts with the network through the SIM card to implement functions such as calls and data communication. In some embodiments, the electronic device 100 uses an eSIM, that is, an embedded SIM card. The eSIM card can be embedded in the electronic device 100 and cannot be separated from the electronic device 100.

[0101] The software system of the electronic device 100 can adopt a layered architecture, event-driven architecture, microkernel architecture, microservices architecture, or cloud architecture.

[0102] When the CPU in the electronic device accesses the memory, the CPU sends a virtual address to the MMU. The MMU maps and converts the virtual address into the corresponding physical address, that is, converts the access to the virtual address into the access to the physical memory, aiming to save the physical address space and protect the physical address space. Among them, the MMU can adopt a paging mechanism to manage the virtual address space in units of pages, and each page can include a virtual address space of a preset size.

[0103] A virtual address space may include more than one virtual address, and a virtual address space may correspond to a set of page tables. The set of page tables can be used to determine the physical address corresponding to the virtual address of the virtual address space. The set of page tables may include a first-level page table, or the set of page tables may include a first-level page table and at least one secondary page table. The secondary page table may include a second-level page table, a third-level page table, and even lower-level page tables. Correspondingly, the MMU can determine the physical address corresponding to the virtual address through at least one level of mapping, and the number of levels of mapping is the same as the number of levels of the set of page tables. For example, when determining the physical address corresponding to the virtual address through a single-level mapping, the single-level mapping is called a segment mapping, and the set of page tables may only include a first-level page table; when determining the physical address corresponding to the virtual address through a two-level mapping, the two-level mapping is called a page mapping, and the set of page tables may include a first-level page table and at least one second-level page table.

[0104] Among them, the page table is a special data structure stored in memory. The page table can be used as an index for the virtual address space and may include multiple table entries. Each table entry includes the association relationship between the table entry index address and the physical address. Among them, the physical address can be carried in the page table descriptor of the table entry, and the page table descriptor can be used to indicate the base address of the next-level page table or the base address of the physical address corresponding to the virtual address. For example, in a single-level mapping, the page table descriptor in the first-level page table is used to indicate the segment base address, and the segment base address is the base address of the physical address corresponding to the virtual address; in a two-level mapping, the page table descriptor in the first-level page table is used to indicate the base address of the second-level page table, and the page table descriptor in the second-level page table can be used to indicate the page base address, and the page base address is the base address of the physical address of the page corresponding to the virtual address.

[0105] Of course, in practical applications, the page table descriptor can also be used to indicate more information related to the virtual-to-physical address mapping. For example, the page table descriptor also includes a mapping level indication bit and a granularity indication bit. The mapping level indication bit can be used to indicate the mapping level of the current mapping or the mapping level indication bit of whether there is a next-level mapping (i.e., single-level mapping or two-level mapping), and the granularity indication bit can be used to indicate the granularity indication bit of the segment mapping or the page mapping (i.e., the size of the virtual address space associated with the page table).

[0106] Please refer to Figure 2, which is a schematic diagram of the logical relationship between a virtual address space, a page table, and a physical address space provided by an embodiment of the present application. The address range of the virtual address space is [0x00000000, 0xFFFFFFFF], and the size of the virtual address space is 4GB. Among them, the address range of the user-mode address space is [0x00000000, 0x80000000) (i.e., the 0th GB - the 2nd GB), and the address range of the kernel-mode address space is [0x80000000 - 0xFFFFFFFF] (i.e., the 2nd GB - the 4th GB). The address range of the physical address space is (0x40000000~0XBFFFFFFF), and the size is 2GB. By setting the TTBCR based on the base address of page table 1 stored in TTBR1, the virtual address of the kernel-mode address space 201 is mapped to the physical address in the physical address space. Based on the base address of page table 2 stored in TTBR0, the virtual address of the user-mode address space is mapped to the physical address in the physical address space.

[0107] Please refer to Figure 3 , which is a schematic diagram of a page table descriptor of a first-level page table provided by an embodiment of the present application. In a 32-bit operating system, the 0th - 1st bits of this page table descriptor are mapping level indicator bits. When the [1:0] bits (i.e., the [1]st bit and the [0]th bit) are 10, the current mapping is a first-level mapping (i.e., segment mapping), and the segment base address stored in the highest 12 or 8 bits of this page table descriptor; when the [1:0] bits are 01, the current mapping is a two-level mapping (i.e., page mapping), and the base address of the second-level page table stored in the highest 22 bits of this page table descriptor. The 18th bit of this page table descriptor can be a mapping granularity indicator bit. When the

[18] th bit is 0, the mapping granularity is 1MB, and the segment base address stored in the highest 12 bits of this page table descriptor. When the

[18] th bit is 1, the mapping granularity is 16MB, and the segment base address stored in the highest 8 bits of this page table descriptor.

[0108] Please refer to Figure 4 , which is a schematic structural diagram of a page table descriptor of a second-level page table provided by an embodiment of the present application. In a 32-bit operating system, the [1:0] bits in this page table descriptor are mapping granularity indicator bits. Among them, when the [1:0] bits are 10 or 11, the mapping granularity is 4KB, and the highest 20 bits of the page descriptor are the page base address; when the [1:0] bits are 01, the mapping granularity is 64KB, and the highest 16 bits of the page descriptor are the page base address.

[0109] In addition, according to different mapping series, each bit of the virtual address in the virtual address space will have different meanings. The virtual address may include at least one-level page table index bits and a physical address offset bit. Among them, each level of index bits can be used to indicate the specific position of the page table descriptor corresponding to the virtual address in the page table of this level. The physical address offset bit can be used to indicate the offset of the physical address corresponding to the virtual address. The sum of the physical address offset bit and the physical address base address (such as segment base address or page base address) determined by the set of page tables corresponding to the virtual address space is the physical address corresponding to the virtual address.

[0110] For example, the operating system in the electronic device is 32-bit, using one-level mapping, with a mapping granularity of 1MB. Bits [31:20] in the virtual address are the one-level page table index bits, and bits [19:0] are the segment offset bits. Or, when using two-level mapping, with a mapping granularity of 4KB, bits [31:20] in the second virtual address are the one-level page table index bits, bits [19:12] are the second-level page table index bits, and bits [11:0] are the page offset bits.

[0111] As can be seen from the foregoing, the starting virtual address of the virtual address space may not start from 0. In some embodiments, the page table, as the index of the virtual address space, has table entries allocated according to the virtual address from 0 to the maximum virtual address of the virtual address space. Therefore, the number of table entries in the page table is greater than the number of table entries actually required by the virtual address space. The lower part of the table entry index addresses in the page table will not be utilized, and the memory space occupied by these table entries will be wasted, resulting in low memory utilization.

[0112] Please refer to Figure 5 , which is a schematic diagram of the logical relationship between a virtual address space, a page table, and a physical address space. In a 32-bit operating system, the address range of the kernel-mode address space 501 is [0x80000000, 0xFFFFFFFF], and the address range of the physical address space 503 is [0x40000000, 0XBFFFFFFF]. One-level page table 502 is used for mapping (i.e., one-level page table 502 corresponds to the kernel-mode address space 501). Each table entry in this one-level page table is associated with 1MB of virtual address. Then, a total of 4GB / 1MB = 4K (i.e., 4096) table entries are required. And since each table entry needs to occupy 4B of memory, this one-level page table 402 altogether needs to occupy 16KB of memory. The starting address of the kernel-mode address space 501 is 0x80000000, and the corresponding table entry index is 0x80000000 / 0x100000 = 0x800. Based on this table entry index 0x800, it can be determined that the physical address corresponding to 0x80000000 is 0x40000000. But by Figure 5It can be seen that in this first-level page table 501, when determining the physical address corresponding to the virtual address in the kernel-mode address space 501, actually only 2K (i.e., 2048) table entries greater than or equal to 0x800 in the high-address direction are occupied. These 2K table entries include page table descriptors, while the 2K table entries in the low-address direction [0X000, 0X7FF] are not utilized. Therefore, the 8KB of memory occupied by the 2K table entries in the low-address direction is wasted. Similarly, the same problem also exists in secondary page tables such as the second-level page table and the third-level page table.

[0113] To solve this technical problem, an embodiment of the present application provides a method for determining a physical address.

[0114] In the embodiment of the present application, when the MMU obtains the first virtual address of the first virtual address space, it can determine the first table entry index address corresponding to the first virtual address in the first page table. According to the first table entry index address, the first target physical address corresponding to the first virtual address is determined from the first page table. Since the first page table can be used to determine the physical address corresponding to each virtual address in the first virtual address space, the starting virtual address of the first virtual address space corresponds to the second table entry index address in the first page table. The second table entry index address is greater than or equal to the base address of the first page table and less than the sum of the quotient of the starting virtual address divided by the size of the second virtual address space and the base address of the first page table. The maximum table entry index address of the first page table is less than the sum of the quotient of the maximum virtual address of the first virtual address space divided by the size of the second virtual address space and the base address of the first page table. The second virtual address space is the virtual address space associated with any table entry in the first page table. Therefore, the first page table can at least only include the table entries actually required by the first virtual address space, thereby saving memory and improving the utilization rate of memory.

[0115] The technical solution of the present application will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0116] Before the MMU first executes the method for determining a physical address provided by the embodiment of the present application, the MMU needs to be initialized.

[0117] Please refer to Figure 6 , which is a flowchart of a mapping initialization setting provided by the embodiment of the present application.

[0118] S601, configure the page table.

[0119] To reduce the memory occupied by the page table, for a page table whose number of included table entries is greater than the number of page tables actually required by the corresponding virtual address space, the page table descriptors in the page table can be offset downward (i.e., in the low-address direction) according to their positions in the page table, so as to reduce the number of unused table entries, and the saved storage space can be released or used as ordinary memory.

[0120] Optionally, a second page table corresponding to the first virtual address space can be obtained. If the fourth table entry index address is greater than the base address of the second page table, it can be determined that there are unused table entries in the second page table. The page table descriptors in the second page table can be sequentially offset downward by the number of the first table entries, and the number of the first table entries in the high-address part of the second page table can be deleted, so as to obtain the first page table corresponding to the first virtual address space.

[0121] Among them, the first page table and the second page table can be used to determine the physical address corresponding to each virtual address in the first virtual address space. The fourth table entry index address is the table entry index address corresponding to the starting virtual address of the first virtual address space in the second page table. When the page table descriptors in the second page table are sequentially offset downward by the number of the first table entries, the fourth table entry index address is the same as the second table entry index address. The second table entry index address is the table entry index address corresponding to the starting address of the first virtual address space in the first page table. The first page table can include at least one table entry. The starting virtual address of the first virtual address space corresponds to the second table entry index address of the first page table. The second table entry index address is greater than or equal to the base address of the first page table and less than the sum of the quotient of the size of the second virtual address space associated with the starting virtual address of the first virtual address space and the table entry and the base address of the first page table. The maximum table entry index address of the first page table is less than the sum of the quotient of the maximum virtual address of the first virtual address space divided by the size of the second virtual address space and the base address of the first page table. The second virtual address space can be the virtual address space corresponding to each table entry in the first page table or the second page table, and the second virtual address space can be a subset of the first virtual address space.

[0122] Optionally, the number of the first table entries can be greater than 0 and less than or equal to the number of the second table entries.

[0123] Among them, the number of the second table entries can be the maximum value by which the page table descriptors in the second page table can be offset downward. There can be multiple calculation methods for the number of the second table entries, but the calculation results under multiple calculation methods can be the same. For example, the number of the second table entries = the starting virtual address of the first virtual address space / the size of the second virtual address space, or the number of the second table entries = the number of table entries of the second page table - the size of the first virtual address space / the size of the second virtual address space.

[0124] It should be noted that the larger the number of the first table entries, the larger the amplitude of the table entry offset and the more memory is saved. Taking the second page table and the first page table as an example, the memory saved by the first page table compared to the second page table = the number of the first table entries * the memory size occupied by each table entry in the second page table (or the first page table).

[0125] Please refer to Figure 7 , which is a schematic diagram of the logical relationship between the virtual address space and the page table provided by the embodiment of the present application. As can be seen from Figure 7 , the virtual address space associated with the second page table 720 is the first virtual address space 710. The second page table 720 includes multiple table entries 721, and the virtual address space associated with each table entry 721 is the second virtual address space 711. The second virtual address space is a subset of the first virtual address space, and the size of the first virtual address space = the number of table entries 721 * the size of the second virtual address space.

[0126] Of course, in practical applications, the first virtual address space can also be obtained first. If the starting virtual address of the first virtual address space is greater than 0, the index address of the fourth table entry in the second page table may be greater than the base address of the second page table. Therefore, the page table descriptors of the second page table can be sequentially offset downward by the number of the first table entries corresponding to the second page table to obtain the first page table.

[0127] Optionally, the first virtual address space is the kernel-mode address space. As can be seen from Figure 5 , its storage space is 2GB, the address range is [0x80000000 - 0xFFFFFFFF], the starting virtual address is 0x80000000, and the second page table corresponding to this kernel-mode address space is the first-level page table 502. Each table entry corresponds to a 1MB second virtual address space, and each table entry occupies 4B of memory. The index address of the fourth table entry corresponding to this starting virtual address in the first-level page table 502 is 0X800. Since 0X800 is greater than the base address 0X00 of the first-level page table, 2GB / 1MB = 2K table entries from 0X00 to 0X7FF in the first-level page table 502 are not utilized. Then, if the first-level page table 502 is offset, it can be offset by at most 2K table entries. When the page table descriptors in the first-level page table 502 are offset downward by 2K table entries, the obtained first page table is the first-level page table 801, as shown in Figure 8 . In the first-level page table 801, the index address of the second table entry is 0X00, and the physical address associated with 0X00 is the same as the physical address associated with 0X800 in the first-level page table Figure 5 502, both are 0x40000000. However, compared with the first-level page table 502, it can be seen that the first-level page table 801 saves 2K * 4B = 8KB of memory.

[0128] It should be noted that the offset methods of secondary page tables such as the second-level page table and the third-level page table can be similar to the offset method of the first-level page table, and the embodiments of the present application will not elaborate on this one by one.

[0129] S602, configure the register.

[0130] Among them, the register configuration may include adding an offset indicator bit in the reserved bit of the TTBCR and setting the offset indicator bit to the first indicator or the second indicator, and may also include specifying the TTBR for current address virtual mapping.

[0131] Optionally, an ALU for implementing virtual address offset operation can be added to the MMU.

[0132] S603, enable the MMU function.

[0133] In order to be compatible with the prior art and reduce user perception, an offset indicator bit (denoted as offset1) can be added to the reserved bit of the TTBCR to indicate whether to offset the virtual address. If offset1 = 1, it means the offset function is enabled, and the ALU performs an offset operation on the virtual address. If offset1 = 0, it means the offset function is disabled, and the ALU does not perform an offset operation on the virtual address, or directly transfers the virtual address to the subsequent functional module. In addition, the TTBR for current address virtual-real mapping can also be indicated by the TTBCR.

[0134] For example, during the startup process of the operating system, the offset indicator bit can be configured through the following instructions to indicate the enabling of the offset function.

[0135] orr r12, #(1<<3);

[0136] mcr p15, 0, r12, c2, c0, 2;

[0137] Among them, orr is a bit set instruction, which is used to perform a logical OR operation on two operands and put the result into the destination register. orr r12, #(1<<3) can indicate setting r12 to 1; mcr is an operation instruction for the coprocessor CP15, and the TTBCR can be located in this coprocessor CP15. mcr p15, 0, r12, c2, c0, 2 means writing r12 to c1 of CP15. Then through the above instructions, the offset1 of TTBCR113 can be set to 1, thereby indicating the enabling of the offset function.

[0138] It should be noted that in the embodiments of the present application, the offset indication bit in the TTBCR is used to indicate whether to offset the virtual address. When the offset indication bit is 1, it can be used as the page table offset flag information indicating the offset of the virtual address. However, it can be understood that in practical applications, other forms of information can be used as the page table offset flag information, and the embodiments of the present application do not specifically limit the form of the page table offset flag information.

[0139] In addition, in another possible implementation, the page table offset flag information may not be set, including not adding an offset indication bit in the reserved bits of the TTBCR. Then, in the subsequent process of determining the physical address, it is no longer necessary to obtain the page table offset flag information.

[0140] It should be noted that in practical applications, S601 can also be executed at any time before S603.

[0141] When the initialization settings of the MMU are completed, the MMU can determine the physical address through the following steps.

[0142] Please refer to Figure 9 , which is a flowchart of a method for determining a physical address provided by the embodiments of the present application. It should be noted that this method is not limited by Figure 9 the specific order described below. It should be understood that in other embodiments, the order of some steps of this method can be exchanged according to actual needs, or some of the steps can also be omitted or deleted. The method includes the following steps:

[0143] S901, the MMU obtains the first virtual address of the first virtual address space.

[0144] Since the CPU needs to access the memory during operation, and the CPU directly accesses the virtual address, in order to convert this access into an access to the physical address of the memory, the MMU can obtain the virtual address from the CPU. And since for the first virtual address space, the associated first page table is the page table after offset, when determining the first target physical address corresponding to the first virtual address in the first virtual address space and the physical address corresponding to the virtual address that does not belong to the first virtual address space, different methods can also be adopted respectively. Therefore, in order to facilitate the method for determining the physical address corresponding to the virtual address subsequently, it can be determined whether the virtual address is the first virtual address in the first virtual address space.

[0145] The MMU can pre-determine the address range of the first virtual address space, compare the obtained virtual address with the starting virtual address and the ending virtual address of the first virtual address space. If the virtual address is greater than or equal to the starting virtual address and less than or equal to the ending virtual address, then this virtual address can be determined as the first virtual address.

[0146] For example, please refer to again Figure 5 and Figure 8 The first virtual address space is the kernel-mode address space, and its address range is [0x80000000 - 0xFFFFFFFF]. The corresponding first page table is the first-level page table 801, and the first-level page table 801 is migrated from the first-level page table 502. Therefore, if any of the obtained first virtual addresses is within [0x80000000 - 0xFFFFFFFF], then S902 can be executed.

[0147] In S902, the MMU obtains the page table offset flag information. If the page table offset flag information is obtained, then S903 is executed; otherwise, S905 is executed.

[0148] As can be seen from the foregoing, the embodiments of the present application can offset the page table. Correspondingly, the method for determining the physical address corresponding to the first virtual address will also be different from that when the page table is not offset. To enable the MMU to be compatible with two different ways of determining the physical address when offsetting and not offsetting the page table, the page table offset flag information can be set, and this page table offset flag information is obtained when determining the physical address corresponding to the first virtual address. If the page table offset flag information is obtained when determining the physical address corresponding to the first virtual address, it can be determined that the page table has been offset, and then an appropriate method can be adopted in the subsequent steps to determine this physical address.

[0149] Optionally, the MMU can obtain the offset indication bit in the TTBCR. If this offset indication bit is the first indicator (such as 1), then it can be determined that the page table offset flag information is obtained, and thus S903 is executed; if this offset indication bit is the second indicator (such as 0), it can be determined that the page table offset flag information is not obtained, and thus S905 is executed.

[0150] Of course, in practical applications, if there are other forms of the page table offset flag information, then other corresponding methods can also be used to determine whether the page table offset flag information is obtained. For example, in another possible implementation, an offset indication module can be additionally set in the MMU. This offset indication module can include a specific string that can serve as the page table offset flag information. This specific string can be obtained from the offset indication module. If this specific string is obtained, it can be determined that the page table offset flag information is obtained; otherwise, it can be determined that the page table offset flag information is not obtained.

[0151] It should be noted that in practical applications, it is also possible not to consider the compatibility of the case where the page table has no offset, that is, not to execute S902, but directly execute S903 after S901. That is, S902 is an optional step.

[0152] S903. The MMU determines the first table entry index address corresponding to the first virtual address in the first page table.

[0153] As can be seen from the foregoing, the table entries in the page table include the association relationship between the table entry index address and the physical address. Therefore, in order to determine the first target physical address corresponding to the first virtual address, the first table entry index address corresponding to the first virtual address in the first page table can be determined first.

[0154] In a possible implementation, when the MMU determines the first table entry index address corresponding to the first virtual address in the first page table, since the page table descriptors stored in the table entries may change before and after the offset of the first page table, the physical address associated with the table entry will also change, that is, the table entry index associated with the same physical address changes. Therefore, when determining the first table entry index address corresponding to the first virtual address in the first page table, it can be implemented by the following method 1 or method 2:

[0155] Method 1. The MMU determines a second virtual address based on the first virtual address and the first offset value. The MMU determines the first table entry index address based on the second virtual address. Wherein, the first virtual address is greater than the second virtual address. In other words, the second virtual address is obtained by subtracting the first offset value from the first virtual address.

[0156] In method 1, the MMU first performs an appropriate offset on the first virtual address.

[0157] Wherein, the MMU can use the ALU to determine the second virtual address based on the first virtual address and the first offset value.

[0158] It should be noted that the first offset value can be determined in advance, and the first offset value can be less than or equal to the starting virtual address of the first virtual address space. Wherein, the first offset value = the number of the first table entries corresponding to the first page table * the size of the second virtual address space associated with each table entry of the first page table, and the second virtual address = the first virtual address - the first offset value.

[0159] For example, the operating system of the electronic device is 32-bit. As Figure 5 and Figure 8 shown, the first page table is a first-level page table, and this first-level page table is offset downward by 2K table entries. Each page table descriptor in each table entry is associated with a 1MB virtual address space. Then the first offset value = 2K * 1MB = 2GB, that is, 0x80000000.

[0160] When the MMU has completed the offset of the first virtual address and determined the second virtual address, the base address of the first page table can be determined. Based on the base address of the first page table and the second virtual address, the first table entry index address is determined. And since when determining the first target physical address corresponding to the first virtual address, the search is sequentially performed from the first-level page table, the second-level page table, the third-level page table, and so on until the corresponding first target physical address is found. Therefore, the first table entry index address can be determined based on the base address of the first page table and the second virtual address through the following two possible implementation methods:

[0161] In a possible implementation method, when the first page table is a first-level page table, the first virtual address can be compared with the virtual address spaces corresponding to each TTBR. If the first virtual address belongs to the virtual address space corresponding to a certain TTBR (the first virtual space can be a subset of the virtual address space corresponding to the TTBR), the base address of the first page table is obtained from the TTBR corresponding to the virtual address space. The sum of the base address of the first page table and the first-level page table index bits in the second virtual address is determined as the first table entry index address.

[0162] To illustrate Method 1 in detail, please now refer to Figure 10, which is a schematic diagram of the logical relationship between a virtual address space, a page table, and a physical address space provided by an embodiment of this application. The operating system in the electronic device is 32-bit, and the first virtual address space is the kernel-mode address space 501, with an address range of [0x80000000 - 0xFFFFFFFF]. Taking the first virtual address in the first virtual address space as 0x80100000 as an example, the MMU can determine that the TTBR corresponding to the kernel-mode address space 501 is TTBR1, and obtain the base address of the first-level page table 801 as 0X000 from TTBR1. From the page table descriptor in the 0X000 entry, it can be seen that the mapping level indication bits [1:0] of the page table descriptor are 10, and the granularity indication bit

[18] is 0. Then it is determined that the current is a first-level mapping, and the mapping granularity is 1MB. Therefore, the first virtual address is offset downward by 0x80000000 to obtain the second virtual address as 0x00100000. The [31:20] bits in the second virtual address are the first-level page table index bits, and the [19:0] bits are the segment offset bits. The MMU determines the sum 0X001 of the [31:20] bits 0X001 of the first virtual address and the base address 0X000 of the first-level page table as the first entry index address. The page table descriptor in the 0X001 entry can indicate that the first target physical address associated with 0x80100000 is 0x40100000. Of course, if the mapping level indication bits [1:0] of the page table descriptor are 01, it is determined that there is also a second-level page table. The [31 - 20] bits of the page table descriptor are the base address of the second-level page table. Correspondingly, the [31:20] bits in the second virtual address are the first-level page table index bits, the [19:12] bits are the second-level page table index bits, and the [11:0] bits are the page offset bits.

[0163] In another possible implementation, when the first page table is a secondary page table, the base address of the first page table can be determined based on the third page table, and the first entry index address can be determined based on the base address of the first page table and the second virtual address, where the third page table is the previous-level page table adjacent to the first page table.

[0164] Taking the first page table as the second-level page table and the third page table as the first-level page table as an example, the MMU can obtain the base address of the second-level page table from the page table descriptor in the third page table based on the granularity indication bit, obtain the second-level page table index bit from the first virtual address space, and determine the sum of the base address of the second-level page table and the second-level page table index bit as the first entry index address.

[0165] For example, the operating system in the electronic device is 32-bit. The MMU determines that the mapping level indication bits [1:0] of the page table descriptor corresponding to the first virtual address in the first-level page table are 01, that is, it is determined that there is also a second-level page table. Then, the [31-20] bits of the page table descriptor are obtained as the base address of the second-level page table, the [19:12] bits of the second virtual address are obtained as the second-level page table index bits, and the sum of the base address of the second-level page table and the second-level page table index bits is determined as the first table entry index address.

[0166] It should be noted that when the first page table is other secondary page tables, the method for determining the first table entry index address based on the second virtual address can be similar to the method when the first page table is the second-level page table, and will not be elaborated here one by one.

[0167] Method 2: The MMU determines the third table entry index address to be offset based on the first virtual address, and determines the first table entry index address based on the third table entry index address and the second offset value.

[0168] Among them, when the first page table is the first-level page table, the MMU can determine the base address of the first-level page table in a similar manner as described above, obtain the first-level page table index bits from the first virtual address, and determine the third table entry index address as the sum of the first-level page table index bits and the base address of the first-level page table. Then, the third table entry index address can be offset, including subtracting the second offset value from the third table entry index address, so as to obtain the first table entry index address.

[0169] It should be noted that the second offset value can be determined in advance, and the second offset value = the number of first table entries.

[0170] To illustrate Method 2 in detail, now refer to Figure 11, which is a schematic diagram of the logical relationship between a virtual address space, a page table, and a physical address space provided by an embodiment of the present application. The operating system in the electronic device is 32-bit, and the first virtual address space is the kernel-mode address space 501, with an address range of [0x80000000, 0xFFFFFFFF]. For the first virtual address 0x80100000 in the first virtual address space, the MMU can determine that the TTBR corresponding to the kernel-mode address space 501 is TTBR1, and obtain the base address of the first-level page table 801 from TTBR1 as 0X000. From the page table descriptor in the 0X000 entry, it can be seen that the mapping level indication bits [1:0] of the page table descriptor are 10, and the granularity indication bit

[18] is 0, so it is determined that the current is a first-level mapping, and the mapping granularity is 1MB. Therefore, the bits [31:20] in 0x80100000 of the first virtual address are the first-level page table index bits, and the bits [19:0] are the segment offset bits. The MMU adds the bits [31:20] 0X801 of the first virtual address and the base address 0X000 of the first-level page table to obtain 0X801 as the index address of the third entry, and then subtracts the difference between the index address of the third entry (0X801) and the number of the first entry 0X800 (the hexadecimal value corresponding to the binary value 2K) to obtain the index address of the first entry 0X001.

[0171] S904. The MMU determines the first target physical address corresponding to the first virtual address from the first page table according to the index address of the first entry.

[0172] Since the index address of the first entry is the index address of the entry corresponding to the first virtual address, the entry corresponding to the first virtual address in the first page table can be determined based on the index address of the first entry, and the first target physical address can be determined based on this entry.

[0173] When the first page table is the last-level page table (such as the first-level page table in the first-level mapping or the second-level page table in the second-level mapping), the page table descriptor in the entry corresponding to the index address of the first entry can indicate the base address of the first target physical address. Therefore, the MMU can obtain the base address of the first target physical address from the page table descriptor, and obtain the physical address offset bit from the first virtual address or the second virtual address, and add the base address of the first target physical address and the physical address offset bit to determine the first target physical address. When the first page table is not the last-level page table, the index address of the first entry can indicate the base address of the next-level page table. The MMU can continue to search for the index address of the first entry corresponding to the first virtual address in the next-level page table until the last-level page table is found, so as to determine the first target physical address. That is, the MMU can execute S903 and S904 at least once to sequentially obtain the first-level page table, the second-level page table, the third-level page table... to determine the first target physical address corresponding to the first virtual address.

[0174] It should be noted that when offsetting the first virtual address, the actually offset is at least one-level page table index bit in the first virtual address, while the physical address offset bit remains unchanged. Therefore, the MMU can obtain the physical address offset bit from the first virtual address or the second virtual address.

[0175] Please continue to refer to Figure 10 and Figure 11 , since the first page table is a one-level page table 801, the page table descriptor in the 0X001 entry of the one-level page table 801 indicates the base address 0x40100000 of the first target physical address corresponding to the first virtual address 0x80100000. And the [19:0] bits of the first virtual address 0x80100000 and the second virtual address are both 0, that is, the physical address offset bit is 0. Therefore, the first target physical address is 0x40100000 + 0x00000000 = 0x40100000. Of course, if the mapping level indication bit [1:0] of the page table descriptor is 01, it is determined that there is also a second-level page table. The [31-20] bits of the page table descriptor are the base address of the second-level page table, then S605 can be returned to determine the first target physical address from the second-level page table.

[0176] As can be seen from the foregoing, in the process of determining the first target physical address corresponding to the first virtual address, it may be necessary to search for page tables of multiple levels. The first page table may be any level of page table, that is, any page table may be offset. Then if the MMU first offsets the first virtual address to obtain the second virtual address, and then based on the second virtual address, determines the corresponding first table entry index address from the first page table, then no matter which page tables in the multiple levels of page tables are offset, at least as long as the first virtual address is offset once, the obtained second virtual address can match the offset page table. If the MMU first determines the third table entry index address from the first virtual address, and then offsets the third table entry index address to obtain the first table entry index address, then when determining the first table entry index address in each level of offset page table, the third table entry index address can be offset separately for that page table to obtain the first table entry index address.

[0177] S905, determine the third table entry index address corresponding to the first virtual address in the second page table corresponding to the first page table, and according to the third table entry index address, determine the second target physical address corresponding to the first virtual address from the second page table corresponding to the first page table.

[0178] Among them, the operation mode of S905 can be similar to that of the foregoing S903 and S904. The difference is that in S905, it is not necessary to offset the first virtual address or the third table entry address.

[0179] It should be noted that in the embodiments of the present application, the first page table is obtained by offsetting the entries in the second page table. Therefore, the first target physical address determined from the first page table through S903 - S904 and the second target physical address determined from the second page table through S905 can be the same. Only the first page table or the second page table can be stored in the memory of the electronic device. If the first page table is stored, the MMU can obtain the page table offset flag information in S902, and thus execute S903 - S904. If the second page table is stored, the MMU cannot obtain the page table offset flag information in S902, and thus execute S905.

[0180] It can be understood that if the MMU determines the first target physical address and the second target physical address from the same page table (the first page table or the second page table) based on S903 - S304 and S905 respectively, the determined first target physical address and second target physical address can be different.

[0181] In the embodiments of the present application, when the MMU obtains the first virtual address of the first virtual address space, it can determine the first table entry index address corresponding to the first virtual address in the first page table, and determine the first target physical address corresponding to the first virtual address from the first page table according to the first table entry index address. Since the first page table can be used to determine the physical address corresponding to each virtual address in the first virtual address space, the starting virtual address of the first virtual address space corresponds to the second table entry index address in the first page table, the second table entry index address is greater than or equal to the base address of the first page table and less than the sum of the quotient of the starting virtual address divided by the size of the second virtual address space and the base address of the first page table, and the maximum table entry index address of the first page table is less than the sum of the quotient of the maximum virtual address of the first virtual address space divided by the size of the second virtual address space and the base address of the first page table, and the second virtual address space is the virtual address space associated with any entry in the first page table, so the first page table can at least only include the entries actually required by the first virtual address space, thereby saving memory and improving the utilization rate of memory.

[0182] In addition, in the embodiments of the present application, the page table descriptors in the second page table including redundant entries are offset downward to reduce or eliminate the redundant entries, resulting in the first page table including fewer entries. In practical applications, to make the method of setting the page table and determining the physical address more flexible, the second page table can also be offset upward (i.e., in the high-address direction). In this case, the second page table can be any page table, and the number of the third entries to be offset upward can also be any value. The obtained first page table can include more entries. Correspondingly, when the MMU determines the first table entry index address corresponding to the first virtual address, the sum of the first virtual address and the first offset value can be determined as the second virtual address (i.e., the first virtual address is also offset in the high-address direction), and then the first table entry index address is determined based on the second virtual address. Alternatively, the third table entry index address to be offset can be determined based on the first virtual address, and the sum of the third table entry index address and the second offset value is determined as the first table entry index address (i.e., the third table entry index address is also offset in the high-address direction). When determining the first table entry index address, the first target physical address corresponding to the first virtual address is then determined from the first page table based on the first table entry index address.

[0183] Wherein, the first offset value = the number of the third entries * the size of the second virtual address space associated with each entry in the first page table, the second offset value = the number of the third entries, the first virtual address can be less than the second virtual address, and the third table entry index address can be less than the first table entry index address.

[0184] Based on the same inventive concept, an embodiment of the present application further provides a chip system 1200.

[0185] Please refer to Figure 12 , the chip system 1200 includes at least one CPU 110 ( Figure 12 only 1 is shown in Figure 12 ), at least one memory 115 ( Figure 12 only 1 is shown in Figure 12 ), and at least one coprocessor 116 ( Figure 12 only 1 is shown in Figure 12 ). At least one coprocessor 116 includes at least one MMU 111 ( Figure 12 only 1 is shown in

[0186] At least one MMU 111 is configured to:

[0187] When receiving an access request for at least one memory 115 initiated by at least one CPU 110 and the access request carries a first virtual address in the first virtual address space, determine the first table entry index address corresponding to the first virtual address;

[0188] According to the first table entry index address, determine the first target physical address corresponding to the first virtual address from the first page table;

[0189] Wherein, the first page table is used to determine the physical address corresponding to each virtual address in the first virtual address space, the starting virtual address of the first virtual address space corresponds to the second table entry index address in the first page table, the second table entry index address is greater than or equal to the base address of the first page table and less than the sum of the quotient of the starting virtual address divided by the size of the second virtual address space and the base address of the first page table, and the maximum table entry index address of the first page table is less than the sum of the quotient of the maximum virtual address of the first virtual address space divided by the size of the second virtual address space and the base address of the first page table, and the second virtual address space is the virtual address space associated with any table entry in the first page table.

[0190] Optionally, at least one ALU 112 is used to determine a second virtual address based on the first virtual address and the first offset value, and the first virtual address is greater than the second virtual address;

[0191] At least one MMU 110 is further used to: determine the first table entry index address based on the second virtual address.

[0192] Optionally, at least one MMU 110 is further used to:

[0193] Determine a third table entry index address to be offset based on the first virtual address;

[0194] Determine the first table entry index address based on the third table entry index address and the second offset value, and the third table entry index address is greater than the first table entry index address.

[0195] Optionally, at least one MMU 110 is further used to:

[0196] Obtain page table offset flag information, and the page table offset flag information is indicated by an offset indication bit in at least one TTBCR 113.

[0197] Optionally, each TTBR 114 can store the base address of a first-level page table. Correspondingly, TTBCR 113 can be used to indicate the TTBR 114 selected when determining the physical address corresponding to the virtual address in different virtual address spaces, that is, to determine the TTBR 114 corresponding to different virtual address spaces.

[0198] Optionally, at least one coprocessor 116 can be integrated in at least one CPU 1210.

[0199] It should be noted that the memory 115 may include Figure 1 the internal memory 121 in

[0200] Please refer to Figure 13 , the structural schematic diagram of another chip system 1300 provided by the embodiments of the present application. The system 1300 includes a CPU 110, an ALU 112, a TTBCR 113, a virtual memory translation module 117, and a memory 115. Among them, the TTBCR 113, the ALU 112, and the virtual memory translation module 117 may be disposed in the MMU 111, and the MMU 111 may be disposed in a coprocessor or integrated in the CPU 110.

[0201] The CPU 110 may issue an access request to the memory 115, and the first virtual address in the kernel mode address space is carried in the access request. When the ALU 112 obtains the first virtual address and determines that the offset indication bit in the TTBCR 113 is the first indicator (such as offset1), the first virtual address is offset to the second virtual address. The virtual memory translation module 117 determines the first table entry index address based on the second virtual address from the set of page tables corresponding to the kernel mode address space, and further determines the first target physical address, and the CPU 110 can access the internal memory 1350 based on the first target physical address.

[0202] It should be noted that the ALU 112, the TTBCR 113, and the virtual memory translation module 117 may be disposed in the MMU 111, and the MMU 111 may further include a TTBR 114.

[0203] It should also be noted that the virtual memory translation module 117 may be used to determine the first table entry index address based on the third table entry index address and the second offset value.

[0204] Based on the same inventive concept, the embodiments of the present application further provide an electronic device, and the electronic device includes the chip system of any one of the foregoing.

[0205] The embodiments of the present application further provide a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the method described in the foregoing method embodiments is implemented.

[0206] The embodiments of the present application further provide a computer program product, and when the computer program product runs on an electronic device, the electronic device is caused to execute the method described in the foregoing method embodiments.

[0207] When the above integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, to implement all or part of the processes in the above method embodiments of this application, a computer program can be used to instruct relevant hardware to complete. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps of the above method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file or some intermediate form, etc. The computer-readable storage medium can at least include: any entity or device, recording medium, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium that can carry the computer program code to the photographing device / terminal device. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disc, etc. In some jurisdictions, according to legislation and patent practice, computer-readable media may not be electrical carrier signals and telecommunication signals.

[0208] In the above embodiments, the descriptions of the various embodiments have their own emphases. For the parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0209] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0210] In the embodiments provided in this application, it should be understood that the disclosed device / equipment and method can be implemented in other ways. For example, the device / equipment embodiments described above are only illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical or other forms.

[0211] It should be understood that, as used in the specification of the present application and the appended claims, the term "comprising" indicates the presence of the described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or their combinations.

[0212] It should also be understood that the term "and / or" as used in the specification of the present application and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0213] As used in the specification of the present application and the appended claims, the term "if" may be construed, depending on the context, as "when", "once", "in response to determining", or "in response to detecting". Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be construed, depending on the context, as meaning "once determined", "in response to determining", "once [the described condition or event] is detected", or "in response to detecting [the described condition or event]".

[0214] In addition, in the description of the specification of the present application and the appended claims, the terms "first", "second", "third", etc. are used only for descriptive distinction and should not be construed as indicating or implying relative importance.

[0215] Reference to "one embodiment" or "some embodiments" or the like described in the specification of the present application means that a specific feature, structure, or characteristic described in connection with that embodiment is included in one or more embodiments of the present application. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc. that appear in different places in this specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in another way. The terms "comprising", "including", "having", and their variants all mean "including but not limited to", unless otherwise specifically emphasized in another way.

[0216] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and are not intended to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for determining a physical address, characterized in that Including: When a first virtual address of a first virtual address space is obtained, determining a first table entry index address corresponding to the first virtual address; According to the first table entry index address, determining a first target physical address corresponding to the first virtual address from a first page table; Wherein, the first page table is used to determine a physical address corresponding to each virtual address in the first virtual address space, a starting virtual address of the first virtual address space corresponds to a second table entry index address in the first page table, the starting virtual address is greater than 0, the second table entry index address is greater than or equal to a base address of the first page table and less than a sum of a quotient of the starting virtual address divided by a size of a second virtual address space and the base address of the first page table, a maximum table entry index address of the first page table is less than a sum of a quotient of a maximum virtual address of the first virtual address space divided by the size of the second virtual address space and the base address of the first page table, and the second virtual address space is a virtual address space associated with any table entry in the first page table.

2. The method according to claim 1, wherein The determining the first table entry index address corresponding to the first virtual address includes: Based on the first virtual address and a first offset value, determining a second virtual address, the first virtual address being greater than the second virtual address; Based on the second virtual address, determining the first table entry index address.

3. The method according to claim 1, wherein The determining the first table entry index address corresponding to the first virtual address includes: Based on the first virtual address, determining a third table entry index address to be offset; Based on the third table entry index address and a second offset value, determining the first table entry index address, the third table entry index address being greater than the first table entry index address.

4. The method according to any one of claims 1 to 3, characterized in that Before the determining the first table entry index address corresponding to the first virtual address, the method further includes: Obtaining page table offset flag information, the page table offset flag information being indicated by an offset indication bit in a translation page table base control register TTBCR.

5. The method according to claim 4, characterized in that The first page table includes: a first-level page table or a second-level page table; or, The first virtual address space is a kernel-mode address space.

6. The method according to any one of claims 1-3, characterized in that, The first page table includes: a first-level page table or a second-level page table; or, The first virtual address space is a kernel-mode address space.

7. A chip system, characterized in that, The chip system includes: at least one central processing unit CPU, at least one memory, and at least one coprocessor, and the at least one coprocessor includes: at least one memory management unit MMU; The at least one MMU is configured to: When receiving an access request initiated by the at least one CPU to the at least one memory, and the access request carries a first virtual address of a first virtual address space, determining a first table entry index address corresponding to the first virtual address; According to the first table entry index address, determining a first target physical address corresponding to the first virtual address from a first page table; Among them, the first page table is used to determine the physical address corresponding to each virtual address in the first virtual address space. The starting virtual address of the first virtual address space corresponds to the second table entry index address in the first page table. The starting virtual address is greater than 0. The second table entry index address is greater than or equal to the base address of the first page table and less than the sum of the quotient of the starting virtual address divided by the size of the second virtual address space and the base address of the first page table. The maximum table entry index address of the first page table is less than the sum of the quotient of the maximum virtual address of the first virtual address space divided by the size of the second virtual address space and the base address of the first page table. The second virtual address space is the virtual address space associated with any table entry in the first page table.

8. The chip system according to claim 7, wherein The at least one MMU includes at least one arithmetic logic unit ALU: The at least one ALU is used to determine a second virtual address based on the first virtual address and a first offset value, where the first virtual address is greater than the second virtual address; The at least one MMU is further used to: determine the first table entry index address based on the second virtual address.

9. The chip system according to claim 7, wherein The at least one MMU is further used to: Determine a third table entry index address to be offset based on the first virtual address; Determine the first table entry index address based on the third table entry index address and a second offset value, where the third table entry index address is greater than the first table entry index address.

10. The chip system according to any one of claims 7-9, characterized in that, The at least one MMU further includes at least one translation page table base address control register TTBCR. The at least one MMU is further used to: Obtain page table offset flag information, where the page table offset flag information is indicated by an offset indication bit in the at least one TTBCR.

11. An electronic device, characterized in that, Including the chip system according to any one of claims 7 to 10.

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