Motherboards and electronic equipment

Abstract

The present invention provides a motherboard and electronic device. The motherboard includes a PCB board, which integrates an interconnected CPU chip and DDR circuit. The CPU chip has a built-in DDR controller. The CPU chip is provided with a DDR interface for external connection of the DDR controller. The signal end of the DDR circuit is directly connected to the DDR interface via metal traces. The DDR circuit is arranged on the front side of the PCB board, and a DDR signal test point is provided on the back side of the PCB board, opposite the position of the DDR circuit. The present invention can test the signal quality of the DDR interface of the CPU chip.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic equipment mainboards, and in particular to a mainboard and electronic equipment. Background Art

[0002] Many issues related to DDR (Double Data Rate SDRAM) have been discovered in actual motherboard applications. However, because existing motherboard memory modules lack test points and DDR chips are packaged in a ball grid array (BGA) package, with solder joints hidden beneath the DDR chips, testing and locating DDR interface issues is challenging. When using an oscilloscope to observe the actual signal waveform, especially when the DDR interface signal rate is low, the oscilloscope probe cannot get close enough to the actual DDR chip pins, making it impossible to observe the true signal waveform quality at those pins. Furthermore, because memory modules are typically DIMMs (Dual-Inline-Memory-Modules), connected to the CPU via a DIMM slot connector, interference introduced by the DIMM slot connector cannot be eliminated when observing the signal waveform with an oscilloscope. To address these issues, better observe DDR signal quality, and identify the root causes of DDR signal rate and other issues, a new motherboard structure is necessary. Summary of the Invention

[0003] To solve the above problems, the present invention provides a motherboard and an electronic device suitable for testing the signal quality of the DDR interface of a CPU chip.

[0004] In a first aspect, the present invention provides a motherboard, comprising a PCB board, wherein an interconnected CPU chip and a DDR circuit are integrated on the PCB board, and the CPU chip has a built-in DDR controller, wherein:

[0005] The CPU chip is provided with a DDR interface for connecting the DDR controller to the outside world;

[0006] The signal end of the DDR circuit is directly connected to the DDR interface through a metal trace;

[0007] Furthermore, the DDR circuit is arranged on the front side of the PCB board, and a DDR signal test point is set on the back side of the PCB board at a position corresponding to the DDR circuit.

[0008] Optionally, the DDR circuit adopts RDIMM mode.

[0009] Optionally, the DDR circuit includes two groups of DDR particles, an RCD chip and an SPD chip, wherein:

[0010] Each group of DDR particles includes multiple DDR particles, wherein the data signal of each DDR particle is directly connected to the DDR interface;

[0011] The RCD chip is used to divide a set of command and address signals connected to the DDR interface into two identical sets of command and address signals, each of which is connected to a set of DDR chips, and distribute clock signals and chip select signals to the two sets of DDR chips;

[0012] The SPD chip is connected to the RCD chip via the SMBUS bus and is also connected to the SMBUS interface of the CPU chip.

[0013] Optionally, the two groups of DDR particles include a total of 18 DDR particles, one group includes 10 DDR particles, 8 DDR particles are used to transmit data signals, and 2 DDR particles are used to transmit ECC signals; the other group includes 8 DDR particles for transmitting data signals.

[0014] Optionally, the 18 DDDR chips adopt a 2Rank design and are numbered sequentially from 0 to 17, with all even-numbered DDR chips constituting a first Rank and all odd-numbered DDR chips constituting a second Rank;

[0015] The first Rank is arranged in one column, the second Rank is arranged in another column, and the DDR chip in the middle of each column is used to transmit 8-bit ECC signals, and the 8 DDR chips on both sides are used to transmit 64-bit data signals;

[0016] Two DDR particles used to transmit 8-bit ECC signals together with the 8 DDR particles on one side constitute a group of DDR particles, and the 8 DDR particles on the other side of the two DDR particles used to transmit 8-bit ECC signals together constitute another group of DDR particles.

[0017] Optionally, the 18 DDDR particles are arranged on the front side of the PCB board, and DDR signal test points are set on the back side of the PCB board relative to the positions of the 18 DDR particles.

[0018] Optionally, the CPU chip is arranged on the front side of the PCB board, a via hole is provided next to the pin of the DDR interface, and the back side of the via hole serves as a DDR interface signal test point.

[0019] Optionally, the CPU chip is further provided with the following interfaces, including:

[0020] 2 PCIe x16 interfaces, used to connect 2 PCIe x16 slots;

[0021] 4 SATA interfaces for connecting standard SATA disks;

[0022] PCIe x2 interface, used to connect a Gigabit network chip I350;

[0023] 2 USB ports.

[0024] Optionally, a BMC chip is integrated on the PCB board, and the BMC chip is interconnected with the CPU chip via an SPI interface, an LPC interface, and a USB interface.

[0025] In a second aspect, the present invention provides an electronic device, comprising the above-mentioned mainboard.

[0026] The motherboard and electronic device provided by the present invention are suitable for testing the signal quality of a CPU chip's DDR interface. Because the DDR circuit is directly integrated onto the motherboard, eliminating connector access and eliminating connector influences, it facilitates testing the maximum performance of the CPU chip's DDR interface. Signal quality can be better observed using an oscilloscope, enabling comparative studies between signal testing and performance testing. Furthermore, integrating the DDR circuit onto the motherboard offers greater vibration resistance than a slot, resulting in higher system reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a schematic diagram of the mainboard frame structure according to an embodiment of the present invention;

[0028] Figure 2 This is a schematic diagram of the mainboard PCB layout according to an embodiment of the present invention;

[0029] Figure 3 This is a schematic diagram of the mainboard frame structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0031] The following embodiments of the present invention are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0032] Figure 1 FIG1 shows a schematic diagram of a frame structure of a motherboard provided by an embodiment of the present invention. The motherboard includes a PCB (Printed Circuit Board), hereinafter referred to as a PCB board. Figure 1 As shown, the PCB board integrates an interconnected CPU chip and DDR circuit. The CPU chip has a built-in DDR controller. The CPU chip is provided with a DDR interface for external connection of the DDR controller. The signal end of the DDR circuit is directly connected to the DDR interface through a metal trace. In addition, the DDR circuit is arranged on the front side of the PCB board, and a DDR signal test point is set on the back side of the PCB board relative to the position of the DDR circuit.

[0033] As an implementation method, the DDR circuit of this embodiment can use RDIMM (Registered DIMM). RDIMM adds a register to the memory module for transmission. This register is located between the CPU and the DDR chip, which reduces the distance of parallel transmission while ensuring the effectiveness of parallel transmission. Due to the high efficiency of the register, the capacity and frequency of RDIMM are easier to increase than unbuffered DIMM.

[0034] Specifically, refer to Figure 1 The DDR circuit in RDIMM mode includes two groups of DDR particles, one RCD chip and one SPD chip. The RCD chip, namely Registering Clock Driver, is a clock buffer register chip, which is used to cache the command and address signals of the DDR controller, split the command and address signals from the DDR controller into two, and reduce the delay of the command and address signals to the DDR particles. The SPD chip, namely Serial Presence Detect, is an erasable memory that records a lot of important information about the DDR circuit: one type is basic parameters, such as frequency, capacity, timing, etc.; the other type is information such as the memory module serial number and manufacturer code. SPD information is generally written into the SPD chip by the manufacturer based on the actual performance of the memory before leaving the factory.

[0035] Among them, the two groups of DDR particles include a total of 18 DDR particles, which can be recorded as Group A and Group B. Group A includes 10 DDR particles, of which 8 DDR particles are used to transmit data signals, and the other 2 DDR particles are used to transmit ECC (Error Correcting Code) signals. Group B includes 8 DDR particles for transmitting data signals. The data signal (including ECC signal) of each DDR particle is directly connected to the CPU DDR interface without any conversion.

[0036] A set of command and address signals connected to the DDR interface of the CPU chip are divided into two groups, A and B, through the RCD chip. Group A's command and address signals are connected to drive the 10 DDR particles in group A. Group B's command and address signals are connected to drive the 8 DDR particles in group B. Using the RCD chip to divide a set of Command & Address (command and address) signals transmitted from the CPU chip into two identical groups of command and address signals, which respectively drive the two groups of DDR particles on both sides, can optimize the signal wiring of the DIMM memory stick, enhance the signal driving capability, and achieve an increase in the DDR interface rate. Currently, the data rate of the DDR4RDIMM memory stick can reach 3200MT / s. In addition, the RCD chip is also used to distribute clock signals and chip select signals to the two groups of DDR particles. Reference Figure 1 , chip select signal CS0_A and clock signal CLK0 are connected to DDR8, DDR10, DDR12, DDR14 and DDR16, chip select signal CSI_A and clock signal CLK1 are connected to DDR9, DDR11, DDR13, DDR15 and DDR17, chip select signal CS0_B and clock signal CLK2 are connected to DDR0, DDR2, DDR4 and DDR6, chip select signal CS1_B and clock signal CLK3 are connected to DDR1, DDR3, DDR5 and DDR7.

[0037] In addition, the SPD chip is connected to the RCD chip via the SMBUS (System Management Bus), and then to the SMBUS interface of the CPU chip. This allows you to configure DDR chips directly through the CPU's DDR interface, or you can write configuration data to the SPD chip and configure the DDR chips through the SPD chip.

[0038] Of course, DDR circuits are not limited to RDIMMs. For example, LRDIMMs (Load Reduced DIMMs) can also be used. Compared to RDIMMs, LRDIMMs do not use complex registers, but rather simple buffering. This buffering reduces the power load on the underlying motherboard but has little impact on memory performance. Furthermore, LRDIMM memory replaces the register chip on RDIMM memory with an iMB (isolation memory buffer) memory isolation buffer chip, which directly reduces the memory bus load and further increases memory support capacity.

[0039] The motherboard provided by the embodiment of the present invention is suitable for testing the signal quality of the DDR interface of the CPU chip. Since the DDR circuit is directly integrated into the motherboard and is not connected through a connector, the influence introduced by the connector is eliminated, which makes it convenient to test the maximum performance of the CPU chip DDR interface. The signal quality can be better observed with an oscilloscope, and a comparative study of signal testing and performance testing can be achieved. At the same time, the DDR circuit is integrated into the motherboard, and the vibration resistance is stronger than the slot, and the system reliability is higher. The design method of integrating RCD and DDR circuits on the motherboard can also be applied to designs that require the integration of DDR controllers and DDR particles on the same PCB board, for example, in high-reliability system designs such as VPX (VPX is a next-generation advanced computing platform standard developed by the VITA organization to meet the high reliability and high bandwidth requirements in harsh environments), CPU chip external DDR design, FPGA external DDR design, and embedded DDR design. That is, the present invention is not only applicable to the testing field, but can also be applied to actual product system design.

[0040] Furthermore, the 18 DDR particles adopt a 2Rank design. Rank refers to a 64-bit unit composed of multiple DDR particle data bits, which is accessed through a CS chip select signal. For ECC DIMM, a memory Rank has 72 data bits, including 64 bits of data + 8 bits of ECC. In this embodiment, the 18 DDR particles are numbered from 0 to 17. All even-numbered DDR particles constitute the first Rank, including DDR0, DDR2, DDR4, DDR6, DDR8, DDR10, DDR12, DDR14, DDR16, recorded as Rank0, and DDR8 in Rank0 is an ECC particle. All odd-numbered DDR particles constitute the second Rank, including DDR1, DDR3, DDR5, DDR7, DDR9, DDR11, DDR13, DDR15, DDR17, recorded as Rank1, and DDR9 in Rank1 is an ECC particle.

[0041] Specifically, in terms of layout and grouping, the first rank is arranged in one column, the second rank is arranged in one column, and the one DDR chip in the middle of each column is used to transmit an 8-bit ECC signal, and the eight DDR chips on both sides are used to transmit a 64-bit data signal. Specifically, DDR0 and DDR1 transmit data signals DQ[7:0], DDR2 and DDR3 transmit data signals DQ[15:8], DDR4 and DDR5 transmit data signals DQ[23:16], DDR6 and DDR7 transmit data signals DQ[31:24], DDR8 and DDR9 transmit data signals ECC[7:0], DDR10 and DDR11 transmit data signals DQ[39:32], DDR12 and DDR13 transmit data signals DQ[47:40], DDR14 and DDR15 transmit data signals DQ[55:48], and DDR16 and DDR17 transmit data signals DQ[63:56].

[0042] When grouping, two DDR chips transmitting 8-bit ECC signals and the eight DDR chips on one side form Group A, while the eight DDR chips on the other side of the two DDR chips transmitting 8-bit ECC signals form Group B. That is, DDR8-17 is Group A, and DDR0-7 is Group B. The 18 DDR chips are arranged on the front of the PCB, with DDR signal test points located on the back of the PCB, corresponding to the 18 DDR chips. This design facilitates signal quality testing.

[0043] Similarly, the CPU chip is placed on the front of the PCB, and DDR interface signal test points are located on the back of the CPU, allowing for convenient monitoring of signal quality at both the transmitter and receiver ends using an oscilloscope or other tools. The test points are designed using DDR chips. Vias are drilled directly next to the CPU chip pins to the back, with copper exposed in the back vias as test points. This allows for signal quality testing at these test points using an oscilloscope. The short distance between the oscilloscope probe and the actual chip pins ensures accurate measurement of the signal waveform quality at the chip pins. Figure 2 Shows the layout of the mainboard PCB and the distribution of test points. Figure 2 The distribution of CPU, RCD and DDR0-17 is shown, where the black dots inside CPU, RCD and DDR0-17 represent signal test points, which are designed according to the pin distribution of the chip.

[0044] The above embodiment is a 1DPC (there is one RCD on one DDR circuit, that is, one DDR controller on the motherboard is externally connected to one DDR circuit), 2Rank design, which can also be expanded to a 2DPC (one DDR controller on the motherboard is externally connected to two DDR circuits) design, that is, a 2DPC, 1R design, or a 2DPC, 2R design.

[0045] In addition, you can refer to Figure 3 In addition to the DDR interface for connecting to the DDR circuit, the CPU chip is also designed with the following interfaces:

[0046] 2 PCIe x16 interfaces, used to connect to 2 PCIe x16 slots, which can be used to insert standard PCIe cards;

[0047] 4 SATA interfaces for connecting standard SATA disks;

[0048] PCIe x2 interface, connected to an external Gigabit network chip I350, I350 outputs 2-way Gigabit electrical network port;

[0049] 2 USB ports, integrated support for USB2.0 and USB3.0 standards.

[0050] In addition, the motherboard also integrates a BMC (Baseboard Manager Controller) chip, which serves as the motherboard's management unit and is connected to the CPU through interfaces such as PCIe x1, LPC (Low Pin Count), USB, and SPI (Serial Peripheral Interface). The BMC chip includes the following peripheral interfaces:

[0051] Gigabit RJ45 port: Remote management port, implemented by connecting the BMC chip to an external Gigabit PHY chip. The remote management platform manages the motherboard over a Gigabit network.

[0052] COM interface: serial port interface;

[0053] VGA interface: display interface, connected to display device;

[0054] LED port80: connect to digital tube to display CPU status;

[0055] FAN CON[1:8]: Fan control interface, controls fan speed;

[0056] SD Card: SD card interface, storing server log information;

[0057] In addition, BMC FW (Firmware) is the BMC system's own firmware, which is stored in the BMC FW Flash.

[0058] The interconnection relationship between the BMC chip and the CPU chip includes:

[0059] SPI interconnection: The CPU BIOS can be switched between connecting to the BMC and the CPU via the SPI SW (Switch). When upgrading the BIOS firmware, the connection is switched to the BMC. During normal boot and operation, the connection is switched to the CPU. This allows the CPU BIOS firmware to be upgraded via a remote management platform. The remote management platform sends the new BIOS to the BMC via the BMC's Gigabit RJ45 port. The BMC then burns the new BIOS to the BIOS chip, and then switches to the CPU via the SPI SW. The CPU then boots up and uses the new BIOS firmware.

[0060] LPC interconnection: The LPC interface between the BMC and the CPU transmits CPU startup status information to the BMC, which is then displayed on LED PORT 80 connected to the BMC. It also connects to the CPLD (Complex Programmable Logic Device) to inform the CPLD of the current CPU startup status.

[0061] USB interconnection: The USB port between the BMC and the CPU is used to implement remote virtual machines. That is, the remote management platform is connected to the BMC through the BMC Gigabit RJ45 network port, and then connected to the CPU through the BMC USB port to implement remote virtual machines.

[0062] On the other hand, an embodiment of the present invention further provides an electronic device, which includes the mainboard of the above embodiment.

[0063] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A motherboard, characterized in that: The mainboard includes a PCB board, on which an interconnected CPU chip and a DDR circuit are integrated, the DDR circuit includes a plurality of DDR particles, and the CPU chip has a built-in DDR controller, wherein: The CPU chip is provided with a DDR interface for connecting the DDR controller to the outside world; The signal end of the DDR circuit is directly connected to the DDR interface through a metal trace; Furthermore, the DDR particles are arranged on the front side of the PCB board, and DDR signal test points are set on the back side of the PCB board relative to the positions of the DDR particles.

2. The motherboard according to claim 1, wherein: The DDR circuit adopts RDIMM mode.

3. The mainboard according to claim 2, wherein: The DDR circuit also includes an RCD chip and an SPD chip, wherein: The multiple DDR particles are divided into two groups, wherein the data signal of each DDR particle is directly connected to the DDR interface; The RCD chip is used to divide a set of command and address signals connected to the DDR interface into two identical sets of command and address signals, each of which is connected to a set of DDR chips, and distribute clock signals and chip select signals to the two sets of DDR chips; The SPD chip is connected to the RCD chip via an SMBUS bus and is connected to the SMBUS interface of the CPU chip. The SPD chip stores the configuration data of the DDR particles.

4. The mainboard according to claim 3, wherein: The two groups of DDR particles include a total of 18 DDR particles, one group includes 10 DDR particles, 8 DDR particles are used to transmit data signals, and 2 DDR particles are used to transmit ECC signals; the other group includes 8 DDR particles for transmitting data signals.

5. The mainboard according to claim 4, wherein: The 18 DDR chips adopt a 2-rank design and are numbered from 0 to 17. All even-numbered DDR chips constitute the first rank, and all odd-numbered DDR chips constitute the second rank. The first Rank is arranged in one column, the second Rank is arranged in another column, and the DDR chip in the middle of each column is used to transmit 8-bit ECC signals, and the 8 DDR chips on both sides are used to transmit 64-bit data signals; Two DDR particles used to transmit 8-bit ECC signals together with the 8 DDR particles on one side constitute a group of DDR particles, and the 8 DDR particles on the other side of the two DDR particles used to transmit 8-bit ECC signals together constitute another group of DDR particles.

6. The mainboard according to claim 5, characterized in that: The 18 DDR chips are arranged on the front side of the PCB board, and DDR signal test points are set on the back side of the PCB board relative to the positions of the 18 DDR chips.

7. The mainboard according to claim 1, wherein: The CPU chip is arranged on the front side of the PCB board, a via hole is provided next to the pin of the DDR interface, and the back side of the via hole serves as a DDR interface signal test point.

8. The mainboard according to claim 1, wherein: The CPU chip is also provided with the following interfaces, including: 2 PCIe x16 interfaces, used to connect 2 PCIe x16 slots; 4 SATA interfaces for connecting standard SATA disks; PCIe x2 interface, used to connect a Gigabit network chip I350; 2 USB ports.

9. The mainboard according to claim 1, wherein: The PCB board is integrated with a BMC chip, and the BMC chip is interconnected with the CPU chip via an SPI interface, an LPC interface, and a USB interface.

10. An electronic device, characterized in that: The electronic device comprises the mainboard according to any one of claims 1 to 9.

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