Spaceborne high performance computing module system

Abstract

The application provides a kind of spaceborne high-performance computing module system, including CPU processing unit, FPGA control unit, storage unit and communication unit, wherein: the CPU processing unit is connected with FPGA control unit, and FPGA control unit, storage unit and communication unit are controlled and resource allocation by LocalBus bus;The data sent by the CPU processing unit is sent to external equipment after being processed by the FPGA control unit;The storage unit stores the program of CPU processing unit and the program of FPGA control unit;The communication unit is used to realize internal RapidIO interface and serial port.The application runs a "3+1" working mode under the premise of meeting high performance, provides a two-out-of-three scheme for application data, and solves the reliability problem of high-performance processors on commercial satellites.The application provides a hardware structure for realizing the reliability of high-performance processors.

Description

Technical Field

[0001] This invention relates to the field of spaceborne satellites, and more specifically, to a spaceborne high-performance computing module system. Background Technology

[0002] To meet the high reliability requirements of commercial satellites for onboard embedded computers, a 3CPU+FPGA architecture was adopted. Under the premise of high performance, a "3+1" working mode was implemented, providing a two-out-of-three solution for application data and supporting online reconfiguration technology for CPU and FPGA software.

[0003] Patent document CN103853561B discloses an embedded spaceborne software reconfiguration system and method. The system includes a loading table, an external interface unit, a private data definition unit, and a private data operation implementation unit. The loading table contains information data from multiple software modules. The external interface unit includes a data operation interface for responding to user commands and an interface providing encapsulated interface functions. The private data definition unit defines the structure of the data in the loading table. The private data operation implementation unit operates the loading table according to ground commands via encapsulated interface functions and performs dynamic space-to-ground loop reconfiguration of the software based on the information provided in the loading table. However, this solution cannot meet the high reliability requirements of commercial satellites for spaceborne embedded computers. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of this invention is to provide a spaceborne high-performance computing module system.

[0005] According to the present invention, a spaceborne high-performance computing module system includes a CPU processing unit, an FPGA control unit, a storage unit, and a communication unit, wherein:

[0006] The CPU processing unit is connected to the FPGA control unit through a high-speed RapidIO interface, and manages and allocates resources to the FPGA control unit, storage unit and communication unit through the LocalBus bus.

[0007] The FPGA control unit processes the data sent by the CPU processing unit and then sends it to an external device.

[0008] The storage unit stores the CPU processing unit program and the FPGA control unit program;

[0009] The communication unit is used to implement the internal RapidIO interface and serial port.

[0010] Preferably, the CPU processing unit includes three P2020 processor chips, each of which is connected to a FIFO of the FPGA control unit.

[0011] Preferably, the CPU processing unit includes a DDR memory controller with attached memory chips.

[0012] Preferably, the FPGA control unit includes a refresh chip and an SRAM-type FPGA chip, wherein:

[0013] The refresh chip is used to reload, read back, and refresh the FPGA software;

[0014] SRAM-type FPGA chips are used for switching between CPU processing units and storage units, and for controlling the sequential startup of the three CPU processing units.

[0015] Preferably, the SRAM-type FPGA chip is externally extended with DDR3 memory for the management and use of the memory units.

[0016] Preferably, the SRAM-type FPGA chip includes a Kintex-7 chip, and the refresh chip includes a JFMSR01RH chip.

[0017] Preferably, the storage unit includes a memory for the CPU program and a memory for the FPGA program, wherein:

[0018] The CPU program's memory contains two FLASH chips, both mounted on an SRAM-type FPGA chip. One is an aerospace-grade FLASH chip with a size of 8MB, and the other is an industrial-grade FLASH chip with a size of 32MB. The aerospace-grade FLASH chip stores one copy of the CPU's bootloader, operating system, and application program, while the industrial-grade FLASH chip stores four identical copies of the CPU's bootloader and application program.

[0019] The memory of an FPGA program includes a main memory and a backup memory connected to a refresh chip. The refresh chip enables the switching between the main and backup FLASH memory and the reconstructing of the program.

[0020] Preferably, the RapidIO interface is a 2-way 1X interface with a speed of 3.125Gbps.

[0021] Preferably, it also includes an external GTX interface, which is a 1-way 1X interface that implements the Aurora protocol, using the Xilinx Aurora 64B / 66B protocol, with a speed of 6.25Gbps.

[0022] Preferably, the FPGA control unit performs a 2-out-of-3 operation on the data sent by the CPU processing unit and then sends the data to an external device through the Aurora interface.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] 1. This invention adopts a 3CPU+FPGA structure to run a "3+1" working mode while meeting high performance requirements. It provides a two-out-of-three solution for application data, thus solving the reliability problem of high-performance processors on commercial satellites.

[0025] 2. This invention provides a hardware structure for achieving high-performance processor reliability, providing a hardware foundation for software architecture. Attached Figure Description

[0026] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0027] Figure 1 This is a schematic diagram of the spaceborne high-performance computing module system of the present invention. Detailed Implementation

[0028] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0029] like Figure 1 As shown, according to the present invention, a spaceborne high-performance computing module system comprises hardware products and supporting software. The hardware consists of a high-performance processing unit, an FPGA control unit, a storage unit, and a communication unit. The software includes boot software, a board support package (BSP), and FPGA control software. The software components are existing, relatively mature solutions and will not be described in detail here.

[0030] The high-performance processing unit of this invention employs three NXP P2020 high-performance, low-power processors, with a maximum clock speed of 1GHz and a maximum power consumption of 5W. These processors are manufactured using a 45nm process and integrate two high-performance processor cores on a single chip. The three CPUs operate simultaneously, primarily responsible for data processing, algorithm execution, and high-speed RapidIO interface connectivity with the FPGA. The FPGA control unit, storage unit, and communication unit are managed and resource-allocated via the LocalBus bus. The memory chip is connected to the DDR memory controller of the P2020 processor and provides network and serial port debugging interfaces.

[0031] The FPGA control unit uses a refresh chip and an SRAM-type FPGA chip (Fudan Microelectronics' Kintex-7 series). The refresh chip mainly implements the reloading, reading back and refreshing of the FPGA software. The FPGA is mainly responsible for the connection between the CPU processing unit and the storage unit, the sequential startup control of the three CPU processors, the two-out-of-three algorithm data selection, external expansion of DDR3 memory, management and use of the storage unit, and is also responsible for the control and implementation of the GTX interface.

[0032] The storage unit mainly includes storage for the CPU program and the FPGA program. The CPU program memory comprises two FLASH chips: one aerospace-grade (8MB) and one industrial-grade (32MHz). The aerospace-grade FLASH stores one copy of the CPU's bootloader, operating system, and application programs, while the industrial-grade FLASH stores four identical copies. The CPU boots from the aerospace-grade FLASH by default upon power-up. If booting fails, it selects two out of three files from the industrial-grade FLASH to boot from, thus improving CPU boot reliability. Both FLASH chips are connected to the FPGA and accessed via the LocalBus bus. The FPGA handles CPU boot configuration. The FPGA program memory consists of two chips, acting as primary and backup for each other, connected to a refresh chip. The refresh chip enables primary / backup switching of the FLASH and program reconfiguration.

[0033] The communication interface unit primarily implements an internal RapidIO interface and two serial ports. The RapidIO interface consists of two 1X channels with a speed of 3.125Gbps, while the external GTX interface is a single 1X channel implementing the Aurora protocol, using the Xilinx Aurora64B / 66B protocol, with a speed of 6.25Gbps. The two serial ports are used for CPU program refactoring and FPGA program refactoring interfaces, respectively.

[0034] The implementation scheme of the present invention is as follows:

[0035] After the module powers on, the refresh chip resets and reads the FPGA program from the main FLASH to load the FPGA. After the FPGA starts up, first, CPU1 reads the CPU boot program from the aerospace-grade FLASH through the interface implemented by the FPGA. After the boot program starts, the operating system is loaded. After the operating system starts up, it sends a startup completion flag to the FPGA. Then, CPU2 reads the CPU program from the aerospace-grade FLASH through the interface implemented by the FPGA. After it starts up, it sends a startup completion flag to the FPGA. Then, CPU3 reads the CPU program from the aerospace-grade FLASH through the interface implemented by the FPGA. After it starts up, it sends a startup completion flag to the FPGA. After the FPGA receives the startup completion flags from the three CPUs, the three CPUs start the application program simultaneously to ensure the synchronous operation of the application program.

[0036] When three CPUs run the same algorithm simultaneously, they send data to the three FIFOs of the FPGA via the RapidIO interface. The FPGA performs a two-out-of-three operation on the data from the three FIFOs and then sends the data to the external device via the Aurora interface. Upon receiving data, the FPGA first buffers the data from the Aurora interface in the extended DDR3 memory, and then sends it to the three CPUs simultaneously for processing.

[0037] The FPGA software is stored on two FLASH chips connected to the refresh chip's interface. Upon power-on, the refresh chip reads data from the primary FLASH chip to load the FPGA. If the primary FLASH fails to load the FPGA, it automatically switches to the backup FLASH. The FLASH program can be updated via the refresh chip's serial port. The refresh function can also be controlled via the serial port to adjust the refresh on / off state and frequency.

[0038] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A spaceborne high-performance computing module system, characterized in that, It includes a CPU processing unit, an FPGA control unit, a storage unit, and a communication unit, wherein: The CPU processing unit is connected to the FPGA control unit through a high-speed RapidIO interface, and manages and allocates resources to the FPGA control unit, storage unit and communication unit through the LocalBus bus. The FPGA control unit processes the data sent by the CPU processing unit and then sends it to an external device. The storage unit stores the CPU processing unit program and the FPGA control unit program; The communication unit is used to implement the internal RapidIO interface and serial port; The FPGA control unit includes a refresh chip and an SRAM-type FPGA chip, wherein: The refresh chip is used to reload, read back, and refresh the FPGA software; SRAM-type FPGA chips are used for the switching between CPU processing units and storage units, and for the sequential startup control of the three CPU processing units; The storage unit includes memory for the CPU program and memory for the FPGA program, wherein: The CPU program's memory contains two FLASH chips, both mounted on an SRAM-type FPGA chip. One is an aerospace-grade FLASH chip with a size of 8MB, and the other is an industrial-grade FLASH chip with a size of 32MB. The aerospace-grade FLASH chip stores one copy of the CPU's bootloader, operating system, and application program, while the industrial-grade FLASH chip stores four identical copies of the CPU's bootloader and application program. The memory of an FPGA program includes a main memory and a backup memory connected to a refresh chip. The refresh chip enables the switching between the main and backup FLASH memory and the reconstruction of the program. The CPU boots from aerospace-grade FLASH by default upon power-up. If booting fails, it boots from two out of three files in industrial-grade FLASH. Both FLASH chips are connected to the FPGA and accessed via the LocalBus bus. The CPU boot configuration is implemented through the FPGA. The FPGA program memory consists of two chips, which are primary and backup for each other. They are connected to the refresh chip, which enables the switching between primary and backup FLASH and the refactoring of the program. After the module is powered on, the refresh chip resets and reads the FPGA program from the main FLASH to load the FPGA. After the FPGA starts up, first, CPU1 reads the CPU boot program from the aerospace-grade FLASH through the interface implemented by the FPGA. After the boot program starts, the operating system is loaded. After the operating system starts up, it sends a startup completion flag to the FPGA. Then, CPU2 reads the CPU program from the aerospace-grade FLASH through the interface implemented by the FPGA. After it starts up, it sends a startup completion flag to the FPGA. Then, CPU3 reads the CPU program from the aerospace-grade FLASH through the interface implemented by the FPGA. After it starts up, it sends a startup completion flag to the FPGA. After the FPGA receives the startup completion flags from the three CPUs, the three CPUs start the application program simultaneously to ensure the synchronous operation of the application program. When three CPUs run the same algorithm simultaneously, they send data to the three FIFOs of the FPGA via the RapidIO interface. The FPGA performs a two-out-of-three operation on the data from the three FIFOs and then sends the data to the external device via the Aurora interface. When receiving data, the FPGA first caches the data from the Aurora interface in the extended memory DDR3, and then sends it to the three CPUs simultaneously for processing. The FPGA software is stored in two FLASH chips and connected to the interface of the refresh chip. When powered on, the refresh chip reads data from the main FLASH chip by default to load the FPGA. If the main FLASH chip fails to start the FPGA, it can automatically switch to the backup FLASH chip. The FLASH program can be updated through the refresh serial port. The refresh function can also control the refresh switch and frequency through the serial port.

2. The spaceborne high-performance computing module system according to claim 1, characterized in that, The CPU processing unit includes three P2020 processor chips.

3. The spaceborne high-performance computing module system according to claim 2, characterized in that, The CPU processing unit includes a DDR memory controller with attached memory chips.

4. The spaceborne high-performance computing module system according to claim 1, characterized in that, SRAM-based FPGA chips can be externally extended with DDR3 memory for the management and use of the memory units.

5. The spaceborne high-performance computing module system according to claim 1, characterized in that, SRAM-type FPGA chips include the Kintex-7 chip, and refresh chips include the JFMSR01RH chip.

6. The spaceborne high-performance computing module system according to claim 1, characterized in that, The RapidIO interface is a 2-way 1X interface with a speed of 3.125Gbps.

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