Dense bee colony interference semi-physical simulation system based on RFSOC

Abstract

The invention, which relates to the technical field of radar electronic countermeasure and semi-physical simulation, discloses an RFSOC-based dense bee colony interference semi-physical simulation system comprising a display control computer, a data exchange module, a power divider, a power supply module and a plurality of code element generation modules. The power divider shunts an externally accessed radar signal and then sends the signal to the code element generation module. The code element generation module takes an RFSOC chip integrated with RF, ADC / DAC, FPGA and ARM as a core, carries out signal processing by using the FPGA according to interference types and parameters issued by the display control computer, and directly synthesizes and outputs radar interference signals through the DAC. A traditional microwave frequency conversion module is replaced by the RFSOC chip, so that the hardware structure is remarkably simplified, and the cost is reduced; meanwhile, the system can generate as many as 50 mutually independent radar interference signals in real time, and the problems that in the prior art, the number of interference channels is small, and the dense bee colony interference environment is difficult to simulate are effectively solved.

Description

Technical Field

[0001] This invention relates to the field of radar electronic countermeasures and hardware-in-the-loop simulation technology, specifically to a dense swarm jamming hardware-in-the-loop simulation system based on RFSOC (Radio Frequency System-on-Chip). Background Technology

[0002] With the continuous competition and development of radar technology and electronic countermeasures technology, the modern electronic warfare environment has undergone tremendous changes. As an important piece of equipment in electronic warfare, radar jammers mainly disrupt, suppress, or deceive enemy electronic equipment by emitting or relaying electromagnetic waves, rendering it unable to function properly and thus seizing control of the electromagnetic spectrum on the battlefield.

[0003] However, traditional radar jammers or their hardware-in-the-loop (HIL) systems have significant limitations. First, traditional equipment typically has only 1-4 independent jamming channels, making it difficult to simulate the dense swarm jamming environments common on modern battlefields and failing to meet increasingly complex testing requirements. Second, in terms of hardware composition, traditional radar jammers usually rely on frequency-converted microwave modules to process signals, resulting in complex, bulky, heavy, and costly hardware structures. Therefore, there is an urgent need for a hardware-in-the-loop (HIL) system that can simplify the hardware structure, reduce costs, and provide large-scale, multi-channel independent jamming signal generation. Summary of the Invention

[0004] The present invention provides a hardware-in-the-loop simulation system for dense swarm interference based on RFSOC, in order to solve the technical problems of existing traditional radar interference simulation systems, such as the small number of interference channels, complex hardware composition (relying on microwave frequency conversion modules), and difficulty in simulating dense swarm interference environments.

[0005] To solve the above problems, the technical solution adopted by the present invention is as follows:

[0006] A hardware-in-the-loop (HIL) simulation system for dense swarm jamming based on an RFSOC chip includes a display and control computer, a data exchange module, a power divider, a power supply module, and several symbol generation modules. The display and control computer communicates with the symbol generation modules through the data exchange module to issue jamming parameter configuration commands and control commands. The power divider's input terminal receives an external radar signal, and its output terminal is split into multiple paths and connected to the signal input terminal of each symbol generation module. The power supply module is electrically connected to the display and control computer, the data exchange module, the power divider, and the symbol generation modules to provide corresponding operating voltages. The symbol generation modules use an RFSOC chip as the core processing unit. The RFSOC chip integrates a radio frequency (RF) unit, a data conversion ADC unit, a data conversion DAC unit, a field-programmable gate array (FPGA) unit, and an ARM processor unit. The symbol generation modules can process signals using the FPGA unit according to the jamming type and parameters issued by the display and control computer, and directly synthesize radar jamming signals through the DAC unit for output to simulate multiple independent jamming channels.

[0007] Furthermore, the hardware circuit structure of the symbol generation module includes:

[0008] The RFSOC chip is connected to the RJ45 interface via the PHY chip, and is connected to the data exchange module via the RJ45 interface and the network cable, for receiving instructions from the display and control computer.

[0009] The storage unit, including QSPI FLASH, is connected to the RFSOC chip and is used to store configuration parameters and program data;

[0010] The debugging interface, including a JTAG interface and a debugging serial port, is connected to the RFSOC chip and used for program downloading and debugging.

[0011] The analog-to-digital converter input channel, the RFSOC chip provides at least one ADC input channel, the ADC input channel is connected to the branch output terminal of the power divider, the sampling rate is 5GSPS, and it is used to collect externally input radar signals;

[0012] The digital-to-analog converter output channel, the RFSOC chip provides at least 4 DAC output channels, each of which has a sampling rate of 9.8 GSPS. The output terminal of each DAC output channel is connected to a filter, which can filter the output signal and output the radar interference signal through the radio frequency interface. The passband frequency range of the filter covers 2300MHz to 4000MHz.

[0013] Furthermore, the system topology and channel allocation method are as follows:

[0014] The system comprises 13 symbol generation modules. The power divider divides the input radar signal into 13 paths, which are then fed into the ADC input channels of these 13 symbol generation modules.

[0015] Each of the symbol generation modules independently generates radar jamming signals. For the first to 12th symbol generation modules, each module uses 4 DAC output channels to output 4 radar jamming signals; the 13th symbol generation module uses 2 DAC output channels to output 2 radar jamming signals.

[0016] The system outputs a total of 50 independent radar jamming signals, corresponding to RF1 to RF50 output ports respectively, thus forming a dense swarm jamming environment. Each radar jamming signal can be configured with an independent jamming pattern.

[0017] Furthermore, the display and control computer runs display and control software, which is configured with a human-computer interaction interface and specifically includes the following functional modules:

[0018] The working mode switching module allows users to select between self-test mode and normal mode.

[0019] The parameter configuration module is used to set the threshold value, self-test frequency, self-test pulse width, self-test bandwidth, center frequency, and signal period parameters.

[0020] The interference type configuration module is used to independently configure the interference style for each interference channel. The interference style includes any one of noise suppression, intermittent noise, dense forwarding, intermittent sampling forwarding, and coherent suppression.

[0021] The detection and display module is used to receive and display the parameter results of the radar signal detected by the symbol generation module. The parameter results of the radar signal include signal type, signal bandwidth, signal power, signal period, and signal pulse width.

[0022] The status monitoring module is used to monitor and display the temperature status information of all code generation modules in real time, and provide status reporting display on the interface;

[0023] The parameter management module supports saving configured interference parameters as configuration files and importing configuration files from storage media to restore previous settings.

[0024] Furthermore, the technical specifications and logic control of the generated radar jamming signal satisfy the following:

[0025] The adaptive signal frequency range is 2.4GHz to 3.9GHz, the adaptive signal bandwidth is no greater than 40MHz, and the adaptive signal pulse width is no greater than 2ms;

[0026] The noise suppression includes broadband noise interference and frequency sweeping interference; the intermittent sampling forwarding includes direct forwarding interference and repeated forwarding interference.

[0027] The system has an output delay control function. The symbol generation module generates a radar interference signal based on the falling edge of the received radar signal pulse, or generates a radar interference signal based on a delay parameter defined by the display and control computer. The simulated distance range corresponding to the delay parameter is 1km to 500km.

[0028] Furthermore, the specific configuration of the power module and signal input link is as follows:

[0029] The power module has a rated power of 1500W, which provides at least 40% power reserve for the system. The power module circuit integrates overload protection circuit, overvoltage protection circuit, undervoltage protection circuit and overtemperature protection circuit to ensure stable operation when the total power consumption of the system is less than 900W.

[0030] Before the radar signal is input to the power divider, the system is also configured with a signal preprocessing link, which includes an attenuator and a bandpass filter network connected in sequence. The line-fed radar signal first passes through the attenuator for power adjustment, then passes through the bandpass filter network for filtering, and finally enters the power divider to be divided into 13 channels, which are then sent to the 13 symbol generation modules respectively.

[0031] Furthermore, the workflow of the system includes:

[0032] Step S1: After the system is powered on, the display and control computer first determines the working mode selected by the user;

[0033] Step S2: If the self-test mode is selected, the display and control computer configures the self-test parameters, including the center frequency, pulse width, period and bandwidth, and sends them to the symbol generation module. The symbol generation module performs the internal loop self-test function and reports the status.

[0034] Step S3: If normal mode is selected, the display and control computer configures the signal reception threshold value;

[0035] Step S4: The display and control computer configures the interference parameters for each of the 50 channels according to the configuration file input by the user or imported, including selecting the noise suppression, intermittent noise, dense forwarding, intermittent sampling forwarding or coherent suppression type, as well as setting the interference power and interference switch;

[0036] Step S5: The display and control computer issues a start switch command, which is forwarded to all code generation modules through the data exchange module;

[0037] Step S6: Each symbol generation module generates and outputs the corresponding radar jamming signal in real time using the RFSOC chip based on the received interference type and parameters.

[0038] Furthermore, the data exchange module adopts a network switch and is connected to the network port of the display and control computer and the RJ45 interfaces of the 13 symbol generation modules through network cables to form a star network topology. A communication protocol is defined between the display and control computer and the symbol generation modules for transmitting control commands and status data. The PL and PS terminals of the symbol generation modules interact with each other through an AXI bus.

[0039] Compared with the prior art, the beneficial effects of the present invention are:

[0040] (1) This invention adopts an architecture based on an RFSOC (Radio Frequency System-on-Chip) chip, integrating an RF unit, an ADC / DAC data conversion unit, an FPGA, and an ARM processor. Direct signal sampling and direct signal synthesis can be achieved through the RFSOC chip, thus eliminating the need for the frequency conversion microwave module required in traditional radar jammers. This design significantly simplifies the system's hardware structure, reduces the overall weight, size, and power consumption of the system, and also greatly saves manufacturing costs.

[0041] (2) Through modular design (such as using a 13-symbol generation module), this system can generate up to 50 independent radar jamming signals in real time. Compared with the 1 to 4 channels of traditional equipment, this invention can construct a high-density swarm jamming environment, significantly improving the complexity and realism of the hardware-in-the-loop simulation.

[0042] (3) This system supports independent configuration of interference patterns for each channel, covering five major types of interference: noise suppression (including wideband and frequency sweep), intermittent noise, dense forwarding, intermittent sampling forwarding (including direct forwarding and repeated forwarding), and coherent suppression. At the same time, with a DAC sampling rate of up to 9.8 GSPS, the system can generate high-bandwidth, high-quality radar interference signals to meet high-precision testing requirements.

[0043] (4) The system has a flexible output delay function, supports radar pulse falling edge triggering and host computer custom delay triggering, and the simulated distance range can reach 1km to 500km, which can adapt to the simulation needs of various tactical scenarios from close range defense to long-range early warning.

[0044] (5) Through a specially designed power supply module (with a 40% power consumption margin and multiple protection circuits) and signal preprocessing link (attenuator and bandpass filter network), the system is effectively protected from the effects of overload, overheating and out-of-band noise, ensuring the system stability when generating 50 high-density signals.

[0045] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, embodiments of the present invention are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0046] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 To disrupt the composition of the hardware-in-the-loop simulation system;

[0048] Figure 2 Block diagram of the hardware-in-the-loop simulation system for interference;

[0049] Figure 3 To interfere with the display and control computer software of the hardware-in-the-loop simulation system;

[0050] Figure 4 Block diagram of the code element generation module;

[0051] Figure 5 Typical workflow diagram of interference hardware-in-the-loop simulation system. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0053] This invention discloses a hardware-in-the-loop simulation system for dense bee colony interference based on RFSOC. For example... Figure 1 As shown, the system mainly consists of a display and control computer, a symbol generation module, a power supply module, a data exchange module, and a power divider. The display and control computer acts as the host computer, responsible for human-computer interaction and command issuance; the data exchange module handles internal data communication; the power supply module provides power to all components; the power divider distributes input signals; and the symbol generation module is the core execution unit of the system, utilizing RFSOC technology to acquire and generate signals.

[0054] 1. System Hardware Architecture and Principles

[0055] like Figure 2 The diagram shown is a schematic diagram of the interference hardware-in-the-loop simulation system.

[0056] (1) Signal input link

[0057] The system is used to receive external radar signals. To ensure the quality of the input signal and protect subsequent circuitry, a signal preprocessing link is configured before the radar signal is input to the power divider. This link includes an attenuator and a bandpass filter network connected in sequence. The line-fed radar signal first undergoes power adjustment by the attenuator to prevent excessive power from damaging the ADC channel; then it passes through the bandpass filter network to filter out out-of-band clutter; finally, it enters the power divider.

[0058] The power divider splits the processed radar signal into 13 channels, which are then fed into the ADC input channels of 13 independent symbol generation modules.

[0059] (2) Symbol generation module and topology

[0060] The system contains 13 symbol generation modules, such as Figure 4 As shown, each symbol generation module uses a Xilinx RFSOC chip (specifically model XCZU47DR) as its core processing unit. This RFSOC chip highly integrates an RF unit, an ADC unit, a DAC unit, a FPGA unit, and an ARM processor unit.

[0061] The hardware circuit structure of the symbol generation module also includes:

[0062] Communication interface: The RFSOC chip is connected to the RJ45 interface through the PHY chip, and then connected to the data exchange module through the network cable to receive interference parameter configuration instructions and control instructions issued by the display and control computer.

[0063] Storage and Debugging: Equipped with QSPI FLASH (four-wire serial peripheral interface flash memory) as non-volatile storage for storing configuration parameters and program data; configured with a JTAG interface and debug serial port for program downloading and debugging. In addition, combined with the attached... Figure 4 As shown, the storage unit also includes high-speed dynamic random access memory (DDR4). Specifically, the PL (programmable logic) end of the RFSOC chip is connected to a 32-bit DDR4 memory for high-speed caching of interference waveform data or acquired radar signal data; the PS (processing system) end is connected to a 64-bit DDR4 memory for running the operating system and caching interactive data.

[0064] Analog-to-digital converter (ADC): The RFSOC chip provides at least one ADC input channel with a sampling rate of up to 5GSPS. It is connected to the branch output of the power divider and is used to acquire externally input radar signals in real time.

[0065] Digital-to-Analog Converter (DAC): The RFSOC chip provides at least four DAC output channels with a sampling rate of up to 9.8 GSPS. Each DAC output channel is connected to a filter with a passband frequency range of 2300MHz to 4000MHz, used to filter the synthesized signal and finally output the radar jamming signal through the RF interface.

[0066] like Figure 2 As shown, the system adopts a star network topology. The data exchange module uses a network switch, and the display and control computer and the 13 symbol generation modules are all connected to this switch. Regarding the output channel allocation:

[0067] The first to twelfth symbol generation modules each use their four DAC output channels to output a total of 48 radar jamming signals (corresponding to RF1~RF48).

[0068] The 13th symbol generation module uses its two DAC output channels to output two radar jamming signals (corresponding to RF49~RF50).

[0069] The system outputs a total of 50 independent radar jamming signals, thereby creating a dense swarm-like jamming environment.

[0070] (3) Power module

[0071] A power supply module is essential for the normal operation of the system. Considering that the actual power consumption of the entire system is less than 900W, a power supply module with a rated power of 1500W was selected in this embodiment to ensure system stability, with a power margin of at least 40%. The power supply module is electrically connected to the display and control computer, data exchange module, power divider, and symbol generation module to provide a stable operating voltage. Simultaneously, to ensure system safety, the power supply module integrates overload protection circuitry, overvoltage protection circuitry, undervoltage protection circuitry, and overtemperature protection circuitry.

[0072] The entire system is integrated into the chassis. The front panel of the chassis features 50 densely packed RF output interfaces and radar signal input interfaces. To meet the system's heat dissipation requirements under full load, the chassis is designed with internal cooling airflow channels, which, together with the power module's over-temperature protection, ensure thermal stability when high-power interference is simultaneously activated in the densely packed channels.

[0073] 2. Software Functions and Human-Computer Interaction

[0074] The computer running the display control software, such as... Figure 3 As shown, a human-computer interaction interface is provided, which mainly includes the following functional modules:

[0075] Operating mode switching module: Allows users to switch between self-test mode and normal mode.

[0076] Parameter configuration module: used to set basic parameters such as threshold value, self-test frequency, self-test pulse width, self-test bandwidth, center frequency, and signal period.

[0077] Interference Type Configuration Module: This is the core control area, where users can independently configure interference patterns for each interference channel from RF1 to RF50. Interference patterns include: noise suppression, intermittent noise, dense forwarding, intermittent sampling forwarding, and coherent suppression.

[0078] Detection and display module: Displays the parameter results of the detected radar signals, including signal type, signal bandwidth, signal power, signal period, and signal pulse width.

[0079] Status monitoring module: Real-time monitoring and display of temperature status information of all code generation modules, with status reporting function.

[0080] Parameter management module: Supports parameter import and export functions. Configured parameters can be saved and directly imported the next time they are used without reconfiguration.

[0081] Regarding the data flow and processing logic within the code generation module, such as Figure 4 As shown, the RFSOC chip adopts a mode in which the PL (Programmable Logic) and PS (Processing System) work together via an on-chip AXI bus:

[0082] 1. Downlink Control and Waveform Generation: The display and control computer sends the configured interference parameters to the PS terminal of the RFSOC via Ethernet. The PS terminal transmits the parameters to the PL terminal via the AXI bus. After parsing the protocol, the PL terminal generates a radar interference signal, which is then output through the DAC.

[0083] 2. Uplink Reception and Display: The external radar signals acquired by the ADC first enter the PL terminal for digital signal processing. The processed characteristic parameters are written to the memory area readable by the PS terminal via the AXI bus. The PS terminal periodically reads these results, packages them, and uploads them to the display and control computer via Ethernet for display.

[0084] 3. System performance indicators and signal generation logic

[0085] The radar jamming signal generated by this system meets the following technical specifications and logic control:

[0086] Frequency and bandwidth: Suitable for signal frequency range of 2.4GHz to 3.9GHz; suitable for signal bandwidth ≤40MHz; suitable for signal pulse width ≤2ms.

[0087] Interference patterns are further subdivided: noise suppression includes broadband noise interference and frequency sweeping interference; intermittent sampling forwarding includes direct forwarding interference and repeated forwarding interference.

[0088] Delay Control: The system features output delay control. Logically, the symbol generation module generates radar interference signals by default, triggered by the falling edge of the received radar signal pulse; or by a delay parameter defined by the display and control computer. The simulated distance range corresponding to the delay parameter is 1km to 500km.

[0089] 4. System Workflow

[0090] The typical workflow of the system is as follows: Figure 5 As shown, the specific steps are as follows:

[0091] Step S1 (Power-on and Mode Selection): After the system is powered on, the operator selects either self-test mode or normal mode on the display and control computer software interface.

[0092] Step S2 (Self-test Process): If the self-test mode is selected, the display and control computer configures the self-test parameters (center frequency, pulse width, period, and bandwidth) and sends them out. After receiving the instruction, the symbol generation module performs an independent loop self-test function and reports the status to the display and control computer.

[0093] Step S3 (Threshold Configuration): If the normal mode is selected, the operator configures the threshold value for signal detection.

[0094] Step S4 (Interference Parameter Configuration): The display and control computer configures the interference parameters for each of the 50 channels based on the configuration file input by the user or imported. This includes selecting the interference type (noise suppression, intermittent noise, dense forwarding, intermittent sampling forwarding, coherent suppression), and setting the interference power level and interference on / off status.

[0095] Step S5 (Startup): After the settings are completed, the display and control computer issues a start switch command. These commands are forwarded to the 13 code generation modules through the data exchange module.

[0096] Step S6 (Signal Generation): Each symbol generation module performs real-time signal processing using the FPGA unit inside the RFSOC chip based on the interference type and parameters sent by the display and control computer, and directly synthesizes the signals through the DAC unit to finally generate and output 50 independent radar interference signals.

[0097] In summary, this invention utilizes the high integration and high sampling rate advantages of the RFSOC chip and the PL / PS collaborative processing architecture to replace the traditional microwave frequency conversion module. This not only simplifies the hardware structure but also achieves the output capability of 50 independent interference channels in a single system, effectively simulating complex dense swarm electromagnetic environments.

[0098] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A hardware-in-the-loop simulation system for dense bee colony interference based on RFSOC, characterized in that, The system includes a display and control computer, a data exchange module, a power divider, a power supply module, and several symbol generation modules. The display and control computer communicates with the symbol generation modules through the data exchange module to issue interference parameter configuration commands and control commands. The input terminal of the power divider receives an external radar signal, and its output terminal is split into multiple paths and connected to the signal input terminal of each symbol generation module. The power supply module is electrically connected to the display and control computer, the data exchange module, the power divider, and the symbol generation modules to provide the corresponding operating voltage. The symbol generation modules use an RFSOC chip as the core processing unit. The RFSOC chip integrates an RF unit, an ADC unit, a DAC unit, a FPGA unit, and an ARM processor unit. The symbol generation modules can process signals using the FPGA unit according to the interference type and parameters issued by the display and control computer, and directly synthesize radar interference signals for output through the DAC unit to simulate multiple independent jamming channels.

2. The hardware-in-the-loop simulation system for dense bee colony interference based on RFSOC according to claim 1, characterized in that, The hardware circuit structure of the symbol generation module includes: The RFSOC chip is connected to the RJ45 interface via the PHY chip, and is connected to the data exchange module via the RJ45 interface and the network cable, for receiving instructions from the display and control computer. The storage unit, including QSPI FLASH, is connected to the RFSOC chip and is used to store configuration parameters and program data; The debugging interface, including a JTAG interface and a debugging serial port, is connected to the RFSOC chip and used for program downloading and debugging. The analog-to-digital converter input channel, the RFSOC chip provides at least one ADC input channel, the ADC input channel is connected to the branch output terminal of the power divider, the sampling rate is 5GSPS, and it is used to collect externally input radar signals; The digital-to-analog converter output channel, the RFSOC chip provides at least 4 DAC output channels, each of which has a sampling rate of 9.8 GSPS. The output terminal of each DAC output channel is connected to a filter, which can filter the output signal and output the radar interference signal through the radio frequency interface. The passband frequency range of the filter covers 2300MHz to 4000MHz.

3. The hardware-in-the-loop simulation system for dense bee colony interference based on RFSOC according to claim 2, characterized in that, The system's topology and channel allocation method are as follows: The system comprises 13 symbol generation modules. The power divider divides the input radar signal into 13 paths, which are then fed into the ADC input channels of these 13 symbol generation modules. Each of the symbol generation modules independently generates radar jamming signals. For the first to 12th symbol generation modules, each module uses 4 DAC output channels to output 4 radar jamming signals; the 13th symbol generation module uses 2 DAC output channels to output 2 radar jamming signals. The system outputs a total of 50 independent radar jamming signals, corresponding to RF1 to RF50 output ports respectively, thus forming a dense swarm jamming environment. Each radar jamming signal can be configured with an independent jamming pattern.

4. The hardware-in-the-loop simulation system for dense bee colony interference based on RFSOC according to claim 3, characterized in that, The display and control computer runs display and control software, which is configured with a human-computer interaction interface and specifically includes the following functional modules: The working mode switching module allows users to select between self-test mode and normal mode. The parameter configuration module is used to set the threshold value, self-test frequency, self-test pulse width, self-test bandwidth, center frequency, and signal period parameters. The interference type configuration module is used to independently configure the interference style for each interference channel. The interference style includes any one of noise suppression, intermittent noise, dense forwarding, intermittent sampling forwarding, and coherent suppression. The detection and display module is used to receive and display the parameter results of the radar signal detected by the symbol generation module. The parameter results of the radar signal include signal type, signal bandwidth, signal power, signal period, and signal pulse width. The status monitoring module is used to monitor and display the temperature status information of all code generation modules in real time, and provide status reporting display on the interface; The parameter management module supports saving configured interference parameters as configuration files and importing configuration files from storage media to restore previous settings.

5. A hardware-in-the-loop simulation system for dense bee colony interference based on RFSOC according to claim 4, characterized in that, The technical specifications and logic control of the generated radar jamming signal meet the following requirements: The adaptive signal frequency range is 2.4GHz to 3.9GHz, the adaptive signal bandwidth is no greater than 40MHz, and the adaptive signal pulse width is no greater than 2ms; The noise suppression includes broadband noise interference and frequency sweeping interference; the intermittent sampling forwarding includes direct forwarding interference and repeated forwarding interference. The system has an output delay control function. The symbol generation module generates a radar interference signal based on the falling edge of the received radar signal pulse, or generates a radar interference signal based on a delay parameter defined by the display and control computer. The simulated distance range corresponding to the delay parameter is 1km to 500km.

6. The hardware-in-the-loop simulation system for dense bee colony interference based on RFSOC according to claim 5, characterized in that, The specific configuration of the power module and signal input link is as follows: The power module has a rated power of 1500W, which provides at least 40% power reserve for the system. The power module circuit integrates overload protection circuit, overvoltage protection circuit, undervoltage protection circuit and overtemperature protection circuit to ensure stable operation when the total power consumption of the system is less than 900W. Before the radar signal is input to the power divider, the system is also configured with a signal preprocessing link, which includes an attenuator and a bandpass filter network connected in sequence. The line-fed radar signal first passes through the attenuator for power adjustment, then passes through the bandpass filter network for filtering, and finally enters the power divider to be divided into 13 channels, which are then sent to the 13 symbol generation modules respectively.

7. A hardware-in-the-loop simulation system for dense bee colony interference based on RFSOC as described in claim 1, characterized in that, The system's workflow includes: Step S1: After the system is powered on, the display and control computer first determines the working mode selected by the user; Step S2: If the self-test mode is selected, the display and control computer configures the self-test parameters, including the center frequency, pulse width, period and bandwidth, and sends them to the symbol generation module. The symbol generation module performs the internal loop self-test function and reports the status. Step S3: If normal mode is selected, the display and control computer configures the signal reception threshold value; Step S4: The display and control computer configures the interference parameters for each of the 50 channels according to the configuration file input by the user or imported, including selecting the noise suppression, intermittent noise, dense forwarding, intermittent sampling forwarding or coherent suppression type, as well as setting the interference power and interference switch; Step S5: The display and control computer issues a start switch command, which is forwarded to all code generation modules through the data exchange module; Step S6: Each symbol generation module generates and outputs the corresponding radar jamming signal in real time using the RFSOC chip based on the received interference type and parameters.

8. A hardware-in-the-loop simulation system for dense bee colony interference based on RFSOC according to claim 2, characterized in that, The data exchange module uses a network switch and is connected to the network port of the display and control computer and the RJ45 interfaces of the 13 symbol generation modules via network cables to form a star network topology. A communication protocol is defined between the display and control computer and the symbol generation modules for transmitting control commands and status data. The PL and PS terminals of the symbol generation modules interact with each other via an AXI bus.

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