A chip design method, design apparatus, computer equipment, and storage medium

Abstract

This invention discloses a chip design method, design apparatus, computer equipment, and storage medium. The chip design method includes creating a power bus network based on pad locations and a chip planar layout; determining the positions of power ports of circuit modules within the power bus network; creating a power supply network model based on the power bus network; generating a netlist embedding the power supply network based on the power supply network model and the positions of the power ports of circuit modules within the power bus network; and performing circuit simulation based on the netlist embedding the power supply network. The chip design method, design apparatus, computer equipment, and storage medium provided by this invention shorten the chip design and development cycle and reduce design costs.

Description

Technical Field

[0001] The present invention relates to the field of chip design technology, and in particular to a chip design method, design apparatus, computer equipment and storage medium. Background Technology

[0002] With the development of integrated circuit technology, signal integrity and power integrity analysis of chips has become increasingly important. As chip process dimensions continue to shrink, the parasitic effects of chip power supply networks are becoming more and more significant. Poor design can lead to timing defects in critical circuit modules, increasingly severe transient noise, and other issues, thereby affecting the actual performance of the chip. In severe cases, it can even cause logic errors and chip failure.

[0003] In chip design, a process of pre-layout simulation and post-layout simulation is required. Power integrity simulation analysis is usually performed only after the complete chip layout design is completed. If the simulation finds that the timing margin does not meet the requirements, the power supply network or circuit needs to be redesigned and verified multiple times, which significantly increases the design and development cycle and cost.

[0004] It should be noted that the information in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This invention provides a chip design method, design apparatus, computer equipment, and storage medium to shorten the chip design and development cycle and reduce design costs.

[0006] In a first aspect, embodiments of the present invention provide a chip design method, comprising:

[0007] Create a power bus network based on the pad locations and chip planar layout;

[0008] Determine the location of the power supply port of the circuit module in the power bus network;

[0009] Create a power supply network model based on the power bus network;

[0010] A netlist containing the power supply network is generated based on the power supply network model and the position of the power ports of the circuit module in the power bus network.

[0011] Circuit simulation is performed based on the netlist containing the embedded power supply network.

[0012] Optionally, the circuit module is a critical timing circuit module.

[0013] Optionally, the key timing circuit module includes circuit modules on any one or more timing paths of the chip, such as the read timing path, write timing path, array timing path, and command timing path.

[0014] Optionally, creating a power supply network model based on the power bus network includes:

[0015] Create a layout of the power bus network based on the power bus network;

[0016] Parasitic parameters are extracted from the layout of the power bus network;

[0017] Calculate the values ​​of the parasitic parameters;

[0018] The power supply network model is created based on the values ​​of the parasitic parameters.

[0019] Optionally, before extracting parasitic parameters from the layout of the power bus network, the layout of the circuit module may be created.

[0020] Optionally, a power supply network model is created based on the power bus network, including:

[0021] Create a power supply network unit, the power supply network unit including multiple power lines and multiple power bridge connections, each of the power lines and the power bridge connections including at least one of resistors and capacitors;

[0022] Based on the power bus network, an array of multiple power supply network units is created to constitute the power supply network model.

[0023] Optionally, the values ​​of the resistor and / or the capacitor can be programmable.

[0024] Optionally, the values ​​of the resistor and / or capacitor are calculated based on the size and material of the power line or the power bridge connection.

[0025] Optionally, the chip design method further includes:

[0026] Create a packaged power supply network model and / or signal supply network model for the chip;

[0027] Creating a power supply network model based on the power bus network includes:

[0028] The power supply network model is created based on the power bus network, the chip's packaged power supply network model, and / or the signal supply network model.

[0029] Optionally, the chip design method further includes:

[0030] Create control chip, channel PDN model and / or SDN model;

[0031] Creating a power supply network model based on the power bus network includes:

[0032] The power supply network model is created based on the power bus network, the control chip, the channel PDN model, and / or the SDN model.

[0033] Optionally, determining the location of the power supply port of the circuit module in the power bus network includes:

[0034] Determine the horizontal and vertical coordinates of the power supply ports of the circuit module in the power bus network.

[0035] Optionally, generating a netlist embedded with the power supply network based on the power supply network model and the location of the power ports of the circuit module in the power bus network includes:

[0036] A power supply network configuration file is generated based on the power supply network model and the location of the power ports of the circuit module in the power bus network. The power supply network configuration file is used to integrate the power supply network model and the circuit module.

[0037] Generate a netlist containing the power supply network based on the power supply network configuration file.

[0038] Optionally, the power supply network configuration file includes at least the horizontal and vertical coordinate information of the power ports of the circuit module in the power bus network.

[0039] Optionally, after performing circuit simulation based on the netlist embedded with the power supply network, the method further includes:

[0040] Modify the power bus network or the circuit module;

[0041] Generate a modified netlist containing the power supply network;

[0042] Circuit simulation is performed based on the modified netlist with embedded power supply network.

[0043] Secondly, embodiments of the present invention also provide a chip design apparatus, the apparatus comprising:

[0044] The power bus network generation module is used to create a power bus network based on the pad locations and chip planar layout.

[0045] A circuit module location determination module is used to determine the location of the power port of the circuit module in the power bus network;

[0046] A power supply network model generation module is used to create a power supply network model based on the power bus network.

[0047] A netlist generation module with embedded power supply network is used to generate a netlist with embedded power supply network based on the power supply network model and the position of the power ports of the circuit module in the power bus network.

[0048] The simulation module is used to perform circuit simulation based on the netlist containing the power supply network.

[0049] Thirdly, embodiments of the present invention also provide a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the design method of any of the chips described in the first aspect.

[0050] Fourthly, embodiments of the present invention also provide a storage medium containing computer-executable instructions, which, when executed by a computer processor, are used to perform the design method of any of the chips described in the first aspect.

[0051] The chip design method, design apparatus, computer equipment, and storage medium provided in this invention create a power bus network based on pad locations and chip planar layout, determine the position of the power ports of circuit modules within the power bus network, create a power supply network model based on the power bus network, generate a netlist embedding the power supply network based on the power supply network model and the positions of the power ports of circuit modules within the power bus network, perform circuit simulation based on the netlist embedding the power supply network, and integrate parasitic parameters in the power bus network into the circuit netlist for simulation, thereby realizing power integrity analysis of the chip to verify whether the chip's power supply network design meets the requirements. This analysis can be performed either after the layout design is completed or after the layout design is finished, reducing the difficulty of power supply network design, thus shortening the chip design development cycle and reducing design costs. Attached Figure Description

[0052] Figure 1 A schematic flowchart illustrating a chip design method provided in an embodiment of the present invention;

[0053] Figure 2 A flowchart illustrating another chip design method provided in an embodiment of the present invention;

[0054] Figure 3 This application provides a schematic diagram of the structure of a power bus network according to an embodiment of the present application.

[0055] Figure 4 for Figure 3 A magnified structural diagram at point A;

[0056] Figure 5 A schematic diagram of an integrated structure of a circuit module and a power bus network provided in an embodiment of the present invention;

[0057] Figure 6 This is a schematic diagram of a power supply network model provided in an embodiment of the present invention;

[0058] Figure 7 This is a schematic diagram of the structure of a power supply network unit provided in an embodiment of the present invention;

[0059] Figure 8 A schematic diagram of the integrated structure of a circuit module and a power supply network model provided in an embodiment of the present invention;

[0060] Figure 9 A schematic diagram of a process for creating a power supply network model provided in an embodiment of the present invention;

[0061] Figure 10 A flowchart illustrating another chip design method provided in an embodiment of the present invention;

[0062] Figure 11 A schematic diagram of the structure of a storage system provided in an embodiment of the present invention;

[0063] Figure 12 A schematic diagram of a chip design apparatus provided in an embodiment of the present invention;

[0064] Figure 13 This is a schematic diagram of the structure of a power supply network model generation module provided in an embodiment of the present invention;

[0065] Figure 14 This is a schematic diagram of the structure of a power supply network model generation module provided in an embodiment of the present invention;

[0066] Figure 15 A schematic diagram of a netlist generation module embedded with a power supply network provided in an embodiment of the present invention;

[0067] Figure 16 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0068] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0069] Figure 1This is a flowchart illustrating a chip design method provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the chip design method provided in this embodiment of the invention includes:

[0070] Step 1: Create a power bus network based on the pad locations and chip planar layout.

[0071] For example, Figure 2 This is a flowchart illustrating another chip design method provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of a power bus network provided in an embodiment of this application, as shown below. Figure 2 and Figure 3 As shown, the chip layout is first planned: determining the chip length and width, arranging the pads, and completing the power supply planning, creating a pads log and power bus plan. The pad arrangement considers multiple factors, including ease of routing on the packaging substrate and ease of internal chip implementation. Based on the chip's required functions, circuit modules are designed, and circuit schematics and netlists are created; the layout of the circuit modules and power bus within the chip is completed, creating a floor plan. The power bus network is then created based on the pad locations and the floor plan, such as... Figure 3 As shown, the power bus network includes pads 10 and a power bus 11. Pads 10 include power pads 101 and signal pads 102. Power pads 101 are used to provide power to each node of the power bus 11, and signal pads 102 are used to provide signals. The power bus 11 is connected to the power pads 101. The power bus 11 may be composed of multiple metal layers. Figure 4 for Figure 3 An enlarged structural diagram at point A, as shown below. Figure 4 As shown, taking a four-layer metal bus as an example, the power bus 11 is composed of four metal layers: M1, M2, M3, and M4, thus allowing the transmission of power at different voltages through different metal layers. It should be noted that in other embodiments, the power bus may also be composed of other numbers of metal layers, which can be selected as needed.

[0072] Step 2: Determine the location of the power supply port of the circuit module in the power bus network.

[0073] For example, Figure 5 This is a schematic diagram of an integrated structure of a circuit module and a power bus network provided in an embodiment of the present invention, as shown below. Figure 5As shown, the location of circuit module 12 in the power bus network is determined based on the chip planar layout diagram. Each power port of each circuit module 12 is identified, and its position in the power bus network is determined. This prepares for subsequently determining the connection path between each power port of each circuit module 12 and the power pad 101. Specifically, as... Figure 5 As shown, taking circuit module 12, which includes power module 1, power module 2, power module 3, and power module 4, as an example, each circuit module 12 includes two power ports, which are used to connect to power pad 101 that provides a high level and power pad 101 that provides a low level, respectively. The positions of power module 1, power module 2, power module 3, and power module 4 in the power bus network are determined according to the chip planar layout diagram. Each power port of each circuit module 12 is found, and the position of the power port in the power bus network is determined. Then, the connection path between each power port of each circuit module 12 and the power pad 101 is determined.

[0074] Step 3: Create a power supply network model based on the power bus network.

[0075] For example, Figure 6 This is a schematic diagram of a power supply network model provided in an embodiment of the present invention. Figure 7 This is a schematic diagram of the structure of a power supply network unit provided in an embodiment of the present invention, as shown below. Figure 6 and Figure 7 As shown, the power supply network model includes an array of multiple pads 20 and multiple power supply network units 23, which are interconnected via power lines 21 and / or power bridge connections 22. Each power supply network unit 23 includes multiple power lines 21 and multiple power bridge connections 22, wherein the power lines 21 and power bridge connections 22 contain at least one of resistors 231 and capacitors 232. The values ​​of parasitic resistance and / or parasitic capacitance on the power lines 21 and power bridge connections 22 can be calculated and added to the resistors 231 and / or capacitors 232 of the power supply network unit 23, so that the power supply network model incorporates parasitic parameters on the power bus network. The method for manually building the power supply network model in this embodiment is simple and effective, and facilitates tracking of optimization modifications to the power supply network.

[0076] Step 4: Generate a netlist containing the power supply network based on the power supply network model and the position of the power ports of the circuit module in the power bus network.

[0077] For example, Figure 8 This is a schematic diagram of an integrated structure of a circuit module and a power supply network model provided in an embodiment of the present invention, with reference to... Figure 5 and Figure 8The power bus network is compared with the power supply network model. Based on the position of the power port of circuit module 12 in the power bus network, the position of the power port of circuit module 12 in the power supply network model is determined. Based on the connection path between the power port of circuit module 12 and the power pad 101 in the power bus network, the connection path between the power port of circuit module 12 and the pad 20 in the power supply network model is determined. The power supply network unit 23 located on the connection path is integrated with the circuit netlist to generate a netlist embedded with the power supply network, so that the netlist embedded with the power supply network contains parasitic parameters on the power bus network. Figure 8 Only a schematic diagram of the integrated structure of circuit module 2 and the power supply network model is shown. Figure 5 In the diagram, PDN2-1 represents the set of power supply network units on the connection path between the power port of circuit module 2 and the power pad 101. Similarly, PDN2-2, PDN1-1, PDN1-2, PDN3-1, PDN3-2, PDN4-1, and PDN4-2 represent the set of power supply network units on the corresponding path between each power port of each circuit module 12 and the power pad 101.

[0078] Step 5: Perform circuit simulation based on the netlist containing the power supply network.

[0079] In this embodiment, circuit simulation is performed on the netlist containing the power supply network, which has parasitic parameters on the power bus network. This verifies in advance whether the chip's power supply network design meets the requirements, reducing the difficulty of subsequent design, thereby shortening the chip design development cycle and reducing design costs. It should be noted that the design method in this embodiment can perform circuit simulation before the layout design is completed, after the complete layout design, or after part of the layout design is completed. Furthermore, multiple simulations can be performed throughout the design process, and those skilled in the art can choose the appropriate method.

[0080] The chip design method provided in this invention creates a power bus network based on pad locations and chip planar layout, determines the position of the power ports of circuit modules within the power bus network, creates a power supply network model based on the power bus network, generates a netlist embedding the power supply network based on the power supply network model and the positions of the power ports of circuit modules within the power bus network, performs circuit simulation based on the netlist embedding the power supply network, integrates parasitic parameters in the power bus network into the circuit netlist for simulation, and realizes power integrity analysis of the chip to verify whether the chip's power supply network design meets the requirements. This reduces the difficulty of power supply network design, thereby shortening the chip design development cycle and reducing design costs.

[0081] Optionally, the circuit module is a critical timing circuit module.

[0082] Among them, the critical timing circuit module is a circuit module that is more sensitive to power supply. By adding the parasitic parameters of the power bus 11 on the connection path between the power port of the critical timing circuit module and the power pad 101 to the circuit netlist for simulation, the circuit modules that are not sensitive to power supply are ignored. This ensures that the voltage and current of the power port of the critical timing circuit module meet the requirements, while helping to reduce the amount of calculation and improve the simulation speed.

[0083] Optionally, the critical timing circuit modules include circuit modules on any one or more timing paths of the chip, such as the read timing path, write timing path, array timing path, and command timing path, and the chip includes dynamic random access memory (DRAM).

[0084] Among them, the circuit modules on the read timing path, write timing path, array timing path, and command timing path of the chip are usually more important and more sensitive to power supply. Therefore, the circuit modules on the read timing path, write timing path, array timing path, and command timing path are set as critical timing circuit modules. The parasitic parameters of the power bus 11 on the connection path between the power port of the critical timing circuit module and the power pad 101 are added to the circuit netlist for simulation. This realizes the power integrity analysis of the critical timing circuit module, ensures that the voltage and current of the power port of the critical timing circuit module meet the requirements, reduces the design difficulty, shortens the chip design development cycle, and reduces the design cost.

[0085] Optionally, creating a power supply network model based on the power bus network includes:

[0086] Create a layout of the power bus network based on the power bus network.

[0087] Parasitic parameters are extracted from the layout of the power bus network.

[0088] Calculate the value of the parasitic parameter.

[0089] The power supply network model is created based on the values ​​of the parasitic parameters.

[0090] Figure 9 This is a flowchart illustrating a process for creating a power supply network model using computational software, as provided in an embodiment of the present invention. Figure 9 As shown, for example, creating a power supply network model based on the power bus network specifically includes:

[0091] Setup design: Based on the width, spacing, and hierarchy of the power buses in the power bus network, design the layout of the power bus network. The layout of the power bus network is a planar geometric description of the physical state of the power bus network.

[0092] Power Grid Extraction (PG): Using the software's parasitic parameter extraction function, parasitic resistance and / or parasitic capacitance in the power distribution network are extracted from the layout of the power bus network.

[0093] Power calculation: Calculates the values ​​of parasitic resistance and / or parasitic capacitance, or other parasitic parameters.

[0094] CPM creation: Automatically create a CPM (chip power model) based on the values ​​of the parasitic parameters mentioned above to form a power supply network model.

[0095] In particular, by using software to extract parasitic parameters from the power distribution network layout to create the power supply network model, the accuracy of the power supply network model can be improved.

[0096] Optionally, before extracting parasitic parameters from the layout of the power bus network, the layout of the circuit module may be created.

[0097] For details, please refer to [link / reference]. Figure 2 In chip design, after creating the chip planar layout, circuit schematic, and circuit netlist, pre-simulation is performed. The circuit is optimized based on the pre-simulation results. After successful pre-simulation, the final layout design of each circuit module is completed. The circuit layout is created, and standard parasitic format extraction is performed on the layout to obtain the parasitic parameters of each circuit module and signal trace on the layout. The parasitic parameters of the layout are added to the circuit for post-simulation. Based on the post-simulation structure, the circuit is optimized, and the layout design is adjusted until it passes post-simulation verification. The layout of the circuit modules can be created before extracting parasitic parameters from the power bus network layout. This allows for simultaneous extraction of parasitic parameters from the power bus network layout and standard parasitic format extraction from the circuit module layout using software, which helps to further shorten the chip design and development cycle.

[0098] Optionally, a power supply network model is created based on the power bus network, including:

[0099] Create a power supply network unit, the power supply network unit including multiple power lines and multiple power bridge connections, each of the power lines and the power bridge connections including at least one of resistors and capacitors;

[0100] Based on the power bus network, an array of multiple power supply network units is created to constitute the power supply network model.

[0101] For example, continue to refer to Figure 6 and Figure 7 The power supply network model can also be created manually. The specific process is as follows: As needed, a power supply network unit 23 is created. Each power supply network unit 23 includes multiple power lines 21 and multiple power bridge connections 22. Each power line 21 and power bridge connection 22 contains at least one of a resistor 231 and a capacitor 232. The position and number of resistors 231 and capacitors 232 can be set according to actual needs; this embodiment of the invention does not limit this. Based on the power bus network, an array formed by multiple power supply network units 23 is created. The multiple power supply network units 23 are electrically connected to each other through power lines 21 and / or power bridge connections 22 to ultimately form the power supply network model.

[0102] Both the power line 21 and the power bridge connection 22 can be composed of a single layer or multiple layers of metal. For example, continue to refer to... Figure 7 The power lines 21 and power bridge connections 22 may include multiple power types, such as V1-1, V2-1, V3-1, V1-2, V3-2, V2-2, V1-3, and V3-3 power supplies as shown in the figure. Multiple power lines 21 include those of the same power type but used for different purposes. Each power bridge connection 22 is used to electrically connect at least some of the power lines 21 of the same power type but used for different purposes. The power pads 101 are used to electrically connect to the power lines 21 of the corresponding power type, providing them with the corresponding type of power. Those skilled in the art can customize the number of metal layers and the number and connection relationships of power lines 21 and power bridge connections 22 within the power supply network unit 23 according to actual needs.

[0103] Optionally, the values ​​of resistor 231 and capacitor 232 can be programmed.

[0104] The values ​​of resistor 231 and capacitor 232 can be programmed, making it easy to modify their values ​​in the power supply network unit 23. When optimizing the circuit, the values ​​of parasitic resistance and / or parasitic capacitance on the power line 21 and power bridge connection 22 can be calculated in real time based on the optimization results. The values ​​of parasitic resistance and / or parasitic capacitance can be added to the resistor 231 and / or capacitor 232 in the power supply network unit 23 through programming, which helps to further shorten the chip design and development cycle.

[0105] Optionally, the values ​​of resistor 231 and capacitor 232 are calculated based on the size and material of power line 21 or power bridge connection 22.

[0106] The values ​​of resistor 231 and capacitor 232 can be calculated based on the size and material of power line 21 or power bridge connection 22. When optimizing the circuit later, it is only necessary to intuitively adjust the size and material of power line 21 or power bridge connection 22 and update the values ​​of resistor 231 and capacitor 232 by calculation.

[0107] In other embodiments, the values ​​of resistor 231 and capacitor 232 can be calculated based on the spacing and layering of power lines 21 or power bridge connections 22 to obtain more accurate parasitic parameters. This embodiment of the invention does not limit this.

[0108] Figure 10 A flowchart illustrating another chip design method provided in an embodiment of the present invention is shown below. Figure 10 As shown, optionally, before creating the power bus network based on the pad locations and chip planar layout, the following steps are also included:

[0109] Create a packaged power supply network (PDN) and / or signal supply network (SDN) model for the chip;

[0110] The creation of a power supply network model based on the power bus network includes:

[0111] Create a power supply network model based on the power bus network, the chip's packaged power supply network model, and / or the signal supply network model.

[0112] In other embodiments, the chip design method may also include:

[0113] Create control chip, channel PDN model and / or SDN model;

[0114] The creation of a power supply network model based on the power bus network includes:

[0115] A power supply network model is created based on the power bus network and control chip, channel PDN model and / or SDN model.

[0116] Figure 11 A schematic diagram of a storage system provided in an embodiment of the present invention is shown below. Figure 11 As shown, exemplarily, the chip designed by the chip design method provided in this embodiment of the invention can be a memory chip. The control chip is used to control the memory chip to perform read and write operations. The control chip and the memory chip are respectively packaged and then mounted on a substrate. (Continue to refer to...) Figure 10Before creating the power bus network based on the pad locations and chip planar layout, creating control chip, channel PDN and / or SDN (signal distribution network) models, and memory chip package power supply network and / or signal supply network models, and integrating them into the creation of the power network supply model in this embodiment, can further improve the accuracy between circuit simulation and actual performance, thereby making the simulation results more consistent with reality, obtaining accurate simulation results, and achieving the effect of "what you design is what you get," further shortening the design cycle, reducing design costs, and increasing the design success rate. It should be noted that... Figure 11 This embodiment only describes one storage system architecture to which the design method is applicable; the packaging and integration forms of the storage chip and the control chip are not limited to these specific examples. Figure 11 The design method of this embodiment is also applicable to other forms of packaging and integration. This embodiment does not limit this, and those skilled in the art can set it up as needed.

[0117] Optionally, determining the location of the power supply port of the circuit module in the power bus network includes:

[0118] Determine the horizontal and vertical coordinates of the power supply ports of the circuit module in the power bus network.

[0119] In this context, a horizontal and vertical axis are defined in the power bus network to represent the position of the power ports of the circuit module within the power bus network. (Continue to refer to...) Figure 5 For example, the power bus network has horizontal coordinates X-2 to X2 and vertical coordinates Y0 to Y2. By determining the horizontal and vertical coordinates of the power port of the circuit module 12 in the power bus network, the position of the power port of the circuit module in the power bus network can be determined. This method is relatively simple and easy to implement.

[0120] In other embodiments, the position of the power port of the circuit module in the power bus network can also be determined in polar coordinates, and the embodiments of the present invention do not limit this.

[0121] Optionally, generating a netlist embedded with the power supply network based on the power supply network model and the location of the power ports of the circuit module in the power bus network includes:

[0122] A power supply network configuration file is generated based on the power supply network model and the location of the power ports of the circuit module in the power bus network. The power supply network configuration file is used to integrate the power supply network model and the circuit module.

[0123] Generate a netlist containing the power supply network based on the power supply network configuration file.

[0124] This process involves generating a power supply network configuration file, which integrates the power supply network model and circuit modules by importing the configuration file, and generating a netlist with the power supply network embedded. This operation is simple and reduces workload.

[0125] Optionally, the power supply network profile may include at least the horizontal and vertical coordinates of the power ports of the circuit modules in the power bus network.

[0126] Specifically, by importing the power supply network configuration file, the horizontal and vertical coordinate information of the power ports of the circuit modules in the power bus network is obtained, the position of the power ports of the circuit modules in the power supply network model is determined, and then the connection path between the power ports of the circuit module 12 and the pads 20 is determined. The power supply network units 23 located on the connection path are integrated with the circuit netlist to generate a netlist with embedded power supply network, so that the netlist with embedded power supply network contains parasitic parameters on the power bus network.

[0127] Table 1 below is a schematic diagram of a power supply network configuration file provided in an embodiment of the present invention.

[0128] Table 1

[0129]

[0130] For example, as shown in Table 1, the power supply network configuration file may include information such as power grid name, net in PDN model, power for instance block, power pin of instance block, decap on power grid, layout location, and notes. Here, instance block is the name of the circuit module in the chip; power pin of instance block is the name of the power port of the circuit module; power bus name is the name of the power bus through which the power port of the circuit module connects to the power pad unit 201; net in PDN model is the name of the aforementioned power bus in the power supply network model; layout location is the horizontal and vertical coordinate information of the power port of the circuit module in the power bus network; decoupling capacitor indicates whether a decoupling capacitor is needed (e.g., 0 represents no decoupling capacitor, 1 represents a decoupling capacitor, but this embodiment does not limit this); this capacitor can provide a more stable power supply and also reduce noise coupled from components to the power supply terminal, indirectly reducing the impact of this component's noise on other components; notes can provide other integration-related information. After importing the power supply network configuration file, identify the power pins and power bus names of the instance module, match them with the circuit netlist, and add power supply network units between the power pins and power buses of the instance module in the circuit netlist according to the location and names in the PDN model, thereby generating a netlist with embedded power supply networks.

[0131] In other embodiments, those skilled in the art can configure the power supply network configuration file according to actual needs, and the embodiments of the present invention do not limit this.

[0132] Optionally, after performing circuit simulation based on the netlist embedded with the power supply network, the method further includes:

[0133] Modify the power bus network or the circuit module;

[0134] Generate a modified netlist containing the power supply network;

[0135] Circuit simulation is performed based on the modified netlist with embedded power supply network.

[0136] For example, continue to refer to Figure 2 and Figure 10After simulating the circuit using a netlist with an embedded power supply network, timing analysis is performed on the simulation results. Based on the analysis results, the power bus network or circuit modules are modified to optimize the circuit. Then, a modified netlist with an embedded power supply network is generated. Circuit simulation is performed based on the modified netlist with an embedded power supply network until the simulation is verified, at which point the tape-out process begins.

[0137] Continue to refer to Figure 2 and Figure 10 The chip design method provided by this invention can be applied to the pre-simulation stage (before creating the layout) and / or the post-simulation stage (after creating the layout), without changing the conventional chip design flow, making it flexible in application.

[0138] The chip design method provided in this invention creates a power bus network based on pad locations and chip planar layout, determines the position of the power ports of circuit modules within the power bus network, creates a power supply network model based on the power bus network, generates a netlist embedding the power supply network based on the power supply network model and the positions of the power ports of circuit modules within the power bus network, performs circuit simulation based on the netlist embedding the power supply network, and integrates parasitic parameters in the power bus network into the circuit netlist for simulation, thereby achieving power integrity analysis of the chip, reducing design complexity, shortening the chip design development cycle, and reducing design costs. Furthermore, this method can be applied to any simulation stage in a conventional chip design flow, offering flexible application.

[0139] Based on the same inventive concept, embodiments of the present invention also provide a chip design apparatus. Figure 12 This is a schematic diagram of a chip design apparatus provided in an embodiment of the present invention, such as... Figure 12 As shown, the chip design apparatus provided in this embodiment of the invention includes:

[0140] The power bus network generation module 31 is used to create a power bus network based on the pad locations and chip planar layout.

[0141] The circuit module location determination module 32 is used to determine the location of the power supply port of the circuit module in the power bus network.

[0142] The power supply network model generation module 33 is used to create a power supply network model based on the power bus network.

[0143] The netlist generation module 34 with embedded power supply network is used to generate a netlist with embedded power supply network based on the power supply network model and the position of the power ports of the circuit module in the power bus network.

[0144] The simulation module 35 is used to perform circuit simulation based on the netlist embedded with the power supply network.

[0145] Figure 13 This is a schematic diagram of the structure of a power supply network model generation module provided in an embodiment of the present invention, as shown below. Figure 13 As shown, optionally, the power supply network model generation module 33 includes:

[0146] The power bus network layout generation unit 331 is used to create the layout of the power bus network based on the power bus network.

[0147] Parasitic parameter extraction unit 332 is used to extract parasitic parameters from the layout of the power bus network.

[0148] Parasitic parameter calculation unit 333 is used to calculate the value of the parasitic parameter.

[0149] The power supply network model generation unit 334 is used to create the power supply network model based on the values ​​of the parasitic parameters.

[0150] Figure 14 This is a schematic diagram of the structure of a power supply network model generation module provided in an embodiment of the present invention, as shown below. Figure 14 As shown, optionally, the power supply network model generation module 33 includes:

[0151] The power supply network unit generation unit 335 is used to generate power supply network units as needed. The power supply network unit includes multiple power lines and multiple power bridge connections. Each power line and power bridge connection includes at least one of resistors and capacitors.

[0152] The power supply network model generation unit 336 is used to create an array of multiple power supply network units to form a power supply network model.

[0153] Figure 15 This is a schematic diagram of a netlist generation module embedded with a power supply network provided in an embodiment of the present invention, as shown below. Figure 15 As shown, optionally, the netlist generation module 34 embedded with the power supply network includes:

[0154] The power supply network configuration file generation unit 341 generates a power supply network configuration file based on the power supply network model and the position of the power port of the circuit module in the power bus network. The power supply network configuration file is used to integrate the power supply network model and the circuit module.

[0155] The netlist generation unit 342, which is embedded with the power supply network, generates a netlist embedded with the power supply network according to the power supply network configuration file.

[0156] The chip design apparatus provided in the embodiments of the present invention can execute the chip design method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the method. The explanations of the same or corresponding structures and terms as described in the above embodiments will not be repeated here.

[0157] Based on the same inventive concept, embodiments of the present invention also provide a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that the processor executes the computer program to implement the chip design method provided in any embodiment of the present invention.

[0158] Figure 16 A schematic diagram of the structure of a computer device provided in an embodiment of the present invention, such as... Figure 16 As shown, the computer device includes a processor 40, a memory 41, an input device 42, and an output device 43; the number of processors 40 in the computer device can be one or more. Figure 16 Taking a processor 40 as an example; the processor 40, memory 41, input device 42, and output device 43 in a computer device can be connected via a bus or other means. Figure 16 Taking the example of a connection between China and Israel via a bus.

[0159] The memory 41, as a computer-readable storage medium, can be used to store software programs, computer-executable programs, and modules, such as the program instructions / modules corresponding to the chip design method in this embodiment of the invention (e.g., the power bus network generation module 31, the circuit module location determination module 32, the power supply network model generation module 33, the netlist generation module 34 with embedded power supply network, and the simulation module 35 in the chip design device). The processor 40 executes various functional applications and data processing of the computer device by running the software programs, instructions, and modules stored in the memory 41, thereby realizing the chip design method described above.

[0160] The memory 41 may primarily include a program storage area and a data storage area. The program storage area may store the operating system and at least one application program required for a given function; the data storage area may store data created based on terminal usage. Furthermore, the memory 41 may include high-speed random access memory and non-volatile memory, such as at least one disk storage device, flash memory, or other non-volatile solid-state storage device. In some instances, the memory 41 may further include memory remotely located relative to the processor 40, which can be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0161] Input device 42 can be used to receive input digital or character information, and to generate key signal inputs related to user settings and function control of the computer device. Output device 43 may include display devices such as a display screen.

[0162] Based on the same inventive concept, embodiments of the present invention also provide a storage medium containing computer-executable instructions, characterized in that the computer-executable instructions, when executed by a computer processor, are used to execute the chip design method provided in any embodiment of the present invention.

[0163] The design methodology for this chip includes:

[0164] Step 1: Create a power bus network based on the pad locations and chip planar layout.

[0165] Step 2: Determine the location of the circuit module's power port within the power bus network.

[0166] Step 3: Create a power supply network model based on the power bus network.

[0167] Step 4: Generate a netlist containing the power supply network based on the power supply network model and the position of the power ports of the circuit module in the power bus network.

[0168] Step 5: Perform circuit simulation based on the netlist containing the power supply network.

[0169] Of course, the computer-executable instructions provided in the embodiments of the present invention are not limited to the method operations described above, but can also perform related operations in the chip design method provided in any embodiment of the present invention.

[0170] Based on the above description of the implementation methods, those skilled in the art can clearly understand that the present invention can be implemented using software and necessary general-purpose hardware, and of course, it can also be implemented using hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as a computer floppy disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk, or optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0171] It is worth noting that in the embodiments of the chip design device described above, the various units and modules included are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of each functional unit are only for easy differentiation and are not used to limit the scope of protection of the present invention.

[0172] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A chip design method, characterized in that, include: Create a power bus network based on the pad locations and chip planar layout; Determine the location of the power port of the circuit module in the power bus network, and then determine the connection path between the power port of the circuit module and the pad; A power supply network model is created based on the power bus network, and the power supply network model includes power supply network units; Based on the power supply network model and the position of the power port of the circuit module in the power bus network, the power supply network unit located on the connection path is integrated with the circuit netlist to generate a netlist embedded with the power supply network; each circuit module includes at least two connection paths, which pass through several repeated power supply network units arranged in an array, and the power supply network units passed through by the two connection paths are different, and each power supply network unit includes the value of parasitic resistance and / or the value of parasitic capacitance; Circuit simulation is performed based on the netlist containing the embedded power supply network.

2. The chip design method according to claim 1, characterized in that, The circuit module is a critical timing circuit module.

3. The chip design method according to claim 2, characterized in that, The key timing circuit module includes circuit modules on any one or more timing paths of the chip, such as the read timing path, write timing path, array timing path, and command timing path.

4. The chip design method according to claim 1, characterized in that, Creating a power supply network model based on the power bus network includes: Create a layout of the power bus network based on the power bus network; Parasitic parameters are extracted from the layout of the power bus network; Calculate the values ​​of the parasitic parameters; The power supply network model is created based on the values ​​of the parasitic parameters.

5. The chip design method according to claim 4, characterized in that, Before extracting parasitic parameters from the layout of the power bus network, the layout of the circuit module is also created.

6. The chip design method according to claim 1, characterized in that, Create a power supply network model based on the power bus network, including: Create a power supply network unit, the power supply network unit including multiple power lines and multiple power bridge connections, each of the power lines and the power bridge connections including at least one of resistors and capacitors; Based on the power bus network, an array of multiple power supply network units is created to constitute the power supply network model.

7. The chip design method according to claim 6, characterized in that, The values ​​of the resistor and / or the capacitor are programmable.

8. The chip design method according to claim 7, characterized in that, The values ​​of the resistor and / or capacitor are calculated based on the size and material of the power line or the power bridge connection.

9. The chip design method according to claim 1, characterized in that, Also includes: Create a packaged power supply network model and / or signal supply network model for the chip; Creating a power supply network model based on the power bus network includes: The power supply network model is created based on the power bus network, the chip's packaged power supply network model, and / or the signal supply network model.

10. The chip design method according to claim 9, characterized in that, Also includes: Create control chip, channel PDN model and / or SDN model; Creating a power supply network model based on the power bus network includes: The power supply network model is created based on the power bus network, the control chip, the channel PDN model, and / or the SDN model.

11. The chip design method according to claim 1, characterized in that, Determining the location of the power supply port of the circuit module within the power bus network includes: Determine the horizontal and vertical coordinates of the power supply ports of the circuit module in the power bus network.

12. The chip design method according to claim 11, characterized in that, Based on the power supply network model and the location of the power ports of the circuit module in the power bus network, a netlist embedded with the power supply network is generated, including: A power supply network configuration file is generated based on the power supply network model and the location of the power ports of the circuit module in the power bus network. The power supply network configuration file is used to integrate the power supply network model and the circuit module. Generate a netlist containing the power supply network based on the power supply network configuration file.

13. The chip design method according to claim 12, characterized in that, The power supply network configuration file includes at least the horizontal and vertical coordinate information of the power ports of the circuit module in the power bus network.

14. The chip design method according to claim 1, characterized in that, After performing circuit simulation based on the netlist embedded with the power supply network, the method further includes: Modify the power bus network or the circuit module; Generate a modified netlist containing the power supply network; Circuit simulation is performed based on the modified netlist containing the power supply network.

15. A chip design apparatus, characterized in that, include: The power bus network generation module is used to create a power bus network based on the pad locations and chip planar layout. A circuit module location determination module is used to determine the location of the power port of the circuit module in the power bus network, and then determine the connection path between the power port of the circuit module and the pad. A power supply network model generation module is used to create a power supply network model based on the power bus network, wherein the power supply network model includes power supply network units. A netlist generation module with embedded power supply network is used to integrate the power supply network unit located on the connection path with the circuit netlist according to the power supply network model and the position of the power port of the circuit module in the power bus network, so as to generate a netlist with embedded power supply network. Each of the circuit modules includes at least two connection paths that pass through several power supply network units arranged in an array, and the power supply network units passed through by the two connection paths are different, each power supply network unit including the value of parasitic resistance and / or the value of parasitic capacitance. The simulation module is used to perform circuit simulation based on the netlist embedded with the power supply network.

16. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the chip design method as described in any one of claims 1-14.

17. A storage medium containing computer-executable instructions, characterized in that, The computer-executable instructions, when executed by a computer processor, are used to perform the design method of the chip according to any one of claims 1-14.

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