Method, device and system for determining the position of a chip decoupling capacitor

Abstract

The present application relates to a method, device, and system for determining the position of a chip decoupling capacitor. The method includes: establishing a first PCB three-dimensional model based on the chip to be tested and the PCB trace; establishing a second PCB three-dimensional model based on the first PCB three-dimensional model and the decoupling capacitor, and confirming the position where the decoupling capacitor is set as the current position; obtaining a corresponding second S parameter based on a preset current absorption frequency; inputting a preset EMI radiation excitation signal into the second PCB three-dimensional model and outputting a second EMI radiation intensity; if the second S parameter and the second EMI radiation intensity do not meet the preset EMI radiation condition, setting the decoupling capacitor on the PCB trace between the power supply pin and the current position, and updating the current position to the position where the decoupling capacitor is set until the preset EMI radiation condition is met, and confirming the updated current position as the optimized position of the decoupling capacitor, thereby optimizing the position of the decoupling capacitor, improving the efficiency of confirming the position of the decoupling capacitor, and thus improving the production efficiency of the chip circuit.

Description

Technical Field

[0001] The present application relates to the field of chip circuit technology, and in particular to a method, device, and system for determining the position of a chip decoupling capacitor. Background Art

[0002] When switching between high- and low-level levels, the chip's high-frequency clocks and high-speed signals draw current from the chip's power supply pins. This current draw aligns with the frequency of these signals, causing the chip's power supply pins and the connected PCB power supply traces to carry the spectrum of these frequency signals, resulting in excessive EMI emissions. Decoupling capacitors are typically required for the chip's power supply pins to provide a smaller loop area for this spectrum energy, reducing the size of the EMI radiation's equivalent antenna and thereby reducing EMI emissions. The placement of the decoupling capacitors varies depending on the location of the decoupling capacitors.

[0003] Conventional design methods cannot determine the allowable distance between decoupling capacitors and chip power pins. Consequently, EMC performance varies depending on the placement of the decoupling capacitors. Consequently, the only way to determine the proper placement of the decoupling capacitors is to first select a decoupling capacitor location, produce samples, and then verify the results in a semi-anechoic chamber. If the test fails, the distance and location of the decoupling capacitors must be adjusted, and samples must be re-produced and re-tested in the semi-anechoic chamber. This process must be repeated until a decoupling capacitor location that passes the test is found. This inefficient decoupling capacitor location verification, in turn, impacts production efficiency. Summary of the Invention

[0004] Based on this, it is necessary to address the problem of low efficiency in determining the position of the decoupling capacitor at the power supply pin of the above-mentioned traditional chip, and provide a chip decoupling capacitor position determination method, device and system that can quickly determine the allowable distance between the decoupling capacitor and the chip power supply pin.

[0005] In a first aspect, the present application provides a method for determining the position of a chip decoupling capacitor, comprising:

[0006] A first PCB three-dimensional model is established based on the chip under test and PCB traces, wherein the PCB traces are traces connected to power supply pins of the chip under test;

[0007] Building a second PCB three-dimensional model based on the first PCB three-dimensional model and the decoupling capacitors arranged on the PCB traces, and confirming the location where the decoupling capacitors are arranged as the current location;

[0008] Obtaining a second S parameter corresponding to the second PCB three-dimensional model according to a preset absorption current frequency; inputting a preset EMI radiation excitation signal to the second PCB three-dimensional model, and outputting a second EMI radiation intensity corresponding to the second PCB three-dimensional model;

[0009] If the second S parameter and the second EMI radiation intensity do not meet the preset EMI radiation condition, the decoupling capacitor is set between the power supply pin of the PCB trace of the first PCB three-dimensional model and the current position, and the current position is updated to the position where the decoupling capacitor is set until the second S parameter and the second EMI radiation intensity meet the preset EMI radiation condition, and the updated current position is confirmed as the optimized position of the decoupling capacitor.

[0010] Optionally, after the step of establishing a first PCB three-dimensional model based on the chip to be tested and PCB traces connected to power supply pins of the chip to be tested, the method includes:

[0011] According to the preset absorption current frequency, a first S parameter corresponding to the first PCB three-dimensional model is obtained; a preset EMI radiation excitation signal is input to the first PCB three-dimensional model, and a first EMI radiation intensity corresponding to the first PCB three-dimensional model is output.

[0012] Optionally, if the second S parameter and the second EMI radiation intensity do not meet the preset EMI radiation condition, before the step of setting a decoupling capacitor between a power supply pin of a PCB trace of the first PCB three-dimensional model and the current position, the method includes:

[0013] Comparing the first S parameter and the second S parameter to obtain an attenuation ratio of the first frequency band;

[0014] Comparing the first EMI radiation intensity with the second EMI radiation intensity to obtain a first radiation intensity difference;

[0015] When the attenuation ratio in the first frequency band falls within a preset attenuation threshold range and the first radiation intensity difference falls within a preset radiation intensity threshold range, a preset EMI radiation condition is determined for the second S parameter and the second EMI radiation intensity.

[0016] Optionally, after the step of comparing the first EMI radiation intensity with the second EMI radiation intensity to obtain a first radiation intensity difference, the method further includes:

[0017] When the attenuation ratio in the first frequency band does not fall within the preset attenuation threshold range and the first radiation intensity difference does not fall within the preset radiation intensity threshold range, replace the PCB trace connected to the power supply pin of the chip to be tested, and set the decoupling capacitor on the replaced PCB trace, and confirm the position where the decoupling capacitor is set as the current position.

[0018] Optionally, the step of inputting a preset EMI radiation excitation signal to the second PCB three-dimensional model and outputting a second EMI radiation intensity corresponding to the second PCB three-dimensional model includes:

[0019] A preset EMI radiation excitation signal is input to the second PCB three-dimensional model, and a second EMI radiation intensity at a preset distance is output.

[0020] Optionally, the preset distance is 3 meters.

[0021] Optionally, the optimized position includes first distance information between the decoupling capacitor and the power supply pin and second distance information between the decoupling capacitor and the ground plane.

[0022] Optionally, the range of the first distance information is 0 to 2 mm; the range of the second distance information is 0 to 2 mm.

[0023] In a second aspect, the present application provides a device for determining the position of a chip decoupling capacitor, comprising:

[0024] A first PCB three-dimensional model building unit is configured to build a first PCB three-dimensional model based on the chip to be tested and PCB traces, wherein the PCB traces are traces connected to power supply pins of the chip to be tested;

[0025] A second PCB three-dimensional model establishing unit is configured to establish a second PCB three-dimensional model based on the first PCB three-dimensional model and the decoupling capacitors arranged on the PCB traces, and to determine the location where the decoupling capacitors are arranged as the current location;

[0026] The model processing unit is configured to obtain a second S parameter corresponding to the second PCB three-dimensional model according to a preset current absorption frequency; input a preset EMI radiation excitation signal to the second PCB three-dimensional model, and output a second EMI radiation intensity corresponding to the second PCB three-dimensional model;

[0027] a position determining unit, configured to, if the second S parameter and the second EMI radiation intensity do not satisfy a preset EMI radiation condition, set a decoupling capacitor between a power supply pin of a PCB trace of the first PCB three-dimensional model and the current position, and update the current position to a position where the decoupling capacitor is set, until the second S parameter and the second EMI radiation intensity satisfy the preset EMI radiation condition, and confirm the updated current position as an optimized position of the decoupling capacitor.

[0028] In a third aspect, the present application provides a chip decoupling capacitor position determination system, which includes a memory, a processor, and a computer program stored in the memory and runnable on the processor. When the processor executes the computer program, it implements the steps of any of the above-mentioned chip decoupling capacitor position determination methods.

[0029] One of the above technical solutions has the following advantages and beneficial effects:

[0030] In the above-mentioned method for determining the position of a chip decoupling capacitor, a first PCB three-dimensional model is established based on the chip to be tested and the PCB traces connected to the power supply pins of the chip to be tested, so as to subsequently establish a second PCB three-dimensional model to build a basic model; a second PCB three-dimensional model is established based on the first PCB three-dimensional model and the decoupling capacitors arranged on the PCB traces, and the position where the decoupling capacitors are arranged is determined as the current position, thereby preliminarily selecting the setting position of the decoupling capacitors; second S parameters corresponding to the second PCB three-dimensional model are obtained based on a preset absorption current frequency; a preset EMI radiation excitation signal is input to the second PCB three-dimensional model, and a second EMI radiation intensity corresponding to the second PCB three-dimensional model is output to perform simulation debugging of the second PCB three-dimensional model; if the second S parameters and the second EMI radiation intensity do not meet the preset EMI radiation conditions, the decoupling capacitors are arranged between the power supply pins of the PCB traces of the first PCB three-dimensional model and the current position, and the current position is updated to the position where the decoupling capacitors are arranged until the second S parameters and the second EMI radiation intensity meet the preset EMI radiation conditions, and the updated current position is determined as the optimized position of the decoupling capacitors, thereby optimizing the position of the decoupling capacitors and enhancing the EMC performance of the chip circuit. This application determines the allowable EMC decoupling capacitor setting position based on the required absorption current frequency, through processing calculation and EMC three-dimensional simulation technology. By establishing a PCB three-dimensional model, then extracting S parameters to obtain an EMI simulation model, and then providing the EMI simulation model with the EMI radiation intensity output by the appropriate noise excitation simulation, the current position of the decoupling capacitor is optimized, and the previous EMC simulation is repeated until the optimized position that meets the preset EMI radiation conditions is obtained. This optimizes the decoupling capacitor position, improves the efficiency of decoupling capacitor position confirmation, and thus improves the production efficiency of the chip circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is a diagram of the application environment of the chip decoupling capacitor position determination method in an embodiment of the present application.

[0032] Figure 2 This is a schematic diagram of the first flow chart of the method for determining the position of a chip decoupling capacitor in an embodiment of the present application.

[0033] Figure 3 This is a second flow chart of the method for determining the position of a chip decoupling capacitor in an embodiment of the present application.

[0034] Figure 4 This is a third flow chart of the method for determining the position of a chip decoupling capacitor in an embodiment of the present application.

[0035] Figure 5 This is a third flow chart of the method for determining the position of a chip decoupling capacitor in an embodiment of the present application.

[0036] Figure 6 This is an overall schematic diagram of setting decoupling capacitors on the power supply pins of the chip under test in an embodiment of the present application.

[0037] Figure 7 This is a schematic diagram of an embodiment of the present application in which the power supply pins of the chip under test are not provided with decoupling capacitors.

[0038] Figure 8 This is a schematic diagram of setting a decoupling capacitor at the power supply pin CV20 of the chip under test in an embodiment of the present application.

[0039] Figure 9 This is a schematic diagram of setting a decoupling capacitor at the power supply pin CV21 of the chip under test in an embodiment of the present application.

[0040] Figure 10 This is a schematic diagram of setting a decoupling capacitor at the power supply pin CV22 of the chip under test in an embodiment of the present application.

[0041] Figure 11 This is a structural block diagram of a device for determining the position of a chip decoupling capacitor in an embodiment of the present application.

[0042] Figure 12 This is an internal structure diagram of the chip decoupling capacitor position determination system in an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0044] The chip decoupling capacitor position determination method provided in this application can be applied to Figure 1In the application environment shown, the processing device 10 includes a processor 102 and a memory 104. The processor 102 can be used to establish a first PCB three-dimensional model based on the chip under test and the PCB trace; the PCB trace is a trace connecting the power supply pin of the chip under test; a second PCB three-dimensional model is established based on the first PCB three-dimensional model and the decoupling capacitor set on the PCB trace, and the location where the decoupling capacitor is set is determined as the current location; second S parameters corresponding to the second PCB three-dimensional model are obtained based on a preset current absorption frequency; a preset EMI radiation excitation signal is input to the second PCB three-dimensional model, and a second EMI radiation intensity corresponding to the second PCB three-dimensional model is output; if the second S parameters and the second EMI radiation intensity do not meet the preset EMI radiation conditions, the decoupling capacitor is set between the power supply pin of the PCB trace of the first PCB three-dimensional model and the current location, and the current location is updated to the location where the decoupling capacitor is set until the second S parameters and the second EMI radiation intensity meet the preset EMI radiation conditions, and the updated current location is determined as the optimized location of the decoupling capacitor. The processing device 10 can be, but is not limited to, various personal computers and laptop computers.

[0045] In one embodiment, Figure 2 As shown, a method for determining the position of a chip decoupling capacitor is provided, and the method is applied to Figure 1 The processor 102 in FIG. 1 is used as an example to illustrate the invention, including:

[0046] In step S210 , a first PCB three-dimensional model is established based on the chip to be tested and PCB (Printed Circuit Board) traces; the PCB traces are traces connected to power supply pins of the chip to be tested.

[0047] The chip under test refers to a processing chip capable of processing high-frequency clocks and high-speed signals. The chip under test has a power supply pin connected to a PCB trace. The PCB trace may include at least one trace. For example, the PCB trace may include two traces, one of which has one end connected to the power supply pin of the chip under test and the other end connected to a power supply. The other PCB trace has one end connected to the power supply pin of the chip under test and the other end connected to a ground plane.

[0048] For example, the chip under test and PCB traces may be disposed on a circuit substrate. A first PCB three-dimensional model may be established based on characteristic information of the chip under test and characteristic information of the PCB traces. The characteristic information of the chip under test may include operating characteristic information of the chip under test, such as operating frequency and operating voltage; the characteristic information of the PCB traces may include dimensional information and impedance information of the PCB traces. Thus, the first PCB three-dimensional model includes the characteristic information of the chip under test and the characteristic information of the PCB traces.

[0049] In step S220 , a second PCB three-dimensional model is established based on the first PCB three-dimensional model and the decoupling capacitors arranged on the PCB traces, and the position where the decoupling capacitors are arranged is determined as the current position.

[0050] Decoupling capacitors are capacitors installed at the power supply terminals of components (chips) in a circuit. They provide a more stable power supply and reduce noise coupled to the power supply terminals, indirectly reducing the impact of this noise on other components. Decoupling capacitors are placed close to the power supply pins of the chip under test. Different placement of the decoupling capacitors will affect the intensity of EMI radiation.

[0051] By selecting a location on the PCB trace to set the decoupling capacitor, the location where the decoupling capacitor is set is determined as the current location. For example, a location on the PCB trace can be randomly selected as the location where the decoupling capacitor is set. The decoupling capacitor includes characteristic information of the decoupling capacitor, such as capacitance value information and withstand voltage value information. Furthermore, a second PCB 3D model can be established based on the first PCB 3D model and the corresponding characteristic information of the decoupling capacitor set on the PCB trace.

[0052] In one example, a decoupling capacitor with a preset capacitance (e.g., 0.1uF) can be selected. A SPICE (Simulation Program with Integrated Circuit Emphasis) model corresponding to the decoupling capacitor is created based on the preset capacitance. The SPICE model is then placed at a selected location on a PCB trace. A second PCB 3D model is then created based on the first PCB 3D model and the SPICE model placed on the PCB trace.

[0053] In step S230 , second S parameters corresponding to the second PCB three-dimensional model are obtained according to a preset absorption current frequency; a preset EMI (Electromagnetic Interference) radiation excitation signal is input to the second PCB three-dimensional model, and a second EMI radiation intensity corresponding to the second PCB three-dimensional model is output.

[0054] The preset current draw frequency refers to the current draw frequency of the power supply pins of the chip under test, which is consistent with the high-frequency clock and high-speed signal frequencies of the chip under test. The second S-parameters (Scatter parameters) describe the frequency-domain characteristics of the transmission channel corresponding to the second 3D PCB model. Obtaining accurate S-parameters for a channel is crucial for serial link SI analysis. These S-parameters reveal nearly all characteristics of the transmission channel.

[0055] Exemplarily, the second PCB 3D model is processed based on a preset current absorption frequency (e.g., a frequency of 600 MHz) to obtain second S-parameters corresponding to the second PCB 3D model. For example, by inputting an S-parameter extraction excitation into the second PCB 3D model, corresponding second S-parameter extraction results can be obtained. The processor can preset an input excitation signal for EMI radiation simulation to obtain a preset EMI radiation excitation signal. By inputting the preset EMI radiation excitation signal into the second PCB 3D model, the EMI radiation excitation signal is processed by the second PCB 3D model to output a second EMI radiation intensity corresponding to the second PCB 3D model.

[0056] In step S240, if the second S parameter and the second EMI radiation intensity do not meet the preset EMI radiation condition, a decoupling capacitor is set between the power supply pin of the PCB trace of the first PCB three-dimensional model and the current position, and the current position is updated to the position where the decoupling capacitor is set until the second S parameter and the second EMI radiation intensity meet the preset EMI radiation condition, and the updated current position is confirmed as the optimized position of the decoupling capacitor.

[0057] The preset EMI radiation conditions may include preset values for noise attenuation and EMI radiation intensity of S parameters. The optimized position may include first distance information between the decoupling capacitor and the power supply pin and second distance information between the decoupling capacitor and the ground plane. For example, the first distance information may range from 0 to 2 mm, and the second distance information may range from 0 to 2 mm.

[0058] The processor may process the acquired second S parameter and the corresponding preset noise attenuation value of the S parameter, and process the acquired second EMI radiation intensity and the corresponding preset EMI radiation intensity value to determine whether the second S parameter and the second EMI radiation intensity meet the preset EMI radiation condition. If the second S parameter and the second EMI radiation intensity do not meet the preset EMI radiation condition, a new position is selected on the PCB trace segment between the power supply pin of the chip under test and the current position, and the decoupling capacitor is set at the selected new position, and the current position is updated to the position where the decoupling capacitor is set. Then, the processor returns to step S230 to acquire a new second S parameter and a second EMI radiation intensity, and re-judges the new second S parameter and the second EMI radiation intensity against the preset EMI radiation condition until the acquired second S parameter and the second EMI radiation intensity meet the preset EMI radiation condition. Then, the updated current position is confirmed as the optimized position of the decoupling capacitor, thereby optimizing the decoupling capacitor position setting, reducing the EMI radiation intensity, and ensuring that the EMC performance of the circuit having the chip under test meets the requirements.

[0059] In one example, if the second S parameter and the second EMI radiation intensity do not meet the preset EMI radiation condition, a new position is selected on the PCB trace segment between the power supply pin of the chip to be tested and the current position, and the SPICE model is set at the selected new position to obtain a new second PCB three-dimensional model, and the current position is updated to the position where the decoupling capacitor is set, and then the process returns to step S230 to obtain a new second S parameter and a second EMI radiation intensity, and the new second S parameter and the second EMI radiation intensity are re-judged and processed with the preset EMI radiation condition until the obtained second S parameter and the second EMI radiation intensity meet the preset EMI radiation condition, and the updated current position is confirmed as the optimized position of the decoupling capacitor.

[0060] In the above embodiment, the allowable EMC decoupling capacitor setting position is determined by processing calculations and EMC three-dimensional simulation technology based on the required absorption current frequency. By establishing a PCB three-dimensional model, then extracting S parameters to obtain an EMI simulation model, and then providing the EMI simulation model with the EMI radiation intensity output by the appropriate noise excitation simulation, the current position of the decoupling capacitor is optimized, and the previous EMC simulation is repeated until the optimized position that meets the preset EMI radiation conditions is obtained. This optimizes the decoupling capacitor position, improves the efficiency of decoupling capacitor position confirmation, and thus improves the production efficiency of the chip circuit.

[0061] In order to facilitate the comparison between the circuit of the chip under test with a decoupling capacitor and the circuit of the chip under test without a decoupling capacitor, in one example, Figure 3 As shown, a method for determining the position of a chip decoupling capacitor is provided, and the method is applied to Figure 1 The following processors are used as an example to illustrate:

[0062] Step S310 , establishing a first PCB three-dimensional model based on the chip to be tested and PCB traces; the PCB traces are traces connected to power supply pins of the chip to be tested.

[0063] Step S320 , obtaining a first S parameter corresponding to the first PCB three-dimensional model according to a preset absorption current frequency; inputting a preset EMI radiation excitation signal to the first PCB three-dimensional model, and outputting a first EMI radiation intensity corresponding to the first PCB three-dimensional model.

[0064] The first S parameter is used to describe the frequency domain characteristics of the transmission channel corresponding to the first PCB 3D model. When performing serial link SI analysis, obtaining accurate channel S parameters is a very important step. Through S parameters, we can see almost all the characteristics of the transmission channel.

[0065] Exemplarily, the first PCB three-dimensional model is processed according to a preset current absorption frequency (e.g., a frequency of 600 MHz) to obtain first S parameters corresponding to the first PCB three-dimensional model. For example, by inputting an S parameter extraction excitation into the first PCB three-dimensional model, a corresponding first S parameter extraction result can be obtained. The processor can preset an input excitation signal for EMI radiation simulation to obtain a preset EMI radiation excitation signal. By inputting a preset EMI radiation excitation signal into the first PCB three-dimensional model, the EMI radiation excitation signal is processed by the first PCB three-dimensional model, and then a first EMI radiation intensity corresponding to the first PCB three-dimensional model can be output, so as to facilitate subsequent comparative analysis of the circuit of the chip under test with a decoupling capacitor and the circuit of the chip under test without a decoupling capacitor.

[0066] Step S330 : Building a second PCB three-dimensional model based on the first PCB three-dimensional model and the decoupling capacitors arranged on the PCB traces, and confirming the location where the decoupling capacitors are arranged as the current location.

[0067] Step S340: obtaining a second S parameter corresponding to the second PCB three-dimensional model according to a preset absorption current frequency; inputting a preset EMI radiation excitation signal to the second PCB three-dimensional model, and outputting a second EMI radiation intensity corresponding to the second PCB three-dimensional model.

[0068] In step S350, if the second S parameter and the second EMI radiation intensity do not meet the preset EMI radiation condition, a decoupling capacitor is set between the power supply pin of the PCB trace of the first PCB three-dimensional model and the current position, and the current position is updated to the position where the decoupling capacitor is set until the second S parameter and the second EMI radiation intensity meet the preset EMI radiation condition, and the updated current position is confirmed as the optimized position of the decoupling capacitor.

[0069] Among them, the specific content and process of the above steps S310, S330, S340 and S350 can be referred to the above content and will not be repeated here.

[0070] In one example, if Figure 4 As shown, if the second S parameter and the second EMI radiation intensity do not meet the preset EMI radiation condition, before the step of setting the decoupling capacitor between the power supply pin of the PCB trace of the first PCB three-dimensional model and the current position, the method includes:

[0071] Step S410 : Compare the first S parameter and the second S parameter to obtain a first frequency band attenuation ratio.

[0072] The first-band attenuation ratio refers to the ratio of the noise value of the first S-parameter in the corresponding frequency band to the noise value of the second S-parameter in the corresponding frequency band. For example, if the first S-parameter without decoupling capacitors is compared with the second S-parameter with decoupling capacitors in the corresponding frequency band, a 5dB attenuation ratio in the first band indicates a 5dB improvement after adding a decoupling capacitor at the corresponding location on the PCB trace.

[0073] Step S420 : Compare the first EMI radiation intensity and the second EMI radiation intensity to obtain a first radiation intensity difference.

[0074] The first radiation intensity difference refers to the difference between the first EMI radiation intensity and the second EMI radiation intensity. For example, if the first EMI radiation intensity is A and the second EMI radiation intensity is B, the first radiation intensity difference is AB. The first radiation intensity difference can be obtained by comparing the first EMI radiation intensity without a decoupling capacitor with the second EMI radiation intensity with a decoupling capacitor.

[0075] Step S430 , when the attenuation ratio in the first frequency band falls within a preset attenuation threshold range and the first radiation intensity difference falls within a preset radiation intensity threshold range, performing a preset EMI radiation condition judgment on the second S parameter and the second EMI radiation intensity.

[0076] Among them, the PCB traces connected to the power supply pin of the chip to be tested may include two, one PCB trace connected between the power supply pin of the chip to be tested and the power supply, and the other PCB trace connected between the power supply pin of the chip to be tested and the ground. The processor may compare the attenuation ratio of the first frequency band with a preset attenuation threshold range, and compare the first radiation intensity difference with a preset radiation intensity threshold range. Based on the processing results, when the attenuation ratio of the first frequency band falls within the preset attenuation threshold range and the first radiation intensity difference falls within the preset radiation intensity threshold range, the processor performs a preset EMI radiation condition judgment process using the second S parameter and the second EMI radiation intensity. If the second S parameter and the second EMI radiation intensity do not meet the preset EMI radiation condition, a new position is selected on the PCB trace segment between the power supply pin of the chip under test and the current position, and the decoupling capacitor is set at the selected new position, and the current position is updated to the position where the decoupling capacitor is set. Then, a new second S parameter and a second EMI radiation intensity are obtained, and the new second S parameter and the second EMI radiation intensity are re-judged with the preset EMI radiation condition until the obtained second S parameter and the second EMI radiation intensity meet the preset EMI radiation condition. The updated current position is then confirmed as the optimized position of the decoupling capacitor, thereby optimizing the decoupling capacitor position setting and reducing the EMI radiation intensity, so that the EMC performance of the circuit having the chip under test meets the requirements.

[0077] In order to avoid selecting the wrong PCB trace decoupling capacitor location, the reliability of decoupling capacitor selection is improved. Figure 4 As shown, after the step of comparing the first EMI radiation intensity with the second EMI radiation intensity to obtain the first radiation intensity difference, the method includes:

[0078] In step S440, when the attenuation ratio in the first frequency band does not fall within the preset attenuation threshold range and the first radiation intensity difference does not fall within the preset radiation intensity threshold range, the PCB trace connected to the power supply pin of the chip to be tested is replaced, and the decoupling capacitor is set on the replaced PCB trace, and the position where the decoupling capacitor is set is confirmed as the current position.

[0079] Among them, the processor can compare the attenuation ratio of the first frequency band with the preset attenuation threshold range, and compare the first radiation intensity difference with the preset radiation intensity threshold range. According to the processing results, when the attenuation ratio of the first frequency band does not fall within the preset attenuation threshold range and the first radiation intensity difference does not fall within the preset radiation intensity threshold range, the PCB trace connected to the power supply pin of the chip to be tested is replaced, and it is determined that the PCB trace where the decoupling capacitor is set in the previous step is the trace connected to the ground plane, and then the PCB trace is replaced, and an arbitrary position is selected on the replaced PCB trace, and then the decoupling capacitor is set on the replaced PCB trace, and the position where the decoupling capacitor is set is confirmed as the current position. Then, a new second PCB three-dimensional model can be established based on the adjusted decoupling capacitor and the first PCB three-dimensional model, and the second PCB three-dimensional model is processed to obtain a new second S parameter and a second EMI radiation intensity. The second S parameter and the second EMI radiation intensity are used to perform a preset EMI radiation condition judgment process. When the obtained second S parameter and the second EMI radiation intensity meet the preset EMI radiation condition, the updated current position is confirmed as the optimized position of the decoupling capacitor, thereby avoiding the power supply PCB trace passing through the power supply pin of the chip under test and then connecting the decoupling capacitor through the PCB extension trace, thereby optimizing the decoupling capacitor position setting, reducing the EMI radiation intensity, and ensuring that the EMC performance of the circuit with the chip under test meets the requirements.

[0080] In order to improve EMI radiation simulation and enhance the reliability of the obtained EMI radiation intensity, in one example, the steps of inputting a preset EMI radiation excitation signal to the second PCB 3D model and outputting a second EMI radiation intensity corresponding to the second PCB 3D model include:

[0081] A preset EMI radiation excitation signal is input to the second PCB three-dimensional model, and a second EMI radiation intensity at a preset distance is output.

[0082] The preset distance can be set to 3 meters. The processor can input a preset EMI radiation excitation signal to the second PCB 3D model, process the EMI radiation excitation signal through the second PCB 3D model, and then output a second EMI radiation intensity corresponding to the second PCB 3D model at the preset distance.

[0083] In one example, the specific process of determining the location of the chip decoupling capacitor is as follows:

[0084] First, the working principle of EMC radiation generated by the power supply pins of the chip under test and the connected PCB traces is: the high-frequency clock and high-speed signal of the chip under test need to draw current from the power supply pins of the chip during the high-low level switching process. The frequency of the drawn current is consistent with the frequency of the high-frequency clock and high-speed signal, resulting in the spectrum of these frequency signals on the chip power supply pins and the PCB power supply traces connected to them, causing EMI radiation to exceed the standard. Based on this, in an example, Figure 5 The figure shows the schematic diagram of setting decoupling capacitors on the power supply pins of the chip under test; Figure 6 The figure shows the equivalent circuit of setting decoupling capacitors on the power supply pins of the chip under test.

[0085] The magnetic permeability in vacuum μ0=4π*10 -7 H / m, we get a parasitic inductance of approximately 1nH per 1mm. Therefore, the impedance between one pin of the decoupling capacitor and the chip power pin, and the impedance between the other pin of the decoupling capacitor and the PCB ground plane, are determined by the length of the PCB traces at both ends of the decoupling capacitor.

[0086] Using a 0.1uF decoupling capacitor with a preset current draw frequency of 600MHz, the decoupling capacitor's impedance is calculated to be 2.7 ohms. To ensure the decoupling capacitor's decoupling impedance is not degraded, the combined impedance of the PCB traces from the decoupling capacitor to the chip's power pins and the impedance of the PCB traces from the decoupling capacitor to the ground plane must be kept constant, as calculated in the table below. This is the basis for subsequent design based on simulated measurements of the decoupling capacitor's location.

[0087] Decoupling capacitor PCB trace length (mm) L(H) f(HZ) Impedance (ohms) 1 1.0E-09 6.0E-08 3.8 5 5.0E-09 6.0E-08 18.8 10 1.0E-08 6.0E-08 37.7 15 1.5E-08 6.0E-08 56.5 100 1.0E-07 6.0E-08 376.8

[0088] Step 1: Based on the need to set at least one decoupling capacitor on the chip power pin, set the capacitance of the decoupling capacitor to 0.1uF, and then build a SPICE model corresponding to the decoupling capacitor.

[0089] Step 2: If decoupling capacitors are not used, Figure 7As shown in the figure, a first PCB 3D model is established and the first S parameters corresponding to the first PCB 3D model are extracted based on a preset current absorption frequency (i.e., the highest frequency to be tested). An EMI radiation simulation input excitation signal is set and the first PCB 3D model is simulated to obtain the first EMI radiation intensity at a distance of three meters.

[0090] Step 2: Place the decoupling capacitor at CV20, as shown in the following example: Figure 8 As shown, a second PCB 3D model is established, and the second S parameters corresponding to the second PCB 3D model are extracted based on the preset current absorption frequency (i.e., the highest frequency to be tested). An EMI radiation simulation input excitation signal is set, and the second PCB 3D model is simulated to obtain the second EMI radiation intensity at a distance of three meters.

[0091] Step 3: Place the decoupling capacitor at CV21, as shown in the following example: Figure 9 As shown, a third PCB 3D model is established, and the third S-parameter corresponding to the third PCB 3D model is extracted based on the preset current absorption frequency (i.e., the highest frequency to be tested). An EMI radiation simulation input excitation signal is set, and the third PCB 3D model is simulated to obtain the third EMI radiation intensity at a distance of three meters.

[0092] Step 4: Place the decoupling capacitor at CV22, as shown in the following example: Figure 10 As shown, a fourth PCB 3D model is established, and fourth S parameters corresponding to the fourth PCB 3D model are extracted based on a preset current absorption frequency (i.e., the highest frequency to be tested). An EMI radiation simulation input excitation signal is set, and the fourth PCB 3D model is simulated to obtain a fourth EMI radiation intensity at a distance of three meters.

[0093] Step 5: Analyze and process the output results of steps 2 to 4 separately. For example, comparing the situation with no decoupling capacitor and the situation with a decoupling capacitor set at CV20, the improvement in the preset frequency band is about 5dB after the decoupling capacitor is set at CV20. Comparing the situation with no decoupling capacitor and the situation with a decoupling capacitor set at CV21, the improvement in the preset frequency band is about 10dB after the decoupling capacitor is set at CV21, which is closer to the chip power pin. The closer the decoupling capacitor is to the chip power pin, the smaller the parasitic inductance, the lower the decoupling impedance, and the lower the radiation. The total length of the PCB traces from the decoupling capacitor to the chip power pin and to the ground plane should be inversely proportional to the highest frequency of interest. For example, at 600MHz, 1mm is a relatively suitable length. It should be noted that by repeating steps 3 to 5, the optimal location of the decoupling capacitor (such as CV21) can be selected.

[0094] It should be noted that placing the decoupling capacitor at CV22 is an incorrect setting position. When designing, avoid having the power supply PCB trace pass through the power supply pin of the chip under test and then connect to the decoupling capacitor through the PCB trace. At the same time, the decoupling capacitor ground PCB trace should be as short as possible.

[0095] In the above embodiment, the allowable EMC decoupling capacitor setting position is determined by processing calculation and EMC three-dimensional simulation technology according to the absorption current frequency that needs to be met. By establishing a PCB three-dimensional model, then extracting S parameters to obtain an EMI simulation model, and then providing the EMI simulation model with the EMI radiation intensity of the appropriate noise excitation simulation output, the current position of the decoupling capacitor is then optimized, and the previous EMC simulation is repeated until the optimized position that meets the preset EMI radiation conditions is obtained. This allows the decoupling capacitor position to be quickly confirmed so that the circuit of the chip to be tested meets the EMI radiation performance when the decoupling capacitor position is newly designed or changed. By optimizing the decoupling capacitor position, the efficiency of decoupling capacitor position confirmation is improved, thereby improving the production efficiency of the chip circuit.

[0096] In one example, the distance between the decoupling capacitor and the chip power pin is related to the highest frequency that needs to be met. For high-frequency and high-speed product applications, the PCB trace segment between one end of the decoupling capacitor and the power pin of the chip under test should be controlled within 2mm. At the same time, the distance between the decoupling capacitor ground pin and the ground plane should also be controlled within 2mm. In addition, avoid placing the decoupling capacitor in the CV22 position, because this method not only adds extra distance, but also causes the power trace to pass through the chip power pin before the decoupling capacitor. The correct way is to pass through the decoupling capacitor before reaching the chip power pin.

[0097] It should be understood that although Figure 2-4 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 2-4 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0098] In one embodiment, Figure 11 As shown, a device for determining the position of a chip decoupling capacitor is provided, comprising:

[0099] The first PCB three-dimensional model building unit 100 is used to build a first PCB three-dimensional model according to the chip to be tested and the PCB traces; the PCB traces are traces connected to the power supply pins of the chip to be tested.

[0100] The second PCB 3D model establishing unit 200 is configured to establish a second PCB 3D model based on the first PCB 3D model and the decoupling capacitors arranged on the PCB traces, and to determine the location where the decoupling capacitors are arranged as the current location.

[0101] The model processing unit 300 is used to obtain second S parameters corresponding to the second PCB three-dimensional model according to a preset absorption current frequency; input a preset EMI radiation excitation signal to the second PCB three-dimensional model, and output a second EMI radiation intensity corresponding to the second PCB three-dimensional model.

[0102] The position determination unit 400 is configured to, if the second S parameter and the second EMI radiation intensity do not satisfy the preset EMI radiation condition, set a decoupling capacitor between the power supply pin of the PCB trace of the first PCB three-dimensional model and the current position, and update the current position to the position where the decoupling capacitor is set, until the second S parameter and the second EMI radiation intensity satisfy the preset EMI radiation condition, and confirm the updated current position as the optimized position of the decoupling capacitor.

[0103] For the specific definition of the chip decoupling capacitor position determination device, please refer to the definition of the brightness adjustment method above, which will not be repeated here. The various modules in the above-mentioned chip decoupling capacitor position determination device can be implemented in whole or in part by software, hardware and their combination. The above-mentioned modules can be embedded in or independent of the processor in the chip decoupling capacitor position determination system in hardware form, or can be stored in the memory of the chip decoupling capacitor position determination system in software form, so that the processor can call and execute the operations corresponding to the above modules.

[0104] In one embodiment, a chip decoupling capacitor location determination system is provided. The chip decoupling capacitor location determination system can be, but is not limited to, various personal computers, laptops, tablet computers, and desktop computers. The internal structure diagram of the chip decoupling capacitor location determination system can be as follows: Figure 12As shown. The chip decoupling capacitor position determination system includes a processor, a memory and a display screen connected via a system bus; the chip decoupling capacitor position determination system may also include a network interface and an input device. Among them, the processor of the chip decoupling capacitor position determination system is used to provide computing and control capabilities. The memory of the chip decoupling capacitor position determination system includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the chip decoupling capacitor position determination system is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a chip decoupling capacitor position determination method is implemented. The display screen of the chip decoupling capacitor position determination system may be a liquid crystal display screen, and the input device of the chip decoupling capacitor position determination method may be a touch layer covering the display screen, or a key, trackball or touchpad provided on the housing of the chip decoupling capacitor position determination method, or an external keyboard, touchpad or mouse, etc.

[0105] Those skilled in the art will understand that Figure 12 The structure shown in the figure is only a block diagram of a part of the structure related to the scheme of the present application, and does not constitute a limitation on the display device to which the scheme of the present application is applied. The specific display device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0106] In one embodiment, a chip decoupling capacitor position determination system is provided. The chip decoupling capacitor position determination system includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of any of the above-mentioned chip decoupling capacitor position determination methods are implemented.

[0107] In one example, when the processor executes the computer program, the processor further implements the following steps:

[0108] A first PCB three-dimensional model is established based on the chip to be tested and the PCB trace; the PCB trace is a trace connecting the power supply pin of the chip to be tested; a second PCB three-dimensional model is established based on the first PCB three-dimensional model and the decoupling capacitor set on the PCB trace, and the position where the decoupling capacitor is set is confirmed as the current position; second S parameters corresponding to the second PCB three-dimensional model are obtained according to a preset current absorption frequency; a preset EMI radiation excitation signal is input to the second PCB three-dimensional model, and a second EMI radiation intensity corresponding to the second PCB three-dimensional model is output; if the second S parameter and the second EMI radiation intensity do not meet the preset EMI radiation condition, the decoupling capacitor is set between the power supply pin of the PCB trace of the first PCB three-dimensional model and the current position, and the current position is updated to the position where the decoupling capacitor is set, until the second S parameter and the second EMI radiation intensity meet the preset EMI radiation condition, and the updated current position is confirmed as the optimized position of the decoupling capacitor.

[0109] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented:

[0110] A first PCB three-dimensional model is established based on the chip to be tested and the PCB trace; the PCB trace is a trace connecting the power supply pin of the chip to be tested; a second PCB three-dimensional model is established based on the first PCB three-dimensional model and the decoupling capacitor set on the PCB trace, and the position where the decoupling capacitor is set is confirmed as the current position; second S parameters corresponding to the second PCB three-dimensional model are obtained according to a preset current absorption frequency; a preset EMI radiation excitation signal is input to the second PCB three-dimensional model, and a second EMI radiation intensity corresponding to the second PCB three-dimensional model is output; if the second S parameter and the second EMI radiation intensity do not meet the preset EMI radiation condition, the decoupling capacitor is set between the power supply pin of the PCB trace of the first PCB three-dimensional model and the current position, and the current position is updated to the position where the decoupling capacitor is set, until the second S parameter and the second EMI radiation intensity meet the preset EMI radiation condition, and the updated current position is confirmed as the optimized position of the decoupling capacitor.

[0111] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0112] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0113] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for determining the position of a chip decoupling capacitor, characterized in that: include: Establish a first PCB three-dimensional model based on the chip to be tested and PCB traces; The PCB trace is a trace connected to the power supply pin of the chip to be tested; Establishing a second PCB three-dimensional model based on the first PCB three-dimensional model and a decoupling capacitor disposed on the PCB trace, and confirming the location where the decoupling capacitor is disposed as the current location; wherein, if it is determined that the PCB trace where the decoupling capacitor is disposed is a trace connected to a ground plane, replacing the PCB trace, selecting an arbitrary location on the replaced PCB trace, disposing the decoupling capacitor on the replaced PCB trace, and confirming the location where the decoupling capacitor is disposed as the current location; Obtaining a second S parameter corresponding to the second PCB three-dimensional model according to a preset absorption current frequency; inputting a preset EMI radiation excitation signal to the second PCB three-dimensional model, and outputting a second EMI radiation intensity corresponding to the second PCB three-dimensional model; If the second S parameter and the second EMI radiation intensity do not meet the preset EMI radiation condition, the decoupling capacitor is set between the power supply pin of the PCB trace of the first PCB three-dimensional model and the current position, and the current position is updated to the position where the decoupling capacitor is set until the second S parameter and the second EMI radiation intensity meet the preset EMI radiation condition, and the updated current position is confirmed as the optimized position of the decoupling capacitor.

2. The method for determining the position of a chip decoupling capacitor according to claim 1, wherein: After the step of establishing a first PCB three-dimensional model based on the chip to be tested and the PCB traces connected to the power supply pins of the chip to be tested, the method includes: According to the preset absorption current frequency, a first S parameter corresponding to the first PCB three-dimensional model is obtained; a preset EMI radiation excitation signal is input to the first PCB three-dimensional model, and a first EMI radiation intensity corresponding to the first PCB three-dimensional model is output.

3. The method for determining the position of a chip decoupling capacitor according to claim 2, wherein: Before the step of setting the decoupling capacitor between the power supply pin of the PCB trace of the first PCB three-dimensional model and the current position if the second S parameter and the second EMI radiation intensity do not meet the preset EMI radiation condition, the method includes: Comparing the first S parameter and the second S parameter to obtain an attenuation ratio of a first frequency band; Comparing the first EMI radiation intensity with the second EMI radiation intensity to obtain a first radiation intensity difference; When the attenuation ratio of the first frequency band falls within a preset attenuation threshold range and the first radiation intensity difference falls within a preset radiation intensity threshold range, a preset EMI radiation condition judgment is performed on the second S parameter and the second EMI radiation intensity.

4. The method for determining the position of a chip decoupling capacitor according to claim 3, wherein: After the step of comparing the first EMI radiation intensity with the second EMI radiation intensity to obtain a first radiation intensity difference, the method further includes: When the attenuation ratio of the first frequency band does not fall within the preset attenuation threshold range and the first radiation intensity difference does not fall within the preset radiation intensity threshold range, the PCB trace connected to the power supply pin of the chip to be tested is replaced, and the decoupling capacitor is set on the replaced PCB trace, and the position where the decoupling capacitor is set is confirmed as the current position.

5. The method for determining the position of a chip decoupling capacitor according to claim 1, wherein: The step of inputting a preset EMI radiation excitation signal to the second PCB three-dimensional model and outputting a second EMI radiation intensity corresponding to the second PCB three-dimensional model includes: A preset EMI radiation excitation signal is input to the second PCB three-dimensional model, and a second EMI radiation intensity at a preset distance is output.

6. The method for determining the position of a chip decoupling capacitor according to claim 5, wherein: The preset distance is 3 meters.

7. The method for determining the position of a chip decoupling capacitor according to claim 1, wherein: The optimized position includes first distance information between the decoupling capacitor and the power supply pin and second distance information between the decoupling capacitor and a ground plane.

8. The method for determining the position of a chip decoupling capacitor according to claim 7, wherein: The range of the first distance information is 0 to 2 mm; the range of the second distance information is 0 to 2 mm.

9. A device for determining the position of a chip decoupling capacitor, characterized in that: include: A first PCB three-dimensional model building unit is used to build a first PCB three-dimensional model according to the chip to be tested and the PCB traces; The PCB trace is a trace connected to the power supply pin of the chip to be tested; a second PCB three-dimensional model establishing unit, configured to establish a second PCB three-dimensional model based on the first PCB three-dimensional model and a decoupling capacitor provided on the PCB trace, and to determine a location where the decoupling capacitor is provided as a current location; wherein, if it is determined that the PCB trace where the decoupling capacitor is provided is a trace connected to a ground plane, the PCB trace is replaced, and a decoupling capacitor is selected at any location on the replaced PCB trace, and the location where the decoupling capacitor is provided is determined as the current location; a model processing unit, configured to obtain a second S parameter corresponding to the second PCB three-dimensional model according to a preset absorption current frequency; input a preset EMI radiation excitation signal to the second PCB three-dimensional model, and output a second EMI radiation intensity corresponding to the second PCB three-dimensional model; a position determining unit, configured to, if the second S parameter and the second EMI radiation intensity do not satisfy a preset EMI radiation condition, set the decoupling capacitor between the power supply pin of the PCB trace of the first PCB three-dimensional model and the current position, and update the current position to a position where the decoupling capacitor is set, until the second S parameter and the second EMI radiation intensity satisfy the preset EMI radiation condition, and confirm the updated current position as an optimized position of the decoupling capacitor.

10. A chip decoupling capacitor position determination system, characterized in that: The chip decoupling capacitor position determination system includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the chip decoupling capacitor position determination method according to any one of claims 1 to 8 are implemented.

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