A method for analyzing the manufacturability of an integrated circuit layout

Abstract

The application discloses a method for analyzing the manufacturability of an integrated circuit layout, which comprises the following steps: providing an initial layout with design patterns; performing layout grid processing on a specified layer of the design patterns; calculating the layout pattern density of each grid after the layout grid processing; calculating the gradient of the layout pattern density of each grid after the layout grid processing; and judging whether the layout pattern density and the gradient of the layout pattern density meet the manufacturing specifications. The method for analyzing the manufacturability of the integrated circuit layout can calculate the gradient of the layout pattern density of each grid while judging the layout pattern density of each grid of the integrated circuit layout, thereby effectively ensuring that the layout pattern density meets the manufacturing specification requirements, and greatly improving the uniformity of the layout density to more than 90%.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for analyzing the manufacturability of integrated circuit layouts. Background Technology

[0002] As integrated circuit manufacturing process nodes continue to advance, manufacturability and reliability checks on integrated circuit designs become increasingly important. The shrinking process node size and the ever-increasing complexity of design patterns force manufacturers to invest significant human and financial resources in evaluating the manufacturability of design layouts. Once the designer's layout data is generated, it undergoes checks based on pattern density-related design rules, indicating that the design data fully meets manufacturing specifications.

[0003] In traditional graphic density checking, the layout is first divided into grid points with a step size of W along the X and Y directions, resulting in D. 00 ~D nn The grid is divided into small points. Then, the density of each grid point is calculated. Finally, it is determined whether the calculated graphic density values ​​of all grid points meet the design rules.

[0004] Clearly, as integrated circuit manufacturing processes have advanced to high-end nodes, the aforementioned pattern density inspection methods only consider the density of a single grid point, making it difficult to obtain a highly uniform pattern density. This inevitably affects the stability of the device and increases manufacturing costs.

[0005] The search for an analytical method that is simple to produce, highly compatible with various processes, and can achieve high uniformity in the density of graphic patterns has become one of the technical problems that urgently need to be solved by those skilled in the art.

[0006] Therefore, in response to the problems existing in the prior art, the designer of this invention, based on years of experience in this industry, actively researched and improved the technology, resulting in the present invention, a method for analyzing the manufacturability of integrated circuit layout. Summary of the Invention

[0007] This invention addresses the shortcomings of existing technologies, where traditional pattern density inspection methods, after the integrated circuit manufacturing process enters high-end nodes, only consider the density of a single grid point, making it difficult to obtain a highly uniform pattern density, which inevitably affects the stability of the device and increases the production and manufacturing costs. This invention provides a method for analyzing the manufacturability of integrated circuit layouts.

[0008] To achieve the objective of this invention, this invention provides a method for analyzing the manufacturability of integrated circuit layouts, the method comprising:

[0009] Execution step S11: Provide an initial layout with design graphics;

[0010] Step S12: Perform layout gridding processing on the specified layers of the design graphic;

[0011] Execute step S13: Calculate the layout graphic density of each grid point after the layout is gridded;

[0012] Step S14: Calculate the gradient of the layout graphic density of each grid point after the layout is gridded; Step S15: Determine whether the layout graphic density and the gradient of the layout graphic density meet the manufacturing specifications.

[0013] Optionally, the method for calculating the graphic density of the layout further includes:

[0014] Execution step S21: Calculate the area of ​​the layout graphic at the specified grid points;

[0015] Execute step S22: Calculate the area of ​​the grid points at the specified level;

[0016] Step S23: The ratio of the area of ​​the grid point to the area of ​​the grid point is the grid point's layout graphic density.

[0017] Optionally, the method for calculating the gradient of the graphic density of the layout further includes:

[0018] Execution step S31: Obtain the layout graphic density D of the specified grid point ii. ii ;

[0019] Execution step S32: Obtain the weight values ​​of grid points jk that are j in the X direction and k in the Y direction from the specified grid point ii. The weight values ​​are normalized to |W(j,k)|=|W(k,j)|. The average value of the graphic density of the layout at a distance j in the X direction and a distance k in the Y direction from the specified grid point ii is A(j,k). Then, the gradient density A of grid point ii is... ii =A(1,0)×|W(1,0)|+A(1,1)×|W(1,1)|+···+A(j,k)×|W(j,k)|;

[0020] Execution step S33: Calculate the gradient X of the layout graphic density of grid point ii. ii =D ii -A ii , where j∈[1,+∞) is any integer value, and k∈[1,+∞) is any integer value;

[0021] Execute step S34: Determine X ii Does it conform to manufacturing specifications?

[0022] Optionally, the method for calculating the gradient of the graphic density of the layout further includes:

[0023] Execute step S41: Obtain the layout graphic density D of the specified grid point ii. ii ;

[0024] Execute step S42: Obtain the weight values ​​of the grid points surrounding the specified grid point ii, and calculate the gradient density X. ii ;

[0025] First, calculate the graphic density of the layout at grid points with a distance of 1 from the specified grid point ii, and then calculate D. i(i-1) D i(i+1) D (i-1)i D (i+1)i The average value is A(1,0), and the weights are set to W(1,0) = w or W(0,1) = w;

[0026] Secondly, the distance from the specified grid point ii is The grid-based graphic density of the map, calculating D. (i-1)(i-1) D (i-1)(i+1) D (i+1)(i-1) D (i+1)(i+1) The average value is A(1,1), and the weights are set to...

[0027] Next, the layout graphic density of grid points with a distance of 2 from the specified grid point ii is calculated as D. i(i-2) D (i-2)i D i(i+2) D (i+2)i The average value is A(2,0), and the weights are set to W(2,0) = w / 2 or W(0,2) = w / 2;

[0028] Similarly, the weight values ​​when the distance from a specified grid point ii in the X direction is j and the distance from ii in the Y direction is k are then calculated as follows: Let A(j,k) be the average density of the layout at grid point ii, where the X-direction distance is j and the Y-direction distance is k. Given W(0,1) + W(1,1) + W(0,2) + ... + W(j,k) = 1, then the gradient density A at grid point ii is... ii =A(1,0)×W(1,0)+A(1,1)×W(1,1)+···+A(j,k)×W(j,k);

[0029] Execute step S43: Calculate the gradient X of the layout graphic density at the specified grid point jj. ii =D ii -A ii; where j∈[1,+∞), and k∈[1,+∞).

[0030] Execution step S44: Determine X ii Does it conform to manufacturing specifications?

[0031] Optionally, the manufacturing specification of the graphic density gradient can take any value within the range of (0,1).

[0032] Optionally, the manufacturing specification of the pattern density gradient is less than 20%.

[0033] Optionally, the feature is that, when calculating the gradient of the graphic density of each grid point, any integer value of j∈[1,+∞) and any integer value of k∈[1,+∞) are used, and the values ​​are set according to specific technical nodes.

[0034] Optionally, when calculating the gradient of the graphic density of each grid point, any integer value of j ∈ [1, +∞) and any integer value of k ∈ [1, +∞) are used, and the values ​​are set according to the specific technical node, and j and k are the maximum values ​​of the X and Y directions of the gridded layout.

[0035] Optionally, the weight value W(0,1)+W(1,1)+W(0,2)+···+W(j,k)=1.

[0036] In summary, the integrated circuit layout manufacturability analysis method of the present invention, while judging the layout pattern density of the grid points of the integrated circuit layout, calculates the gradient of the layout pattern density of each grid point. This not only effectively ensures that the layout pattern density meets the manufacturing specifications, but also significantly improves the density uniformity of the layout, reaching over 90%. Attached Figure Description

[0037] Figure 1 The diagram shown is a flowchart of the integrated circuit layout manufacturability analysis method of the present invention;

[0038] Figure 2 The diagram shown is a schematic representation of the layout gridding process performed in the integrated circuit layout manufacturability analysis method of the present invention.

[0039] Figure 3 The diagram shown illustrates the calculation of layout gradient density in the integrated circuit layout manufacturability analysis method of the present invention.

[0040] Figure 4 The diagram shown is a schematic representation of a specific embodiment of the integrated circuit layout manufacturability analysis method of the present invention;

[0041] Figure 5The gradient of layout pattern density obtained by the integrated circuit layout manufacturability analysis method of the present invention is shown. Detailed Implementation

[0042] To explain in detail the technical content, structural features, objectives, and effects of this invention, the following will provide a detailed description in conjunction with embodiments and accompanying drawings.

[0043] Please see Figure 1 , Figure 1 The diagram shows a flowchart of the integrated circuit layout manufacturability analysis method of the present invention. The integrated circuit layout manufacturability analysis method includes:

[0044] Execution step S11: Provide an initial layout with design graphics;

[0045] Step S12: Perform layout gridding processing on the specified layers of the design graphic;

[0046] Execute step S13: Calculate the layout graphic density of each grid point after the layout is gridded;

[0047] Execute step S14: Calculate the gradient of the layout graphic density at each grid point after the layout is gridded;

[0048] Step S15: Determine whether the layout graphic density and the gradient of the layout graphic density meet the manufacturing specifications.

[0049] In this invention, the design pattern is an integrated circuit layout. The method for calculating the layout pattern density further includes:

[0050] Execution step S21: Calculate the area of ​​the layout graphic at the specified grid points;

[0051] Execute step S22: Calculate the area of ​​the grid points at the specified level;

[0052] Step S23: The ratio of the area of ​​the grid point to the area of ​​the grid point is the grid point's layout graphic density.

[0053] The method for calculating the gradient of the graphic density of the layout further includes:

[0054] Execution step S31: Obtain the layout graphic density D of the specified grid point ii. ii ;

[0055] Execution step S32: Obtain the weight values ​​of grid points jk that are j in the X direction and k in the Y direction from the specified grid point ii. The weight values ​​are normalized to |W(j,k)|=|W(k,j)|. The average value of the graphic density of the layout at a distance j in the X direction and a distance k in the Y direction from the specified grid point ii is A(j,k). Then, the gradient density A of grid point ii is... ii =A(1,0)×|W(1,0)|+A(1,1)×|W(1,1)|+···+A(j,k)×|W(j,k)|;

[0056] Execution step S33: Calculate the gradient X of the layout graphic density of grid point ii. ii =D ii -A ii ; where j∈[1,+∞) is any integer value, and k∈[1,+∞) is any integer value.

[0057] Execute step S34: Determine X ii Does it conform to manufacturing specifications?

[0058] To more intuitively reveal the technical solution of the present invention and highlight its beneficial effects, the specific steps and working principle of the integrated circuit layout manufacturability analysis method are now described in conjunction with specific embodiments. In the specific embodiments, the specific values ​​of the grid number, spacing, layout pattern density, and gradient of layout pattern density are merely examples and should not be regarded as limitations on the technical solution of the present invention.

[0059] Please see Figure 2 , Figure 2 The diagram shows a schematic representation of the layout gridding process performed in the integrated circuit layout manufacturability analysis method of the present invention. In a specific embodiment, the layout is first divided into grids with a step size of W along the X and Y directions to obtain D. 00 ~D nn The grid points are then used. Density calculations are performed on each grid point. Finally, it is determined whether the calculated density values ​​of all grid points conform to the design rules. (A non-restrictive example: for grid point 201, D is defined...) n3 Contains figures A1 to A n The corresponding area of ​​the figure is S1 to S2. n Then D n3 The graphic density of the map is (S1+S2+...+S...) n ) / W 2 .

[0060] Please see Figure 3 and in conjunction with reference Figure 2 , Figure 3 The diagram illustrates the calculation of layout pattern gradient density in the integrated circuit layout manufacturability analysis method of the present invention. The method for calculating the gradient of layout pattern density further includes:

[0061] Execution step S41: Obtain the layout graphic density D of the specified grid point ii. ii ;

[0062] Execute step S42: Obtain the weight values ​​of the grid points surrounding the specified grid point ii, and calculate the gradient density X. ii ;

[0063] For example, the layout graphic density of grid points with a distance of 1 from the specified grid point ii is calculated as D. i(i-1) D i(i+1) D (i-1)i D (i+1)i The average value is A(1,0), and the weights are set to W(1,0) = w or W(0,1) = w;

[0064] The distance from the specified grid point ii is The grid-based graphic density of the map, calculating D. (i-1)(i-1) D (i-1)(i+1) D (i+1)(i-1) D (i+1)(i+1) The average value is A(1,1), and the weights are set to...

[0065] The layout graphic density of grid points with a spacing of 2 from the specified grid point ii is calculated as D. i(i-2) D (i-2)i D i(i+2) D (i+2)i The average value is A(2,0), and the weights are set to W(2,0) = w / 2 or W(0,2) = w / 2;

[0066] It is readily apparent that the weight value when the distance in the X direction from the specified grid point ii is j and the distance in the Y direction from the specified grid point ii is k is then calculated as follows: The average value of the graphic density of the layout at a distance j in the X direction and a distance k in the Y direction from the specified grid point ii is A(j,k). This weight value is normalized to |W(j,k)|=|W(k,j)|, meaning that when W(0,1)+W(1,1)+W(0,2)+···+W(j,k)=1, the gradient density A at the specified grid point ii is... ii =A(1,0)×|W(1,0)|+A(1,1)×|W(1,1)|+···+A(j,k)×|W(j,k)|;

[0067] Execute step S43: Calculate the gradient X of the layout graphic density at the specified grid point jj. ii =D ii -A ii; where j∈[1,+∞), and k∈[1,+∞).

[0068] Execution step S44: Determine X ii Does it conform to manufacturing specifications?

[0069] Please see Figure 4 , Figure 4 The diagram shown is a schematic representation of a specific embodiment of the integrated circuit layout manufacturability analysis method of the present invention. Figure 4 The figures show the numerical values ​​of the pattern density at each grid point, all calculated according to the method described in this invention. For example, the layout may be gridded into 64 grid points: X0–X7 and Y0–Y7. If the manufacturing specification for the pattern density is [20%, 65%], then the grid points listed in this invention all conform to the manufacturing specification. However, considering only the density of a single grid point makes it difficult to obtain a highly uniform pattern density, which inevitably affects the stability of the device and increases manufacturing costs. Therefore, this invention further includes analyzing the gradient of the pattern density at each grid point.

[0070] In a specific implementation, for example, the values ​​j=1 and k=1 are taken. Then, the weight value w is obtained according to the method for calculating the gradient of the graphic density of the layout described in this invention, specifically as follows:

[0071] When j=1 and k=1, the weight values ​​W(0,1), W(1,0) and W(1,1) need to be calculated.

[0072] Let W(0,1) = W(1,0) = w;

[0073] but,

[0074] Where W(0,1)+W(1,1)=1;

[0075] Calculations show that W(0,1) = W(1,0) = 0.5858 and W(1,1) = 0.4142.

[0076] After obtaining the weight values, the gradient of the layout density of the grid points can be further calculated. Similarly, taking grid point X1Y1 as an example, the method for calculating the gradient of its layout density is as follows:

[0077] First, obtain the grid points that are 1 distance from grid point X1Y1, namely X1Y0, X0Y1, X1Y2, and X2Y1; then... Figure 2Given that D(X1Y0) = 50%, D(X1Y2) = 20%, D(X0Y1) = 50%, and D(X2Y1) = 20%, the average graphic density of the layout at a distance of 1 from grid point X1Y1 is [D(X1Y0) + D(X1Y2) + D(X0Y1) + D(X2Y1)] / 4 = 35%.

[0078] Furthermore, the gradient density of the graph at a distance of 1 from grid point X1Y1 is 35% × 0.5858 = 20.5%.

[0079] Then the distance from grid point X1Y1 is obtained as follows: The lattice points are X0Y0, X0Y2, X2Y0, and X2Y2; by Figure 2 Given that D(X0Y0) = 50%, D(X0Y2) = 50%, D(X2Y0) = 60%, and D(X2Y2) = 20%, the distance from grid point X1Y1 is... The average density of the pattern is [D(X0Y0)+D(X0Y2)+D(X2Y0)+D(X2Y2)] / 4=45%;

[0080] Furthermore, the distance from grid point X1Y1 is The gradient density of the graph is 45% × 0.4142 = 18.6%.

[0081] According to the integrated circuit layout manufacturability analysis method described in this invention, it is readily known that the gradient of the layout pattern density with grid point X1Y1 spacing is 20.5% + 18.6% - 25% = 14%.

[0082] Please see Figure 5 , Figure 5 The diagram shows the gradient of layout pattern density obtained by the integrated circuit layout manufacturability analysis method of the present invention. According to the calculation method of layout pattern density gradient described in the present invention, the density gradients of each of the 64 grid points X0 to X7 and Y0 to Y7 can be obtained sequentially.

[0083] If the manufacturing specification stipulates that the density gradient of the pattern must not exceed 20%, then the density gradient of X2Y1 is 24%, which does not meet the manufacturing requirements. Clearly, the manufacturing specification for the pattern density gradient takes any value within the range of (0,1).

[0084] As will be readily apparent to those skilled in the art, when calculating the gradient of the pattern density of each grid point, any integer value of j ∈ [1, +∞) and any integer value of k ∈ [1, +∞) are set according to the specific technology node. The larger the values ​​of j and k in advanced technologies, the stronger the manufacturability and reliability of the device. Therefore, j and k are the maximum values ​​in the X and Y directions of the gridded layout.

[0085] In summary, the integrated circuit layout manufacturability analysis method of the present invention, while judging the layout pattern density of the grid points of the integrated circuit layout, calculates the gradient of the layout pattern density of each grid point. This not only effectively ensures that the layout pattern density meets the manufacturing specifications, but also significantly improves the density uniformity of the layout, reaching over 90%.

[0086] Those skilled in the art will understand that various modifications and variations can be made to this invention without departing from its spirit or scope. Therefore, if any modification or variation falls within the scope of the appended claims and their equivalents, the invention is considered to cover such modifications and variations.

Claims

1. A method of integrated circuit layout manufacturability analysis, characterized by, The integrated circuit layout manufacturability analysis method comprises: Step S11: providing an initial layout with design patterns; Step S12: performing layout griding on the design patterns of a specified layer; Step S13: calculating the layout pattern density of each grid after layout griding; Step S14: calculating the gradient of the layout pattern density of each grid after layout griding; Step S15: determining whether the layout pattern density and the gradient of the layout pattern density meet the manufacturing specifications; The calculation method of the gradient of the layout pattern density further comprises: Performing step S31: Obtain the layout pattern density D of the specified grid point ii ii ; Step S32 is performed to obtain the weight value of the grid point jk at the X-direction distance j and the Y-direction distance k from the distance specifying grid point ii and the weight value is normalized as |W(j,k)| = |W(k,j)|, the average value of the layout pattern density of the X-direction distance j from the distance specifying grid point ii and the Y-direction distance k from the distance specifying grid point ii is A(j,k), and the gradient density A of the grid point ii is ii A(1,0) x |W(1,0)| + A(1,1) x |W(1,1)| + ··· + A(j,k) x |W(j,k)|. Performing step S33: calculating the gradient X of the layout pattern density of the grid point ii ii = D ii -A ii wherein j is any integer value in [1, +∞), and k is any integer value in [1, +∞). Perform step S34: judge X ii whether it meets the manufacturing specifications.

2. The method of claim 1, wherein the integrated circuit layout is a layout of a semiconductor integrated circuit. The calculation method of the layout pattern density further comprises: Step S21: calculating the layout pattern area of a grid of a specified layer; Step S22: calculating the area of the grid of the specified layer; Step S23: obtaining the ratio of the layout pattern area of the grid to the area of the grid as the layout pattern density of the grid.

3. The method of claim 1, wherein the integrated circuit layout manufacturability analysis is performed by a computer system. The calculation method of the gradient of the layout pattern density further comprises: Performing step S41: Obtain the layout pattern density D of the specified grid point ii ii ; Performing step S42: Obtain the weight value of the grid points around the specified grid point ii, and calculate the gradient density X ii ; First, the density of the layout pattern of the lattice points having a distance of 1 from the specified lattice point ii is calculated as D i(i-1) , D i(i+1) , D (i-1)i , D (i+1)i The average value of D i(i-1) , D i(i+1) , D (i-1)i , D (i+1)i is A(l,0), and the weight is set as W(l,0)=w or W(0,l)=w. Second, the distance between the specified grid point ii is the grid pattern density of the grid point, calculate D (i-1)(i-1) , D (i-1)(i+1) , D (i+1)(i-1) , D (i+1)(i+1) The average value of A (1, 1) is set as the weight Again, the average of the pattern density of the layout pattern of the grid point ii spaced apart from the specified grid point by a distance of 2 is calculated as D i(i-2) , D (i-2)i , D i(i+2) , D (i+2)i A(2,0), and the weight is set as W(2,0)=w / 2 or W(0,2)=w / 2. By analogy, the weight value when the distance from the specified grid point ii in the X direction is j and the distance from the specified grid point ii in the Y direction is k is The average value of the layout pattern density when the distance from the specified grid point ii in the X direction is j and the distance from the specified grid point ii in the Y direction is k is A(j, k), and in the case of W(0, 1) + W(1, 1) + W(0, 2) + ··· + W(j, k) = 1, the gradient density A of the specified grid point ii is ii = A(1, 0) x W(1, 0) + A(1, 1) x W(1, 1) + ··· + A(j, k) x W(j, k); Performing step S43: calculating the gradient X of the layout pattern density at the specified grid point ii ii = D ii -A ii ; wherein j is any integer value in the range [1, +∞), and k is any integer value in the range [1, +∞). Perform step S44: judge X ii whether it meets the manufacturing specifications.

4. The method of claim 1, wherein the integrated circuit layout is a layout of a semiconductor integrated circuit. 5 The manufacturing specification value range of the gradient of the layout pattern density is any value in the range of (0, 1).

5. The method of claim 1, wherein the integrated circuit layout manufacturability analysis is performed by a computer system. The manufacturing specification value of the gradient of the layout pattern density is less than 20%.

6. The method of claim 1, wherein the integrated circuit layout is a layout of a semiconductor integrated circuit. 5 In the calculation of the gradient of the layout pattern density of each grid, j is any integer value in the range of [1, +∞), and k is any integer value in the range of [1, +∞), and the values are set according to the specific technology node.

7. The method for analyzing the manufacturability of integrated circuit layout as described in claim 1, characterized in that, In the calculation of the gradient of the layout pattern density of each grid, j is any integer value in the range of [1, +∞), and k is any integer value in the range of [1, +∞), and the values are set according to the specific technology node, and j and k are the maximum values of the X direction and the Y direction of the layout griding.

8. The method for analyzing the manufacturability of integrated circuit layout as described in claim 1, characterized in that, The weight value W(0, 1) + W(1, 1) + W(0, 2) + … + W(j, k) = 1.

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