Method for copying data into a storage device, and storage and electronic devices

Abstract

This document describes a storage device, including a command decoder configured to receive a copy command to directly copy data stored in a first storage location to a second storage location without transferring the data to an external controller; a memory array electrically connected to the command decoder and including a plurality of storage locations, the plurality of storage locations including the first storage location and the second storage location; a data line electrically connected to the memory array and configured to receive data to be transferred to the second storage location from the first storage location through the same data line; and an output buffer configured to store the data received from the first storage location through the data line to directly write the data into the second storage location without transferring the data to an external controller. Embodiments of the present invention also relate to a method and an electronic device for copying data in a storage device.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method, a storage device, and an electronic device for copying data in a storage device. Background Art

[0002] Generally, for volatile storage devices that temporarily store binary data, such as dynamic random access memory (DRAM), static random access memory (SRAM), and resistive random access memory (RRAM), etc., it will consume a large amount of time and energy to complete the copying of a data block from a first location in the storage device to a second location in the storage device. Usually, a copy operation of copying a data block from one part of the storage device to another part of the storage device or a move operation of moving a data block from one part of the storage device to another part of the storage device will involve performing a read operation at the first location in the storage device to obtain the data stored at the first location, transmitting the data output from the storage device to a central processing unit (CPU) or a memory controller, and then transmitting the data back from the CPU to the storage device to write the data into the second memory. Due to the possible execution of multiple iterations of read operations and write operations, such operations will consume a large amount of time, and since the data block may be moved out of the storage device and received back into the storage device, such operations will consume a large amount of energy.

[0003] To perform a move operation or a copy operation without transmitting the data to a memory controller or a CPU, multiple methods can be adopted. One method is to first copy the data from the first storage location to a sense amplifier typically connected to multiple cells, and then copy the data from the sense amplifier to the second storage location. Although this technique does not require additional hardware, such a method is limited to copying data within the same bank, but cannot copy data outside the same bank. Another method is to add additional hardware, such as a temporary memory storage location, commonly referred to as the "pseudo row" technique, which may involve copying the data from the first storage location to the temporary memory storage device, and then copying the data from the temporary memory storage device to the second storage location. However, such a technique will involve additional hardware. Other currently known techniques involve modifying the internal circuit of the storage device to create the required data path and generate the required signals. These techniques may involve significantly increasing the hardware for the internal circuit and also require additional energy corresponding to the additional signals.

[0004] Since minimizing the use of additional hardware and energy consumption has already been a trend in the design of storage devices, the future design of storage devices that do not require transmitting data outside the storage device and do not require a large amount of additional hardware corresponding to performing a copy operation or a move operation may help enhance the efficiency of the storage device and the overall performance of the electronic device using the storage device. Summary of the Invention

[0005] According to one aspect of an embodiment of the present invention, there is provided a storage device, including: a command decoder configured to receive a copy command to directly copy data stored in a first storage location to a second storage location; a memory array electrically connected to the command decoder and including a plurality of storage locations, the plurality of storage locations including the first storage location and the second storage location; a data line electrically connected to the memory array and configured to receive data to be transmitted to the second storage location through the same data line from the first storage location; and an output buffer configured to store the data received from the first storage location through the data line to directly write the data into the second storage location.

[0006] According to another aspect of an embodiment of the present invention, there is provided a method for copying data into a storage device, the method including: receiving a copy command, a source address, and a destination address from a memory controller, wherein the source address and the destination address correspond to locations in the storage device; performing a read operation at the source address in response to receiving the copy command to obtain data; after performing the read operation, transmitting the data through the data line to the output buffer; storing the data in the output buffer in response to the output buffer receiving the data; transmitting the data stored in the output buffer through the data line to the destination address; and writing the data at the destination address in response to transmitting the data stored in the output buffer.

[0007] According to still another aspect of an embodiment of the present invention, there is provided an electronic device, including: a controller; and a storage device electrically connected to the memory controller, the storage device including: a command decoder configured to receive a copy command to copy data stored in a first storage location to a second storage location; a memory array electrically connected to the command decoder and including a plurality of storage locations, the plurality of storage locations including the first storage location and the second storage location; a data line electrically connected to the memory array and configured to receive data to be transmitted to the second storage location through the same data line from the first storage location; and an output buffer configured to store the data received from the first storage location through the data line to directly write the data into the second storage location. Description of the Drawings

[0008] The accompanying drawings provided by the present invention provide further understanding and are incorporated into the present specification to form a part thereof. The drawings illustrate embodiments of the present invention and, together with the detailed description, explain the principles of the present invention.

[0009] Figure 1 is a conceptual block diagram of an electronic device having a storage device according to an exemplary embodiment of the present invention.

[0010] Figure 2A is a conceptual block diagram of a storage device according to an exemplary embodiment of the present invention.

[0011] Figure 2B is a conceptual block diagram of a storage device according to another exemplary embodiment of the present invention.

[0012] Figure 3A is a conceptual block diagram of a command decoder of a storage device according to an exemplary embodiment of the present invention.

[0013] Figure 3B is an alternative embodiment of a special move command according to an exemplary embodiment of the present invention Figure 3A of.

[0014] Figure 4A is a table showing the correspondence between input signals and commands according to an exemplary embodiment of the present invention.

[0015] Figure 4B is a truth table of a special move command according to an exemplary embodiment of the present invention.

[0016] Figure 5 is a flowchart showing the implementation concept of a copy operation according to an exemplary embodiment of the present invention.

[0017] Figure 6 is a flowchart showing the steps of a method for performing a copy operation in a storage device according to an exemplary embodiment of the present invention.

[0018] Figure 7 shows a hardware block diagram of a storage device according to an exemplary embodiment of the present invention.

[0019] Figure 8 shows a hardware block diagram of a storage device for performing a copy operation according to an exemplary embodiment of the present invention.

[0020] Figure 9A shows performing a copy operation according to a first exemplary embodiment of the present invention.

[0021] Figure 9B shows a finite state machine related to a copy operation according to a first exemplary embodiment of the present invention.

[0022] Figure 10 shows performing a copy operation related to a copy operation according to a second exemplary embodiment of the present invention.

[0023] Figure 11 shows a finite state machine related to according to a second exemplary embodiment of the present invention.

[0024] Figure 12 shows a finite state machine related to according to a third exemplary embodiment of the present invention.

[0025] Figure 13 Shows a finite state machine related to a fourth exemplary embodiment of the present invention. Detailed implementation

[0026] The following disclosure provides many different embodiments or examples for implementing different components of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a second component above or on a first component may include embodiments where the second component and the first component are in direct contact, and may also include embodiments where additional components may be formed between the second component and the first component, such that the second component and the first component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate a relationship between the various embodiments and / or structures discussed.

[0027] Moreover, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "on", "covering", "over", "upper", etc. may be used herein to describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatially related descriptors used therein may be interpreted accordingly.

[0028] Reference will now be made in detail to the exemplary embodiments of the present invention, which are illustrated in the accompanying drawings. As much as possible, the same reference numerals will be used throughout the drawings and the description to refer to the same or similar parts.

[0029] The present invention provides a method for moving or copying operations of a storage device as moving or copying a data block from a first storage location to a second storage location in the storage device without transferring data to an external controller. The storage device implementing the copying or moving operation does not require significant modification of the hardware structure of an existing storage device to generate the required signals and data paths for implementing the moving or copying operation. The first storage location can be any storage location of the storage device, and the second storage location can be from a different memory array or a different bank or from the same memory array or the same bank. The above-mentioned another storage location can also be another row, another section, or another page in the same bank. The external controller can be, for example, a DRAM controller, a memory controller, a central processing unit (CPU), or another external processor or controller. Thus, the present invention provides a method for transferring a data block, such as graphic image data, from one location to another location in one or more DRAM chips.

[0030] To utilize the present invention, two new C library functions, memcpy and bcopy, are available to users. The function memcpy(void* str1, const void* str2, size_t n) copies n characters from the storage area pointed to by str2 to the storage area pointed to by str1. The function bcopy(const void* src, void* dest, size_t n) copies n bytes from the address pointed to by src to the destination pointed to by dest. At the chip level, a new command having, for example, the form move(A, B, N) can utilize the moving or copying command of the present invention, where in move(A, B, N), A is the source address, B is the destination address, and N is the number of data blocks, each block having the width of the READ FIFO storage buffer.

[0031] The moving or copying operation can be implemented by introducing a new command, which can be, for example, a copying command. The copying command will execute the aforementioned moving or copying operation by combining an existing read command and an existing write command. The present invention provides an input or a set of inputs, which will be decoded into a new command. The present invention also provides a modification of the function associated with the existing read command, such that when the copying command has been received, the existing read command does not output data to the output buffer to be read by the external controller. Similarly, in order to write the output data to the second storage location, the existing read command will be followed by a write command. The above concept of the copying command and its associated modification will be illustrated by the following figure and its corresponding description of the write.

[0032] Figure 1FIG. 0 shows a conceptual block diagram of an electronic device 100 having a storage device 104. The electronic device 100 includes a CPU, a memory controller 102, a DRAM controller 103, and a storage device 104. The storage device 104 will receive a set of signals to be decoded into a copy command that originates from the CPU 101 and is transmitted through the memory controller 102 and the DRAM controller 103. The copy command will copy a data block from a first storage location to a second storage location by performing a read operation from the first storage location followed by a write operation to the second storage location, and the data block is not read by the DRAM controller and not sent back to the CPU. The functions of the CPU 101, the memory controller 102, and the DRAM controller 103 conform to the currently known CPU 101, the memory controller 102, and the DRAM controller 103, and thus a description of their respective functions will not be necessary.

[0033] The present invention provides a storage device 104 that, for example, implements a copy operation. A conceptual block diagram of the storage device 104 is shown in Figure 2A FIG. 5. The storage device 104 will include a memory array 201, control logic 206 electrically coupled to at least one memory array 201, and the memory array 201 is electrically coupled to an output buffer 202 and an input buffer 203 through data lines 204. The control logic 206 will include a command decoder configured to receive a copy command to copy data stored in a first storage location 207 to a second storage location 208 without transmitting the data to an external controller (e.g., the CPU 101, the memory controller 102, and the DRAM controller 103). The memory array 201 will include one or more memory arrays electrically connected to the command decoder of the control logic 206 and include a plurality of storage locations, and the storage locations include a first storage location 207 and a second storage location 208. The first storage location 207 and the second storage location 208 may be located in the same or different memory arrays or banks. The first storage location 207 and the second storage location 208 may be in different rows, different columns, different pages, or different portions in the same bank. The memory array 201 will be electrically connected to the output buffer 202 through the data line 204, and the data line 204 is configured to receive data to be transmitted to the second storage location 208 from the first storage location 207 through the same data line and is also electrically connected to the output buffer 202, and the output buffer 202 is configured to store the data received from the first storage location 207 through the data line 204 for writing to the second storage location 208 without transmitting the data to an external controller.

[0034] Since the copy command is determined based on at least one first predetermined binary value (e.g., "1") received by the special read input and a second predetermined binary value (e.g., "1") received by the special write input, the command decoder of the control logic 206 may include a special read input 302 and a special write input 303. The first predetermined binary value may be the same as or different from the second predetermined binary value. The control logic 206 may be configured to initialize a regular read program in response to receiving an activation command when the special read input is not the first predetermined binary value (e.g., "0"). However, the control logic 206 may be configured to initialize a copy program corresponding to the copy command in response to receiving an activation command when the special read input is the first predetermined binary value (e.g., "1"). In other words, when the special read input is not the first predetermined binary value, the storage device 104 may execute a set of regular finite state machines (FSMs), but when the special read input is the first predetermined binary value, the storage device 104 may execute an alternative set of FSMs. The copy program corresponding to the copy command may include a regular read program and a regular write program. The regular read program may include reading from a first storage location 207, and the regular write program will include writing to a second storage location 208.

[0035] Since the data is received by the output buffer 202 in response to the special read input receiving the first predetermined binary value, the output buffer 202 may include a first input / output interface connected to the data line 204 and a second input / output interface connected to the read driver. For this exemplary embodiment, the control logic 206 will be configured to control the output buffer 202 to directly output the data back to the data line 204 to be written into the second storage location 208 instead of being received by the external controller in response to the special write input receiving the second predetermined binary value (e.g., "1"). Thus, a data block is moved from one location in one or more DRAM chips to another location.

[0036] Figure 2B is shown in connection with Figure 2ASimilar optional exemplary embodiments. For this exemplary embodiment, the input buffer 203 includes a first interface 203a connected to the global input / output data line 204, a second interface 203b connected to the write driver, and a third interface 203c connected to the data line 205. The output buffer 202 can transmit data to the input buffer 203 through the data line 205 to write the data stored in the first storage location 207 into the second storage location 208. In other words, the data stored in the first storage location 207 can be transmitted from the first storage location 207 via the output buffer 202 and then transmitted to the input buffer 203 via the third interface 203c. The data can be copied from the first storage location 207 and directly written into the second storage location 208 without being transmitted to an external controller.

[0037] Similarly, data can also be written into the write driver and transmitted to the second storage location 208 according to the received data in the input buffer 203. In some embodiments, according to the received data, the data stored in the first storage location 207 is transmitted from the first storage location 207 to the output buffer 202 and written into the write driver. The written data is transmitted from the output buffer 202 to the second storage location 208 through the input buffer 203 without transmitting the data to an external controller.

[0038] The present invention also provides an electronic device 100. The electronic device 100 includes a controller (e.g., CPU 101, memory controller 102, and DRAM controller 103) and a storage device 104 electrically connected to the controller. The storage device 104 includes a command decoder configured to receive a copy command to copy the data stored in the first storage location to the second storage location without transmitting the data to the controller; a memory array 201 having one or more memory arrays, each memory array having a plurality of banks, the plurality of banks being electrically connected to the command decoder and including a plurality of storage locations, the plurality of storage locations including a first storage location 207 and a second storage location 208; a data line 204 electrically connected to the memory array 201 and configured to receive the data to be transmitted from the first storage location 207 to the second storage location 208 through the same data line 204; and an output buffer 202 configured to store the data received from the first storage location 207 through the data line 204 to directly write the data into the second storage location 208 without transmitting the data to the controller.

[0039] For the CPU 101, since the copy command is determined based on at least one first predetermined binary value (e.g., "1") received by a special read input and a second predetermined binary value (e.g., "1") received by a special write input, the command decoder may include a special read input (e.g., 302) and a special write input (e.g., 303). Since data is received by the output buffer in response to the special read input receiving the first predetermined binary value, the output buffer 202 may include a first interface 202a connected to the data line 204 and a second input / output interface 202b connected to the read driver. The output buffer 202 may be configured to output the data back to the data line 204 for writing into the second storage location 208 instead of being received by the controller.

[0040] As Figure 2B shown in the embodiment of, the electronic device 100 may further include an input buffer 203. The input buffer 203 includes a first interface 203a connected to the data line 204, a second interface 203b connected to the write driver, and a third interface 203c connected to the output buffer 205. And the input buffer 203 may be configured to directly receive the data transmitted from the output buffer 202 through the third interface 203c, so as to output the data to the data line 204 for being written into the second storage location 208 without transmitting the data to the controller.

[0041] The copy command may be sent from, e.g., the CPU 101, or generated inside, e.g., the storage device 104. Whether the copy command is received is determined based on a combination of different input signals corresponding to the command decoder. Figure 3A A conceptual diagram of the command decoder 301 as part of the control logic 206 is shown. The command decoder 301 will receive a plurality of input signals, and the plurality of input signals may include a chip select (CS#) input, a row address strobe (RAS#) input, a column address strobe (CAS#) input, a write enable (WE#) input, a special read input, and a special write input. The copy command is determined based on whether the special read input and the special write input have received their respective predetermined signals.

[0042] The CS# input is used to activate a subset of the entire memory array (e.g., 201). The RAS# input is used to select a specific row, and the specific row may be kept open for a read operation or a write operation. The CAS# input is used to select a specific column from the currently selected row, and the specific column performs a read operation or a write operation. The WE# input is used to perform a read operation or a write operation based on whether the WE# is kept high or low. For example, the WE# input may receive a binary "0" for a read operation and a binary "1" for a write operation.

[0043] The combination of a first predetermined value for a special read input and a second predetermined value for a special write input will determine whether a copy command has been received. For example, the first predetermined value and the second predetermined value can both be binary "1", such that the first predetermined value and the second predetermined value can be the same value. However, they can also be different binary values. If the special read input is not the first predetermined input, then other FSMs will be executed. However, if the special read input matches the first predetermined input, then in response to the second determined input that has been received, another set of FSMs will be executed to implement the special read input and then implement the special write input. The special read input includes a regular read operation that reads data blocks to be stored in the output buffer, except for data stored in the output buffer that has not been read by an external controller (e.g., CPU 101, memory controller 102, and DRAM controller 103). The special write input includes a regular write operation, except for data received from the output buffer that is to be written to a different storage location.

[0044] Figure 3B illustrates Figure 3A an optional exemplary embodiment of. With respect to Figure 3B , the command decoder 301 can include an additional input, namely a special move command. The special move command can be implemented as an additional input / input (I / O) or an additional pin of the command decoder 301. The special move command can be automatically decoded by the command decoder 301 in the same manner as the above-described special read input and special write input. For example, when the special move command S311 is received, the command decoder 301 will decode the special move command in the same manner as the special read input of a high-level signal and the special write input of a high-level signal. Next, the special read input of the high-level signal will trigger a special read operation S312, and the special read operation S312 will read the data block in the first storage location and temporarily store the first storage location in the output buffer (e.g., 202). After the data block is stored in the output buffer (e.g., 202), the special write input will trigger a special write operation that will copy the data block stored in the output buffer (e.g., 202) to the second storage location. Optionally, the data block stored in the output buffer (e.g., 202) can be moved to another temporary location, such as a write FIFO buffer (e.g., 709), before being moved to the second storage location.

[0045] Figure 4AIt is a partial table showing the correspondence between input signals and various commands. For example, if the CS# input is low level (L), the RAS# input is L, the CAS# input is H, and the WE# input is H, the command decoder 301 will decode this set of input signals as an activate command. Similarly, if the CS# input is L, the RAS# input is H, the CAS# input is L, and the WE# input is H, the command decoder 301 will decode this set of input signals as a read command. Figure 4A The commands typically also include precharge commands, auto-refresh commands, self-refresh and mode register load commands, etc. The command decoder 301 will determine that if the special read input is H and then the special read input is L, a copy command has been received. It should be noted that H corresponds to the binary code "1", and L corresponds to the binary code "0". However, the present invention is not limited to the Figure 4A exact definition of the H value and L value as shown. Figure 4A The various commands described are conventional known commands, except for the copy command or move command, which did not previously exist in the conventional command decoder 301.

[0046] When receiving an activate command that typically will be before a read operation or a write operation, the storage device will be configured to select a row in a specific bank and activate the word line of the row. When receiving a read command, the storage device will be configured to perform a read operation at a specific column of the activated row. When receiving a write command, the storage device is configured to write a data block at a specific column of the activated row. When receiving a copy command, the storage device is configured to read a data block from a first storage location and write the data block to a second storage location. When receiving a precharge command, the storage device is configured to precharge the circuit before a read operation or a write operation. When receiving an auto-refresh command, the storage device is configured to periodically restore the charge stored in the memory cells. When receiving a self-refresh command, the storage device is configured to restore the charge stored in the memory cells when entering the standby or power-saving state.

[0047] Figure 4B It is a truth table associated with a special move command. In response to the special move command being a high-level signal or binary 1, the command decoder 301 will decode the special move command as a high-level signal or binary 1 corresponding to the special read input and also decode the special move command as a high-level signal or binary 1 corresponding to the special write input. In response to the special move command being a low-level signal or binary 0, the command decoder 301 will decode the special move command as a low-level signal or binary 0 corresponding to the special read input and also decode the special move command as a low-level signal or binary 0 corresponding to the special write input.

[0048] Figure 5A conceptual flowchart of the copy operation of a storage device is shown. In step S511, the storage device will receive a copy command to perform a copy operation, and in step S512, the storage device will be involved in receiving the copy command, the source address, and the destination address. In step S501, the storage device will read a data block by performing a read operation at a first storage location corresponding to the source address. In step S502, the storage device will transfer the data block to a first temporary memory. To impose no significant changes on the current structure, the temporary memory can be an existing structure, such as the read latch of a DRAM. Optionally, the temporary memory can also be a pseudo row, a temporary buffer, and a set of auxiliary units activated by blown fuses, etc. In optional step S503, the storage device can choose to transfer the data block to a second temporary memory that can be a write first-in first-out (FIFO) buffer. The optional step can provide higher flexibility to the storage device as it can store more data and can also solve potential timing problems. In step S504, the storage device will write the data block previously stored in the first temporary memory or the second temporary memory to a second storage location.

[0049] If the first temporary memory is a read latch and the second temporary memory is a write FIFO buffer, then since different databases will typically be connected via data lines, such as global input / output (GIO) data lines, this will enable the data block to be written on different databases. If the pseudo row technique is used, it will be more difficult to transfer the data block across different databases. It should be noted that the storage device can be a DRAM, SRAM, RRAM, spin transfer torque magnetoresistive RAM (STT-MRAM), and / or resistive RAM (ReRAM), etc. However, for illustrative purposes, the present invention will use a DRAM structure as an example to provide further explanation regarding the concepts of the present invention.

[0050] Figure 6FIG. 0 is a flowchart showing steps of a method for performing a copy operation in a storage device according to an exemplary embodiment of the present invention. In step S601, the storage device 104, for example, receives a copy command, a source address, and a destination address from a controller (e.g., CPU 101, memory controller 102, and DRAM controller 103), and the source address and the destination address correspond to positions in the storage device. In step S602, the storage device will perform a read operation at the source address in response to receiving the copy command to obtain data. In step S603, after performing the read operation, the storage device will transfer the data to an output buffer (e.g., 202) via a GPIO line (e.g., 204). In step S604, the storage device will store the data in the output buffer (e.g., 202) in response to the output buffer receiving the data. In step S605, the storage device will transfer the data stored in the output buffer to the destination address via a data line (e.g., 205). In step S606, the storage device will write the data at the destination address in response to transferring the data stored in the output buffer.

[0051] The step of receiving the copy command may include receiving a copy command determined based on at least a first predetermined binary value (e.g., “1”) received via a special read input (e.g., 302) of the storage device and a second predetermined binary value (e.g., “1”) received via a special write input (e.g., 303) of the storage device, and the first predetermined binary value may be the same as or different from the second predetermined binary value. In response to receiving an activation command, the storage device may initialize a conventional read program, and the special read input is not the first predetermined binary value (e.g., “0”), or in response to receiving an activation command, the storage device may initialize a copy program corresponding to the copy command, and the special read input is the first predetermined binary value. In other words, based on the values received via the special read input and the special write input, the storage device will determine whether to execute a set of conventional finite state machines (FSMs) or alternative FSMs. The copy program corresponding to the copy command may include a conventional read program and a conventional write program, and the conventional read program may include reading from the source address, and the conventional write program includes writing to the destination address.

[0052] The step of transferring the data to the output buffer via the data line after performing the read operation may include transferring the data from the source address to the output buffer via a first interface (e.g., 203a) connected to the data line in response to the special read input having received the first predetermined binary value. The step of transferring the data stored in the output buffer to the destination address via the data line may include transferring the data directly from the output buffer back to the data line to be written to the destination address instead of being received by the memory controller in response to the special write input receiving the second predetermined binary value.

[0053] In an alternative exemplary embodiment, the output buffer may include a first interface (e.g., 202a) connected to a data line, a second interface (e.g., 202b) connected to a write driver, and a third interface (e.g., 202c), and the step of transferring data stored in the output buffer to a target address via the data line may include directly transferring the data stored in the output buffer to the input buffer via the third interface (e.g., 202c), storing the data in the input buffer, and transferring the data from the input buffer to the target address. The step of directly transferring the data stored in the output buffer to the input buffer via the third interface (e.g., 202c) may further include transferring the data from the input buffer to an input buffer that does not have data read by the memory controller.

[0054] Since the copy command includes a combination of a read operation and a write operation, the operating principles of the read operation and the write operation are provided. Referring to Figure 7 FIG., which shows a hardware block diagram of a DRAM memory device, the copy command begins when the command decoder 702 of the control logic 701 receives a read command and a special read input matches a first predetermined value. The address register 703 will receive a source address including a row address and a column address of a first storage location. The row address will be decoded by the row address and latch and decoder 704, and the column address will be decoded by the column address decoder 705. Next, the column select lines (CSLs) associated with the resource address of the memory array 706 will be activated so that the sense amplifiers will sense the data blocks of the selected cells, and the data blocks will then be transferred to the local input-output (LIO) data lines, then to the GIO data line 707, and then latched by the output buffer, which is the read latch 708. The data blocks that have been read are then stored in the read latch 708.

[0055] Next, the copy command will also involve a write operation. The write operation begins when the command decoder 702 of the control logic 701 receives a write command and a special write input matches a second predetermined value. The address register 703 will receive a target address including a row address and a column address of a second storage location. The row address will be decoded by the row address and latch and decoder 704, and the column address will be decoded by the column address decoder 705. The second storage location may receive a data block stored in the read latch 708 or may receive a data block stored in the write FIFO buffer 709. Next, the CSL associated with the cell of the target address of the memory array 706 will be activated to receive the data block. Next, the data block is sent via the GIO data line 707 to the LIO data line associated with the target address. Next, the data block will subsequently be transferred to the sense amplifier of the bit line that has been precharged and is associated with the cell of the target address. As the data block is written into the cell of the target address, the write operation will be completed.

[0056] Figure 8 A hardware block diagram of a general storage device for performing a copy command is shown. The special read operation described so far is the same as the conventional read operation, except that the data block does not directly enter the serial-to-parallel conversion and is not sent out to be received by an external controller (e.g., CPU 101, memory controller 102, and DRAM controller 103). Conventionally, the data block would have undergone serial-to-parallel conversion through the read latch 801 to convert the bits of the data block from a parallel format to a serial format, but with respect to the present invention, the data block is transferred back to the memory array to be moved or copied. In other words, a read operation is performed, but the output stops at the read latch 801 including the first interface 801a and the second interface 801b. The first interface 801a is connected to the GIO data line 803 and receives data from the GIO data line 803. The second interface 801b is connected to the read driver, but the data block is not received by the external controller through the read driver.

[0057] In addition, the special write operation described so far is consistent with the regular write operation, except that the data block is received from the read latch 801 and written back to the memory array via the GIO data line 803 and the LIO data line associated with the target address. Alternatively, the read latch 801 may further include a third interface 801c so that the data block can be directly received from the write FIFO buffer 802 and written back to the memory array via the GIO data line 803 and the LIO data line associated with the target address. Alternatively, the data block can be transferred from the read latch 801 to the write FIFO buffer 802 via the GIO data line. The write FIFO buffer 802 is not limited to the first interface 802a connected to the GIO data line 803 to transfer data to the GIO data line 803, the second interface 802b for receiving data from the write driver, and optionally, the third interface 802c for directly receiving data from the read latch 801.

[0058] It is also worth noting that the concept of the program involving the copy command will also apply to storage devices other than DRAM storage devices, except for storage devices such as SRAM, RRAM, and flash memory that do not require sense amplifiers to perform read and write operations. In other words, although some storage devices do not use sense amplifiers, it will be apparent to those of ordinary skill in the art that necessary adjustments are made to implement the technology provided by the present invention. In general, the foregoing concepts of the present invention apply to being used in or as part of an electronic device and being capable of performing a copy operation or a move operation to copy data from a storage location to another storage location without having to transfer the data to a central processor through a memory controller. The advantages or benefits or improvements to the industry will include the ability to execute the copy command without imposing significant changes on the current storage device structure. Similarly, since the locations can be in the same or different parts, the same bank, or between different banks, the locations involved in the copy command can be flexible.

[0059] To further clarify the concepts provided so far, the present invention also provides several exemplary embodiments corresponding to a double data rate (DDR) 3256Mb x 8 storage device and its associated FSM for executing a copy command. Figure 9AShows a first exemplary embodiment corresponding to executing a copy command for a single data block. The copy command will copy a single data block of size M bits stored in a cell associated with a source address to a cell associated with a target address, where M is an integer greater than 0, such as 64. In step S901, the row of the cell associated with the source address in which the single data block is stored is activated. In step S902, the single data block stored in the cell associated with the source address is read and transferred to a read latch. In step S903, the single data block stored in the read latch (e.g., output buffer) is written to the cell associated with the target address. The source address and the target address can be addresses in the same bank or different banks. An alternative step to step S903, regarding step S904, the single data block stored in the read latch can be transferred from the read latch to a write FIFO buffer (i.e., input buffer), and then written to the cell associated with the target address. By using the Figure 9A embodiment of the present invention, a copy command can be used to copy a single data block stored in a read latch or output buffer (e.g., 202) and directly copy it back into the memory array (e.g., 201), rather than outputting it to an external processor before copying the single data block back into the memory array 201.

[0060] Figure 9B Shows the Figure 9A FSM schematic related to an example of. In step S911, the memory control device activates the row of the cell associated with the source address in which a single data block is stored. In response to the cell being activated, in step S912, a read operation is performed corresponding to the cell associated with the source address to obtain a single data block, which will be transferred via GIO data lines to be stored in a read latch or output buffer (e.g., 202). After the single data block has been stored in the read latch, in step S913, a read operation is performed in the read latch to transfer the single data block to be written to the cell associated with the source address. In step S914, the memory control device activates the row of the cell associated with the target address into which the single data block is written. In response to the cell being activated, in step S915, the single data block is written to the cell associated with the target address. In step S916, a precharge operation is performed for the next iteration of the read operation or write operation. By using the Figure 9B embodiment of the present invention, the copy command can be executed by copying a single data block back to the target address from an output buffer (e.g., 202).

[0061] Figure 10Shows a second exemplary embodiment corresponding to the execution of a copy command for a plurality of data blocks. The copy command will copy N data blocks stored in a unit associated with a source address to a unit associated with a target address, each data block having a size of M bits. N is an integer greater than 1, and M is an integer greater than 0, such as 64. The source address and the target address are in the same row of the same database but in different columns. In step S1001, the word line of the unit associated with the source address is activated, and then one of the plurality of data blocks is read from one or more columns of the same row, where one of the plurality of data blocks is already stored in the source address. In step S1002, one of the plurality of data blocks stored in the unit associated with the source address is transferred to the read latch. Steps S1001 and S1002 are repeated N - 1 times until all of the plurality of data blocks belonging to the same row are transferred to the read latch. In step S1003, one of the plurality of data blocks of the same row stored in the read latch (i.e., the output buffer) is transferred via GIO and then written into the unit associated with the target address, where the target address belongs to the same row but is in a different column.

[0062] Similarly, corresponding to the second exemplary embodiment, the source address and the target address are assumed to be in the same bank. In step S1004, steps S1001 - S1003 can be repeated for the remaining data blocks of the plurality of data blocks corresponding to the same row until all of the plurality of data blocks are stored in the unit associated with the target address. An alternative step to step 1003, regarding step S1005, one or more of the plurality of data blocks stored in the read latch can be transferred from the read latch to the write FIFO buffer (i.e., the input buffer) and then written into the unit associated with the target address. By using the Figure 10 embodiment of the present invention, a copy command can be used to copy a single data block stored in the read latch or the output buffer (e.g., 202) and directly copy it back into the memory array (e.g., 201), rather than outputting it to an external processor before copying the single data block back into the memory array 201, and the copy command can be executed in such a way as to copy a single data block from a source address in a column to a target address in a different column but the same row.

[0063] Figure 11 Shows the one related to Figure 10FSM schematic diagram related to an example. In step S1111, the memory control device activates the word line of the cell associated with the source address, and one of a plurality of data blocks is stored in the source address. In response to the cell being activated, in step S1112, a read operation is performed corresponding to the cell associated with the source address to obtain one of the plurality of data blocks, and one of the plurality of data blocks will be transmitted through the GIO data line to be stored in the read latch. After a single data block has been stored in the read latch, in step S1113, a read operation will be performed in the read latch to transmit the single data block to be written into the cell associated with the source address. In step S1114, the memory control device writes the single data block into the cell associated with the target address. In step S1115, the memory control device will determine whether all of the plurality of data blocks have been written into the cell associated with the target address. If so, in step S1116, a precharge operation is performed for the next iteration of the read operation or the write operation, otherwise step S1113 is repeated. By using the Figure 11 embodiment of the present invention, a copy command can be used to copy a plurality of data blocks stored in the read latch or the output buffer (e.g., 202) and directly copy them back into the memory array (e.g., 201), rather than outputting them to an external processor before copying a single data block back into the memory array 201, and the copy command can be executed in such a way that a single data block among the plurality of data blocks is copied from the source address of the column to the target address in a different column but the same row (as described between step S1113 and step S1115) until all the copy operations or move operations corresponding to the plurality of data blocks are completed.

[0064] Figure 12 Shows a third exemplary embodiment of executing a copy command corresponding to a plurality of data blocks. Figure 12 The third exemplary embodiment of Figure 11 and the difference between the second exemplary embodiment of Figure 11 includes that, regarding the third embodiment, the source address and the target address are in different rows but the same column in the same database. However, regarding Figure 12 the second exemplary embodiment of Figure 10 the source address and the target address are in the same row but different columns in the same database. Since the source address and the target address are in different rows, each of the rows corresponding to the source address and the target address must be activated separately. Figure 12 The third exemplary embodiment of Figure 10 can be understood in conjunction with the Figure 1 hardware schematic. Referring again to Figure 10, first, for the word line associated with the source address in step S1001, the word line associated with the source address from the row in which one of the plurality of data blocks is stored is activated, and subsequently, one of the plurality of data blocks is read from the same row. In step S1002, one of the plurality of data blocks is transferred from the same row associated with the source address to the read latch. In step S1003, one of the plurality of data blocks stored in the read latch (i.e., the output buffer) is transferred through the GIO and then written into the cell associated with the target address, where the target address is in a different row that is subsequently activated. In step S1104, steps S1001 - S1003 can be repeated N - 1 times until all of the plurality of data blocks are stored in the cells associated with the target address. An alternative step to step 1103, regarding step S1105, one or more of the plurality of data blocks stored in the read latch can be transferred from the read latch to the write FIFO buffer (i.e., the input buffer) and then written into the cell associated with the target address.

[0065] Now referring to the FSM related to the third exemplary embodiment in step S1201 Figure 12, the memory control device activates the word lines of the cells in the row associated with the source address, where one of the multiple data blocks is stored in the source address. In response to the cells being activated, in step S1202, a read operation is performed corresponding to the cells associated with the source address to obtain one of the multiple data blocks in the same row, and one of the multiple data blocks will be transmitted via the GIO data line to be stored in the read latch. After one of the multiple data blocks in the same row has been stored in the read latch, in step S1203, a read operation is performed in the read latch to transmit one of the multiple data blocks in the same row to be written into the cells associated with the source address. In step S1204, the memory control device activates another row of the cells associated with the target address, where one of the multiple data blocks will be stored in the target address. The cells in the target address are in a different row from the source address. In step S1204, one of the multiple data blocks is written into the cells associated with the target address. In step S1206, the memory control device determines whether all of the multiple data blocks have been written into the cells associated with the target address. If so, in step S1207, a precharge operation is performed for the next iteration of the read operation or the write operation; otherwise, step S1201 is repeated. Compared with the second exemplary embodiment, since the source address and the target are in different rows, the third exemplary embodiment has an additional step of row activation. Similarly, regarding the second exemplary embodiment, once a row is activated until all columns of the row are completed before the precharge operation, but regarding the third exemplary embodiment, before the precharge operation, all of the multiple data blocks in the row are copied to another row. By using the Figure 12 embodiment of the present invention, a copy command can be used to copy multiple data blocks stored in the read latch or the output buffer (e.g., 202) and directly copy them back into the memory array (e.g., 201), rather than outputting them to an external processor before copying a single data block back into the memory array 201, and the copy command can be executed in such a way that multiple data blocks stored in the same row are copied from the source address to different columns of the target address (as described between step S1201 and step S1205) until the entire copy operation or movement operation of the multiple data blocks is completed.

[0066] Figure 13 The fourth exemplary embodiment corresponding to executing the copy command for multiple data blocks is shown. The copy command will copy N data blocks stored in M columns of one row into the cells associated with the target address and be stored in multiple rows. Each data block stored in the cells associated with the source address has a size of M bits, where M is an integer greater than 0, such as 64. Referring again to Figure 10, in step S1001, the word lines of the cells associated with the source address of the row in which the multiple data blocks are located in multiple columns of the row will be copied into multiple rows, where each of the multiple rows is associated with a target address. In step S1002, the multiple data blocks stored in the cells of the same row associated with the source address are transferred to the read latch. In step S1003, among the multiple data blocks stored in the read latch (i.e., the output buffer), they are transferred through GIO and then written into the cells associated with the target addresses in different rows. In step S1004, one iteration of steps S1001 - S1003 can be repeated until the remaining data blocks among the multiple data blocks have been stored in the cells associated with one row of the target address, and each row performs multiple iterations. An alternative step to step 1203, regarding step S1205, one or more of the multiple data blocks stored in the read latch can be transferred from the read latch to the write FIFO buffer (i.e., the input buffer) and then written into the cells associated with the target address.

[0067] Referring to the Figure 13 . In step S1301, the word lines and multiple columns of the row of the cells associated with the source address in which the multiple data blocks have been stored are activated. In step S1302, the multiple data blocks stored in the multiple columns associated with the row of the source address are transferred to the read latch.

[0068] In step S1303, the multiple data blocks stored in the read latch (e.g., the output buffer) are transferred through GIO to be written into the first row of the cells associated with the target address. In step S1304, the memory control device activates the first row of the cells associated with the target address, where one of the multiple data blocks will be stored in the target address. In step S1305, one of the multiple data blocks is written into the first row of the cells associated with the target address. In step S1306, the memory control device will determine whether one of the multiple data blocks has been written into the cells associated with the first row of the target address. If so, in step S1307, a precharge operation is performed for the next iteration of the read operation or the write operation, otherwise step S1303 is repeated for another data block to be written into the second row of the cells associated with the target address. Steps S1303 - S1306 can be repeated for the second row, where another one of the multiple blocks is the data to be stored. Steps S1303 - S1306 can be repeated multiple times until the remaining data blocks of the multiple data blocks have been stored in the cells of the multiple rows associated with the target address. By using the present invention's Figure 13In an embodiment, the copy command may be used to copy multiple data blocks stored in a read latch or an output buffer (e.g., 202) and directly copy them back to the memory array (e.g., 201), rather than outputting a single data block to an external processor before copying it back to the memory array 201, and multiple data columns in one row may be copied from a source address to multiple rows at a target address (between step S1303 and step S1306) until all copy operations or move operations of multiple data blocks are completed.

[0069] In some embodiments of the present invention, a storage device is provided. The storage device includes a command decoder configured to receive a copy command to directly copy data stored in a first storage location to a second storage location without transmitting the data to an external controller; a memory array electrically connected to the command decoder and including multiple storage locations, the multiple storage locations including the first storage location and the second storage location; a data line electrically connected to the memory array and configured to receive data to be transmitted to the second storage location from the first storage location through the same data line; and an output buffer configured to store the data received from the first storage location through the data line to directly write the data into the second storage location without transmitting the data to an external controller.

[0070] According to an exemplary embodiment, since the copy command is determined based on at least one first predetermined binary value received based on a special read input and a second predetermined binary value received based on a special write input, the command decoder includes the special read input and the special write input, wherein the first predetermined binary value is the same as or different from the second predetermined binary value.

[0071] According to an exemplary embodiment, the storage device further includes control logic configured to initialize a normal read program in response to receiving an activation command and the special read input is not the first predetermined binary value, or the control logic is configured to initialize a copy program corresponding to the copy command in response to receiving an activation command and the special read input is the first predetermined binary value.

[0072] According to an exemplary embodiment, the copy program corresponding to the copy command includes a normal read program and a normal write program, wherein the normal read program includes reading from the first storage location, and the normal write program includes writing to the second storage location.

[0073] According to an exemplary embodiment, since the output buffer receives data in response to receiving the first predetermined binary value based on the special read input, the output buffer includes a first interface connected to the data line and a second interface connected to a read driver.

[0074] According to an exemplary embodiment, the control logic is configured to receive a second predetermined binary value in response to a special write input, and control the output buffer to directly output the data back to the data line to be written into a second storage location instead of being received by an external controller.

[0075] According to an exemplary embodiment, the storage device further includes a first interface connected to the data line, a second interface connected to the write driver, and a third interface connected to the output buffer.

[0076] According to an exemplary embodiment, the control logic is configured to control the input buffer to receive the data directly transmitted from the output buffer through the third interface and output the data to the data line to be written into a second storage location without transmitting the data to an external controller.

[0077] In some embodiments of the present invention, a method of copying data in a storage device without transmitting the data to a memory controller is described. The method will include, but not be limited to, receiving a copy command, a source address, and a target address from a memory controller, wherein the source address and the target address correspond to locations in the storage device; in response to the copy command, performing a read operation at the source address to obtain the data; after performing the read operation, transmitting the data to the output buffer through the data line; in response to the output buffer receiving the data, storing the data in the output buffer; transmitting the data stored in the output buffer to the target address through the data line; and in response to transmitting the data stored in the output buffer, writing the data at the target address.

[0078] According to an exemplary embodiment, a copy command determined based on at least one first predetermined binary value received by a special read input of the storage device and a second predetermined binary value received by a special write input of the storage device is received, and the first predetermined binary value is the same as or different from the second predetermined binary value.

[0079] According to an exemplary embodiment, the method further includes initializing a regular read program in response to receiving an activation command, and the special read input is not the first predetermined binary value, or includes initializing a copy program corresponding to the copy command in response to receiving an activation command, and the special read input is the first predetermined binary value.

[0080] According to an exemplary embodiment, the copy program corresponding to the copy command includes a regular read program and a regular write program, wherein the regular read program includes reading from the source address, and the regular write program includes writing to the target address.

[0081] According to an exemplary embodiment, transferring data to an output buffer via a data line after a read operation is performed will include transferring data from a source address to the output buffer via a first interface connected to the data line in response to a special read input having received a first predetermined binary value.

[0082] According to an exemplary embodiment, transferring data stored in an output buffer to a target address via a data line will include transferring the data directly back from the output buffer to the data line to be written into the target address rather than being received by a memory controller in response to a special write input receiving a second predetermined binary value.

[0083] According to an exemplary embodiment, the output buffer includes a first interface connected to the data line, a second interface and a third interface connected to a write driver, and transferring data stored in the output buffer to a target address via the data line will include transferring the data stored in the output buffer directly to an input buffer via the third interface, storing the data in the input buffer, and transferring the data from the input buffer to the target address.

[0084] According to an exemplary embodiment, transferring the data stored in the output buffer directly to the input buffer via the third interface will further include transferring the data from the input buffer to an input buffer that does not have data read by the memory controller.

[0085] In some embodiments of the present invention, an electronic device is provided. The electronic device includes a controller; and a storage device electrically connected to the controller, wherein the storage device includes a command decoder configured to receive a copy command to directly copy data stored in a first storage location to a second storage location without transferring the data to the controller; a memory array electrically connected to the command decoder and including a plurality of storage locations, the plurality of storage locations including the first storage location and the second storage location; a data line electrically connected to the memory array and configured to receive data to be transferred to the second storage location from the first storage location via the same data line; and an output buffer configured to store data received from the first storage location via the data line to directly write the data into the second storage location without transferring the data to the controller.

[0086] According to an exemplary embodiment, since a copy command is determined based on at least one first predetermined binary value received for a special read input and a second predetermined binary value received for a special write input, the command decoder includes the special read input and the special write input. The first predetermined binary value may be the same as or different from the second predetermined binary value.

[0087] In accordance with an exemplary embodiment, in response to receiving a first predetermined binary value in response to a special read input, an output buffer includes a first interface connected to a data line and a second interface connected to a read driver, and the output buffer is configured to directly output data back to the data line to write the data into a second storage location instead of being received by a controller.

[0088] In accordance with an exemplary embodiment, an electronic device further includes an input buffer, the input buffer includes a first interface connected to a data line, a second interface connected to a write driver, and a third interface connected to the output buffer, and the input buffer is configured to directly receive data transmitted from the output buffer through the third interface so as to output the data to the data line to be written into a second storage location without transmitting the data to a controller.

[0089] Unless otherwise specified, the elements, acts, or instructions used in the detailed description of the embodiments disclosed in this application should not be construed as the absolute scope or essence of the present invention. Similarly, as used herein, "a" or "an" can include one or more items. If it is intended to be only one item, the term "single" or similar language will be used. In addition, as used herein, the term "any of" followed by a list of multiple items and / or multiple item types is intended to include "any of", "any combination of", "any plurality of", and / or "any combination of a plurality of items and / or item types, individually or in combination with other items and / or other item types". In addition, as used herein, the term "group" is intended to include any number of items, including zero. In addition, as used herein, the term "quantity" is intended to include any number, including zero.

[0090] Those skilled in the art will readily appreciate that various modifications and changes can be made to the structure of the disclosed embodiments without departing from the scope or spirit of the present invention. In view of the foregoing description, it is intended that the present invention cover various modifications and variations of the present invention provided herein that fall within the scope of the present invention and its equivalents.

[0091] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those of ordinary skill in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present invention.

Claims

1. A storage device, comprising: A command decoder configured to receive a copy command to directly copy data stored in a first storage location to a second storage location, the command decoder including a special read input and a special write input, the copy command being determined based on at least one first predetermined binary value received by the special read input and a second predetermined binary value received by the special write input; A memory array electrically connected to the command decoder and including a plurality of storage locations, the plurality of storage locations including the first storage location and the second storage location; A data line electrically connected to the memory array and configured to receive data to be transferred from the first storage location to the second storage location through the same data line; An output buffer configured to store the data received from the first storage location through the data line to directly write the data into the second storage location; And Control logic configured to initialize a copy program corresponding to the copy command in response to receiving an activation command and the special read input being the first predetermined binary value, wherein the data is received by the output buffer in response to the special read input receiving the first predetermined binary value, and the data is directly output back to the data line by the output buffer in response to the special write input receiving the second predetermined binary value to be written into the second storage location.

2. The storage device according to claim 1, wherein, The output buffer is a read latch.

3. The storage device according to claim 1, wherein, The control logic is further configured to: Initialize a conventional read program in response to receiving the activation command and the special read input not being the first predetermined binary value.

4. The memory device according to claim 3, wherein, The copy program corresponding to the copy command includes the conventional read program and a conventional write program, wherein the conventional read program includes reading from the first storage location, and the conventional write program includes writing to the second storage location.

5. The storage device according to claim 1, wherein The output buffer includes a first interface connected to the data line and a second interface connected to a read driver.

6. The memory device according to claim 5, wherein, The control logic controls the output buffer to directly output the data back to the data line to be written into the second storage location rather than being received by an external controller in response to the special write input receiving the second predetermined binary value.

7. The storage device according to claim 1, further comprising: An input buffer including a first interface connected to the data line, a second interface connected to a write driver, and a third interface connected to the output buffer.

8. The memory device according to claim 7, wherein, The output buffer is configured to store the data received from the first storage location through the data line to directly write the data into the second storage location, including: The control logic is configured to control the input buffer to receive the data directly transferred from the output buffer through the third interface and output the data to the data line to be written into the second storage location without transferring the data to an external controller.

9. A method for copying data into a storage device, the method comprising: Receiving a copy command, a source address, and a destination address from the memory controller, wherein the source address and the destination address correspond to positions in the storage device, and the copy command is determined based on at least a first predetermined binary value received at a special read input of the storage device and a second predetermined binary value received at a special write input of the storage device; Initializing a conventional read program corresponding to the copy command in response to receiving an activation command and the special read input being the first predetermined binary value to perform a read operation at the source address to obtain the data; Transmitting the data from the source address to an output buffer via a data line in response to the special read input having the first predetermined binary value received; Storing the data in the output buffer in response to the output buffer receiving the data; Directly transmitting the data stored in the output buffer back to the data line and transmitting it to the destination address in response to the special write input receiving the second predetermined binary value; and Writing the data at the destination address in response to transmitting the data stored in the output buffer.

10. The method according to claim 9, wherein, The first predetermined binary value is the same as or different from the second predetermined binary value.

11. The method according to claim 10, further comprising: Initializing a conventional read program in response to receiving an activation command, and the special read input not being the first predetermined binary value.

12. The method according to claim 11, wherein, The copy program corresponding to the copy command includes the conventional read program and a conventional write program, wherein the conventional read program includes reading from the source address, and the conventional write program includes writing to the destination address.

13. The method according to claim 10, wherein, Transmitting the data from the source address to the output buffer via a first interface.

14. The method according to claim 13, wherein, Directly transmitting the data from the output buffer back to the data line to be written into the destination address instead of being received by the memory controller.

15. The method according to claim 9, wherein, The output buffer includes a first interface connected to the data line, a second interface connected to a write driver, and a third interface, and transmitting the data stored in the output buffer to the destination address includes: Directly transmitting the data stored in the output buffer to an input buffer via the third interface; Storing the data in the input buffer; and Transmitting the data from the input buffer to the destination address.

16. The method according to claim 15, wherein, Directly transmitting the data stored in the output buffer to the input buffer via the third interface includes: Transmitting the data from the input buffer to the input buffer that does not have the data read by the memory controller.

17. An electronic device, comprising: A controller; And A storage device electrically connected to the controller, the storage device comprising: A command decoder configured to receive a copy command to copy data stored in a first storage location to a second storage location, the command decoder including a special read input and a special write input, the copy command being determined based on at least one first predetermined binary value received at the special read input and a second predetermined binary value received at the special write input; A memory array electrically connected to the command decoder and including a plurality of storage locations, the plurality of storage locations including the first storage location and the second storage location; A data line electrically connected to the memory array and configured to receive data to be transferred from the first storage location to the second storage location through the same data line; An output buffer configured to store the data received from the first storage location through the data line to directly write the data into the second storage location; and Control logic configured to initialize a copy program corresponding to the copy command in response to receiving an activation command and the special read input being the first predetermined binary value, wherein the data is received by the output buffer in response to the special read input receiving the first predetermined binary value, and the data is directly output back to the data line by the output buffer in response to the special write input receiving the second predetermined binary value to be written into the second storage location.

18. The electronic device according to claim 17, wherein, The output buffer is a read latch.

19. The electronic device according to claim 17, wherein, The output buffer includes a first interface connected to the data line and a second interface connected to a read driver, and the output buffer is configured to directly output the data back to the data line to write the data into the second storage location rather than being received by the controller.

20. The electronic device according to claim 19, further comprising: An input buffer including a first interface connected to the data line, a second interface connected to a write driver, and a third interface connected to the output buffer, and the input buffer is configured to directly receive the data transferred from the output buffer through the third interface so as to output the data to the data line to be written into the second storage location without transferring the data to the controller.

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