Silicon carbide transistor and method of making the same

Abstract

The present specification discloses a silicon carbide transistor and a preparation method thereof. Specifically, the preparation method comprises: forming a Poly thin layer and a first mask layer on the silicon carbide epitaxial layer; the first mask layer comprises a first implantation window and a mask mark; using the first mask layer to perform non-penetration etching on the Poly thin layer to form a Poly implantation mask layer; implanting first ions to form a first conductive type region at a position corresponding to the first conductive type mask region of the silicon carbide epitaxial layer; using the Poly layer mark as an alignment reference to form a second conductive type region in the first conductive type region; and a region of the first conductive type region beyond the second conductive type region is a channel structure. The technical solution of the present specification can effectively control the deviation of the second conductive type region relative to the first conductive type region, thereby improving the alignment accuracy of the transistor, and is beneficial to the preparation of a short channel silicon carbide transistor.

Description

Technical Field

[0001] This specification relates to the field of semiconductor technology, and more particularly to a silicon carbide transistor and a method for its fabrication. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used in analog and digital circuits. Silicon carbide (SiC) MOSFETs, in particular, possess characteristics such as low on-resistance, fast switching speed, and high-temperature resistance, offering significant advantages in high-voltage frequency conversion, new energy vehicles, and rail transportation. To improve the current density of SiC MOSFETs, effectively controlling and shortening the channel length has become a major research direction. When the channel length is shortened, the photolithography alignment process requires extremely high precision, posing a significant challenge to the manufacturing process. Summary of the Invention

[0003] In view of this, the purpose of one or more embodiments of this specification is to provide a silicon carbide transistor and a method for fabricating the same, so as to improve the alignment accuracy of the channel and reduce the difficulty of the manufacturing process.

[0004] To achieve the above objectives, a first aspect of this specification provides a method for fabricating a silicon carbide transistor, comprising:

[0005] Provides a silicon carbide epitaxial layer;

[0006] A Poly thin layer and a first mask layer are formed on the silicon carbide epitaxial layer; the first mask layer includes a first implantation window and a mask mark;

[0007] The first mask layer is used to perform non-penetrating etching on the Poly thin layer to form a Poly injection mask layer; the Poly injection mask layer includes a first conductivity type masking region corresponding to the first injection window and a Poly layer mark corresponding to the mask mark;

[0008] Implanting first ions forms a first conductivity type region at the position corresponding to the first conductivity type masking region on the silicon carbide epitaxial layer;

[0009] Using the Poly layer marker as an alignment reference, a second conductivity type region is formed within the first conductivity type region; wherein, the region of the first conductivity type region extending beyond the second conductivity type region is a channel structure.

[0010] Furthermore, the silicon carbide epitaxial layer includes alignment marks; the fabrication steps of the first mask layer include:

[0011] A first initial mask layer is deposited on the Poly thin layer;

[0012] Using the alignment mark as an alignment reference and the Poly thin layer as an etching stop layer, the first initial mask layer is photolithographically formed to form a first mask layer including a first injection window and a mask mark.

[0013] Furthermore, the alignment mark and the Poly layer mark are located in the scribing lane area, and the extension directions of the alignment mark and the Poly layer mark are perpendicular to each other.

[0014] Furthermore, the alignment marks and the Poly layer marks have different patterns.

[0015] Furthermore, it also includes: removing the first mask layer after the step of implanting the first ion.

[0016] Furthermore, the step of forming a second conductivity type region within the first conductivity type region using the Poly layer mark as an alignment reference specifically includes:

[0017] Using the Poly layer marker as an alignment reference, a second mask layer is formed on the Poly injection mask layer; the second mask layer includes a second injection window and the second injection window is located within the first conductivity type masking region;

[0018] A second ion is injected to form a second conductivity type region within the first conductivity type region at the position corresponding to the second injection window.

[0019] Further, the step of forming a second mask layer on the Poly injection masking layer includes:

[0020] A second initial mask layer is deposited on the Poly injection mask layer;

[0021] Using the Poly layer as an alignment reference and the Poly injection mask layer as an etching stop layer, photolithography is performed on the second initial mask layer to form a second mask layer including a second injection window.

[0022] Furthermore, the thickness of the first type of conductive masking region is 50 nm to 200 nm.

[0023] Furthermore, the depth of the Poly layer marking is 450nm to 800nm.

[0024] The second aspect of this specification provides silicon carbide transistors obtained by any of the foregoing preparation methods.

[0025] As can be seen from the above description, the method for fabricating a silicon carbide transistor provided in one or more embodiments of this specification involves depositing a Poly layer and a first mask layer on a silicon carbide epitaxial layer; forming a first conductivity type masking region and a Poly layer marker on the Poly layer using the first mask layer; implanting first ions to form a first conductivity type region on the silicon carbide epitaxial layer at a position corresponding to the first conductivity type masking region; and forming a second conductivity type region within the first conductivity type region using the Poly layer marker as an alignment reference. The region of the first conductivity type region extending beyond the second conductivity type region then forms a channel structure. Using the Poly layer marker, formed simultaneously with the first conductivity type masking region, as an alignment reference for the second conductivity type region effectively controls the deviation of the second conductivity type region relative to the first conductivity type region, thereby improving the alignment accuracy of the transistor and benefiting the fabrication of short-channel silicon carbide transistors. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in one or more embodiments of this specification or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only one or more embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A schematic diagram of the fabrication process of a silicon carbide transistor provided in one or more embodiments of this specification;

[0028] Figure 2 This is a partial structural schematic diagram of a silicon carbide epitaxial layer provided in one or more embodiments of this specification.

[0029] Figure 3 A schematic diagram showing the position of alignment marks in a chip, provided for one or more embodiments of this specification;

[0030] Figure 4 A schematic diagram of the structure of the Poly thin layer and the first initial mask layer provided for one or more embodiments of this specification;

[0031] Figure 5 A schematic diagram of the structure of the Poly thin layer and the first mask layer provided for one or more embodiments of this specification;

[0032] Figure 6 for Figure 5 Top view of the provided Poly thin layer and first mask layer;

[0033] Figure 7A schematic diagram of the structure of a first conductivity type region provided for one or more embodiments of this specification;

[0034] Figure 8 A schematic diagram of the structure of the Poly injection masking layer provided in one or more embodiments of this specification;

[0035] Figure 9 for Figure 8 A top view of the provided Poly injection masking layer;

[0036] Figure 10 This is a schematic diagram of the structure of the second mask layer provided in one or more embodiments of this specification;

[0037] Figure 11 This is a schematic diagram of the structure of a second conductivity type region provided for one or more embodiments of this specification. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0039] It should be noted that, unless otherwise defined, the technical or scientific terms used in one or more embodiments of this specification should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar words used in one or more embodiments of this specification do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0040] Typically, SiC MOSFET power devices have a relatively small number of layers, generally around 8. Currently, the conventional approach is to first form mark markers on the scribe line area of ​​the SiC wafer. These mark markers serve as alignment references for photolithography, forming the first conductivity type region and the second conductivity type region. Finally, the area where the first conductivity type region extends beyond the second conductivity type region forms the channel structure of the SiC MOSFET. Using this manufacturing process, since both the first and second conductivity type regions use the mark markers for alignment, if the interlayer alignment accuracy deviation caused by equipment factors is ΔL, then the alignment accuracy deviation between the first and second conductivity type regions could potentially be 2ΔL.

[0041] To reduce the alignment deviation between the first conductivity type region and the second conductivity type region, a first aspect of this specification provides a method for fabricating a silicon nitride transistor.

[0042] Specifically, please refer to Figure 1 The preparation method includes: step 101: providing a silicon carbide epitaxial layer.

[0043] It should be noted that, as Figure 2 As shown, the silicon carbide epitaxial layer 202 is disposed on the silicon carbide substrate layer 201. The silicon carbide epitaxial layer 202 includes alignment marks 203.

[0044] Furthermore, the alignment mark 203 is formed on the silicon carbide epitaxial layer 202 by photolithography.

[0045] Optionally, the depth of the alignment mark 203 is 400 nm to 1 μm. Optionally, as... Figure 3 As shown, the alignment mark 203 is located in the scribe line region 2. It should be understood that the scribe line region 2 is typically located between adjacent chips 1.

[0046] Optionally, the silicon carbide epitaxial layer 202 is subjected to RCA cleaning before photolithography.

[0047] Step 102: Reference Figure 5 As shown, a Poly thin layer 301 and a first mask layer 302 are formed on the silicon carbide epitaxial layer 202; the first mask layer 302 includes a first injection window 303 and a mask mark 304.

[0048] Here, the material of the Poly thin layer 301 can be doped polycrystalline silicon, undoped polycrystalline silicon, amorphous silicon, or other dielectric materials.

[0049] Optionally, the thickness of the Poly thin layer 301 is selected from 500nm to 1000nm. Those skilled in the art can reasonably set the thickness of the Poly thin layer 301 based on the specific needs of the product, and no specific limitation is made here. For example, the thickness of the Poly thin layer can be 500nm, 600nm, 650nm, 625nm, 650nm, 700nm, 810nm, 850nm, 900nm, or 100nm.

[0050] It should be noted that, as Figure 6 As shown, the mask mark 304 is located in the scribe line region 2 and at a different position from the alignment mark 203 in the scribe line region 2. This design facilitates the differentiation of the two different types of marks during subsequent fabrication.

[0051] Optionally, the extending directions of the mask mark 304 and the alignment mark 203 are perpendicular to each other (e.g., Figure 6 (As shown).

[0052] It should be noted that the patterns of the mask mark 304 and the alignment mark 203 can be selected from circles, rectangles, squares, triangles, crosses, trapezoids and stars, etc.

[0053] Optionally, the mask mark 304 and the alignment mark 203 may have different patterns. For example, the alignment mark 203 may be a square, while the mask mark 304 may be a rectangle. Choosing different patterns for the mask mark 304 and the alignment mark 203 also helps to distinguish between the two different types of marks in subsequent fabrication processes.

[0054] In some alternative embodiments, reference is made to Figure 4 and Figure 5 The preparation steps of the first mask layer include:

[0055] like Figure 4 As shown, a first initial mask layer 302' is deposited on the Poly thin layer 301;

[0056] Using the alignment mark 203 as an alignment reference and the Poly thin layer 301 as an etching stop layer, photolithography is performed on the first initial mask layer 302' to form a first mask layer 302 including a first injection window 303 and a mask mark 304. For the specific structure, please refer to... Figure 5 .

[0057] Here, the first initial mask layer 302' is selected from one or more of SiO2, SiN and AlN.

[0058] Optionally, the thickness of the first initial mask layer 302' is selected from any value between 2 μm and 3 μm. Those skilled in the art can reasonably set the thickness of the first initial mask layer 302' based on the specific needs of the product, and no specific limitation is made here. For example, the thickness of the first initial mask layer 302' can be 2 μm, 2.2 μm, 2.3 μm, 2.5 μm, 2.7 μm, 2.75 μm, 2.8 μm, or 3 μm.

[0059] It should be understood that when the silicon carbide epitaxial layer 202 includes alignment marks 203, after depositing the Poly thin layer 301 and the first initial mask layer 302', the surface of the first initial mask layer 302' opposite to the alignment marks 203 will also form marks, which can be used for photolithography, next layer or multiple layers for alignment, etc.

[0060] Step 103: Please refer to Figure 7 The first mask layer 302 is used to perform non-penetrating etching on the Poly thin layer 301 to form a Poly injection mask layer 301'; the Poly injection mask layer 301' includes a first conductivity type masking region 401 corresponding to the first injection window 303 and a Poly layer mark 402 corresponding to the mask mark 304.

[0061] It should be understood that the first mask layer 302 serves as an etching mask, and the first injection window 303 and the mask mark 304 on it can be copied onto the Poly thin layer 301, ultimately forming a Poly injection mask layer 301'.

[0062] Optionally, by controlling the etching conditions, the etching ratio in the non-penetrating etching step can be 4 / 5 to 9 / 10 of the total thickness of the Poly thin layer 301. For example, when the thickness of the Poly thin layer 301 is 500 nm to 1000 nm, the etching depth can be 450 nm to 800 nm. For instance, when the thickness of the Poly thin layer 301 is 500 nm, the etching depth can be 450 nm; as another example, when the thickness of the Poly thin layer 301 is 600 nm, the etching depth can be 500 nm; as yet another example, when the thickness of the Poly thin layer 301 is 650 nm, the etching depth can be 520 nm; and as yet another example, when the thickness of the Poly thin layer 301 is 1000 nm, the etching depth can be 800 nm.

[0063] It should be noted that the depth of the Poly layer mark 402 corresponds to the etching depth. Optionally, the depth of the Poly layer mark 402 is 450 nm to 800 nm.

[0064] Optionally, the alignment mark 203 and the Poly layer mark 402 are located in the scribing lane area, and the extension directions of the alignment mark 203 and the Poly layer mark 402 are perpendicular to each other.

[0065] Optionally, the alignment mark 203 and the Poly layer mark 402 have different patterns.

[0066] It should be understood that the Poly layer mark 402 corresponds to the mask mark 304. When the extending directions of the mask mark 304 and the alignment mark 203 are perpendicular to each other, then the extending directions of the alignment mark 203 and the Poly layer mark 402 are perpendicular to each other. When the patterns of the mask mark 304 and the alignment mark 203 are different, then the patterns of the alignment mark 203 and the Poly layer mark 402 are different.

[0067] Here, the specific designs of the Poly layer mark 402 and the alignment mark 203 are as described above, and can be selected from circles, rectangles, squares, triangles, crosses, trapezoids and stars, etc., which will not be repeated here.

[0068] This design facilitates the differentiation of two different types of markings during subsequent preparation, making it easier for staff to operate and ensuring improved alignment accuracy.

[0069] It should be noted that the remaining portion of the Poly thin layer 301 at the position corresponding to the first injection window 303 is etched to form the first conductivity type masking region 401. Optionally, the thickness of the first conductivity type masking region 401 is 50 nm to 200 nm.

[0070] Step 104: Implant first ions to form a first conductivity type region 403 at the position corresponding to the first conductivity type masking region 401 on the silicon carbide epitaxial layer 202.

[0071] It should be understood that the first ion is selected from one or more of Al ions and B ions.

[0072] Here, the first conductivity type masking region 401 can act as a masking layer for the implanted first ions, preventing the high-energy first ions from damaging the silicon carbide epitaxial layer 202, which is conducive to the stable and accurate implantation of the first ions and the formation of a high-quality first conductivity type region 403.

[0073] Step 105: Using the Poly layer mark 402 as an alignment reference, a second conductivity type region is formed in the first conductivity type region 403; wherein, the area of ​​the first conductivity type region 403 that extends beyond the second conductivity type region is a channel structure.

[0074] It should be noted that you should refer to [link / reference]. Figure 8 and Figure 9 After step 104 and before step 105, the fabrication method further includes the step of removing the first mask layer 302. Specifically, after removing the first mask layer 302, the Poly injection masking layer 301' is as follows: Figure 8 As shown, its corresponding top view is as follows: Figure 9 As shown.

[0075] Therefore, the technical solution of this specification improves the alignment accuracy between the first and second conductive type regions by forming a Poly layer mark in the scribe line region of the same layer while forming the first conductive type masking region; and by utilizing the Poly layer mark for photolithographic alignment during the formation of the second conductive type region. When the interlayer alignment accuracy deviation caused by equipment factors is ΔL, if the existing technology aligns both the first and second conductive type regions using the alignment mark on the silicon carbide epitaxial layer as a reference, the alignment accuracy deviation between the first and second conductive type regions will reach 2ΔL. Using the technical solution of this specification, since the Poly layer mark and the first conductive type masking region are formed simultaneously, the first conductive type masking region and the first conductive type region are perfectly matched. Therefore, the error between the Poly layer mark and the first conductive type region is zero, thereby reducing the error between the second conductive type region (using the Poly layer mark as an alignment reference) and the first conductive type region to within the equipment's own alignment deviation value ΔL. In other words, the technical solution of this specification can reduce the alignment deviation between the first and second conductive type regions by half and double the accuracy. The technical solutions provided in this specification offer a feasible photolithographic alignment scheme for the fabrication of short-current SiC MOSFET devices.

[0076] Furthermore, since the Poly layer marker is located in the Poly injection masking layer, it has a better marking morphology and higher recognition accuracy compared to the alignment marker located in the silicon carbide epitaxial layer, which is more conducive to improving alignment accuracy.

[0077] refer to Figures 10-11 In one or more embodiments of this specification, the step of forming a second conductivity type region within the first conductivity type region, using the Poly layer mark as an alignment reference, specifically includes:

[0078] like Figure 10 As shown, with the Poly layer mark 402 as an alignment reference, a second mask layer 501 is formed on the Poly injection mask layer 301'; the second mask layer 501 includes a second injection window 502 and the second injection window 502 is located within the first conductivity type mask area 401.

[0079] Optionally, the material of the second mask layer 501 is selected from one or more of SiO2, SiN and AlN.

[0080] Optionally, the thickness of the second mask layer 501 is any value between 1 μm and 2 μm.

[0081] In one optional embodiment, the step of forming a second mask layer on the Poly injection masking layer includes:

[0082] A second initial mask layer is deposited on the Poly injection masking layer 301';

[0083] Using the Poly layer marker 402 as an alignment reference and the Poly injection mask layer 301' as an etching stop layer, the second initial mask layer is photolithographically formed to form a second mask layer 501 including a second injection window 502.

[0084] It should be understood that in one or more embodiments of this specification, photolithography is a prior art technique, including processes such as spin coating, exposure, development, and etching, which will not be described in detail here.

[0085] It should be noted that the Poly layer mark 402 is used as an alignment reference to ensure that the second injection window 502 is located within the first conductivity type masking area 401, ensuring accurate alignment between the second injection window 502 and the first conductivity type area. This is beneficial for the precise alignment of the position of the second conductivity type area 503 formed by the second injection serial port 502 with the first conductivity type area 403.

[0086] like Figure 11 As shown, a second ion is implanted, forming a second conductivity type region 503 within the first conductivity type region 403 at a position corresponding to the second implantation window 502. Those skilled in the art will understand that the region of the first conductivity type region 403 extending beyond the second conductivity type region 503 constitutes a channel structure.

[0087] Optionally, the second ion is selected from one or more of N ions, P ions, and As ions.

[0088] As will be understood by those skilled in the art, the first ion and the second ion can be interchanged. For example, the first ion is selected from one or more of N ions, P ions, and As ions, and correspondingly, the second ion is selected from one or more of Al ions and B ions.

[0089] It should be noted that the area of ​​the first conductivity type masking region 401 that exposes the second injection window 502 can also act as a masking layer for the injected second ions, preventing the high-energy second ions from damaging the silicon carbide epitaxial layer 202, which is conducive to the stable and accurate injection of the second ions and the formation of a high-quality second conductivity type region 503.

[0090] Therefore, in the technical solution of this specification, the first conductivity type masking region 401 can serve not only as a masking layer for the first ion implantation but also as a masking layer for the second ion implantation, improving the utilization rate of the entire Poly implantation masking layer 301'. The two ion implantations do not require separate masking layer fabrication, reducing manufacturing costs. Furthermore, the technical solution of this specification can improve the uniformity of SiC MOSFET dimensions, is compatible with conventional SiC MOSFET fabrication processes, and is particularly suitable for the fabrication of short-channel SiC MOSFETs.

[0091] It should be noted that the processes used to form the first initial mask layer 302', the second initial mask layer, and the Poly thin layer 301 in this specification are conventional methods in the art, such as chemical vapor deposition, thermal evaporation deposition, and plasma sputtering deposition, etc., and are not specifically limited here. Those skilled in the art can reasonably select appropriate deposition methods according to their needs, and will not elaborate further.

[0092] A second aspect of this specification also provides a silicon carbide transistor obtained by any of the foregoing fabrication methods. Optionally, the silicon carbide transistor is selected from metal-oxide-semiconductor field-effect transistors. The silicon carbide transistors of the above embodiments employ the corresponding fabrication methods in the foregoing embodiments and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0093] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0094] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure (including the claims) is limited to these examples; within the framework of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of one or more embodiments of this specification as described above, which are not provided in detail for the sake of brevity.

[0095] One or more embodiments of this specification are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of this disclosure.

Claims

1. A method of fabricating a silicon carbide transistor, comprising: The method comprises the following steps: providing a silicon carbide epitaxial layer; forming a Poly thin layer and a first mask layer on the silicon carbide epitaxial layer; the first mask layer comprises a first implantation window and a mask mark; performing non-penetration etching on the Poly thin layer by using the first mask layer to form a Poly implantation mask layer; the Poly implantation mask layer comprises a first conductive type mask area corresponding to the first implantation window and a Poly layer mark corresponding to the mask mark; implanting first ions to form a first conductive type area at a position corresponding to the first conductive type mask area on the silicon carbide epitaxial layer; removing the first mask layer, and forming a second conductive type area in the first conductive type area by taking the Poly layer mark as an alignment reference; wherein, a region of the first conductive type area beyond the second conductive type area is a channel structure; wherein, a thickness of the first conductive type mask area is 50 nm to 200 nm; and a depth of the Poly layer mark is 450 nm to 800 nm; the silicon carbide epitaxial layer comprises an alignment mark; and the preparation step of the first mask layer comprises the following steps: depositing a first initial mask layer on the Poly thin layer; performing photolithography on the first initial mask layer by taking the alignment mark as an alignment reference and taking the Poly thin layer as an etching stop layer to form the first mask layer comprising the first implantation window and the mask mark; the alignment mark and the Poly layer mark are located in a scribe lane area, and an extension direction of the alignment mark is perpendicular to an extension direction of the Poly layer mark; the step of forming the second conductive type area in the first conductive type area by taking the Poly layer mark as an alignment reference comprises the following steps: forming a second mask layer on the Poly implantation mask layer by taking the Poly layer mark as an alignment reference; the second mask layer comprises a second implantation window, and the second implantation window is located in the first conductive type mask area; implanting second ions to form a second conductive type area at a position corresponding to the second implantation window in the first conductive type area.

2. The production method according to claim 1, characterized by, the alignment mark and the Poly layer mark have different patterns.

3. The preparation method according to claim 1, characterized in that, the step of forming the second mask layer on the Poly implantation mask layer comprises the following steps: depositing a second initial mask layer on the Poly implantation mask layer; performing photolithography on the second initial mask layer by taking the Poly layer mark as an alignment reference and taking the Poly implantation mask layer as an etching stop layer to form the second mask layer comprising the second implantation window.

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