A process channel construction method, field effect transistor, storage medium and device

Abstract

The present invention belongs to the field of microelectronic technology, and in particular relates to a method for constructing a process trench, a field effect transistor, a storage medium and related equipment; by adopting the process trench structure disclosed in an embodiment of the present invention, a high-mobility material can be placed in a fin structure, and by further constructing an isolation structure, a corresponding device or functional structure can be obtained, thereby improving the defects and deficiencies of the planar structure in terms of electrical characteristics.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, and particularly relates to a method for constructing a process channel, a field-effect transistor, a storage medium, and related equipment. Background Technology

[0002] Increasing the channel doping concentration of a planar device (PD) will reduce the mobility M and thus affect the device's performance. For FinFET (Fin Field-Effect Transistor) and SOI (Silicon-On-Insulator) architectures, it is necessary to improve the channel structure in order for materials with high mobility M to function effectively. Summary of the Invention

[0003] This invention discloses a method for constructing a process channel and the corresponding field-effect transistor, storage medium, and related equipment; by introducing a material with high mobility, the electrical and mechanical properties of the device are improved in the fin structure.

[0004] Specifically, in this embodiment of the invention, a first process region and a second process region are constructed on a substrate using a photolithography process; the first process region includes at least two process channels, and at least one set of process composite layer structures are constructed between the two process channels, which must be realized through a common feature pattern transfer process.

[0005] The process composite layer is used to construct the fin structure; the process composite layer consists of raised substrate steps, a first dielectric layer and a second dielectric layer.

[0006] Furthermore, a first intermediate component is formed by filling the first process area with a first medium of the same type as the first medium layer.

[0007] The first process area of ​​the first intermediate component is engraved back, and the first step is formed in the first process area.

[0008] By constructing a third medium in the first step region, the height is continuously increased until the third medium is flush with the second medium layer to form a second intermediate component.

[0009] The area of ​​the second intermediate component in the second process zone is further opened to form a second step; wherein, the second step is further opened to a preset first fin depth based on the step depth of the first step, and a third intermediate component is formed.

[0010] Then, by filling the trench in the second process area of ​​the third intermediate with the fourth medium until it is higher than the third medium and away from the substrate, a fin structure filled with the fourth medium is formed.

[0011] The fin structure is enclosed between the substrate, the first dielectric, and the third dielectric; the fin structure is open outside the second process area on the side away from the substrate.

[0012] Furthermore, the feature pattern is transferred onto the substrate to define the relative positions of the first process area and the second process area; this process can employ a double-layer patterning technique.

[0013] The first fin depth is the effective dimension of the working area of ​​the process channel.

[0014] Furthermore, the first intermediate part can be annealed, and the surface of the annealed workpiece can be polished and cleaned.

[0015] The above process can be performed by constructing the first dielectric layer using FCVD (Flowable Chemical Vapor Deposition) and polishing the workpiece surface using CMP (Chemical Mechanical Polishing).

[0016] Furthermore, the depth of the first step can be selected to be between 10 and 20 nm; the first step is isolated from the substrate by a first dielectric layer.

[0017] Furthermore, the fourth dielectric can be SiGe or Ge; wherein the filling process includes epitaxial processing methods.

[0018] Furthermore, chemical mechanical polishing (CMP) can be performed on the workpiece surface where the fourth medium is located.

[0019] Furthermore, during the process of etching back the third medium, the third medium can be SiC.

[0020] In this process, the third medium is etched back to form a third step on the surface of the workpiece; the depth of the third step conforms to a preset value.

[0021] Furthermore, the fourth dielectric is subjected to a rounded corner oxidation process; this rounded corner oxidation process causes the unoxidized portion of the fourth dielectric on the side away from the substrate to be in a rounded corner state.

[0022] The oxidized portion of the fourth medium covers the unoxidized fourth medium.

[0023] Furthermore, by removing the oxidized portion of the fourth medium, the unoxidized portion of the fourth medium is opened.

[0024] Further, by opening a portion of the first medium within the first process area (201, 202, 203, 204), the fourth medium, which has been rounded, is exposed at a predetermined length on the side away from the substrate.

[0025] Furthermore, in this embodiment of the invention, a sixth dielectric layer is deposited on the side of the workpiece away from the substrate; the thickness of the sixth dielectric layer conforms to a preset value; and the sixth dielectric layer covers the surface of the workpiece.

[0026] Furthermore, the sixth dielectric layer in this embodiment of the invention is obtained using the ALD (Atomic Layer Deposition) atomic layer deposition method.

[0027] Furthermore, a protective layer or isolation structure is obtained by oxidizing the sixth dielectric layer; wherein the dielectric material of the sixth dielectric layer can be the same as the dielectric material used in the first dielectric after oxidation.

[0028] Furthermore, a field-effect transistor can be constructed using the method disclosed in the embodiments of the present invention, a trench structure can be constructed using the embodiments of the present invention, and / or a high-mobility active region including a fourth dielectric layer can be used.

[0029] Furthermore, a computer storage medium or processing device can be constructed, including a storage medium body for storing a computer program; when the computer program is executed by a microprocessor, it implements any of the methods disclosed in the embodiments of the present invention.

[0030] By employing the trench structure disclosed in the embodiments of this invention, high-mobility materials can be placed within the fin structure. By further constructing an isolation structure, corresponding devices or functional structures can be obtained, thus improving the defects and deficiencies of planar structures in terms of electrical characteristics.

[0031] It should be noted that the terms "first," "second," and similar terms used in this article are merely for describing the constituent elements of the technical solution and do not constitute a limitation on the technical solution, nor should they be interpreted as an indication or implication of the importance of the corresponding elements; elements with terms such as "first," "second," or similar terms indicate that at least one of the elements is included in the corresponding technical solution. Attached Figure Description

[0032] To more clearly illustrate the technical solution of the present invention and facilitate a further understanding of its technical effects, features, and objectives, the present invention will be described in detail below with reference to the accompanying drawings. The drawings constitute an essential part of the specification and are used together with Embodiment 1 of the present invention to illustrate the technical solution of the present invention, but do not constitute a limitation on the present invention.

[0033] The same reference numerals in the attached diagrams represent the same parts, specifically:

[0034] Figure 1 This is a schematic diagram of the structure of the first and second process zones in an embodiment of the present invention;

[0035] Figure 2This is a schematic diagram of the first dielectric layer interconnection structure and the first planarization process according to an embodiment of the present invention;

[0036] Figure 3 This is a schematic diagram of the first step structure (re-engraving) according to an embodiment of the present invention;

[0037] Figure 4 This is a schematic diagram of the third medium blocking effect and the second planarization process in an embodiment of the present invention;

[0038] Figure 5 This is a schematic diagram of the second process trench (second step) structure according to an embodiment of the present invention;

[0039] Figure 6 This is a schematic diagram of the fourth medium filling in an embodiment of the present invention;

[0040] Figure 7 This is a schematic diagram of the third planarization process in an embodiment of the present invention;

[0041] Figure 8 This is a schematic diagram of the third step structure in an embodiment of the present invention;

[0042] Figure 9 This is a schematic diagram of the rounded corner structure oxidation process according to an embodiment of the present invention;

[0043] Figure 10 This is a schematic diagram of the rounded corner forming process according to an embodiment of the present invention;

[0044] Figure 11 This is a schematic diagram of the fin structure forming according to an embodiment of the present invention;

[0045] Figure 12 This is a schematic diagram of the protective layer structure according to an embodiment of the present invention;

[0046] Figure 13 This is a schematic diagram of the heat treatment of the protective layer in an embodiment of the present invention;

[0047] Figure 14 This is a flowchart illustrating the process channel construction of an embodiment of the present invention;

[0048] Figure 15 This is a flowchart illustrating the construction process of the fin structure device according to an embodiment of the present invention;

[0049] in:

[0050] 10-Process area graphic transfer steps;

[0051] 20-Steps for constructing interlayer media;

[0052] 30 - Construction steps of the first step;

[0053] 40 - Construction steps of the sealing layer;

[0054] 50-Fin process groove forming steps;

[0055] 60-Fin media filling step;

[0056] 61-Fin tip pretreatment steps;

[0057] 62-Fin top step treatment steps;

[0058] 63-Fin tip rounded corner construction steps;

[0059] 64-Steps for removing the rounded corner of the fin tip;

[0060] 65 - Fin Removal Procedure;

[0061] 66 - Fin Protective Layer Construction Steps;

[0062] 67-Fin forming steps;

[0063] 100 - Substrate or wafer;

[0064] 101 - First medium (layer);

[0065] 102 - Second medium (layer);

[0066] 103 - Third medium (layer);

[0067] 104 - Fourth medium (layer);

[0068] 105 - Fifth medium (layer);

[0069] 106 - Sixth medium (layer);

[0070] 201, 202, 203, 204 - First process area;

[0071] 301, 302, 303 - Second process area;

[0072] 401 - First step (height);

[0073] 402 - Second step (height);

[0074] 403 - Third step (height). Detailed Implementation

[0075] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Of course, the specific embodiments described below are merely illustrative of the technical solutions of the present invention, and not intended to limit the invention. Furthermore, the parts described in the embodiments or drawings are merely illustrative examples of relevant parts of the present invention, and not the entirety of the invention.

[0076] like Figure 14 As shown in the flowchart of the process channel construction embodiment of the present invention, a method for constructing a process channel is disclosed.

[0077] In such Figure 1 On the workpiece shown, first process regions 201, 202, 203, 204 and second process regions 301, 302, 303 are constructed on substrate 100.

[0078] The first process regions 201, 202, 203, and 204 include at least two process channels, and at least one set of process composite layers is constructed between the at least two process channels; the process composite layer is used to construct the fin structure; wherein, the process composite layer is composed of a raised substrate 100 step, a first dielectric layer 101, and a second dielectric layer 102.

[0079] Furthermore, such as Figure 2 The first dielectric layer interconnection structure and first planarization process of the present invention are shown in the following schematic diagram. The first intermediate is formed in the first process areas 201, 202, 203, and 204 by filling the first dielectric layer 101 with a first dielectric of the same type.

[0080] like Figure 3 The first step structure (back-etching) schematic diagram of the embodiment of the present invention is shown. The first process areas 201, 202, 203, and 204 of the first intermediate part are etched back; the first step 401 is formed in the first process areas 201, 202, 203, and 204.

[0081] like Figure 4 The third medium blocking effect and the second planarization process of the present invention are shown in the following schematic diagram. The third medium 103 is constructed to the first step 401 region until the third medium 103 is flush with the second medium layer 102 to form the second intermediate.

[0082] like Figure 5 A schematic diagram of the second process trench (second step) in an embodiment of the present invention is shown, in which the second intermediate part is opened in the area of ​​the second process zone 301, 302, 303; thus forming the second step 402.

[0083] The second step 402 further opens the preset first fin depth based on the step depth of the first step 401, and forms the third intermediate component.

[0084] like Figure 6 The fourth medium filling diagram of the present invention shows that the fourth medium 104 is filled into the trenches of the third intermediate located in the second process areas 301, 302, and 303 until it reaches the side of the third medium away from the substrate 100; forming a fin-shaped structure filled with the fourth medium.

[0085] The fin structure is enclosed between the substrate 100, the first dielectric 101, and the third dielectric 103; the fin structure is open outside the second process area on the side away from the substrate 100.

[0086] Furthermore, such as Figure 1 As shown, transferring the feature pattern onto the substrate 100 involves defining the relative positions of the first process regions 201, 202, 203, 204 and the second process regions 301, 302, 303; wherein, the transfer of the feature pattern can employ processes including a dual patterning method; and its first fin depth is the effective size of the process channel working area.

[0087] Furthermore, such as Figure 7 The schematic diagram of the third planarization process of the present invention shown shows that the first intermediate part is annealed, and the surface of the annealed workpiece is polished and cleaned.

[0088] The first dielectric layer 101 is constructed using the FCVD deposition method; the workpiece surface is polished using the CMP method.

[0089] Optionally, the depth of the first step 401 may be between 10 and 20 nm; the first step 401 is isolated from the substrate 100 by a first dielectric layer 101.

[0090] Furthermore, the fourth medium can be SiGe or Ge; its filling method includes epitaxial processing methods.

[0091] Furthermore, such as Figure 7 , Figure 8 As shown in the diagram, the third planarization process and the third step structure are illustrated. The workpiece surface containing the fourth medium is subjected to chemical mechanical polishing (CMP); the third medium is then etched back.

[0092] The third medium can be SiC material; after the third medium is etched back, a third step 403 is formed on the surface of the workpiece; the depth of the third step conforms to a preset value.

[0093] Furthermore, such as Figure 9 A schematic diagram of the rounded corner oxidation process in an embodiment of the present invention shows the rounded corner oxidation treatment performed on the fourth medium.

[0094] The rounded corner oxidation process causes the unoxidized portion of the fourth medium on the side away from the substrate 100 to be in a rounded corner state; the oxidized portion 105 of the fourth medium covers the unoxidized fourth medium.

[0095] Furthermore, such as Figure 10 A schematic diagram of the rounded corner forming process in an embodiment of the present invention: removing the oxidized portion 105 of the fourth medium; opening the unoxidized portion 104 of the fourth medium; and obtaining the corresponding fin structure.

[0096] Specifically, such as Figure 11As shown in the schematic diagram of the fin structure forming in this embodiment of the invention, the portion of the first medium 101 within the first process areas 201, 202, 203, and 204 is opened; and the fourth medium 104, which has been rounded, is exposed at a predetermined length on the side away from the substrate 100.

[0097] like Figure 12 As shown in the schematic diagram of the protective layer structure in this embodiment of the invention, a sixth dielectric layer 106 is deposited on the side of the workpiece away from the substrate 100; wherein, the thickness of the sixth dielectric layer 106 meets a preset value; the sixth dielectric layer 106 covers the surface of the workpiece.

[0098] The sixth dielectric layer 106 was obtained using the ALD atomic layer deposition method.

[0099] Furthermore, such as Figure 13 As shown in the schematic diagram of the protective layer conditioning in this embodiment of the invention, the sixth dielectric layer 106 is oxidized; the dielectric material of the sixth dielectric layer 106 becomes the dielectric material used in the first dielectric 101 after oxidation.

[0100] Furthermore, a field-effect transistor can be adopted as follows: Figure 13 The trench structure shown includes, and / or contains, active regions with high mobility related to the fourth dielectric layer 104 structure.

[0101] Computer storage media and processing equipment that include the storage media and contain a program for performing the above methods also fall within the scope of the embodiments of the present invention.

[0102] By adopting such Figure 6 The process trench structure disclosed in the embodiment of the present invention can place high-mobility materials within the fin structure.

[0103] like Figure 13 As shown, by further constructing an isolation structure, the corresponding device or functional structure can be obtained, thus improving the defects and deficiencies of planar structures in terms of electrical characteristics.

[0104] It should be noted that the above embodiments are only for more clearly illustrating the technical solution of the present invention. Those skilled in the art will understand that the implementation of the present invention is not limited to the above content. Any obvious changes, substitutions or replacements made based on the above content do not exceed the scope of the technical solution of the present invention. Other implementations will also fall within the scope of the present invention without departing from the concept of the present invention.

Claims

1. A method for constructing a process channel, characterized in that: include: A first process area and a second process area are constructed on a substrate (100); the first process area includes at least two process channels, and at least one group of process composite layers is constructed between the at least two process channels; the process composite layer is used to construct a fin structure; wherein the process composite layer is composed of a raised substrate (100) step, a first dielectric layer (101) and a second dielectric layer (102); a first dielectric of the same type as the first dielectric layer (101) is filled in the first process area to form a first intermediate piece; the first process area of ​​the first intermediate piece is back-etched; a first step (401) is formed in the first process area; a third dielectric (103) is constructed to the first step (401) area until the third dielectric (103) is flush with the second dielectric layer (102) to form a second The invention relates to a method for manufacturing a fin-shaped intermediate member; opening the second intermediate member in the area of ​​the second process zone; forming a second step (402); wherein the second step (402) further opens a preset first fin depth based on the step depth of the first step (401), and forms a third intermediate member; filling a fourth medium (104) into the groove of the third intermediate member located in the second process zone until it is higher than the side of the third medium away from the substrate (100); forming a fin-shaped structure filled with the fourth medium; the fin-shaped structure is wrapped between the substrate (100), the first medium (101) and the third medium (103); the fin-shaped structure is opened outside the second process zone on the side away from the substrate (100); the fourth medium comprises SiGe or Ge.

2. The method for constructing a process channel according to claim 1, wherein: The characteristic pattern is transferred onto the substrate (100); the relative position of the first process area and the second process area is defined; the transfer of the characteristic pattern adopts a process including a double patterning method; the first fin depth is the effective size of the process channel working area.

3. The method for constructing a process channel according to claim 1, further comprising: The first intermediate piece is annealed, and the surface of the annealed workpiece is polished and cleaned.

4. The method for constructing a process channel according to claim 1, wherein: The first dielectric layer (101) is constructed by using an FCVD deposition method; and the surface of the workpiece is polished by using a CMP method.

5. The method for constructing a process channel according to claim 3, wherein: The depth of the first step (401) is between 10 and 20 nm; the first step (401) is isolated from the substrate (100) via the first dielectric layer (101).

6. The method for constructing a process channel according to any one of claims 1 to 5, wherein: The method of filling the first medium and the fourth medium comprises an epitaxial process method; The surface of the workpiece where the fourth medium is located is subjected to chemical mechanical polishing (CMP).

7. The method for constructing a process channel according to claim 6, further comprising: The third medium is back-etched; wherein the third medium comprises SiC; after the third medium is back-etched, a third step (403) is formed on the surface of the workpiece; and the depth of the third step meets a preset value.

8. The method for constructing a process channel according to claim 7, wherein: The fourth medium is subjected to a rounded corner oxidation treatment; the rounded corner oxidation treatment causes the unoxidized portion of the fourth medium on the side away from the substrate (100) to be in a rounded corner state; the oxidized portion (105) of the fourth medium covers the unoxidized portion of the fourth medium.

9. The method for constructing a process channel according to claim 8, further comprising: removing the oxidized portion of the fourth medium (105); The unoxidized portion (104) of the fourth medium is opened.

10. The method for constructing a process channel according to claim 9, wherein: The portion of the first medium (101) within the first process zone is opened; and the fourth medium (104) that has undergone rounded corner processing is exposed at a preset length on a side away from the substrate (100).

11. The method for constructing a process channel according to claim 10, further comprising: Depositing a sixth dielectric layer (106) onto a side of the workpiece away from the substrate (100); The thickness of the sixth dielectric layer (106) meets a preset value; The sixth dielectric layer (106) covers the surface of the workpiece.

12. The method for constructing a process channel according to claim 11, wherein: The sixth dielectric layer (106) is obtained by using an ALD atomic layer deposition method.

13. The method for constructing a process channel according to claim 12, wherein: The sixth dielectric layer (106) is subjected to an oxidation treatment; the dielectric material of the sixth dielectric layer (106) becomes the dielectric material used by the first dielectric (101) after being oxidized.

14. A computer storage medium comprising: A storage medium for storing a computer program; When the computer program is executed by a microprocessor, the computer program implements the method for constructing a process channel according to any one of claims 1 to 13.

15. A processing device comprising: The storage medium as claimed in claim 14 and / or for producing and processing field effect transistors; the processing process of the device adopts the construction method of the process channel as claimed in claims 1-13.

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