A method for improving the contact hole size of FDSOI device

Abstract

The present invention provides a method for improving the size of the contact hole of an FDSOI device, wherein the semiconductor structure comprises a source / drain region and a gate of an NMOS region and a PMOS region; the source / drain region and the gate are covered with a silicon oxide layer; the silicon oxide layer is etched to form a source / drain contact hole; a first oxide film layer is formed on the sidewall of the source / drain contact hole; metal is deposited to fill the source / drain contact hole, and the surface is flattened to adjust the depth of the source / drain contact hole; the silicon oxide layer on the gate of the NMOS region and the PMOS region is etched to form a gate contact hole; a second oxide film layer is formed on the sidewall of the gate contact hole; metal is deposited to fill the gate contact hole, and the surface is flattened to adjust the depth of the gate contact hole. The present invention is applied to the FDSOI CMOS semiconductor device process of 22nm and below. Compared with the traditional FDSOI process, the present invention grows an oxide film layer on the sidewall of the through hole before the through hole is filled with metal and after the through hole etching process is completed, and then removes the oxide film layer on the upper surface of the gate by etching, thereby adjusting the size of the through hole.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a method for improving the size of a contact hole of an FDSOI device. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, in order to improve the integration of integrated circuits, while increasing the operating speed of devices and reducing their power consumption, the key dimensions of devices are constantly shrinking, and the corresponding through-holes connected to the devices are also getting smaller and smaller. Smaller contact sizes require more advanced photolithography machines. Traditional device contact hole processes are usually obtained by etching after exposure and development, and the size of the contact holes is also directly defined by photolithography. Therefore, photolithography machines need to have more advanced functions to meet the requirements of smaller contact holes. Therefore, traditional photolithography machines have process limitations when they meet the requirements of directly forming contact hole sizes for technology nodes of 22nm and below; and advanced photolithography machines are very expensive, becoming a bottleneck restricting process development.

[0003] Therefore, a new method needs to be proposed to solve the above problems. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for improving the contact hole size of an FDSOI device, so as to solve the problem in the prior art that traditional lithography machines cannot meet the process requirements of smaller contact holes in advanced processes.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a method for improving the contact hole size of an FDSOI device, the method comprising at least the following steps:

[0006] Step 1, providing a semiconductor structure for forming an FDSOI device, wherein the semiconductor structure at least includes a source / drain region and a gate of an NMOS region; a source / drain region and a gate of a PMOS region; and the source / drain region and the gate are covered with a silicon oxide layer;

[0007] Step 2: etching the silicon oxide layer on the source and drain regions of the NMOS region and the PMOS region to form source and drain contact holes;

[0008] Step 3, removing byproducts generated by etching the source-drain contact holes on the semiconductor structure;

[0009] Step 4: forming a first oxide film layer on the semiconductor structure, wherein the bottom and sidewalls of the source-drain contact holes are covered by the first oxide film layer;

[0010] Step 5: etching and removing the first oxide film layer on the upper surface of the semiconductor structure and the bottom of the source-drain contact hole, and retaining the first oxide film layer on the sidewall of the source-drain contact hole;

[0011] Step 6: Cleaning the semiconductor structure to remove byproducts generated by etching the first oxide film layer;

[0012] Step 7: depositing metal on the semiconductor structure to fill the source-drain contact holes, and then flattening the surface of the semiconductor structure to adjust the depth of the source-drain contact holes;

[0013] Step 8: etching the silicon oxide layer on the gates of the NMOS region and the PMOS region to form gate contact holes;

[0014] Step nine, removing byproducts generated by etching the gate contact hole on the semiconductor structure;

[0015] Step 10: forming a second oxide film layer on the semiconductor structure, wherein the bottom and sidewalls of the gate contact hole are covered by the second oxide film layer;

[0016] Step 11: etching and removing the second oxide film layer on the semiconductor structure and at the bottom of the gate contact hole, and retaining the second oxide film layer on the sidewall of the gate contact hole;

[0017] Step 12: cleaning the semiconductor structure to remove byproducts generated by etching the second oxide film layer;

[0018] Step 13: depositing metal on the semiconductor structure to fill the gate contact hole, and then planarizing the surface of the semiconductor structure to adjust the depth of the gate contact hole.

[0019] Preferably, the NMOS region also includes: a P-type silicon substrate, an oxide layer located on the P-type silicon substrate, a first silicon layer located on the oxide layer, the gate of the NMOS region is located on the first silicon layer, and the source and drain regions of the NMOS region are respectively located on both sides of the gate of the NMOS region; the PMOS region also includes an N-type silicon substrate, an oxide layer located on the N-type silicon substrate, a first silicon layer located on the oxide layer, the gate of the PMOS region is located on the first silicon layer, and the source and drain regions of the PMOS region are respectively located on both sides of the gate of the PMOS region.

[0020] Preferably, B ions are implanted into the P-type silicon substrate of the NMOS region; and P ions are implanted into the N-type silicon substrate of the PMOS region.

[0021] Preferably, the source and drain regions of the NMOS region include: a second silicon layer and a metal silicide located on the second silicon layer; the source and drain regions of the PMOS region include: a SiGe layer and a metal silicide located on the SiGe layer.

[0022] Preferably, in step 2, the silicon oxide layer on the source and drain regions of the NMOS region and the PMOS region is etched until the metal silicide is exposed, thereby forming the source and drain contact holes.

[0023] Preferably, in step three, a wet cleaning method is used to remove byproducts generated by etching the source-drain contact holes on the semiconductor structure; the byproducts include organic matter and tiny particles.

[0024] Preferably, in step four, the first oxide film layer is grown on the semiconductor structure using an atomic layer deposition method.

[0025] Preferably, the thickness of the first oxide film layer grown in step 4 is to

[0026] Preferably, in step five, a dry etching method is used to remove the first oxide film layer on the upper surface of the semiconductor structure and the bottom of the source-drain contact hole.

[0027] Preferably, in step six, a wet cleaning method is used to remove byproducts generated by etching the first oxide film layer, wherein the byproducts include organic matter and tiny particles.

[0028] Preferably, the metal deposited on the semiconductor structure in step seven is tungsten.

[0029] Preferably, in step nine, a wet cleaning method is used to remove byproducts generated by etching to form the gate, wherein the byproducts include organic matter and tiny particles.

[0030] Preferably, in step ten, an atomic layer deposition method is used to grow and form the second oxide film layer on the semiconductor structure.

[0031] Preferably, the thickness of the first oxide film layer grown in step 10 is to

[0032] Preferably, in step eleven, a dry etching method is used to remove the second oxide film layer on the semiconductor structure and at the bottom of the gate contact hole.

[0033] Preferably, in step twelve, a wet cleaning method is used to remove byproducts generated by etching the second oxide film layer, wherein the byproducts include organic matter and tiny particles.

[0034] Preferably, the metal deposited on the semiconductor structure in step thirteen is tungsten.

[0035] As described above, the method of improving the contact hole size of the FDSOI device of the present invention has the following beneficial effects: the present invention is applied to the 22nm and below FDSOI CMOS semiconductor device process. Compared with the traditional FDSOI process, before the through hole is filled with metal, a layer of oxide film is grown on the side wall of the through hole after the through hole etching process is completed, and then the oxide film layer on the upper surface of the gate is removed by etching, thereby adjusting the size of the through hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a schematic diagram of the structure after etching to form source-drain contact holes in the present invention;

[0037] Figure 2 Shown is a schematic diagram of the gate enlarged structure of the NMOS region in the present invention;

[0038] Figure 3 Shown is a schematic diagram of the gate enlarged structure of the PMOS region in the present invention;

[0039] Figure 4 It is a schematic diagram showing the structure after a first oxide film layer is formed on the semiconductor structure in the present invention;

[0040] Figure 5 It is a schematic diagram of the structure after the first oxide film layer is formed on the side wall of the source-drain contact hole in the present invention;

[0041] Figure 6 It is a schematic diagram of the structure after the source-drain contact holes are filled with metal in the present invention;

[0042] Figure 7 It is a schematic diagram of the structure after etching to form a gate contact hole in the present invention;

[0043] Figure 8 It is a schematic diagram of the structure after a second oxide film layer is formed on the semiconductor structure in the present invention;

[0044] Fig. 9 It is a schematic diagram of the structure after the second oxide film layer is formed on the side wall of the gate contact hole in the present invention. DETAILED DESCRIPTION

[0045] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0046] See also Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0047] The present invention provides a method for improving the contact hole size of an FDSOI device, the method comprising at least the following steps:

[0048] Step 1, providing a semiconductor structure for forming an FDSOI device, wherein the semiconductor structure at least includes a source / drain region and a gate of an NMOS region; a source / drain region and a gate of a PMOS region; and the source / drain region and the gate are covered with a silicon oxide layer;

[0049] The present invention further, as Figure 1 As shown, the NMOS region in step one also includes: a P-type silicon substrate 01, an oxide layer 03 located on the P-type silicon substrate 01, a first silicon layer 04 located on the oxide layer 03, a gate 14 of the NMOS region located on the first silicon layer 04, and source and drain regions of the NMOS region are respectively located on both sides of the gate 14 of the NMOS region; the PMOS region also includes an N-type silicon substrate 02, an oxide layer 03' located on the N-type silicon substrate 02, a first silicon layer 04' located on the oxide layer 03', a gate 15 of the PMOS region is located on the first silicon layer 04', and source and drain regions of the PMOS region are respectively located on both sides of the gate 15 of the PMOS region.

[0050] Figure 2 The enlarged structural diagram of the gate 14 of the NMOS region is shown, and the gate 14 includes: a first silicon oxide structure 17, an HFO layer 18 located on the first silicon oxide structure 17, a TiN layer 19 located on the HFO layer 18, a TaN groove 20 located on the TiN layer 19, a TiAL groove 21 located in the TaN groove 20, metal aluminum 22 filled in the TiAL groove 21, a SiCN layer 23 located outside the first silicon oxide structure 17, the HFO layer 18, the TiN layer 19 and the TaN groove 20, and a second silicon oxide structure 24 located outside the SiCN layer 23.

[0051] Figure 3The enlarged structure schematic diagram of the gate 15 of the PMOS region is shown, and the gate 15 includes: a third silicon oxide structure 25, an HFO layer 26 located on the third silicon oxide structure 25, a TiN layer 27 located on the HFO layer 26, a TaN groove 28 located on the TiN layer 27, a TiN groove 29 located in the TaN groove 28, a TiAL groove 30 located in the TiN groove 29, a metal aluminum 31 filled in the TiAL groove 30, a SiCN layer 32 located outside the third silicon oxide structure 25, the HFO layer 26, the TiN layer 27 and the TaN groove 28, a fourth silicon oxide structure 33 located outside the SiCN layer 32, and a SiN layer 34 attached to the fourth silicon oxide structure 33, wherein the SiN layer 34 and the SiN layer 07 outside the source and drain regions are formed in the same process.

[0052] Depend on Figure 1 It can be seen that the NMOS region and the PMOS region are isolated by the STI region 11 , and a SiN layer 16 is provided on the STI region. The SiN layer 16 is formed in the same process as the SiN layer 34 and the SiN layer 07 .

[0053] In the present invention, further, in step one, B (boron) ions are implanted into the P-type silicon substrate 01 of the NMOS region; and P (phosphorus) ions are implanted into the N-type silicon substrate 02 of the PMOS region.

[0054] In this embodiment, the source and drain regions of the NMOS region in step 1 include: a second silicon layer 05 and a metal silicide 06 located on the second silicon layer 05. In this embodiment, the metal silicide 06 is NiSi. The source and drain regions of the PMOS region include: a SiGe layer 12 and a metal silicide 13 located on the SiGe layer 12.

[0055] Step 2: etching the silicon oxide layer on the source and drain regions of the NMOS region and the PMOS region to form source and drain contact holes; further, in step 2, etching the silicon oxide layer on the source and drain regions of the NMOS region and the PMOS region until the metal silicide is exposed to form the source and drain contact holes. Figure 1 As shown, the silicon oxide layers located on the NMOS region and the PMOS region include 08, 09, and 10, and the silicon oxide layers 08, 09, and 10 are formed on the NMOS region and the PMOS region three times. In step 2, the silicon oxide layers (08-10) on the source and drain regions of the NMOS region and the PMOS region are etched until the metal silicide 06 on the NMOS region and the metal silicide 13 on the source and drain regions of the PMOS region are exposed, thereby forming source and drain contact holes A.

[0056] Step three, removing byproducts generated by etching the source-drain contact holes on the semiconductor structure; further, in step three, a wet cleaning method is used to remove byproducts generated by etching the source-drain contact holes on the semiconductor structure; the byproducts include organic matter and tiny particles.

[0057] Step 4: forming a first oxide film layer on the semiconductor structure, wherein the bottom and sidewalls of the source-drain contact holes are covered by the first oxide film layer; Figure 4 As shown, the first oxide film layer 35 covers the sidewalls of the source-drain contact hole A (ie, the sidewalls of the silicon oxide layers 08-10), and covers the upper surface of the remaining silicon oxide layers (08-10).

[0058] Furthermore, in step 4, the first oxide film layer 35 is grown on the semiconductor structure by using atomic layer deposition (ALD). The thickness of the first oxide film layer 35 grown in step 4 is to By growing the first oxide film layer 35 on the sidewall of the source-drain contact hole A and adjusting its thickness, the required size of the source-drain contact hole A can be obtained.

[0059] Step 5: etching and removing the first oxide film layer on the upper surface of the semiconductor structure and the bottom of the source-drain contact hole, and retaining the first oxide film layer on the sidewall of the source-drain contact hole; Figure 5 As shown, step five etches the upper surface of the semiconductor structure (i.e., the first oxide film layer 35 located on the upper surface of the silicon oxide layer 10) and the first oxide film layer 35 at the bottom of the source-drain contact hole A to expose the metal silicide 06 and metal silicide 13 in the source-drain region of the NMOS region and the PMOS region, while the first oxide film layer 35 on the side wall of the source-drain contact hole A is retained.

[0060] Furthermore, in step five, a dry etching method is used to remove the first oxide film layer on the upper surface of the semiconductor structure and the bottom of the source-drain contact hole.

[0061] Step six, cleaning the semiconductor structure to remove byproducts generated by etching the first oxide film layer; further, in step six, a wet cleaning method is used to remove byproducts generated by etching the first oxide film layer, wherein the byproducts include organic matter and tiny particles.

[0062] Step 7: depositing metal on the semiconductor structure to fill the source-drain contact holes, and then flattening the surface of the semiconductor structure to adjust the depth of the source-drain contact holes; further, the metal deposited on the semiconductor structure in step 7 is tungsten. Figure 6 As shown, Figure 6 It is a schematic diagram of a semiconductor structure after metal tungsten is filled in the source-drain contact hole in the present invention. The source-drain contact hole AA filled with metal tungsten forms contact with the metal silicide.

[0063] Step eight, etching the silicon oxide layer on the gates of the NMOS region and the PMOS region to form gate contact holes; Figure 7 As shown, the silicon oxide layers 08 to 10 on the gate 14 of the NMOS region and the gate 15 of the PMOS region are etched to form gate contact holes B exposing the tops of the gates 14 and 15 .

[0064] Step nine, removing byproducts generated by etching the gate contact hole on the semiconductor structure; further, in step nine, a wet cleaning method is used to remove byproducts generated by etching the gate, and the byproducts include organic matter and tiny particles.

[0065] Step 10: forming a second oxide film layer on the semiconductor structure, wherein the bottom and sidewalls of the gate contact hole are covered by the second oxide film layer; further, in step 10, the second oxide film layer is grown on the semiconductor structure by atomic layer deposition. Further, the thickness of the first oxide film layer grown in step 10 is to like Figure 8 As shown, in this embodiment, the second oxide film layer 36 grown on the semiconductor structure in step ten covers the sidewalls of the gate contact hole B and the upper surface of the semiconductor structure.

[0066] Step 11: etching and removing the second oxide film layer on the semiconductor structure and at the bottom of the gate contact hole, and retaining the second oxide film layer on the sidewall of the gate contact hole; further, in step 11, a dry etching method is used to remove the second oxide film layer on the semiconductor structure and at the bottom of the gate contact hole. Fig. 9 As shown, in this embodiment, the step eleven uses dry etching to remove the second oxide film layer 36 at the bottom of the gate contact hole B and the upper surface of the semiconductor structure, leaving the second oxide film layer 36 on the side wall of the gate contact hole B, and the bottom of the gate contact hole B, the gate 14 of the NMOS region and the gate 15 of the PMOS region are exposed.

[0067] Step twelve, cleaning the semiconductor structure to remove byproducts generated by etching the second oxide film layer; further, in step twelve, a wet cleaning method is used to remove byproducts generated by etching the second oxide film layer, wherein the byproducts include organic matter and tiny particles.

[0068] Step 13: depositing metal on the semiconductor structure to fill the gate contact hole, and then planarizing the surface of the semiconductor structure to adjust the depth of the gate contact hole. Further, in step 13, the metal deposited on the semiconductor structure is tungsten.

[0069] In summary, the present invention is applied to 22nm and below FDSOI CMOS semiconductor device processes. Compared with the traditional FDSOI process, the present invention grows an oxide film layer on the side wall of the through hole before the through hole is filled with metal and after the through hole etching process is completed, and then removes the oxide film layer on the upper surface of the gate by etching, thereby adjusting the size of the through hole. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0070] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for improving the contact hole size of a FDSOI device, characterized in that: The method comprises at least the following steps: Step 1, providing a semiconductor structure for forming an FDSOI device, wherein the semiconductor structure at least includes a source / drain region and a gate of an NMOS region; a source / drain region and a gate of a PMOS region; and the source / drain region and the gate are covered with a silicon oxide layer; Step 2: etching the silicon oxide layer on the source and drain regions of the NMOS region and the PMOS region to form source and drain contact holes; Step 3, removing byproducts generated by etching the source-drain contact holes on the semiconductor structure; Step 4: forming a first oxide film layer on the semiconductor structure, wherein the bottom and sidewalls of the source-drain contact holes are covered by the first oxide film layer; Step 5: etching and removing the first oxide film layer on the upper surface of the semiconductor structure and the bottom of the source-drain contact hole, and retaining the first oxide film layer on the sidewall of the source-drain contact hole; Step 6: Cleaning the semiconductor structure to remove byproducts generated by etching the first oxide film layer; Step 7: depositing metal on the semiconductor structure to fill the source-drain contact holes, and then flattening the surface of the semiconductor structure to adjust the depth of the source-drain contact holes; Step 8: etching the silicon oxide layer on the gates of the NMOS region and the PMOS region to form gate contact holes; Step nine, removing byproducts generated by etching the gate contact hole on the semiconductor structure; Step 10: forming a second oxide film layer on the semiconductor structure, wherein the bottom and sidewalls of the gate contact hole are covered by the second oxide film layer; Step 11: etching and removing the second oxide film layer on the semiconductor structure and at the bottom of the gate contact hole, and retaining the second oxide film layer on the sidewall of the gate contact hole; Step 12: cleaning the semiconductor structure to remove byproducts generated by etching the second oxide film layer; Step 13: depositing metal on the semiconductor structure to fill the gate contact hole, and then planarizing the surface of the semiconductor structure to adjust the depth of the gate contact hole.

2. The method for improving the contact hole size of a FDSOI device according to claim 1, characterized in that: The NMOS region in step one also includes: a P-type silicon substrate, an oxide layer located on the P-type silicon substrate, a first silicon layer located on the oxide layer, the gate of the NMOS region is located on the first silicon layer, and the source and drain regions of the NMOS region are respectively located on both sides of the gate of the NMOS region; the PMOS region also includes an N-type silicon substrate, an oxide layer located on the N-type silicon substrate, a first silicon layer located on the oxide layer, the gate of the PMOS region is located on the first silicon layer, and the source and drain regions of the PMOS region are respectively located on both sides of the gate of the PMOS region.

3. The method for improving the contact hole size of a FDSOI device according to claim 2, characterized in that: In step 1, B ions are implanted into the P-type silicon substrate of the NMOS region; and P ions are implanted into the N-type silicon substrate of the PMOS region.

4. The method for improving the contact hole size of a FDSOI device according to claim 3, characterized in that: The source and drain regions of the NMOS region in step 1 include: a second silicon layer and a metal silicide located on the second silicon layer; the source and drain regions of the PMOS region include: a SiGe layer and a metal silicide located on the SiGe layer.

5. The method for improving the contact hole size of a FDSOI device according to claim 1, characterized in that: In step 2, the silicon oxide layer on the source and drain regions of the NMOS region and the PMOS region is etched until the metal silicide is exposed, thereby forming the source and drain contact holes.

6. The method for improving the contact hole size of a FDSOI device according to claim 1, characterized in that: In step three, a wet cleaning method is used to remove byproducts generated by etching the source-drain contact holes on the semiconductor structure; the byproducts include organic matter and tiny particles.

7. The method for improving the contact hole size of a FDSOI device according to claim 1, characterized in that: In step 4, the first oxide film layer is grown on the semiconductor structure using an atomic layer deposition method.

8. The method for improving the contact hole size of a FDSOI device according to claim 7, characterized in that: The thickness of the first oxide film layer grown in step 4 is to 9. The method for improving the contact hole size of a FDSOI device according to claim 1, characterized in that: In step five, a dry etching method is used to remove the first oxide film layer on the upper surface of the semiconductor structure and the bottom of the source-drain contact hole.

10. The method for improving the contact hole size of a FDSOI device according to claim 1, characterized in that: In step six, a wet cleaning method is used to remove byproducts generated by etching the first oxide film layer, wherein the byproducts include organic matter and tiny particles.

11. The method for improving the contact hole size of a FDSOI device according to claim 1, characterized in that: The metal deposited on the semiconductor structure in step seven is tungsten.

12. The method for improving the contact hole size of a FDSOI device according to claim 1, characterized in that: In step nine, a wet cleaning method is used to remove byproducts generated by etching to form the gate, wherein the byproducts include organic matter and tiny particles.

13. The method for improving the contact hole size of a FDSOI device according to claim 1, characterized in that: In step ten, the second oxide film layer is grown on the semiconductor structure by using an atomic layer deposition method.

14. The method for improving the contact hole size of a FDSOI device according to claim 13, characterized in that: The thickness of the first oxide film layer grown in step 10 is to 15. The method for improving the contact hole size of a FDSOI device according to claim 1, characterized in that: In step eleven, the second oxide film layer on the semiconductor structure and at the bottom of the gate contact hole is removed by dry etching.

16. The method for improving the contact hole size of a FDSOI device according to claim 1, characterized in that: In step 12, a wet cleaning method is used to remove byproducts generated by etching the second oxide film layer, wherein the byproducts include organic matter and tiny particles.

17. The method for improving the contact hole size of a FDSOI device according to claim 1, characterized in that: The metal deposited on the semiconductor structure in step thirteen is tungsten.

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