Device chips and their manufacturing methods, packaging structures and their manufacturing methods

Abstract

This invention provides a device chip comprising: a substrate structure having at least one thermally conductive via structure formed on its bottom, each thermally conductive via structure including a first blind via formed on the bottom of the substrate structure and a first thermally conductive material filled within the first blind via; and at least one device unit formed on the substrate structure. Accordingly, this invention also provides a method for manufacturing the device chip, and a packaging structure formed based on the device chip and a method for manufacturing the same. This invention is advantageous for improving the heat dissipation performance of the packaging structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a device chip and its manufacturing method, as well as a packaging structure and its manufacturing method. Background Technology

[0002] Please refer to Figure 1 , Figure 1 This is a cross-sectional schematic diagram of a common flip-chip packaging structure in the prior art. As shown in the figure, the flip-chip packaging structure includes an FBAR device chip, a cap, a sealing ring 30, a packaging substrate, and a molding compound 50. The FBAR device chip includes a substrate 10, a resonant device located on the substrate 10, and a cavity 11 located between the substrate 10 and the resonant device. The resonant device sequentially includes a lower electrode 12, a piezoelectric layer 13, and an upper electrode 14. The cap includes a body 20, a via structure 21 formed within the body 20, and solder balls 22 formed on the back side of the body 20. The sealing ring 30 is formed between the FBAR device chip and the cap, forming a sealing structure with the FBAR device chip and the cap. The resonant device on the FBAR device chip is located in the cavity 31 of the sealing structure. The packaging substrate includes a body 40, a front pad 41, a back pad 42, and a via structure 43 electrically connecting the front pad 41 and the back pad 42. The solder balls 22 on the back of the cap are soldered to the solder pads 41 on the front of the packaging substrate, thereby connecting the sealing structure to the packaging substrate. The molding compound 50 is formed on the outer surface of the sealing structure to encapsulate it.

[0003] The resonant devices in the FBAR chip generate heat during operation, making them the heat-generating components of the aforementioned flip-chip structure. This heat is primarily transferred to the outside of the package through the substrate. Existing substrates are mainly made of insulating or semiconductor materials (such as Si, SiO2, SiN, AlN, SiC, etc.). Due to the poor thermal conductivity of these materials, the existing flip-chip structures often fail to achieve efficient heat dissipation. Inefficient heat dissipation leads to high temperatures in the heat-generating components, reducing the flip-chip's lifespan, reliability, and power handling capacity. In severe cases, it can even cause the physical structure of the flip-chip to crack or burn out. Summary of the Invention

[0004] To overcome the above-mentioned deficiencies in the prior art, the present invention provides a device chip, the device chip comprising:

[0005] A substrate structure having at least one thermally conductive hole structure formed on its bottom, each of the thermally conductive hole structures including a first blind hole formed on the bottom of the substrate structure and a first thermally conductive material filled in the first blind hole.

[0006] At least one device unit is formed on the substrate structure.

[0007] According to one aspect of the present invention, in the device chip, each of the device units consists of a lower electrode, a piezoelectric layer and an upper electrode from bottom to top, and an acoustic reflection structure is formed between each of the device units and the substrate structure.

[0008] According to another aspect of the present invention, in the device chip, the substrate structure comprises, from bottom to top, a first substrate layer and a second substrate layer; the first substrate layer has at least one through-hole formed in the thickness direction, the at least one through-hole and the bottom surface of the second substrate forming the first blind hole; the at least one through-hole is filled with the first thermally conductive material.

[0009] According to another aspect of the invention, in the device chip, the substrate structure further includes a third substrate layer formed between the first substrate layer and the second substrate layer, the material of the third substrate layer being a second thermally conductive material.

[0010] According to another aspect of the present invention, in the device chip, the thermal conductivity of the second substrate material is greater than or equal to the thermal conductivity of the first substrate material; the thermal conductivity of the first thermally conductive material and the second thermally conductive material is greater than the thermal conductivity of the first substrate material.

[0011] According to another aspect of the invention, in the device chip, the ratio of the sum of the projected areas of the thermally conductive hole structures in the horizontal direction to the projected area of ​​the device chip in the horizontal direction is in the range of 30% to 90%.

[0012] According to another aspect of the present invention, in the device chip, the first substrate layer includes a core region corresponding to each of the device units, each core region being located below the corresponding device unit; the region of the first substrate layer other than the core region is a non-core region; wherein the distribution density of the thermally conductive hole structure in the core region is greater than the distribution density of the thermally conductive hole structure in the non-core region.

[0013] According to another aspect of the invention, in the device chip, the projected edge of each device unit in the horizontal direction and the projected edge of the core region located below it in the horizontal direction form an annular shape, the width of the annular shape being less than or equal to 100 μm.

[0014] According to another aspect of the present invention, in the device chip, when the number of the thermally conductive hole structures is greater than or equal to two, a first interconnect structure is also formed on the first substrate layer. The first interconnect structure is formed in a groove on the upper surface of the first substrate layer and interconnects the first thermally conductive materials in the thermally conductive hole structures.

[0015] According to another aspect of the present invention, in the device chip, when the number of device units is greater than or equal to two, the third substrate layer includes a thermally conductive region corresponding to each device unit and a second interconnect structure, wherein each of the thermally conductive regions is located below the corresponding device unit, and the second interconnect structure interconnects the thermally conductive regions.

[0016] According to another aspect of the invention, in the device chip, the ratio of the projected area of ​​the third substrate layer in the horizontal direction to the projected area of ​​the device chip in the horizontal direction is in the range of 30% to 90%; and there is an overlapping area between the projection of each thermally conductive region in the horizontal direction and the projection of the corresponding device unit in the horizontal direction, the ratio of the projected area of ​​the overlapping area to the projected area of ​​the corresponding device unit in the horizontal direction is greater than 50%.

[0017] The present invention also provides a method for manufacturing a device chip, the method comprising:

[0018] A substrate structure is formed, wherein at least one thermally conductive hole structure is formed at the bottom of the substrate structure, and each of the thermally conductive hole structures includes a first blind hole formed at the bottom of the substrate structure and a first thermally conductive material filled in the first blind hole.

[0019] At least one device unit is formed on the substrate structure.

[0020] According to one aspect of the invention, in the manufacturing method, each of the device units consists of a lower electrode, a piezoelectric layer, and an upper electrode from bottom to top, and an acoustic reflection structure is formed between each of the device units and the substrate structure.

[0021] According to another aspect of the present invention, in the manufacturing method, the step of forming a substrate structure includes: providing a first substrate layer and forming at least one second blind hole on the upper surface of the first substrate layer; filling the at least one second blind hole with a first thermally conductive material; depositing a second substrate layer on the first substrate layer; and performing a planarization operation on the lower surface of the first substrate layer to expose the first thermally conductive material, thereby forming the substrate structure, wherein the sidewall of the second blind hole and the bottom surface of the second substrate layer constitute the first blind hole.

[0022] According to another aspect of the invention, the step of forming the substrate structure in the manufacturing method further includes: forming a third substrate layer between the first substrate layer and the second substrate layer, wherein the material of the third substrate layer is a second thermally conductive material.

[0023] According to another aspect of the invention, in this manufacturing method, the thermal conductivity of the second substrate material is greater than or equal to the thermal conductivity of the first substrate material; the thermal conductivity of the first thermally conductive material and the second thermally conductive material is greater than the thermal conductivity of the first substrate material.

[0024] According to another aspect of the invention, in this manufacturing method, the ratio of the sum of the projected areas of the heat-conducting hole structure in the horizontal direction to the projected area of ​​the device chip in the horizontal direction is in the range of 30% to 90%.

[0025] According to another aspect of the present invention, in the manufacturing method, the first substrate layer includes a core region corresponding to each of the device units, each core region being located below the corresponding device unit; the region of the first substrate layer other than the core region is a non-core region; wherein the distribution density of the thermally conductive hole structure in the core region is greater than the distribution density of the thermally conductive hole structure in the non-core region.

[0026] According to another aspect of the invention, in the manufacturing method, the projected edge of each device unit in the horizontal direction and the projected edge of the core region located below it in the horizontal direction form an annular shape, the width of which is less than or equal to 100 μm.

[0027] According to another aspect of the present invention, in the manufacturing method, when the number of the thermally conductive hole structures is greater than or equal to two, the step of forming the substrate structure further includes: forming a first interconnect structure on the first substrate layer, the first interconnect structure being formed in a groove on the upper surface of the first substrate layer and interconnecting the first thermally conductive materials within the thermally conductive hole structures.

[0028] According to another aspect of the invention, in the manufacturing method, when the number of device units is greater than or equal to two, the third substrate layer includes a thermally conductive region corresponding to each device unit and a second interconnect structure, wherein each of the thermally conductive regions is located below the corresponding device unit, and the second interconnect structure interconnects the thermally conductive regions.

[0029] According to another aspect of the invention, in this manufacturing method, the ratio of the projected area of ​​the third substrate layer in the horizontal direction to the projected area of ​​the device chip in the horizontal direction is in the range of 30% to 90%; and there is an overlapping area between the projected area of ​​each thermally conductive region in the horizontal direction and the projected area of ​​the corresponding device unit in the horizontal direction, the ratio of the projected area of ​​the overlapping area to the projected area of ​​the corresponding device unit in the horizontal direction is greater than 50%.

[0030] The present invention also provides a packaging structure, the packaging structure comprising:

[0031] The aforementioned device chip;

[0032] A cap, the front of which is positioned opposite to the device chip, and a connecting portion on the back;

[0033] A sealing ring is disposed between the device chip and the cap, forming a sealing structure with the device chip and the cap, and the at least one device unit is located within the cavity of the sealing structure;

[0034] The encapsulation substrate, wherein the sealing structure is connected to the encapsulation substrate via the connecting portion;

[0035] A molding compound that encapsulates the sealing structure.

[0036] The present invention also provides a method for manufacturing a packaging structure, the method comprising:

[0037] Provide the aforementioned device chip or form the device chip using the aforementioned manufacturing method;

[0038] A cap is provided, the front of which is positioned opposite the device chip;

[0039] A sealing ring is formed between the device chip and the cap, the sealing ring forming a sealing structure with the device chip and the cap, and the at least one device unit is located within the cavity of the sealing structure;

[0040] A connecting portion is formed on the back of the cap, and the sealing structure is connected to the packaging substrate through the connecting portion;

[0041] A plastic encapsulation is formed to encapsulate the sealing structure.

[0042] The device chip provided by this invention has a thermally conductive hole structure made of a high thermal conductivity material formed at the bottom of its substrate structure. In this way, after the device chip is packaged to form a package structure, the heat generated by the operation of the device unit in the device chip can be efficiently transferred to the outside through the thermally conductive hole structure in the substrate structure while being transferred through the heat dissipation channel on one side of the substrate structure, thereby effectively improving the heat dissipation efficiency of the package structure. The improved heat dissipation efficiency of the package structure helps to reduce the temperature of the device unit, thereby improving the lifespan, reliability, and power handling capacity of the package structure. The heat dissipation effect of this invention is particularly significant when there is a cavity below the device unit. The manufacturing method provided by this invention can produce a device chip with high heat dissipation efficiency. Accordingly, the package structure formed based on the device chip provided by this invention and its manufacturing method can effectively improve the heat dissipation efficiency of the package structure. Attached Figure Description

[0043] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0044] Figure 1 This is a cross-sectional schematic diagram of a common flip-chip structure in existing technology;

[0045] Figure 2 This is a flowchart of a method for manufacturing a device chip according to a specific embodiment of the present invention;

[0046] Figures 3 to 9 This is a cross-sectional schematic diagram of various stages of manufacturing a device chip according to a preferred embodiment of the present invention;

[0047] Figures 10(a) and 10(b-1) are top views of the first substrate layer according to two specific embodiments of the present invention;

[0048] Figures 10(b-2) and 10(b-3) are schematic cross-sectional views of the structure shown in Figure (b-1) along lines AA' and BB', respectively.

[0049] Figure 11 and Figure 12 These are schematic cross-sectional views of a device chip according to two preferred embodiments of the present invention;

[0050] Figures 13(a) and 13(b) are top views of the third substrate layer according to two specific embodiments of the present invention;

[0051] Figure 14 This is a flowchart of a manufacturing method for a packaging structure according to a specific embodiment of the present invention;

[0052] Figures 15 to 19 According to Figure 14The diagram shows cross-sectional views of each stage in the process of forming the encapsulation structure.

[0053] The same or similar reference numerals in the accompanying drawings represent the same or similar parts. Detailed Implementation

[0054] To better understand and explain the present invention, a further detailed description of the invention will be provided below in conjunction with the accompanying drawings.

[0055] This invention provides a device chip, the device chip comprising:

[0056] A substrate structure having at least one thermally conductive hole structure formed on its bottom, each of the thermally conductive hole structures including a first blind hole formed on the bottom of the substrate structure and a first thermally conductive material filled in the first blind hole.

[0057] At least one device unit is formed on the substrate structure.

[0058] The following will describe in detail each component of the above-mentioned device chip with reference to the accompanying drawings.

[0059] Specifically, the device chip provided by the present invention includes a substrate structure, the bottom of which at least one thermally conductive hole structure is formed. In this embodiment, each thermally conductive hole structure includes a blind hole (hereinafter referred to as a first blind hole) formed at the bottom of the substrate structure and a thermally conductive material (hereinafter referred to as a first thermally conductive material) filling the first blind hole. The lower surface of the first thermally conductive material is flush with the lower surface of the substrate structure (in this invention, "flush" means that the height difference between the two is within the allowable range of process tolerance).

[0060] In this embodiment, the depth of the first blind via is less than the thickness of the substrate structure, and correspondingly, the height of the thermally conductive hole structure is less than the thickness of the substrate structure. This invention does not impose any limitations on the thickness of the substrate structure or the height of the thermally conductive hole structure; these can be determined according to actual design requirements. To improve the heat dissipation performance of the substrate structure, preferably, the thickness of the substrate structure does not exceed 100 μm, and the height of the thermally conductive hole structure is greater than 30 μm.

[0061] In this embodiment, the main body of the substrate structure (i.e., the part of the substrate structure excluding the heat-conducting hole structure) can be implemented using conventional substrate materials. For the sake of simplicity, conventional substrate materials will not be listed here. Furthermore, in this embodiment, the thermal conductivity of the first thermally conductive material is higher than that of the material of the main body of the substrate structure. Preferably, the first thermally conductive material is implemented using a high thermal conductivity metallic material, such as one or any combination of Cu, Au, Ag, Al, Ni, Fe, Mo, and W. Those skilled in the art will understand that the first thermally conductive material is not limited to metallic materials. In other embodiments, non-metallic materials with higher thermal conductivity than the main body of the substrate structure are also suitable as the first thermally conductive material. For the sake of simplicity, all possible first thermally conductive materials will not be listed here. It should also be noted that the first thermally conductive material can be a single-crystal material, a polycrystalline material, or a combination of single-crystal and polycrystalline materials; this invention does not impose any limitations on this.

[0062] The device chip provided by this invention further includes at least one device unit formed on a substrate structure. In one specific embodiment, the device unit is a resonant unit, which consists of a lower electrode, a piezoelectric layer, and an upper electrode from bottom to top, and an acoustic reflection structure for acoustic wave reflection is formed between each resonant unit and the substrate structure. For example, the acoustic reflection structure can be a cavity, a Bragg reflector layer, etc. Each resonant unit, the acoustic reflection structure below it, and the substrate constitute a bulk acoustic wave resonator. Accordingly, the device chip can be a bulk acoustic wave filter chip, a duplexer chip, or a multiplexer chip. Those skilled in the art will understand that the device unit and the device chip are not limited to the above illustrative examples; all device units that can be formed on the substrate structure fall within the protection scope of this invention. For the sake of brevity, not all possible device units will be listed here. Furthermore, it should be noted that the specific number of device units is determined by the actual design requirements of the device chip, and this invention does not impose any limitations on this.

[0063] The device chip provided by this invention has a thermally conductive hole structure made of a high thermal conductivity material formed at the bottom of its substrate structure. In this way, after the device chip is packaged to form a package structure, the heat generated by the operation of the device unit in the chip, while being transferred through the heat dissipation channel on one side of the substrate structure, can be efficiently transferred to the outside through the thermally conductive hole structure in the substrate structure, thereby effectively improving the heat dissipation efficiency of the package structure. The improved heat dissipation efficiency of the package structure helps to reduce the temperature of the device unit, thereby improving the lifespan, reliability, and power handling capacity of the package structure. This is particularly suitable for situations where there is a cavity beneath the device unit.

[0064] The following will combine Figure 9The device chip provided by the present invention will be described with reference to a preferred embodiment.

[0065] like Figure 9 As shown, the device chip provided by the present invention has a substrate structure that, from bottom to top, includes a first substrate layer 100 and a second substrate layer 105.

[0066] In this embodiment, the material of the first substrate layer 100 is an insulating material or a semiconductor material, such as one or any combination of Si, SiO2, SiN, AlN, SiC, and sapphire. Those skilled in the art will understand that the above-mentioned Si, SiO2, SiN, AlN, SiC, and sapphire are merely illustrative examples; all existing and future suitable substrate materials are applicable to the first substrate layer of this invention. For the sake of simplicity, not all possible materials for the first substrate layer will be listed here. When the material of the first substrate layer 100 is a semiconductor material, it is preferable that the resistivity of the semiconductor material is greater than 2000 Ω·cm. Furthermore, the thickness of the first substrate layer 100 is preferably in the range of 30 μm to 100 μm.

[0067] In this embodiment, the material of the second substrate layer 105 is an insulating or semiconductor material with high thermal conductivity, which is greater than that of the first substrate layer 100. Examples include one or any combination of Si, AlN, SiC, diamond, graphite, GaN, and quartz. Those skilled in the art will understand that the above-mentioned Si, AlN, SiC, diamond, graphite, GaN, and quartz are merely illustrative examples, and the actual selection of the material of the second substrate layer 105 depends on the material of the first substrate layer 100. Wherein, when the material of the second substrate layer 105 is a semiconductor material, it is preferable that the resistivity of the semiconductor material is greater than 2000 Ω·cm. Furthermore, the thickness range of the second substrate layer 105 is preferably from 3 μm to 10 μm.

[0068] In this embodiment, a heat-conducting hole structure is formed in the first substrate layer 100. Specifically, the first substrate layer 100 has at least one through-hole extending through it in the thickness direction, and the at least one through-hole is filled with a first thermally conductive material 103. The upper and lower surfaces of the first thermally conductive material 103 are flush with the upper and lower surfaces of the first substrate layer 100, respectively. For any through-hole, it, together with the bottom surface of the second substrate layer 105 located at its upper opening, forms a first blind hole, and together with the first thermally conductive material 103 filled in the through-hole, further constitutes a heat-conducting hole structure. Since the thickness of the heat-conducting hole structure is the same as that of the first substrate layer 100, the height range of the heat-conducting hole structure is preferably 30 μm to 100 μm.

[0069] In this embodiment, the thermal conductivity of the first thermally conductive material 103 is higher than that of the first substrate 100 material. In this embodiment, the first thermally conductive material 103 is preferably a metallic material with high thermal conductivity, such as one or any combination of Cu, Au, Ag, Al, Ni, Fe, Mo, and W. Of course, the first thermally conductive material can also be a non-metallic material with a thermal conductivity higher than that of the first substrate 100.

[0070] Preferably, such as Figure 9 As shown, an adhesion layer 102 is also formed between the first substrate layer 100 and the first thermally conductive material 103. The adhesion layer 102 is made of a metallic material with good adhesion, preferably one of Ti, TiW, and Cr, or any combination thereof. The thickness of the adhesion layer 102 is preferably in the range of 0.1 μm to 0.5 μm. The function of the adhesion layer 102 is, on the one hand, to improve the adhesion between the first thermally conductive material 103 and the first substrate layer 100, and on the other hand, to prevent the diffusion of atoms from the first thermally conductive material 103 into the first substrate layer 100.

[0071] Preferably, a seed layer (not shown) is further formed between the adhesion layer 102 and the first thermally conductive material 103. In this embodiment, the material of the seed layer is the same as that of the first thermally conductive material 103.

[0072] The device chip provided by this invention further includes at least one device unit formed on the substrate structure. For example... Figure 9 As shown, in this embodiment, all device units are resonant units. Each resonant unit includes a lower electrode 107a, a piezoelectric layer 108, and an upper electrode 109 from bottom to top. A cavity 106 is formed between each resonant unit and the substrate structure. It should be noted that (1) the cavity 106 is formed within the second substrate layer 105, therefore its depth is less than or equal to the thickness of the second substrate layer 105; (2) actual device chips often include multiple device units. For the sake of simplicity, only one device unit is used here. Figure 9 A device unit is shown for illustration, while other device units and the connection relationships between device units are omitted. (3) Typically, in addition to the lower electrode 107a, the device chip often forms a connection part (the part circled in dashed circle) connected to the lower electrode, which is used to bring out the signals of the device unit during subsequent packaging or for electrical connection between device units. (4) Figure 9 The portion marked 107b in the attached figure is formed at the edge of the substrate structure (i.e., on the outside of the device unit), and a subsequent sealing ring is formed on this portion.

[0073] After the device chip is packaged to form a package structure, the heat generated by the device units in the device chip is transferred to the outside through heat dissipation channels on one side of the substrate structure. Based on the device chip provided in this embodiment, its substrate structure consists of a second substrate layer 105 and a first substrate layer 100 from top to bottom. A heat-conducting hole structure penetrating the first substrate layer 100 in the thickness direction is formed in the first substrate layer 100. The thermal conductivity of the material of the second substrate layer 105 is greater than that of the material of the first substrate layer 100, which is beneficial for the efficient transfer of heat generated by the device units to the first substrate layer 100. The thermal conductivity of the heat-conducting hole structure in the first substrate layer 100 is greater than that of the material of the first substrate layer 100, which is beneficial for the efficient transfer of heat transferred to the first substrate layer 100 to the outside of the package structure through the heat-conducting hole structure. In this way, a low thermal resistance and high thermal conductivity heat dissipation channel is provided for the device units in the package structure on one side of the substrate structure. Compared to a single-layer substrate structure (i.e., where all parts of the substrate except for the heat-conducting holes are made of the same substrate material), in this embodiment, the substrate structure is configured as a two-layer structure along the heat dissipation channel direction, consisting of a second substrate layer 105 and a first substrate layer 100, and the thermal conductivity of the second substrate layer 105 is greater than that of the first substrate layer 100. This further improves the heat dissipation efficiency of the packaging structure. Of course, those skilled in the art will understand that in other embodiments, the thermal conductivity of the second substrate layer 105 may also be equal to that of the first substrate layer 100.

[0074] This invention does not limit the specific shape of the heat-conducting hole structure. For example, its horizontal cross-section can be any regular shape such as a polygon or a circle, or it can be any irregular shape. Please refer to Figure 10(a), which is a top view of the first substrate layer according to a specific embodiment of the present invention, wherein the adhesion layer and the seed layer are omitted. As shown in Figure 10(a), in this embodiment, the cross-section of the heat-conducting hole structure in the horizontal direction is rectangular.

[0075] In this invention, the horizontal projection of all heat-conducting hole structures in the device chip is defined as the first projection, and the area of ​​this first projection is called the first projected area (i.e., the sum of the horizontal projected areas of all heat-conducting hole structures); and the horizontal projection of the device chip is defined as the second projection, and the area of ​​this second projection is called the second projected area. It should be noted that a region is reserved on the device chip to form an annular bonding portion. This annular bonding portion is used for subsequent bonding with the bonding portion of the cap to form a sealing ring, thereby sealing the device unit on the device chip within the sealed space formed by the device chip, the cap, and the sealing ring. The outer edge of the annular bonding portion region on the device chip is defined as the boundary of the device chip, and correspondingly, the horizontal projection of the outer edge of the annular bonding portion region on the device chip is the second horizontal projection of the device chip. To enable effective heat transfer through the heat-conducting hole structure, preferably, the ratio of the first projected area of ​​the heat-conducting hole structure to the second projected area of ​​the device chip is between 30% and 90%.

[0076] Considering that the main heat-generating part of the device chip is the device unit, it is preferable to have a denser distribution of heat-conducting hole structures in the region below the device unit. Specifically, the first substrate layer 100 can be divided into core regions corresponding to the device units, with each core region located below the corresponding device unit. Regions of the first substrate layer 100 other than the core regions are called non-core regions. The distribution density of heat-conducting hole structures in the core regions is greater than that in the non-core regions. In this invention, for each device unit and its corresponding core region, the horizontal projection of the former is defined as the third projection, and the horizontal projection of the latter is defined as the fourth projection. In a specific embodiment, the edges of the third projection and the fourth projection form an annular shape (either the third projection falls within the range of the fourth projection, or vice versa), and the width of this annular shape is less than or equal to 100 μm. It should be noted that, for the case where the device unit is a resonant unit, the third projection of the device unit mainly refers to the horizontal projection of the lower electrode. Furthermore, those skilled in the art will understand that in other embodiments, the thermally conductive hole structure may also be uniformly distributed in the first substrate layer 100 as shown in FIG10(a).

[0077] For cases where the number of heat-conducting hole structures is greater than or equal to two, the first substrate layer of the device chip substrate structure provided by the present invention also forms an interconnect structure (hereinafter referred to as the first interconnect structure). A groove connecting the heat-conducting hole structures is formed on the upper surface of the first substrate layer, and the first interconnect structure is formed within the groove to enable communication between the first thermally conductive materials within the heat-conducting hole structures. Please refer to Figures 10(b-1), 10(b-2), and 10(b-3). Figure 10(b-1) is a top view of the first substrate layer according to a specific embodiment of the present invention. Figures 10(b-2) and 10(b-3) are cross-sectional views along lines AA' and BB', respectively, of the structure shown in Figure (b-1). As shown, the first interconnect structure 103' is embedded in the groove on the upper surface of the first substrate layer 100, and the first thermally conductive materials 103 in each heat-conducting hole structure are interconnected through the first interconnect structure 103'. Those skilled in the art will understand that the first interconnect structure should not be limited to the structure shown in Figure 10(b-1). Any structure that allows heat to be transferred between some or all of the heat-conducting hole structures is applicable to the first interconnect structure in this invention. For the sake of simplicity, not all possible first interconnect structures will be listed here. The presence of the first interconnect structure allows the heat generated by the device unit to be quickly transferred through all the heat-conducting hole structures, thereby further improving heat dissipation efficiency.

[0078] In the device chip provided by this invention, the substrate structure further includes a third substrate layer formed between the first substrate layer and the second substrate layer. This third substrate layer is connected to the first thermally conductive material in the thermally conductive hole structure of the first substrate layer. The material of the third substrate layer is a thermally conductive material (hereinafter referred to as the second thermally conductive material), wherein the thermal conductivity of the second thermally conductive material is greater than that of the material of the first substrate layer. Preferably, a metal material with high thermal conductivity is used, such as one or any combination of Cu, Au, Ag, Al, Ni, Fe, Mo, and W. Of course, the second thermally conductive material can also be a non-metallic material with a higher thermal conductivity than that of the first substrate layer. It should also be noted that the second thermally conductive material can be a single-crystal material, a polycrystalline material, or a combination of single-crystal and polycrystalline materials; this invention does not impose any limitations on this. The presence of the third substrate layer facilitates the transfer of heat from the second substrate layer to the first substrate layer, thereby further improving heat dissipation efficiency. Furthermore, the thickness of the third substrate layer is preferably less than or equal to 50 μm.

[0079] The material of the third substrate layer can be different from that of the first thermally conductive material, such as... Figure 11 As shown, the third substrate layer 104 and the first thermally conductive material 103 in the thermally conductive hole structure are two independent parts. The material of the third substrate layer can also be the same as the first thermally conductive material, such as... Figure 12As shown, the third substrate layer 104 and the first thermally conductive material 103 in the thermally conductive hole structure are integrated into one structure.

[0080] It should be noted that, in the case where a third substrate layer is provided in the substrate structure to achieve efficient heat transfer from the second substrate layer to the first substrate layer, the materials of the first substrate layer and the second substrate layer can be different or the same.

[0081] Figure 11 In the structure shown, the third substrate layer 104 is a single layer. In other embodiments, considering that the main heat-generating part of the device chip is the device unit, it is preferable that the third substrate layer is formed only below the device unit. Therefore, in a preferred embodiment, the third substrate layer includes thermally conductive regions corresponding one-to-one with the device unit, each thermally conductive region being located below its corresponding device unit. For cases where the number of device units is greater than or equal to two, more preferably, the third substrate layer also includes an interconnect structure (hereinafter referred to as the second interconnect structure), which interconnects the thermally conductive regions. Please refer to Figures 13(a) and 13(b). In Figure 13(a), the third substrate layer 104 only includes the thermally conductive regions located below the device units. The figure only schematically shows two device units and the thermally conductive regions located below them, ignoring other components of the device chip. The device unit is a resonant unit, represented by the lower electrode 107 in the figure. In Figure 13(b), the third substrate layer includes a thermally conductive region 104a located below the device unit and a second interconnection structure 104b for interconnecting the thermally conductive region 104a. The figure only schematically illustrates two device units, the thermally conductive regions located below these two device units, and the second interconnection structure, omitting other components of the device chip. The device unit is a resonant unit, represented by the lower electrode 107 in the figure. Those skilled in the art will understand that the thermally conductive region located below the device unit is sheet-like rather than annular. For Figures 13(a) and 13(b), the thermally conductive region is a regular pentagonal region, not an annular region. Furthermore, those skilled in the art will understand that the thermally conductive region and the second interconnection structure are not limited to the structure shown in Figure 13(b). For example, the thermally conductive region can be a polygon other than a regular pentagon, or it can be a circle, or even an irregular shape. For simplicity, all possibilities for the thermally conductive region and the second interconnection structure will not be listed here. The presence of the second interconnect structure allows the heat generated by the device unit to be quickly transferred to the first substrate layer through the third substrate layer, thereby further improving heat dissipation efficiency.

[0082] Furthermore, in this invention, the projection of the third substrate layer in the horizontal direction is defined as the fifth projection, and the area of ​​the fifth projection is called the fifth projection area; and the projection of each heat-conducting region in the third substrate layer in the horizontal direction is defined as the sixth projection, and the area of ​​the fifth projection is called the fifth projection area. To ensure the heat transfer effect of the third substrate layer, in a preferred embodiment, the ratio of the fifth projection area of ​​the third substrate layer to the second projection area of ​​the device chip is in the range of 30% to 90%; and there is an overlapping area between the sixth projection of each heat-conducting region and the third projection of the corresponding device unit, the ratio of the horizontal projection area of ​​the overlapping area to the third projection area of ​​the device unit is greater than 50%.

[0083] This invention also provides a method for manufacturing a device chip. Please refer to [link / reference]. Figure 2 , Figure 2 This is a flowchart of a method for manufacturing a device chip according to a specific embodiment of the present invention. As shown in the figure, the manufacturing method includes:

[0084] In step S101, a substrate structure is formed, and at least one thermally conductive hole structure is formed at the bottom of the substrate structure. Each of the thermally conductive hole structures includes a first blind hole formed at the bottom of the substrate structure and a first thermally conductive material filled in the first blind hole.

[0085] In step S102, at least one device unit is formed on the substrate structure.

[0086] The following is a detailed explanation of steps S101 to S102.

[0087] Specifically, in step S101, a substrate structure is formed, and at least one thermally conductive hole structure is formed on the bottom of the substrate structure. In this embodiment, each thermally conductive hole structure includes a blind hole (hereinafter referred to as a first blind hole) formed on the bottom of the substrate structure and a thermally conductive material (hereinafter referred to as a first thermally conductive material) filling the first blind hole. The lower surface of the first thermally conductive material is flush with the lower surface of the substrate structure.

[0088] There are multiple ways to implement the above-mentioned substrate structure. For example, a substrate can be provided first, then the lower surface of the substrate can be etched to form at least one first blind hole, and finally the first blind hole can be filled with a first thermally conductive material to form a thermally conductive hole structure, thus forming the substrate structure. Those skilled in the art will understand that the above examples are merely illustrative, and any method that can form the above-mentioned substrate structure with a thermally conductive hole at the bottom falls within the protection scope of this invention. For the sake of brevity, all implementations of step S101 will not be described here.

[0089] In this embodiment, the depth of the first blind via is less than the thickness of the substrate structure, and correspondingly, the height of the thermally conductive hole structure is less than the thickness of the substrate structure. This invention does not impose any limitations on the thickness of the substrate structure or the height of the thermally conductive hole structure; these can be determined according to actual design requirements. To improve the heat dissipation performance of the substrate structure, preferably, the thickness of the substrate structure does not exceed 100 μm, and the height of the thermally conductive hole structure is greater than 30 μm.

[0090] In this embodiment, the main body of the substrate structure (i.e., the part of the substrate structure excluding the heat-conducting hole structure) can be implemented using conventional substrate materials. For the sake of simplicity, conventional substrate materials will not be listed here. Furthermore, in this embodiment, the thermal conductivity of the first thermally conductive material is higher than that of the material of the main body of the substrate structure. Preferably, the first thermally conductive material is implemented using a high thermal conductivity metallic material, such as one or any combination of Cu, Au, Ag, Al, Ni, Fe, Mo, and W. Those skilled in the art will understand that the first thermally conductive material is not limited to metallic materials. In other embodiments, non-metallic materials with higher thermal conductivity than the main body of the substrate structure are also suitable as the first thermally conductive material. For the sake of simplicity, all possible first thermally conductive materials will not be listed here. It should also be noted that the first thermally conductive material can be a single-crystal material, a polycrystalline material, or a combination of single-crystal and polycrystalline materials; this invention does not impose any limitations on this.

[0091] In step S102, at least one device unit is formed on the substrate structure. In one specific embodiment, the device unit is a resonant unit, which consists of a lower electrode, a piezoelectric layer, and an upper electrode from bottom to top, and an acoustic reflection structure for acoustic wave reflection is formed between each resonant unit and the substrate structure. For example, the acoustic reflection structure can be a cavity, a Bragg reflector layer, etc. Each resonant unit, the acoustic reflection structure below it, and the substrate constitute a bulk acoustic wave resonator. Correspondingly, the device chip can be a bulk acoustic wave filter chip, a duplexer chip, or a multiplexer chip. Those skilled in the art will understand that the device unit and device chip are not limited to the above illustrative examples; all device units that can be formed on the substrate structure fall within the protection scope of this invention. For the sake of brevity, not all possible device units will be listed here. Furthermore, it should be noted that (1) the specific number of device units is determined by the actual design requirements of the device chip, and this invention does not impose any restrictions on this; (2) this invention mainly focuses on improving the substrate structure in the device chip, so it does not impose any restrictions on how to form device units on the substrate structure. Those skilled in the art can form device units on the substrate structure using existing and future manufacturing methods according to the specific type of device chip. Considering that there are many possibilities for device units and manufacturing methods, all possible formation processes of device units will not be described one by one here.

[0092] The device chip manufacturing method provided by this invention allows for the formation of a thermally conductive hole structure made of a high thermal conductivity material at the bottom of the substrate structure. In this way, after the device chip is packaged to form a package structure, the heat generated by the operation of the device unit within the device chip can be efficiently transferred to the outside through the thermally conductive hole structure in the substrate structure when heat is transferred through the heat dissipation channel on one side of the substrate structure, thereby effectively improving the heat dissipation efficiency of the package structure. The improved heat dissipation efficiency of the package structure helps to reduce the temperature of the device unit, thereby improving the lifespan, reliability, and power handling capacity of the package structure. This is particularly suitable for situations where there is a cavity beneath the device unit.

[0093] The manufacturing method of the device chip provided by the present invention will now be described with reference to the accompanying drawings and a preferred embodiment.

[0094] like Figure 3As shown, a first substrate layer 100 is provided. In this embodiment, the material of the first substrate layer 100 is an insulating material or a semiconductor material, such as one or any combination of Si, SiO2, SiN, AlN, SiC, and sapphire. Those skilled in the art will understand that the above-mentioned Si, SiO2, SiN, AlN, SiC, and sapphire are merely illustrative examples. All existing and future suitable substrate materials are applicable to the first substrate layer of this invention. For the sake of simplicity, not all possible materials for the first substrate layer will be listed here. When the material of the first substrate layer 100 is a semiconductor material, it is preferable that the resistivity of the semiconductor material is greater than 2000 Ω·cm.

[0095] Next, as Figure 4 As shown, the upper surface of the first substrate layer 100 is etched to form at least one blind via 101 (hereinafter referred to as a second blind via) on the first substrate layer 100, wherein the depth of the second blind via is less than the thickness of the first substrate layer 100. Preferably, as Figure 5 As shown, after forming the second blind via 101, an adhesion layer 102 is deposited on the first substrate layer 100. This adhesion layer 102 covers the upper surface of the first substrate layer 100 and the surface of the second blind via 101 (i.e., the sidewalls and bottom surface of the second blind via 101). The adhesion layer 102 is made of a metal material with good adhesion, preferably one of Ti, TiW, and Cr, or any combination thereof. The thickness of the adhesion layer 102 is preferably in the range of 0.1 μm to 0.5 μm. The function of the adhesion layer 102 is, on the one hand, to improve the adhesion between the first thermally conductive material filling the second blind via 101 and the surface of the second blind via 101 in subsequent steps, and on the other hand, to prevent the atomic diffusion of the first thermally conductive material into the first substrate layer 100. The following will be based on... Figure 5 The structure shown illustrates the subsequent steps.

[0096] Next, as Figure 6As shown, a first thermally conductive material 103 is filled in the second blind via 101, and the upper surface of the first thermally conductive material 103 is flush with the upper surface of the first substrate layer 100. The thermal conductivity of the first thermally conductive material 103 is higher than that of the material of the first substrate layer 100. In this embodiment, the first thermally conductive material 103 is preferably a metallic material with high thermal conductivity, such as one or any combination of Cu, Au, Ag, Al, Ni, Fe, Mo, and W. Of course, the first thermally conductive material can also be a non-metallic material with a thermal conductivity higher than that of the first substrate layer 100. It should be noted that filling the blind via with material can be achieved using conventional techniques in the art. The following description only uses the example of the first thermally conductive material 103 being a metallic material. First, a metal layer is formed on the surface of the adhesion layer 102 by electroplating, which fills the second blind via 101. Then, the metal layer on the upper surface of the first substrate layer 100 and the adhesion layer 102 are planarized until the upper surface of the first substrate layer 100 is exposed, leaving only the metal layer portion in the second blind via 101. Preferably, before filling the second blind via 101 with the first thermally conductive material 103, a seed layer (not shown) is deposited on the adhesion layer 102, wherein the material of the seed layer is the same as the first thermally conductive material 103.

[0097] Next, as Figure 7 As shown, a second substrate layer 105 is deposited on the first substrate layer 100. Figure 6 The upper surface of the structure shown is covered. In this embodiment, the material of the second substrate layer 105 is an insulating material or a semiconductor material with high thermal conductivity, which is greater than that of the first substrate layer 100. For example, one or any combination of Si, AlN, SiC, diamond, graphite, GaN, and quartz. Those skilled in the art will understand that the above-mentioned Si, AlN, SiC, diamond, graphite, GaN, and quartz are merely illustrative examples, and the actual selection of the material of the second substrate layer 105 is related to the material of the first substrate layer 100. Wherein, when the material of the second substrate layer 105 is a semiconductor material, it is preferable that the resistivity of the semiconductor material is greater than 2000 Ω·cm. In addition, the thickness range of the second substrate layer 105 is preferably from 3 μm to 10 μm.

[0098] Next, as Figure 8As shown, a planarization operation is performed on the lower surface of the first substrate layer 100 to expose the first thermally conductive material 103 and to ensure that the thickness of the first substrate layer 100 meets the design requirements, thus forming the substrate structure. The sidewall of the second blind via and the bottom surface of the second substrate layer 105 constitute a first blind via formed at the bottom of the substrate structure. This first blind via and the first thermally conductive material 103 filling it together constitute a thermally conductive hole structure. The thickness of the first substrate layer 100 after the planarization operation is preferably between 30 μm and 100 μm. Since the thermally conductive hole structure penetrates the first substrate layer 100 in the thickness direction, the height of the thermally conductive hole structure is the same as the thickness of the first substrate layer 100.

[0099] It should be noted that in this embodiment, the second substrate layer 105 is formed first and then the lower surface of the first substrate layer 100 is planarized. In other embodiments, the lower surface of the first substrate layer 100 may be planarized first and then the second substrate layer 105 may be formed. Alternatively, an acoustic reflection structure and device unit may be formed on the second substrate layer 105 and encapsulated with a matching cap before the lower surface of the first substrate layer 100 is planarized.

[0100] Finally, as Figure 9 As shown, at least one device unit is formed on the substrate structure to obtain a device chip. In this embodiment, all device units are resonant units, and each resonant unit includes a lower electrode 107a, a piezoelectric layer 108 and an upper electrode 109 from bottom to top. A cavity 106 is formed between each resonant unit and the substrate structure. The specific implementation process is as follows: First, the upper surface of the substrate structure (i.e., the upper surface of the second substrate layer 105) is etched to form a groove. Then, the groove is filled with a sacrificial material. Next, the lower electrode 107a, the piezoelectric layer 108 and the upper electrode 109 are formed sequentially above the sacrificial material. The lower electrode 107a, the piezoelectric layer 108 and the upper electrode 109 have an overlapping area above the sacrificial material. Finally, the sacrificial material is released to form a cavity 106 between the lower electrode 107a and the substrate structure. It should be noted that (1) the cavity 106 is formed in the second substrate layer 105, so its depth is less than or equal to the thickness of the second substrate layer 105; (2) the actual device chip often includes multiple device units. For the sake of simplicity, only the cavity 106 is formed here. Figure 9 A device unit is shown for illustration, while other device units and the connections between device units are omitted. (3) Typically, in addition to the lower electrode 107a, a connection part (the part circled in dashed circle) is often formed to connect to the lower electrode, which is used to bring out the signal of the device unit during subsequent packaging or for electrical connection between device units. (4) Figure 9The portion marked 107b in the attached figure is formed at the edge of the substrate structure (i.e., on the outside of the device unit), and a sealing ring is subsequently formed on this portion. This portion is often formed simultaneously with the lower electrode 107a.

[0101] After the device chip is packaged to form a package structure, the heat generated by the device units in the device chip is transferred to the outside through heat dissipation channels on one side of the substrate structure. Based on the device chip formed in this embodiment, its substrate structure consists of a second substrate layer 105 and a first substrate layer 100 from top to bottom. A heat-conducting hole structure penetrating the first substrate layer 100 in the thickness direction is formed in the first substrate layer 100. The thermal conductivity of the material of the second substrate layer 105 is greater than that of the material of the first substrate layer 100, which facilitates the efficient transfer of heat generated by the device units to the first substrate layer 100. The thermal conductivity of the heat-conducting hole structure in the first substrate layer 100 is greater than that of the material of the first substrate layer 100, which facilitates the efficient transfer of heat transferred to the first substrate layer 100 to the outside of the package structure through the heat-conducting hole structure. In this way, a low thermal resistance and high thermal conductivity heat dissipation channel is provided for the device units in the package structure on one side of the substrate structure. Compared to a single-layer substrate structure (i.e., where all parts of the substrate except for the heat-conducting holes are made of the same substrate material), in this embodiment, the substrate structure is configured as a two-layer structure along the heat dissipation channel direction, consisting of a second substrate layer 105 and a first substrate layer 100, and the thermal conductivity of the second substrate layer 105 is greater than that of the first substrate layer 100. This further improves the heat dissipation efficiency of the packaging structure. Of course, those skilled in the art will understand that in other embodiments, the thermal conductivity of the second substrate layer 105 may also be equal to that of the first substrate layer 100.

[0102] This invention does not limit the specific shape of the heat-conducting hole structure. For example, its horizontal cross-section can be any regular shape such as a polygon or a circle, or it can be any irregular shape. Please refer to Figure 10(a), which is a top view of the first substrate layer according to a specific embodiment of the present invention, wherein the adhesion layer and the seed layer are omitted. As shown in Figure 10(a), in this embodiment, the cross-section of the heat-conducting hole structure in the horizontal direction is rectangular.

[0103] In this invention, the horizontal projection of all heat-conducting hole structures in the device chip is defined as the first projection, and the area of ​​this first projection is called the first projected area (i.e., the sum of the horizontal projected areas of all heat-conducting hole structures); and the horizontal projection of the device chip is defined as the second projection, and the area of ​​this second projection is called the second projected area. It should be noted that a region is reserved on the device chip to form an annular bonding portion. This annular bonding portion is used for subsequent bonding with the bonding portion of the cap to form a sealing ring, thereby sealing the device unit on the device chip within the sealed space formed by the device chip, the cap, and the sealing ring. The outer edge of the annular bonding portion region on the device chip is defined as the boundary of the device chip, and correspondingly, the horizontal projection of the outer edge of the annular bonding portion region on the device chip is the second horizontal projection of the device chip. To enable effective heat transfer through the heat-conducting hole structure, preferably, the ratio of the first projected area of ​​the heat-conducting hole structure to the second projected area of ​​the device chip is between 30% and 90%.

[0104] Considering that the main heat-generating part of the device chip is the device unit, it is preferable to have a denser distribution of heat-conducting hole structures in the region below the device unit. Specifically, the first substrate layer 100 can be divided into core regions corresponding to the device units, with each core region located below the corresponding device unit. Regions of the first substrate layer 100 other than the core regions are called non-core regions. The distribution density of heat-conducting hole structures in the core regions is greater than that in the non-core regions. In this invention, for each device unit and its corresponding core region, the horizontal projection of the former is defined as the third projection, and the horizontal projection of the latter is defined as the fourth projection. In a specific embodiment, the edges of the third projection and the fourth projection form an annular shape (either the third projection falls within the range of the fourth projection, or vice versa), and the width of this annular shape is less than or equal to 100 μm. It should be noted that, for the case where the device unit is a resonant unit, the third projection of the device unit mainly refers to the horizontal projection of the lower electrode. Furthermore, those skilled in the art will understand that in other embodiments, the thermally conductive hole structure may also be uniformly distributed in the first substrate layer 100 as shown in FIG10(a).

[0105] For cases where the number of thermally conductive via structures is greater than or equal to two, the manufacturing method provided by this invention further includes the step of forming the substrate structure by: forming an interconnect structure (hereinafter referred to as the first interconnect structure) on a first substrate layer. This first interconnect structure is formed within a groove on the upper surface of the first substrate layer, creating communication between the first thermally conductive materials within the thermally conductive via structures. In one specific embodiment, the upper surface of the first substrate layer can be etched to form a groove for communicating with the second blind via, and the groove can be filled with a thermally conductive material (which can be the first thermally conductive material or other thermally conductive materials) to form the second interconnect structure. This document does not limit the execution order of the second interconnect structure formation step. For example, it can be performed after filling the second blind via with the first thermally conductive material, or after forming the second blind via, the upper surface of the first substrate layer can be etched to form the groove, and the groove can be filled simultaneously with the filling of the second blind via, etc. Please refer to Figures 10(b-1), 10(b-2), and 10(b-3). Figure 10(b-1) is a top view of the first substrate layer according to a specific embodiment of the present invention. Figures 10(b-2) and 10(b-3) are cross-sectional views along lines AA' and BB' of the structure shown in Figure (b-1), respectively. As shown, the first interconnect structure 103' is embedded in a groove on the upper surface of the first substrate layer 100, and the first thermally conductive material 103 in each thermally conductive hole structure is interconnected through the first interconnect structure 103'. Those skilled in the art will understand that the first interconnect structure should not be limited to the structure shown in Figure 10(b-1). Any structure that allows heat transfer between some or all of the thermally conductive hole structures is applicable to the first interconnect structure in this invention. For the sake of simplicity, all possible first interconnect structures will not be listed here. The presence of the first interconnect structure allows the heat generated by the device unit to be quickly transferred through all the thermally conductive hole structures, thereby further improving heat dissipation efficiency.

[0106] In the manufacturing method provided by this invention, the step of forming the substrate structure further includes: forming a third substrate layer between the first substrate layer and the second substrate layer, wherein the third substrate layer is connected to the first thermally conductive material in the thermally conductive hole structure of the first substrate layer. The material of the third substrate layer is a thermally conductive material (hereinafter referred to as the second thermally conductive material), wherein the thermal conductivity of the second thermally conductive material is greater than that of the material of the first substrate layer. Preferably, a metallic material with high thermal conductivity is used, such as one or any combination of Cu, Au, Ag, Al, Ni, Fe, Mo, and W. Of course, the second thermally conductive material can also be a non-metallic material with a higher thermal conductivity than that of the first substrate layer. It should also be noted that the second thermally conductive material can be a single-crystal material, a polycrystalline material, or a combination of single-crystal and polycrystalline materials, and this invention does not limit it in any way. The presence of the third substrate layer facilitates the transfer of heat from the second substrate layer to the first substrate layer, thereby further improving the heat dissipation efficiency. In addition, the thickness of the third substrate layer is preferably less than or equal to 50 μm.

[0107] In one specific embodiment, a third substrate layer is formed on the first substrate layer after the second blind via is filled with a first thermally conductive material and before the second substrate layer is formed. For example... Figure 11 As shown, the third substrate layer 104 is formed between the first substrate layer 100 and the second substrate layer 105. In another specific embodiment, the third substrate layer can also be formed simultaneously with filling the second blind via with the first thermally conductive material. Taking the filling of the second blind via with metal material as an example, firstly, a metal layer is formed on the surface of the adhesion layer (or seed layer) by electroplating. By controlling the thickness of the metal layer, on the one hand, the metal layer fills the second blind via, and on the other hand, the thickness of the portion of the metal layer on the surface of the first substrate layer is greater than the thickness of the third substrate layer; then, the metal layer is planarized until the thickness of the portion of the metal layer on the surface of the first substrate layer is equal to the thickness of the third substrate layer. In this way, the second blind via is filled while the third substrate layer is formed. In this case, the material of the third substrate layer is the first thermally conductive material, and the third substrate layer and the filling material in the second blind via have an integrated structure. Figure 12 As shown, the third substrate layer 104 is formed between the first substrate layer 100 and the second substrate layer 105, and is integrated with the filling material in the second blind hole.

[0108] It should be noted that, in the case where a third substrate layer is provided in the substrate structure to achieve efficient heat transfer from the second substrate layer to the first substrate layer, the materials of the first substrate layer and the second substrate layer can be different or the same.

[0109] Figure 11In the structure shown, the third substrate layer 104 is a single layer. In other embodiments, considering that the main heat-generating part of the device chip is the device unit, it is preferable that the third substrate layer is formed only below the device unit. Therefore, in a preferred embodiment, the third substrate layer includes thermally conductive regions corresponding to the device units, with each thermally conductive region located below its corresponding device unit. For cases where the number of device units is greater than or equal to two, more preferably, the third substrate layer also includes an interconnect structure (hereinafter referred to as a second interconnect structure), which interconnects the thermally conductive regions. In a specific embodiment, the formation process of the third substrate layer is as follows: first, a third substrate layer material is deposited on the first substrate layer; then, the third substrate layer material is etched to form thermally conductive regions corresponding to the device units and a second interconnect structure, wherein each thermally conductive region is located below its corresponding device unit, and the second interconnect structure interconnects the thermally conductive regions. In another specific embodiment, when filling the second blind via with the first thermally conductive material, the thickness of the first thermally conductive material located above the first substrate layer and the second blind via can be controlled through process control to be greater than the thickness of the third substrate layer to be formed. Then, the first thermally conductive material located above the first substrate layer and the second blind via is planarized until its thickness is equal to the thickness of the third substrate layer to be formed. Finally, the first thermally conductive material located above the first substrate layer and the second blind via is patterned to form the third substrate layer. This method achieves the deposition of the third substrate layer material while filling the second blind via, which is beneficial to the simplification of the process. Please refer to Figures 13(a) and 13(b). In Figure 13(a), the third substrate layer 104 only includes the thermally conductive region located below the device unit. The figure only schematically shows two device units and the thermally conductive region located below them, ignoring other components of the device chip. The device unit is a resonant unit, represented by the lower electrode 107 in the figure. In Figure 13(b), the third substrate layer includes a thermally conductive region 104a located below the device unit and a second interconnection structure 104b for interconnecting the thermally conductive region 104a. The figure only schematically illustrates two device units, the thermally conductive regions located below these two device units, and the second interconnection structure, omitting other components of the device chip. The device unit is a resonant unit, represented by the lower electrode 107 in the figure. Those skilled in the art will understand that the thermally conductive region located below the device unit is sheet-like rather than annular. For Figures 13(a) and 13(b), the thermally conductive region is a regular pentagonal region, not an annular region. Furthermore, those skilled in the art will understand that the thermally conductive region and the second interconnection structure are not limited to the structure shown in Figure 13(b). For example, the thermally conductive region can be a polygon other than a regular pentagon, or it can be a circle, or even an irregular shape. For simplicity, all possibilities for the thermally conductive region and the second interconnection structure will not be listed here.The presence of the second interconnect structure allows the heat generated by the device unit to be quickly transferred to the first substrate layer through the third substrate layer, thereby further improving heat dissipation efficiency.

[0110] Furthermore, in this invention, the projection of the third substrate layer in the horizontal direction is defined as the fifth projection, and the area of ​​the fifth projection is called the fifth projection area; and the projection of each heat-conducting region in the third substrate layer in the horizontal direction is defined as the sixth projection, and the area of ​​the fifth projection is called the fifth projection area. To ensure the heat transfer effect of the third substrate layer, in a preferred embodiment, the ratio of the fifth projection area of ​​the third substrate layer to the second projection area of ​​the device chip is in the range of 30% to 90%; and there is an overlapping area between the sixth projection of each heat-conducting region and the third projection of the corresponding device unit, the ratio of the horizontal projection area of ​​the overlapping area to the third projection area of ​​the device unit is greater than 50%.

[0111] The present invention also provides a packaging structure, the packaging structure comprising:

[0112] The aforementioned device chip;

[0113] A cap, the front of which is positioned opposite to the device chip, and a connecting portion on the back;

[0114] A sealing ring is disposed between the device chip and the cap, forming a sealing structure with the device chip and the cap, and the at least one device unit is located within the cavity of the sealing structure;

[0115] The encapsulation substrate, wherein the sealing structure is connected to the encapsulation substrate via the connecting portion;

[0116] A molding compound that encapsulates the sealing structure.

[0117] The following is a detailed description of each component of the above packaging structure.

[0118] Specifically, the packaging structure provided by this invention includes a device chip, which is implemented using the aforementioned device chip of this invention. For the sake of simplicity, the specific structure of the device chip will not be described here, but can be referred to the relevant sections above. The following will use a device chip based on... Figure 11 The packaging structure formed by the device chip shown is used as an example for illustration.

[0119] like Figure 19As shown, the packaging structure provided by the present invention also includes a cap, the front side of which is disposed opposite to the device chip. In this embodiment, the cap includes a body 200, a first via (TSV) structure, and a connecting portion 205. The first via structure is formed within the body 200, wherein the first via structure includes a through hole penetrating the body 200 in the thickness direction, and a metal material 201 (e.g., Cu) filling the through hole. Preferably, an adhesion layer 202 may also be formed between the metal material 201 and the sidewall of the through hole. The connecting portion 205 is formed on the back side of the cap body 200. In this embodiment, the connecting portion 205 is a solder ball formed on the back side of the cap body 200 and connected to the first via structure. It should be noted that in other embodiments, a groove may also be formed on the front side of the cap body 200 at a position corresponding to the device unit, for maintaining a sufficient distance between the device unit on the device chip and the cap after packaging, so as to ensure that the performance of the device unit is not affected.

[0120] like Figure 19 As shown, the packaging structure provided by the present invention further includes a sealing ring 300a, which is disposed between the device chip and the cap, forming a sealed structure with the device chip and the cap. The device unit in the device chip is located within the cavity 301 of the sealed structure. In this embodiment, the material of the sealing ring 300a is a bonding material such as Au. It should be noted that, as Figure 19 As shown, the sealing structure also includes a connection structure 300b located within the cavity 301. One end of the connection structure 300b is connected to the connection portion of the lower electrode 107 of the device unit in the device chip, and the other end is connected to the first through hole on the cap for signal output from the device unit. Preferably, an adhesion layer 204 is formed between the sealing ring 300a and the connection structure 300b and the cap, and an adhesion layer 120 is formed between the sealing ring 300a and the connection structure 300b and the device chip.

[0121] like Figure 19As shown, the packaging structure provided by the present invention also includes a packaging substrate. In this embodiment, the packaging substrate includes a substrate body 400, a front pad 401 formed on the front side of the substrate body 400 (the surface facing the sealing structure), a back pad 402 formed on the back side of the substrate body 400, and a second via structure 403 formed in the substrate body 400 for electrically connecting the front pad 401 and the back pad 402. The front pad 401 is formed on the front side of the substrate body 400 at a position corresponding to the back solder ball 205 (i.e., the connecting portion 205) of the cap. By soldering the back solder ball 205 of the cap to the front pad 401 of the packaging substrate, the connection between the sealing structure and the packaging substrate is achieved. Those skilled in the art will understand that, depending on actual design requirements, electronic components such as spiral inductors (not shown) are usually formed within the substrate body 400. The device units on the device chip can be electrically connected to the electronic components within the substrate body 400 through the connection structure 300b, the first via structure in the cap, the solder ball 205, the front pad 401 of the substrate body 400, and the via structure (not shown) within the substrate body 400. These are all existing conventional technical means, and for the sake of brevity, they will not be described in detail here.

[0122] like Figure 19 As shown, the packaging structure provided by the present invention also includes a molding compound 500, which encapsulates the sealing structure. The material of the molding compound 500 can be achieved using conventional techniques, and for the sake of simplicity, it will not be described in detail here.

[0123] It should be noted that since the device chip is flip-chip mounted on the packaging substrate, the corresponding packaging structure is a flip-chip structure.

[0124] The packaging structure provided by this invention is implemented using the aforementioned device chip. During operation, the heat generated by the device units within the device chip can be efficiently transferred to the outside through the thermally conductive holes in the substrate structure. Therefore, compared to existing packaging structures, the packaging structure provided by this invention has superior heat dissipation efficiency. This excellent heat dissipation efficiency results in a longer lifespan, higher reliability, and stronger power handling capacity for the packaging structure provided by this invention.

[0125] This invention also provides a method for manufacturing a packaging structure. Please refer to [link / reference]. Figure 14 , Figure 14 This is a flowchart illustrating a manufacturing method for a packaging structure according to a specific embodiment of the present invention. As shown, the manufacturing method includes:

[0126] In step S201, the aforementioned device chip is provided, or the device chip is formed using the aforementioned manufacturing method;

[0127] In step S202, a cap is provided, the front side of which is disposed opposite to the device chip;

[0128] In step S203, a sealing ring is formed between the device chip and the cap, the sealing ring forming a sealing structure with the device chip and the cap, and the at least one device unit is located in the cavity of the sealing structure;

[0129] In step S204, a connecting portion is formed on the back of the cap, and the sealing structure is connected to the packaging substrate through the connecting portion;

[0130] In step S205, a plastic sealant is formed to encapsulate the sealing structure.

[0131] The following will combine Figures 15 to 19 The steps S201 to S205 described above will be explained in detail.

[0132] Specifically, in step S201, a device chip is provided or a device chip is formed, wherein the device chip is implemented using the aforementioned device chip of the present invention or using the aforementioned manufacturing method of the present invention. For the sake of brevity, the formation process of the device chip will not be described here, but can be referred to the relevant sections above. The following will use... Figure 11 The following steps will be explained using the device chip shown as an example.

[0133] After the device chip is formed, a first bonding structure needs to be formed within the first bonding region of the device chip. Typically, such as... Figure 15 As shown, the first bonding structure includes a first bonding portion 121a and a second bonding portion 121b. The first bonding portion 121a is formed in the edge region of the device chip and is subsequently used to form a sealing ring; the second bonding portion 121b is formed in the inner region of the device chip and is connected to the lower electrode 107a via a connecting portion for signal extraction from subsequent device units. The first bonding portion 121a and the second bonding portion 121b are made of conventional bonding materials (e.g., Au). Preferably, an adhesion layer 120 is formed in the first bonding region before forming the first bonding structure.

[0134] In step S202, a cap is provided for use with the device chip, the front side of which is positioned opposite to the device chip. In this embodiment, as... Figure 16As shown, the cap includes a body 200 and a first via (TSV) structure. The first via structure is formed within the body 200, and includes a through-hole extending through the body 200 in the thickness direction, and a metal material 201 (e.g., Cu) filling the through-hole. Preferably, an adhesion layer 202 may be formed between the metal material 201 and the sidewall of the through-hole. A second bonding structure is also formed on the cap, which is formed on the front side of the body 200 and connected to the first via structure. The second bonding structure includes a third bonding portion 203a corresponding to the first bonding portion 121a of the device chip, and a fourth bonding portion 203b corresponding to the second bonding portion 121b of the device chip. The third bonding portion 203a and the fourth bonding portion 203b are made of conventional bonding materials (e.g., Au). Preferably, an adhesion layer 204 is also formed between the second bonding structure and the cap body 200.

[0135] It should be noted that in other embodiments, a groove may also be formed on the front side of the cap body 200 at the position corresponding to the device unit, so as to maintain a sufficient distance between the device unit on the device chip and the cap after encapsulation, so as to ensure that the performance of the device unit is not affected.

[0136] In step S203, as Figure 17 As shown, the third bonding portion 203a of the cap is aligned with the first bonding portion 121a of the device chip, and the fourth bonding portion 203b of the cap is aligned with the second bonding portion 121b of the device chip. Then, the cap and the device chip are bonded and fixed. The third bonding portion 203a of the cap and the first bonding portion 121a of the device chip are bonded together to form a sealing ring 300a. This sealing ring 300a, the cap, and the device chip form a sealed structure, with the device unit within the device chip located within the cavity 301 of this sealed structure. Furthermore, the fourth bonding portion 203b of the cap and the second bonding portion 121b of the device chip are bonded together to form a connection structure 300b for signal extraction. This connection structure 300b is also located within the cavity 301 of the sealed structure.

[0137] In step S204, as Figure 18As shown, a connecting portion 205 is formed on the back side of the cap, and the sealing structure is connected to the packaging substrate through this connecting portion 205. In this embodiment, the connecting portion 205 is a solder ball, which is formed on the back side of the cap body 200 and connected to the first via structure. The packaging substrate includes a substrate body 400, a front pad 401 formed on the front side of the substrate body 400 (facing the surface of the sealing structure), a back pad 402 formed on the back side of the substrate body 400, and a second via structure 403 formed in the substrate body 400 for realizing the electrical connection between the front pad 401 and the back pad 402. The front pad 401 is formed on the front side of the substrate body 400 at a position corresponding to the back pad 205 of the cap. By soldering the back pad 205 of the cap to the front pad 401 of the packaging substrate, the connection between the sealing structure and the packaging substrate is realized. Those skilled in the art will understand that, depending on actual design requirements, electronic components such as spiral inductors (not shown) are usually formed within the substrate body 400. The device units on the device chip can be electrically connected to the electronic components within the substrate body 400 through the connection structure 300b, the first via structure in the cap, the solder ball 205, the front pad 401 of the substrate body 400, and the via structure (not shown) within the substrate body 400. These are all existing conventional technical means, and for the sake of brevity, they will not be described in detail here.

[0138] In step S205, as Figure 19 As shown, the sealing structure is encapsulated to form a plastic encapsulation body 500 that surrounds the sealing structure. The encapsulation process and the material of the plastic encapsulation body 500 can be achieved using conventional techniques, and will not be described in detail here for the sake of simplicity.

[0139] It should be noted that the process of forming the device chip includes a step of planarizing the lower surface of the first substrate layer 100 to expose the first thermally conductive material 103. In some applications, this step can also be performed after the cap and the device chip are bonded to form a sealed structure.

[0140] The packaging structure formed by implementing the manufacturing method provided by this invention has excellent heat dissipation efficiency.

[0141] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be embraced within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims. Furthermore, it is clear that the word "comprising" does not exclude other components, units, or steps, and the singular does not exclude the plural. Multiple components, units, or devices recited in the system claims may also be implemented by a single component, unit, or device in software or hardware.

[0142] The above-disclosed embodiments are merely some preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A device chip, characterized in that, The device chip includes: The substrate structure comprises, from bottom to top, a first substrate layer, a third substrate layer, and a second substrate layer. At least one heat-conducting hole structure is formed at the bottom of the substrate structure. Each heat-conducting hole structure includes a first blind hole formed at the bottom of the substrate structure and a first heat-conducting material filled in the first blind hole. At least one second blind hole is formed on the upper surface of the first substrate layer. At least one device unit is formed on the substrate structure. A first substrate layer includes a core region corresponding to each device unit. The area of ​​the first substrate layer other than the core region is a non-core region. The distribution density of the thermally conductive hole structure in the core region is greater than that in the non-core region. A third substrate layer includes a thermally conductive region corresponding to each device unit. Each thermally conductive region is located below its corresponding device unit, and there is an overlap between the horizontal projection of each thermally conductive region and the horizontal projection of the corresponding device unit. The ratio of the projected area of ​​the overlapping region to the horizontal projection area of ​​the corresponding device unit is greater than 50%. The first substrate layer has a through hole formed in the thickness direction, and the through hole is filled with a first thermally conductive material. The sidewall of the second blind hole and the bottom surface of the second substrate layer form a first blind hole. The third substrate layer is made of a second thermally conductive material and covers the upper surface of the first substrate layer. The thermal conductivity of the material of the second substrate layer is greater than that of the material of the first substrate layer. The thermal conductivity of both the first thermally conductive material and the second thermally conductive material is greater than that of the material of the first substrate layer.

2. The device chip according to claim 1, characterized in that, in: Each of the device units consists of a lower electrode, a piezoelectric layer, and an upper electrode from bottom to top, and an acoustic reflection structure is formed between each of the device units and the substrate structure.

3. The device chip according to claim 1, characterized in that, in: The ratio of the sum of the projected areas of the heat-conducting hole structure in the horizontal direction to the projected area of ​​the device chip in the horizontal direction is between 30% and 90%.

4. The device chip according to claim 1, characterized in that, in: The horizontal projection edge of each device unit and the horizontal projection edge of the core region below it form an annular shape, the width of which is less than or equal to 100 μm.

5. The device chip according to claim 3, characterized in that, in: When the number of the thermally conductive hole structures is greater than or equal to two, a first interconnect structure is also formed on the first substrate layer. The first interconnect structure is formed in the groove on the upper surface of the first substrate layer and interconnects the first thermally conductive materials in the thermally conductive hole structure.

6. The device chip according to claim 4, characterized in that, in: When the number of device units is greater than or equal to 2, the third substrate layer further includes a second interconnect structure, which interconnects the thermally conductive regions.

7. The device chip according to claim 6, characterized in that, in: The ratio of the projected area of ​​the third substrate layer in the horizontal direction to the projected area of ​​the device chip in the horizontal direction ranges from 30% to 90%.

8. A method for manufacturing a device chip, characterized in that, The manufacturing method includes: A substrate structure is formed, wherein a first substrate layer, a third substrate layer and a second substrate layer are formed sequentially from bottom to top in the substrate structure, and at least one heat-conducting hole structure is formed at the bottom of the substrate structure, each of the heat-conducting hole structures including a first blind hole formed at the bottom of the substrate structure and a first heat-conducting material filled in the first blind hole; and at least one second blind hole is formed on the upper surface of the first substrate layer. At least one device unit is formed on the substrate structure. The first substrate layer includes a core region corresponding to each device unit. The area of ​​the first substrate layer other than the core region is a non-core region. The distribution density of the thermally conductive hole structure in the core region is greater than that in the non-core region. The third substrate layer includes a thermally conductive region corresponding to each device unit. Each thermally conductive region is located below its corresponding device unit, and there is an overlap between the horizontal projection of each thermally conductive region and the horizontal projection of the corresponding device unit. The ratio of the projected area of ​​the overlapping region to the horizontal projection area of ​​the corresponding device unit is greater than 50%. The first substrate layer has a through hole formed in the thickness direction, and the through hole is filled with a first thermally conductive material. The sidewall of the second blind hole and the bottom surface of the second substrate layer form a first blind hole. The third substrate layer is made of a second thermally conductive material and covers the upper surface of the first substrate layer. The thermal conductivity of the material of the second substrate layer is greater than that of the material of the first substrate layer. The thermal conductivity of both the first thermally conductive material and the second thermally conductive material is greater than that of the material of the first substrate layer.

9. The manufacturing method according to claim 8, characterized in that, in, Each of the device units consists of a lower electrode, a piezoelectric layer, and an upper electrode from bottom to top, and an acoustic reflection structure is formed between each of the device units and the substrate structure.

10. The manufacturing method according to claim 8 or 9, characterized in that, in, The steps for forming the substrate structure include: A first thermally conductive material is filled into the at least one second blind hole; The substrate structure is formed by depositing a second substrate layer on the first substrate layer and planarizing the lower surface of the first substrate layer to expose the first thermally conductive material, wherein the sidewall of the second blind via and the bottom surface of the second substrate layer constitute the first blind via.

11. The manufacturing method according to claim 8, characterized in that, in, The ratio of the sum of the projected areas of the heat-conducting hole structure in the horizontal direction to the projected area of ​​the device chip in the horizontal direction is between 30% and 90%.

12. The manufacturing method according to claim 8, characterized in that, in: The horizontal projection edge of each device unit and the horizontal projection edge of the core region below it form an annular shape, the width of which is less than or equal to 100 μm.

13. The manufacturing method according to claim 8, characterized in that, in, When the number of the thermally conductive hole structures is greater than or equal to two, the step of forming the substrate structure further includes: A first interconnect structure is formed on the first substrate layer. The first interconnect structure is formed in a groove on the upper surface of the first substrate layer and interconnects the first thermally conductive materials within the thermally conductive hole structure.

14. The manufacturing method according to claim 8, characterized in that, in: When the number of device units is greater than or equal to 2, the third substrate layer further includes a second interconnect structure, which interconnects the thermally conductive regions.

15. The manufacturing method according to claim 8, characterized in that, in: The ratio of the projected area of ​​the third substrate layer in the horizontal direction to the projected area of ​​the device chip in the horizontal direction ranges from 30% to 90%.

16. A packaging structure, characterized in that, The packaging structure includes: The device chip as described in any one of claims 1 to 7; A cap, the front of which is positioned opposite to the device chip, and a connecting portion on the back; A sealing ring is disposed between the device chip and the cap, forming a sealing structure with the device chip and the cap, and the at least one device unit is located within the cavity of the sealing structure; The encapsulation substrate, wherein the sealing structure is connected to the encapsulation substrate via the connecting portion; A molding compound that encapsulates the sealing structure.

17. A method for manufacturing a packaging structure, characterized in that, The manufacturing method includes: A device chip is provided, which is implemented using any one of claims 1 to 7 or formed using any one of claims 8 to 15; A cap is provided, the front of which is positioned opposite the device chip; A sealing ring is formed between the device chip and the cap, the sealing ring forming a sealing structure with the device chip and the cap, and the at least one device unit is located within the cavity of the sealing structure; A connecting portion is formed on the back of the cap, and the sealing structure is connected to the packaging substrate through the connecting portion; A plastic encapsulation is formed to encapsulate the sealing structure.

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