A chip packaging structure comprising a carrier board and a chip

Abstract

The present invention discloses a carrier board for chip packaging and a chip packaging structure. The carrier board includes a carrier sheet, a substrate, and a plurality of unit circuits arranged in a matrix. The unit circuits include a plurality of electrodes, and the electrodes include a top electrode and a bottom electrode. The carrier sheet can be peelably attached to the bottom surface of the substrate. The substrate includes N substrate layers, where N is an integer greater than or equal to 1. The substrate layer includes a copper-plated resin layer and a circuit layer. The circuit layer is arranged on the top surface of the copper-plated resin layer. The copper-plated resin layer includes a plurality of copper pillars. The lower end of the copper pillar is connected to the circuit of the circuit layer on the top surface of the next substrate layer, and the upper end is connected to the circuit of the circuit layer on the top surface of the current substrate layer. The circuit layer of the top substrate layer includes the top electrode, and the copper pillars of the bottom substrate layer are connected to the corresponding bottom electrodes. The present invention can adjust the number of substrate layers according to the complexity of the circuit, so as to arrange more complex circuits in a smaller space.

Description

[Technical field]

[0001] The present invention relates to chip packaging, and in particular to a carrier board used for chip packaging and a chip packaging structure. [Background Technology]

[0002] The package carrier (lead frame) is a key dedicated basic material for IC packaging. The invention with application number CN202011273348.X discloses a lead frame for chip packaging, a preparation method and a chip packaging structure. The lead frame includes a carrier sheet, a first solder resist ink layer and a plurality of unit circuits arranged in a matrix. The unit circuit includes a plurality of electrodes, and the electrodes include a top electrode and a bottom electrode; the top electrode is arranged on the top surface of the first solder resist ink layer; corresponding to each unit circuit, the first solder resist ink layer includes a bottom electrode hole corresponding to the electrode, the bottom electrode is arranged in the bottom electrode hole, and the top of the bottom electrode is fixed on the bottom surface of the top electrode; the carrier sheet is removably attached to the first solder resist ink layer and the bottom surface of the bottom electrode. The lead frame preparation process of this invention requires repeated processing of the upper and lower surfaces of the workpiece, and the workpiece is flipped during the processing, which increases the process difficulty and preparation cost; in addition, when the circuit of the lead frame of this invention is more complex, the circuit layout is difficult. [Summary of the invention]

[0003] The technical problem to be solved by the present invention is to provide a chip packaging carrier that is convenient for arranging complex circuits in a relatively small space.

[0004] A further technical problem to be solved by the present invention is to provide a chip packaging carrier which does not require flipping during the preparation process and has a simple process.

[0005] Another technical problem to be solved by the present invention is to provide a chip packaging structure with a simple carrier board preparation process.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is a carrier board for chip packaging, comprising a carrier sheet, a substrate and a plurality of unit circuits arranged in a matrix, the unit circuits comprising a plurality of electrodes, the electrodes comprising a top electrode and a bottom electrode, the carrier sheet being removably adhered to the bottom surface of the substrate, the substrate comprising N substrate layers, N being an integer greater than or equal to 1; the substrate layer comprising a copper-plated resin layer and a circuit layer, the circuit layer being arranged on the top surface of the copper-plated resin layer, the copper-plated resin layer comprising a plurality of copper pillars; the lower end of the copper pillar is connected to the circuit of the circuit layer on the top surface of the next substrate layer, and the upper end is connected to the circuit of the circuit layer on the top surface of the current substrate layer; the circuit layer of the top substrate layer comprises the top electrode, and the copper pillar of the bottom substrate layer is connected to the corresponding bottom electrode.

[0007] The carrier described above includes a beam connecting copper pillar corresponding to the top electrode, the beam connecting copper pillar is arranged above the corresponding top electrode, and the bottom of the beam connecting copper pillar is connected to the corresponding top electrode; the circuit layer of the top substrate layer includes a base island for fixing the chip.

[0008] The carrier board mentioned above includes a solder resist ink layer covering the top substrate layer. The solder resist ink layer includes windows corresponding to the unit circuits, and the pads of the top electrodes of the unit circuits are exposed in the windows.

[0009] The carrier board described above, the manufacturing process of the carrier board includes the following steps:

[0010] 401) The top surface of the carrier sheet is covered with an anti-sticking layer, a hollow pattern corresponding to the shape of the bottom electrode is made on the anti-sticking layer, and the bottom electrode is formed by electroplating in the hollow pattern area of ​​the anti-sticking layer;

[0011] 402) disposing a first copper-deposited resin layer on the top surfaces of the anti-sticking layer and the bottom electrode, and photoetching or laser drilling a first through hole corresponding to the bottom electrode on the first copper-deposited resin layer, with the bottom surface of the first through hole being the top surface of the corresponding bottom electrode; or covering the top surfaces of the anti-sticking layer and the bottom electrode with a first copper pillar photosensitive film, and photoetching a first through hole corresponding to the bottom electrode on the first copper pillar photosensitive film, with the bottom surface of the first through hole being the top surface of the corresponding bottom electrode;

[0012] 403) copper plating in the first through hole on the first copper-depositable resin layer to form a first copper pillar whose bottom surface is connected to the corresponding bottom electrode and whose top surface is flush with the top surface of the first copper-depositable resin layer; or copper plating in the first through hole on the first copper pillar photosensitive film to form a first copper pillar whose bottom surface is connected to the corresponding bottom electrode, removing the first copper pillar photosensitive film, and then disposing a first copper-depositable resin layer on the top surface of the anti-sticking layer and the bottom electrode, and grinding the first copper-depositable resin layer to expose the top surface of the first copper pillar on the surface of the first copper-depositable resin layer;

[0013] 404) depositing copper on the top surface of the first copper-depositable resin layer and the first copper pillar to form a first circuit layer, wherein the first copper-depositable resin layer and the first circuit layer constitute the bottommost substrate layer;

[0014] 405) When N is equal to 1, the first circuit layer is the top circuit layer, the top circuit layer includes the top electrode, and the top of the first copper column is connected to the corresponding top electrode.

[0015] In the aforementioned carrier board, step 404 of forming the first circuit after copper is deposited on the top surface of the first copper-depositable resin layer includes the following steps:

[0016] 501) depositing copper on the top surface of the first copper-depositable resin layer and the top surface of the first copper pillar to form a first seed copper layer; and covering the top surface of the first seed copper layer with a first circuit photosensitive film;

[0017] 502) Photoetching a first hollow pattern corresponding to the first circuit layer on the first circuit photosensitive film, and copper plating the first hollow pattern area of ​​the first circuit photosensitive film to form the main body of the first circuit layer;

[0018] 503) Remove the first circuit photosensitive film, and etch away the seed copper of the first seed copper layer outside the main body of the first circuit layer to form a first circuit layer.

[0019] In the aforementioned carrier board, step 404 of forming the first circuit after copper is deposited on the top surface of the first copper-depositable resin layer includes the following steps:

[0020] 601) copper plating is performed on the top surface of the first copper-platable resin layer and the top surface of the first copper pillar after copper plating; and a second circuit photosensitive film is covered on the top surface of the copper plating layer;

[0021] 602) Photoetching a second hollow pattern corresponding to the first circuit layer on the second circuit photosensitive film, wherein the solid portion of the second hollow pattern has the same shape as the solid portion of the first circuit layer;

[0022] 603) etching the copper plating layer on the top surface of the first copper-platable resin layer;

[0023] 604) The second circuit photosensitive film is removed to form a first circuit layer.

[0024] For the carrier board described above, when N is greater than 1, the manufacturing process of the carrier board includes the following steps:

[0025] 701) disposing a second copper-depositable resin layer on the top surface of the lower substrate layer, and forming a plurality of second through holes on the second copper-depositable resin layer by photolithography or laser drilling, wherein the bottom surface of the second through holes is the top surface of the circuit layer of the lower substrate layer;

[0026] 702) Copper is plated in the second through hole to form a second copper pillar whose bottom surface is connected to the circuit layer of the underlying substrate layer and whose top surface is flush with the top surface of the second copper-depositable resin layer;

[0027] 703) After copper is deposited on the second copper-depositable resin layer and the top surface of the second copper pillar, a second circuit layer is formed. The second copper-depositable resin layer, the second copper pillar and the second circuit layer constitute the second substrate layer.

[0028] 704) Repeat steps 701 to 703 until the number of substrate layers reaches N. The second circuit layer of the Nth substrate layer is the top circuit layer, and the top circuit layer includes the top electrode. The second copper column in the top substrate layer is connected to the corresponding top electrode.

[0029] The carrier described above can embed a chip in one or more substrate layers of the carrier. The manufacturing process of the carrier includes the following steps:

[0030] 801) forming a third copper pillar photosensitive film covering the main body of the first circuit layer formed in step 502, and photoetching a plurality of third through holes in the third copper pillar photosensitive film, wherein the bottom surface of the third through holes is the top surface of the main body of the first circuit layer below;

[0031] 802) Copper is plated in the third through hole to form a third copper pillar whose bottom surface is connected to the main body of the first circuit layer below and whose top surface is flush with the top surface of the third copper pillar photosensitive film;

[0032] 803) Remove the first circuit photosensitive film and the third copper pillar photosensitive film to expose the main body of the first circuit layer and the third copper pillar; etch away the seed copper of the first seed copper layer located outside the main body of the first circuit layer to form a first circuit layer; when N is equal to 1 and the upright chip is embedded, the first circuit layer includes a base island for fixing the chip.

[0033] A chip packaging structure includes a chip, a unit carrier and a packaging layer, the unit carrier includes a substrate and a unit circuit, the unit circuit includes a plurality of electrodes, the electrodes include a top electrode and a bottom electrode, and the electrodes of the chip are electrically connected to the top electrode; the substrate includes N substrate layers, N is an integer greater than or equal to 1; the substrate layer includes a copper-plated resin layer and a circuit layer, the circuit layer is arranged on the top surface of the copper-plated resin layer, and the copper-plated resin layer includes copper pillars corresponding to the electrodes; the lower end of the copper pillar is connected to the circuit of the circuit layer on the top surface of the next substrate layer, and the upper end is connected to the circuit of the circuit layer on the top surface of the current substrate layer; the circuit layer of the top substrate layer includes the top electrode, and the copper pillar of the bottom substrate layer is connected to the corresponding bottom electrode.

[0034] In the packaging structure described above, the chip is a front-mounted chip, the circuit layer of the top substrate layer includes a base island for fixing the chip, and the front-mounted chip is fixed on the top surface of the base island; the unit circuit includes a metal beam corresponding to the top electrode and a beam-connected copper column, the beam-connected copper column is arranged above the corresponding top electrode, and the bottom of the beam-connected copper column is connected to the corresponding top electrode; the packaging layer includes a fourth copper-plated resin layer and a plastic encapsulation layer, the fourth copper-plated resin layer covers the top of the top substrate layer, the front-mounted chip and the beam-connected copper column; the top of the fourth copper-plated resin layer includes a first vertical hole corresponding to a plurality of beam-connected copper columns and a plurality of second vertical holes corresponding to the front-mounted chip electrodes; the metal beam is arranged on the top surface of the fourth copper-plated resin layer, the first end of the metal beam passes through the first vertical hole to be connected to the corresponding beam-connected copper column, and the second end of the metal beam passes through the second vertical hole to be connected to the corresponding front-mounted chip electrode; the plastic encapsulation layer covers the fourth copper-plated resin layer and the metal beam.

[0035] The packaging process of the packaged chip in the above-mentioned packaging structure includes the following steps:

[0036] 1101 fix the upright chip on the base island;

[0037] 1102 , a fourth copper-depositable resin layer is covered on the top substrate layer, the front-mounted chip, and the lintel connecting copper pillars;

[0038] 1103 lithography or laser drilling is performed on the fourth copper-depositable resin layer to expose the top surface of the front-mounted chip electrode and the top surface of the lintel connecting copper column;

[0039] 1104 : depositing copper and electroplating copper on the top surface of the fourth copper-depositable resin layer, the top surface of the chip electrodes, and the top surface of the copper pillars connected to the lintels to form a second metal layer. The second metal layer is etched to form a plurality of metal lintels.

[0040] 1105 A plastic encapsulation layer is formed on top of the fourth copper-depositable resin layer and the metal lintel.

[0041] The present invention can adjust the number of substrate layers according to the complexity of the circuit, so as to arrange more complex circuits in a smaller space. [Brief Description of the Drawings]

[0042] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0043] Figure 1 This is a schematic diagram of step 1 of the method for preparing a chip packaging carrier according to embodiment 2 of the present invention.

[0044] Figure 2 2 is a schematic diagram of step 2 of the method for preparing a chip packaging carrier according to embodiment 2 of the present invention.

[0045] Figure 3 Schematic diagram of step 3 of the method for preparing a chip packaging carrier according to embodiment 2 of the present invention.

[0046] Figure 4 2 is a schematic diagram of step 4 of the method for preparing a chip packaging carrier according to embodiment 2 of the present invention.

[0047] Figure 5 Schematic diagram of step 5 of the method for preparing a chip packaging carrier according to embodiment 2 of the present invention.

[0048] Figure 6 2 is a schematic diagram of step 6 of the method for preparing a chip packaging carrier according to embodiment 2 of the present invention.

[0049] Figure 7 2 is a schematic diagram of step 7 of the method for preparing a chip packaging carrier according to embodiment 2 of the present invention.

[0050] Figure 8 2 is a schematic diagram of step 8 of the method for preparing a chip packaging carrier according to embodiment 2 of the present invention.

[0051] Figure 9 2 is a schematic diagram of step 9 of the method for preparing a chip packaging carrier according to embodiment 2 of the present invention.

[0052] Figure 10 It is a structural schematic diagram of the chip packaging carrier unit of embodiment 1 of the present invention.

[0053] Figure 11 1 is a schematic diagram of the first step of step 3 of the method for preparing a chip packaging carrier in embodiment 3 of the present invention.

[0054] Figure 12 2 is a schematic diagram of the second step of step 3 of the method for preparing a chip packaging carrier in embodiment 3 of the present invention.

[0055] Figure 13 Schematic diagram of step 4 of the method for preparing a chip packaging carrier according to embodiment 3 of the present invention.

[0056] Figure 14 Schematic diagram of step 5 of the method for preparing a chip packaging carrier according to embodiment 3 of the present invention.

[0057] Figure 15 Schematic diagram of step 6 of the method for preparing a chip packaging carrier according to embodiment 5 of the present invention.

[0058] Figure 16 Schematic diagram of step 7 of the method for preparing a chip packaging carrier according to embodiment 5 of the present invention.

[0059] Figure 17 Schematic diagram of step 8 of the method for preparing a chip packaging carrier according to embodiment 5 of the present invention.

[0060] Figure 18 Schematic diagram of step 9 of the method for preparing a chip packaging carrier according to embodiment 5 of the present invention.

[0061] Figure 19 1 is a schematic diagram of step 10 of the method for preparing a chip packaging carrier according to embodiment 5 of the present invention.

[0062] Figure 20 1 is a schematic diagram of step 11 of the method for preparing a chip packaging carrier according to embodiment 5 of the present invention.

[0063] Figure 21 1 is a schematic diagram of step 12 of the method for preparing a chip packaging carrier according to embodiment 5 of the present invention.

[0064] Figure 22 It is a structural schematic diagram of a chip packaging carrier unit according to embodiment 4 of the present invention.

[0065] Figure 23 It is a schematic diagram of the first step of step 8 of the method for preparing a chip packaging carrier in embodiment 7 of the present invention.

[0066] Figure 24 It is a schematic diagram of the second step of step 8 of the method for preparing a chip packaging carrier in Example 7 of the present invention.

[0067] Figure 25 Schematic diagram of step 9 of the method for preparing a chip packaging carrier according to embodiment 7 of the present invention.

[0068] Figure 26 1 is a schematic diagram of step 10 of the method for preparing a chip packaging carrier according to embodiment 7 of the present invention.

[0069] Figure 27 It is a structural diagram of the chip packaging carrier unit of Example 6 of the present invention.

[0070] Figure 28 This is a schematic diagram of step 1 of the method for preparing a chip packaging carrier according to embodiment 9 of the present invention.

[0071] Figure 29 This is a schematic diagram of step 2 of the method for preparing a chip packaging carrier according to embodiment 9 of the present invention.

[0072] Figure 30 This is a schematic diagram of step 3 of the method for preparing a chip packaging carrier according to Example 9 of the present invention.

[0073] Figure 31 It is a structural schematic diagram of the chip packaging carrier unit of Example 8 of the present invention.

[0074] Figure 32 This is a schematic diagram of step 1 of the upright chip packaging method according to embodiment 11 of the present invention.

[0075] Figure 33 This is a schematic diagram of step 2 of the upright chip packaging method according to embodiment 11 of the present invention.

[0076] Figure 34 This is a schematic diagram of step 3 of the upright chip packaging method according to embodiment 11 of the present invention.

[0077] Figure 35 This is a schematic diagram of step 4 of the upright chip packaging method according to embodiment 11 of the present invention.

[0078] Figure 36 This is a schematic diagram of step 5 of the upright chip packaging method according to embodiment 11 of the present invention.

[0079] Figure 37 This is a schematic diagram of step 6 of the upright chip packaging method according to embodiment 11 of the present invention.

[0080] Figure 38 It is a schematic diagram of the upright chip packaging structure of embodiment 10 of the present invention.

[0081] Figure 39 It is a schematic diagram of the flip chip packaging structure of Example 12 of the present invention.

[0082] Figure 40This is a schematic diagram of step 12 of the method for preparing a chip packaging carrier according to embodiment 13 of the present invention.

[0083] Figure 41 1 is a schematic diagram of step 13 of the method for preparing a chip packaging carrier according to embodiment 13 of the present invention.

[0084] Figure 42 It is a schematic diagram of step 14 of the method for preparing a chip packaging carrier according to embodiment 13 of the present invention.

[0085] Figure 43 This is a schematic diagram of step 15 of the method for preparing a chip packaging carrier according to embodiment 13 of the present invention.

[0086] Figure 44 1 is a schematic diagram of step 16 of the method for preparing a chip packaging carrier according to embodiment 13 of the present invention.

[0087] Figure 45 This is a schematic diagram of step 17 of the method for preparing a chip packaging carrier according to embodiment 13 of the present invention.

[0088] Figure 46 It is a structural schematic diagram of the chip packaging carrier unit of embodiment 13 of the present invention.

[0089] Figure 47 This is a schematic diagram of step 9 of the method for preparing a chip packaging carrier according to embodiment 14 of the present invention.

[0090] Figure 48 This is a schematic diagram of step 10 of the chip packaging carrier preparation method according to embodiment 14 of the present invention.

[0091] Figure 49 This is a schematic diagram of step 11 of the method for preparing a chip packaging carrier according to embodiment 14 of the present invention.

[0092] Figure 50 It is a schematic diagram of step 12 of the method for preparing a chip packaging carrier according to embodiment 14 of the present invention.

[0093] Figure 51 This is a schematic diagram of step 13 of the method for preparing a chip packaging carrier according to embodiment 14 of the present invention.

[0094] Figure 52 14 is a schematic diagram of step 14 of the method for preparing a chip packaging carrier according to embodiment 14 of the present invention.

[0095] Figure 53 This is a schematic diagram of step 15 of the method for preparing a chip packaging carrier according to embodiment 14 of the present invention.

[0096] Figure 54 1 is a schematic diagram of step 16 of the method for preparing a chip packaging carrier according to embodiment 14 of the present invention.

[0097] Figure 5517 is a schematic diagram of step 17 of the method for preparing a chip packaging carrier according to embodiment 14 of the present invention.

[0098] Figure 56 It is a structural schematic diagram of the chip packaging carrier unit of embodiment 14 of the present invention. [Specific implementation method]

[0099] The chip packaging carrier of the embodiment 1 of the present invention is used for packaging the chip, and its structure is as follows: Figure 10 As shown, it includes a stainless steel carrier sheet 1, a substrate, and multiple unit circuits arranged in a matrix. The carrier sheet 1 is releasably adhered to the bottom surface of the substrate via an anti-sticking layer 2. The unit circuit includes multiple electrodes, including a top electrode and a bottom electrode 3. The anti-sticking layer 2 has bottom electrode holes corresponding to the bottom electrodes 3, and the bottom electrodes 3 are electroplated in the bottom electrode holes. The substrate can have N substrate layers, where N is an integer greater than or equal to 1. Each substrate layer includes a copper-plated resin layer 4 and a circuit layer 6. The circuit layer 6 is arranged on the top surface of the copper-plated resin layer 4, and the copper-plated resin layer 4 has copper pillars 5 corresponding to the electrodes.

[0100] The copper-immersable resin can adopt the copper-immersable resin ink of Taiyo Company PSR-4000BN BLACK / CA-40BN or PSR-4000LEW3 / CA-40LEW3, which can be photolithographically punched or laser punched.

[0101] like Figure 10 As shown, in this embodiment, N=1. If N≥2, the lower end of the copper pillar 5 of the substrate layer is connected to the circuit of the top circuit layer of the lower substrate layer, the upper end is connected to the circuit of the top circuit layer of the substrate layer, and the copper pillar 5 of the bottom substrate layer is connected to the corresponding bottom electrode 3.

[0102] In this embodiment, N=1. The lower end of the copper pillar 5 is connected to the corresponding bottom electrode 3. The substrate layer is the top substrate layer, and the circuit layer 6 thereon includes a top electrode 6-1 and a base island 6-2.

[0103] Embodiment 2 of the present invention is a method for preparing the chip packaging carrier of embodiment 1, comprising the following steps:

[0104] 1) If Figure 1 As shown, the top surface of the stainless steel carrier sheet 1 is covered with a photosensitive anti-sticking layer 2. A hollow pattern corresponding to the shape of the bottom electrode 3 is made on the anti-sticking layer 2. The hollow pattern has a hollow area (bottom electrode hole) 2-1.

[0105] 2) If Figure 2 As shown, the bottom electrode 3 is formed by electroplating in the hollow area (bottom electrode hole) 2 - 1 of the hollow pattern of the anti-sticking layer 2 .

[0106] 3) If Figure 3 As shown, a first copper-platable resin layer 4 is printed on the top surface of the anti-sticking layer 2 and the bottom electrode 3 .

[0107] 4) If Figure 4 As shown, a first through hole 4 - 1 corresponding to the bottom electrode 3 is produced on the first copper-platable resin layer 4 by photolithography or laser drilling, and the bottom surface of the first through hole 4 - 1 is the top surface of the corresponding bottom electrode 3 .

[0108] 5) If Figure 5 As shown, copper is plated in the first through hole 4 - 1 on the first copper-platable resin layer 4 to form a first copper column 5 whose bottom surface is connected to the corresponding bottom electrode 3 and whose top surface is flush with the top surface of the first copper-platable resin layer 4 .

[0109] 6) If Figure 6 As shown, chemical copper deposition is performed on the top surface of the first copper-depositable resin layer 4 and the top surface of the first copper pillar 5 to form a first seed copper layer 6-3. The top surface of the first seed copper layer 6-3 is covered with a first circuit photosensitive film 7.

[0110] 7) If Figure 7 As shown, a first hollow pattern 7-1 corresponding to the first circuit layer 6 is photoetched on the first circuit photosensitive film 7.

[0111] 8) If Figure 8 As shown, copper is plated in the hollow area of ​​the first hollow pattern 7 - 1 of the first circuit photosensitive film 7 to form the main body 6 - 4 of the first circuit layer 6 .

[0112] 9) If Figure 9 As shown, the first circuit photosensitive film 7 is removed by soaking in a chemical solution.

[0113] 10) If Figure 10 As shown, the seed copper layer 6-3 located outside the main body 6-4 of the first circuit layer 6 is etched away to form the first circuit layer 6. The unit circuit of the first circuit layer 6 includes a plurality of top electrodes 6-1 and a base island 6-2 for fixing the mounted chip. Thus, the chip package carrier of Example 1 is obtained.

[0114] Embodiment 3 of the present invention is another method for preparing the chip packaging carrier of embodiment 1, comprising the following steps:

[0115] Steps 1 and 2 of the method for preparing the chip packaging carrier in Example 3 are the same as steps 1 and 2 in Example 2.

[0116] 3) If Figure 11 As shown, the top surface of the anti-sticking layer 2 and the bottom electrode 3 is covered with a first copper column photosensitive film 7'. Figure 12 As shown, a first through hole 7 ′- 1 corresponding to the bottom electrode 3 is photoetched on the first copper column photosensitive film 7 ′, and the bottom surface of the first through hole 7 ′- 1 is the top surface of the corresponding bottom electrode 3 .

[0117] 4) If Figure 13As shown, copper is plated in the first through hole 7 ′- 1 on the first copper pillar photosensitive film 7 ′ to form a first copper pillar 5 whose bottom surface is connected to the corresponding bottom electrode 3 .

[0118] 5) If Figure 14 As shown, after removing the first copper column photosensitive film 7', the first copper-deposited resin layer 4 is printed on the top surface of the anti-sticking layer 2 and the bottom electrode 3, and the first copper-deposited resin layer 4 is ground to expose the top surface of the first copper column 5 on the surface of the first copper-deposited resin layer 4.

[0119] 6) Steps 6 to 9 of the method for preparing the chip packaging carrier in Example 3 are the same as steps 6 to 9 in Example 2.

[0120] The chip packaging carrier of the fourth embodiment of the present invention is used for packaging of flip chips, and its structure is as follows: Figure 22 As shown, the difference from Example 1 is that in this embodiment, N=2, the lower end of the copper pillar 5 of the top substrate layer is connected to the circuit of the top surface circuit layer of the underlying substrate layer, the upper end of the copper pillar 5 of the top substrate layer is connected to the circuit of the top surface circuit layer of the substrate layer, and the copper pillar 5 of the bottom substrate layer is connected to the corresponding bottom electrode 3. In addition, a solder resist ink layer 15 is included. The solder resist ink layer 15 covers the top of the top substrate layer and includes a window corresponding to the unit circuit. The pad 12 of the top electrode 6-1 of the unit circuit is exposed in the window of the solder resist ink layer 15.

[0121] Embodiment 5 of the present invention is a method for preparing the chip packaging carrier of embodiment 4, comprising the following steps:

[0122] Steps 1 to 5 of the method for preparing the chip packaging carrier in Example 5 are the same as steps 1 to 5 in Example 2 or steps 1 to 5 in Example 3.

[0123] 6) If Figure 15 As shown, copper is plated after copper is deposited on the top surface of the first copper-platable resin layer 4 and the top surface of the first copper pillar 5. The top surface of the copper-plated layer 6-5 is covered with a second circuit photosensitive film 8.

[0124] 7) If Figure 16 As shown, a second hollow pattern 8 - 1 corresponding to the first circuit layer 6 is photoetched on the second circuit photosensitive film 8 , and the solid part of the second hollow pattern 8 - 1 has the same shape as the solid part of the first circuit layer 6 .

[0125] 8) If Figure 17 As shown, the copper plating layer 6 - 5 on the top surface of the first copper-platable resin layer 4 is etched.

[0126] 9) If Figure 18 As shown, the second circuit photosensitive film 8 is removed to form the first circuit layer 6.

[0127] 10) If Figure 19As shown, a second copper-plated resin layer 4A is printed on the top surface of the lower substrate layer, and a second through hole 4A-1 corresponding to the electrode is produced on the second copper-plated resin layer 4A by photolithography or laser drilling. The bottom surface of the second through hole 4A-1 is the top surface of the circuit layer 6 of the lower substrate layer.

[0128] 11) If Figure 20 As shown, copper is plated in the second through hole 4A-1 to form a second copper column 5A whose bottom surface is connected to the underlying substrate circuit layer 6 and whose top surface is flush with the top surface of the second copper-platable resin layer 4A.

[0129] 12) If Figure 21 As shown, after copper is deposited on the top surface of the second copper-depositable resin layer 4A, copper is plated and then etched to form a second circuit layer 6A.

[0130] 13) If N>2, repeat steps 6 to 12 until the number of substrate layers reaches N. The second circuit layer 6A on the top surface of the top substrate layer is the top surface circuit layer. The top surface circuit layer includes a top electrode 6-1. The second copper pillar 5A in the top substrate layer is connected to the corresponding top electrode 6-1.

[0131] 14) If Figure 22 As shown, a solder resist ink layer 15 is printed on the top substrate layer, and a window is opened to expose the soldering area by photolithography. The pad 12 of the top electrode 6-1 is plated with solderable metal. At this point, the manufacturing process of the chip package carrier of Example 4 is completed.

[0132] The chip packaging carrier of the embodiment 6 of the present invention is used for embedding the chip in the packaging mode, and the structure is as follows: Figure 27 As shown, the chip package carrier of Example 6, based on Example 1, further includes a crossbar connecting copper pillar 5B corresponding to the top electrode 6-1. The crossbar connecting copper pillar 5B is arranged above the corresponding top electrode 6-1, and the bottom of the crossbar connecting copper pillar 5B is connected to the corresponding top electrode 6-1. The circuit layer 6 of the top substrate layer includes a base island 6-2 for fixing the chip.

[0133] Embodiment 7 of the present invention is a method for preparing the chip packaging carrier of embodiment 6. Steps 1 to 7 of the method for preparing the chip packaging carrier of embodiment 5 are the same as steps 1 to 7 of embodiment 2. Based on step 7 of embodiment 2, the method includes the following steps:

[0134] 8) If Figure 23 As shown, the first hollow pattern 7-1 of the first circuit photosensitive film formed in step 7 of embodiment 2 and the main body 6-4 of the first circuit layer 6 are covered with a third copper pillar photosensitive film 9. The height of the third copper pillar photosensitive film 9 is greater than the thickness of the mounted chip by 5-10 μm. Figure 24 As shown, a third through hole 9 - 1 corresponding to the electrode is photoetched on the third copper column photosensitive film 9 , and the bottom surface of the third through hole 9 - 1 is the top surface of the main body 6 - 4 of the first circuit layer 6 below.

[0135] 9) If Figure 25 As shown, copper is plated in the third through hole 9-1 to form a lintel connecting copper column (third copper column) 5B whose bottom surface is connected to the main body 6-4 of the first circuit layer 6 below and whose top surface is flush with the top surface of the third copper column photosensitive film 9.

[0136] 10) If Figure 26 As shown, the third copper pillar photosensitive film 9 and the first circuit photosensitive film 7 are removed by immersion in a chemical solution, exposing the main body 6-4 of the first circuit layer 6, part of the seed copper layer 6-3 and the lintel connecting copper pillar (third copper pillar) 5B.

[0137] 11) If Figure 27 As shown, the seed copper of the first seed copper layer 6-3 located in the main body 6-4 of the first circuit layer 6 is etched away to form the first circuit layer 6. When N is equal to 1 and the chip adopts a buried capacitance method, the first circuit layer 6 includes a top electrode 6-1 and a base island 6-2. At this point, the preparation process of the chip package carrier according to Example 6 of the present invention is completed.

[0138] The chip packaging carrier of the embodiment 8 of the present invention is used for the upright chip packaging, and its structure is as follows: Figure 31 As shown, the chip package carrier of Example 8, based on Example 1, has an additional substrate layer, i.e., the number of substrate layers N is equal to 2. A third copper-platable resin layer 4B of the top substrate layer overlies the bottom substrate layer. The circuit layer 6B of the top substrate layer includes a plurality of top electrodes 6-1 and a base island 6-2 for securing the chip. The lower ends of the copper pillars 5B in the top substrate layer are connected to the circuitry of the circuit layer 6 on the top surface of the bottom substrate layer, and the upper ends are connected to the corresponding top electrodes 6-1 in the circuit layer 6B on the top surface of the substrate layer.

[0139] Embodiment 9 of the present invention is a method for preparing the chip packaging carrier of embodiment 8. The method for preparing the chip packaging carrier of embodiment 9 is performed on the basis of embodiment 7 and includes the following steps:

[0140] 901) Figure 28 As shown, a third copper-depositable resin layer 4B is filled above the bottom substrate layer, that is, above the first copper-depositable resin layer 4, the first circuit layer 6 and the third copper pillar 5B.

[0141] 902) Figure 29 As shown, the top surface of the third copper pillar 5B is exposed by photolithography or laser drilling on the third copper-depositable resin layer 4B.

[0142] 903) Figure 30 As shown, copper is deposited and plated on the top surface of the third copper-depositable resin layer 4B and the top surface of the third copper pillar 5B to form a copper layer 6C.

[0143] 904) Figure 31As shown, copper layer 6C is etched to form top circuit layer 6B, which includes top electrode 6-1 and chip-mounting island 6-2. A solderable metal layer is electroplated on the top surfaces of top electrode 6-1 and chip-mounting island 6-2, completing the chip package carrier of Example 8 of the present invention.

[0144] The packaging structure of the chip in embodiment 10 of the present invention is as follows Figure 38 As shown, the device includes a face-up chip 10A, a unit carrier, and an encapsulation adhesive layer. The unit carrier includes a substrate and a unit circuit. The unit circuit includes multiple electrodes, including a top electrode 6-1, a bottom electrode 3, and a copper pillar 5 connecting the top electrode 6-1 and the bottom electrode 3. The substrate may include N substrate layers, where N is 1 in this embodiment.

[0145] The substrate layer includes a copper-depositable resin layer 4 and a circuit layer 6. Circuit layer 6 is arranged on top of the copper-depositable resin layer 4 and includes a base island and a top electrode 6-1 to which the front-mounted chip 10A is secured. Copper pillars 5 corresponding to the electrodes are located within the copper-depositable resin layer 4. The upper ends of the copper pillars 5 are connected to the corresponding top electrodes 6-1, and the lower ends are connected to the corresponding bottom electrodes 3. The front-mounted chip 10A is secured to the top surface of the base island.

[0146] The unit circuit also includes a metal crossbeam corresponding to the top electrode 6-1 and a crossbeam connecting copper pillar 5B. The crossbeam connecting copper pillar 5B is arranged above the corresponding top electrode 6-1, and the bottom of the crossbeam connecting copper pillar 5B is connected to the corresponding top electrode 6-1. The packaging glue layer includes a fourth copper-plated resin layer 4C and a plastic sealing glue layer 14. The fourth copper-plated resin layer 4C covers between and above the substrate layer, the front-mounted chip 10A and the copper pillar 5B. The top of the fourth copper-plated resin layer 4C includes a first vertical hole corresponding to a plurality of crossbeam connecting copper pillars 5B and a plurality of second vertical holes corresponding to the electrodes of the front-mounted chip 10A. The metal crossbeam 13-1 is arranged on the top surface of the fourth copper-plated resin layer 4C. The first end of the metal crossbeam 13-1 passes through the first vertical hole to connect to the corresponding crossbeam connecting copper pillar 5B, and the second end of the metal crossbeam 13-1 passes through the second vertical hole to connect to the corresponding electrode 10-1 of the front-mounted chip 10A. The plastic encapsulation layer 14 covers the fourth copper-depositable resin layer 4C and the metal lintel 13 - 1 .

[0147] Embodiment 11 of the present invention is a packaging step of the upright chip of embodiment 10. The upright chip of embodiment 10 is packaged on the chip packaging carrier of embodiment 6, including the following steps:

[0148] 1) If Figure 32 As shown, a plurality of upright chips 10A are fixed in a matrix form on the corresponding base islands 6-2 of the entire chip packaging carrier of Example 6.

[0149] 2) If Figure 33As shown, a fourth copper-immersable resin layer 4C is filled between and above the top substrate layer, the front-mounted chip 10A and the lintel connecting copper pillars 5B.

[0150] 3) If Figure 34 As shown, the fourth copper-depositable resin layer 4C is photoetched or laser-drilled to expose the top surface of the electrode 10-1 of the face-up chip 10A and the top surface of the lintel connecting copper column 5B.

[0151] 4) If Figure 35 As shown, copper is deposited and electroplated on the top surface of the fourth copper-depositable resin layer 4C, the top surface of the electrode 10-1 of the chip 10A, and the top surface of the lintel connecting copper column 5B to form a second metal layer 13.

[0152] 5) If Figure 36 As shown, the second metal layer 13 is etched to form a plurality of metal beams 13 - 1 that connect the copper pillars 5B and the top surface of the electrodes of the chip 10A.

[0153] 6) If Figure 37 As shown, a plastic encapsulation layer 14 is covered on the fourth copper-depositable resin layer 4C and the metal lintel 13 - 1 .

[0154] 7) If Figure 38 As shown, the carrier sheet 1 together with the anti-sticking layer 2 is peeled off from the bottom surface of the substrate, and the plastic-sealed package body is cut to obtain the single-chip package structure of Example 10.

[0155] The packaging structure of the flip chip of embodiment 12 of the present invention is packaged using the chip packaging carrier of embodiment 4. Figure 39 As shown, the flip chip 10B includes a unit carrier and an encapsulation adhesive layer 14. The unit carrier includes a substrate, a solder mask ink layer 15, and a unit circuit. The unit circuit includes multiple electrodes, including a top electrode 6-1 and a bottom electrode 3. The substrate may include N substrate layers. In this embodiment, N is equal to 2, i.e., it includes a bottom substrate layer and a top substrate layer.

[0156] The bottom substrate layer includes a copper-depositable resin layer 4 and a circuit layer 6. The circuit layer 6 is arranged on top of the copper-depositable resin layer 4. Copper pillars 5 corresponding to the electrodes are located in the copper-depositable resin layer 4. The upper ends of the copper pillars 5 are connected to the corresponding circuits in the circuit layer 6. The lower ends are connected to the corresponding bottom electrodes 3.

[0157] The top substrate layer includes a copper-plated resin layer 4A and a circuit layer 6A. Circuit layer 6A is arranged on top of copper-plated resin layer 4A. Copper pillars 5A corresponding to electrodes are located in copper-plated resin layer 4A. The upper ends of copper pillars 5A are connected to top electrodes 6A-1 corresponding to circuit layer 6A. The lower ends of copper pillars 5A are connected to corresponding circuits in the bottom circuit layer 6.

[0158] The solder resist ink layer 15 covers the top substrate layer. The solder resist ink layer 15 includes windows corresponding to the unit circuits. The pads 12 of the top electrodes 6A- 1 of the unit circuits are exposed in the windows of the solder resist ink layer 15 .

[0159] The flip chip 10B is seated on the pads 12 of the top electrode 6A-1, and the electrodes of the flip chip 10B are respectively soldered to the corresponding pads 12 of the top electrode 6A-1. The encapsulation layer 14 is encapsulated on the solder resist ink layer 15 and the flip chip 10B.

[0160] The method for preparing the chip packaging carrier of embodiment 13 of the present invention is as follows Figures 40 to 46 As shown, the number of substrate layers N is equal to 2, which can be achieved in step 11 (eg, Figure 27 The manufacturing process of the carrier board includes the following steps:

[0161] 12) If Figure 40 As shown, a fifth copper-depositable resin layer 4D is filled above the first copper-depositable resin layer 4, the first circuit layer 6 and the third copper pillar 5B. The fifth copper-depositable resin layer 4D is ground to expose the top surface of the third copper pillar 5B.

[0162] 13) If Figure 41 As shown, copper is deposited on the top surface of the fifth copper resin layer 4D and the top surface of the third copper pillar 5B to form a second seed copper layer 6D-3.

[0163] 14) If Figure 42 As shown, the top surface of the second seed copper layer 6D- 3 is covered with a fourth circuit photosensitive film 21 .

[0164] 15) If Figure 43 As shown, a third hollow pattern 21 - 1 corresponding to the third circuit layer 6D is photoetched on the fourth circuit photosensitive film 21 .

[0165] 16) If Figure 44 As shown, copper is plated in the hollow area of ​​the third hollow pattern 21-1 of the fourth circuit photosensitive film 21 to form the main body 6D-4 of the third circuit layer 6D, and a solderable metal layer 6D-5 is plated on the surface of the main body 6D-4 of the third circuit layer.

[0166] 17) If Figure 45 As shown, the fourth circuit photosensitive film 21 is removed, exposing the main body of the third circuit layer 6D and the seed copper 6D-3 outside the main body area of ​​the third circuit layer 6D.

[0167] 18) If Figure 46As shown, the seed copper 6D-3 outside the third circuit layer main body 6D-4 area is etched away to form the third circuit layer 6D. The third circuit layer 6D is the top circuit layer of the carrier board, and the first circuit layer 6 is the middle circuit layer of the carrier board. This completes the chip packaging carrier board of this embodiment.

[0168] The method for preparing the chip packaging carrier of embodiment 14 of the present invention is as follows Figures 6 to 8 ,as well as Figures 47 to 56 The number N of substrate layers of the package carrier in embodiment 14 of the present invention is equal to 3, and the method can be performed based on steps 6 to 8 of the method for preparing the chip package carrier in embodiment 2 of the present invention. The carrier manufacturing process includes the following steps:

[0169] 6) If Figure 6 As shown, chemical copper deposition is performed on the top surface of the lower copper-depositable resin layer (first copper-depositable resin layer) 4 and the top surface of the lower copper pillar (first copper pillar) 5 to form a lower seed copper layer (first seed copper layer) 6-3. The top surface of the first seed copper layer 6-3 is covered with a lower circuit photosensitive film (first circuit photosensitive film) 7.

[0170] 7) If Figure 7 As shown, a lower hollow pattern (first hollow pattern) 7-1 corresponding to the lower circuit layer (first circuit layer) 6 is photoetched on the lower circuit photosensitive film (first circuit photosensitive film) 7.

[0171] 8) If Figure 8 As shown, copper is plated in the hollow area of ​​the first hollow pattern 7-1 of the lower circuit photosensitive film (first circuit photosensitive film) 7 to form the main body 6-4 of the lower circuit layer (the main body of the first circuit layer 6).

[0172] 9) If Figure 47 As shown, a second copper column photosensitive film 8' is covered above the main body 6-4 of the lower circuit layer 6, and a plurality of upper through holes 8-1 are photoetched on the second copper column photosensitive film 8'. The bottom surface of the upper through holes 8-1 is the top surface of the main body 6-4 of the lower circuit layer 6.

[0173] 10) If Figure 48 As shown, copper is plated in the upper through hole 8-1 to form a plurality of upper copper pillars 5A whose bottom surfaces are connected to the main body 6-4 of the lower circuit layer 6 and whose top surfaces are flush with the top surface of the second copper pillar photosensitive film 8'.

[0174] 11) If Figure 49 As shown, the lower first circuit photosensitive film 7 and the upper second copper pillar photosensitive film 8' are removed by soaking with chemical solution, exposing the main body 6-4 of the lower circuit layer and the upper copper pillar 5A. The seed copper 6-3 of the lower seed copper layer outside the main body of the lower circuit layer is etched away to form the lower circuit layer 6.

[0175] 12) If Figure 50As shown, an upper copper-depositable resin layer 4A is filled above the lower copper-depositable resin layer 4, the lower circuit layer 6 and the upper copper pillar 5A, and the upper copper-depositable resin layer 4A is ground to expose the top surface of the upper copper pillar 5A.

[0176] 13) If Figure 51 As shown, repeat steps 6 to 12 to bring the number of substrate layers to 3.

[0177] 14) If Figure 52 As shown, copper is deposited on the top surface of the uppermost copper-depositable resin layer 4A2 and the top surface of the uppermost copper pillar 5A2 to form a top-layer seed copper layer 6A-3.

[0178] 15) If Figure 53 As shown, the top surface of the top seed copper layer is covered with a top third circuit photosensitive film 17 .

[0179] 16) If Figure 54 As shown, a hollow pattern corresponding to the top circuit layer 6A is photoetched on the top third circuit photosensitive film 17, and copper is plated in the hollow area of ​​the hollow pattern of the top third circuit photosensitive film 17 to form the main body 6A-4 of the top surface circuit layer 6A, and a solderable metal layer 6A-5 is plated on the surface of the top surface circuit layer main body 6A-4.

[0180] 17) If Figure 55 As shown, the top third circuit photosensitive film 17 is removed, exposing the main body 6A-4 of the top circuit layer and the seed copper 6A-3 outside the area of ​​the main body 6A-4 of the top circuit layer.

[0181] like Figure 56 As shown, the seed copper 6A-3 outside the top surface circuit layer main body 6A-4 area is etched away to form the top surface circuit layer 6A. The top surface circuit layer 6A includes a top electrode 6-1. The topmost copper pillar 5A2 is connected to the corresponding top electrode 6-1. Thus, the chip package carrier of this embodiment is completed. The above embodiment of the present invention has the following beneficial effects:

[0182] 1) The chip packaging substrate is prepared by stacking layers, without the need for flipping, and the process is simple, the process difficulty is low, and the preparation cost is low.

[0183] 2) The number of substrate layers can be adjusted according to the complexity of the circuit, making it easier to arrange more complex circuits in a smaller space.

[0184] 3) Use copper-plated resin to make the substrate, and use the characteristic that the surface of the copper-plated resin can be metallized to achieve a multi-layer routing stacking structure.

[0185] 4) The N-layer substrate can realize the interconnection between any two or more adjacent electrical networks, thereby meeting the layout of complex circuit networks.

Claims

1. A carrier for chip packaging, comprising a carrier sheet, a substrate, and a plurality of unit circuits arranged in a matrix, wherein the unit circuits include a plurality of electrodes, each of which includes a top electrode and a bottom electrode, and the carrier sheet is releasably adhered to the bottom surface of the substrate, characterized in that: The substrate includes N substrate layers, where N is an integer greater than 1; the substrate layer includes a copper-plated resin layer and a circuit layer, the circuit layer is arranged on the top surface of the copper-plated resin layer, and the copper-plated resin layer includes a plurality of copper pillars; the lower ends of the copper pillars are connected to the circuits of the circuit layer on the top surface of the next substrate layer, and the upper ends are connected to the circuits of the circuit layer on the top surface of the current substrate layer; the circuit layer of the top substrate layer includes the top electrode, and the copper pillars of the bottom substrate layer are connected to the corresponding bottom electrodes; The carrier board production process includes the following steps: 101) Covering the top surface of the carrier sheet with an anti-sticking layer, forming a hollow pattern corresponding to the shape of the bottom electrode on the anti-sticking layer, and forming the bottom electrode by electroplating in the hollow pattern area of ​​the anti-sticking layer; 102) Disposing a first copper-deposited resin layer on the top surface of the anti-sticking layer and the bottom electrode, and photoetching or laser drilling a first through hole corresponding to the bottom electrode on the first copper-deposited resin layer, with the bottom surface of the first through hole being the top surface of the corresponding bottom electrode; or covering the top surface of the anti-sticking layer and the bottom electrode with a first copper pillar photosensitive film, and photoetching a first through hole corresponding to the bottom electrode on the first copper pillar photosensitive film, with the bottom surface of the first through hole being the top surface of the corresponding bottom electrode; 103) Plating copper in the first through-hole on the first copper-depositable resin layer to form a first copper pillar whose bottom surface is connected to the corresponding bottom electrode and whose top surface is flush with the top surface of the first copper-depositable resin layer; or plating copper in the first through-hole on the first copper pillar photosensitive film to form a first copper pillar whose bottom surface is connected to the corresponding bottom electrode, removing the first copper pillar photosensitive film, and then providing a first copper-depositable resin layer on the top surface of the anti-sticking layer and the bottom electrode, and grinding the first copper-depositable resin layer to expose the top surface of the first copper pillar on the surface of the first copper-depositable resin layer; 104) Copper is deposited on the top surface of the first copper-depositable resin layer and the first copper pillar to form a first circuit layer. The first copper-depositable resin layer and the first circuit layer constitute the bottommost substrate layer.

2. The carrier board according to claim 1, characterized in that It includes a beam connecting copper column corresponding to the top electrode, the beam connecting copper column is arranged above the corresponding top electrode, and the bottom of the beam connecting copper column is connected to the corresponding top electrode; the circuit layer of the top substrate layer includes a base island for fixing the chip.

3. The carrier board according to claim 1, characterized in that It comprises a solder resist ink layer which covers the top substrate layer and includes windows corresponding to the unit circuits. The pads of the top electrodes of the unit circuits are exposed in the windows.

4. The carrier board according to claim 1, wherein: Step 104, after copper is deposited on the top surface of the first copper-depositable resin layer, to form the first circuit layer, includes the following steps: 401) Copper is deposited on the top surface of the first copper-depositable resin layer and the top surface of the first copper pillar to form a first seed copper layer; and a first circuit photosensitive film is covered on the top surface of the first seed copper layer; 402) Photoetching a first hollow pattern corresponding to the first circuit layer on the first circuit photosensitive film, and copper plating the first hollow pattern area of ​​the first circuit photosensitive film to form the main body of the first circuit layer; 403) The first circuit photosensitive film is removed, and the seed copper of the first seed copper layer located outside the main body of the first circuit layer is etched away to form the first circuit layer.

5. The carrier board according to claim 1, characterized in that Step 104, after copper is deposited on the top surface of the first copper-depositable resin layer, to form the first circuit layer, includes the following steps: 501) copper plating is performed after copper is deposited on the top surface of the first copper-depositable resin layer and the top surface of the first copper pillar; and a second circuit photosensitive film is covered on the top surface of the copper-plated layer; 502) A first circuit layer pattern is formed on the second circuit photosensitive film, and the copper layer outside the first circuit layer pattern is etched away, and the second circuit photosensitive film is removed.

6. The carrier board according to claim 4, characterized in that The carrier board production process includes the following steps: 601) Disposing a second copper-depositable resin layer on the top surface of the lower substrate layer, and forming a plurality of second through holes in the second copper-depositable resin layer by photolithography or laser drilling, wherein the bottom surface of the second through holes is the top surface of the circuit layer of the lower substrate layer; 602) Copper is plated in the second through hole to form a second copper pillar whose bottom surface is connected to the circuit layer of the underlying substrate layer and whose top surface is flush with the top surface of the second copper-depositable resin layer; 603) After copper is deposited on the second copper-depositable resin layer and the top surface of the second copper pillar, a second circuit layer is formed. The second copper-depositable resin layer, the second copper pillar and the second circuit layer constitute a second substrate layer. 604) Repeat steps 601 to 603 until the number of substrate layers reaches N. The second circuit layer of the Nth substrate layer is the top circuit layer. The top circuit layer includes the top electrode. The second copper pillar in the top substrate layer is connected to the corresponding top electrode.

7. The carrier board according to claim 6, characterized in that: The chip is embedded in one or more substrate layers of the carrier board. The carrier board manufacturing process includes the following steps: 701) Covering the main body of the first circuit layer formed in step 402 with a third copper pillar photosensitive film, and photoetching a plurality of third through holes on the third copper pillar photosensitive film; 702) The bottom surface of the third through hole is the top surface of the main body of the first circuit layer below; 703) Copper is plated in the third through hole to form a third copper pillar whose bottom surface is connected to the main body of the first circuit layer below and whose top surface is flush with the top surface of the third copper pillar photosensitive film; 704) Remove the first circuit photosensitive film and the third copper pillar photosensitive film to expose the main body of the first circuit layer and the third copper pillar; etch away the seed copper of the first seed copper layer outside the main body of the first circuit layer to form the first circuit layer.

8. A chip packaging structure, comprising a chip, a unit carrier, and a packaging layer, wherein the unit carrier comprises a substrate and a unit circuit, the unit circuit comprises a plurality of electrodes, the electrodes comprising a top electrode and a bottom electrode, the electrodes of the chip being electrically connected to the top electrode; characterized in that: The unit carrier is formed by dividing the carrier according to claim 1, and the unit circuit is the unit circuit according to claim 1.

9. The packaging structure according to claim 8, wherein: The chip is a front-mounted chip, and the circuit layer of the top substrate layer includes a base island for fixing the chip, and the front-mounted chip is fixed on the top surface of the base island; the unit circuit includes a metal beam corresponding to the top electrode and a beam-connected copper column, the beam-connected copper column is arranged above the corresponding top electrode, and the bottom of the beam-connected copper column is connected to the corresponding top electrode; the packaging layer includes a fourth copper-plated resin layer and a plastic encapsulation layer, and the fourth copper-plated resin layer covers the top substrate layer, the front-mounted chip and the beam-connected copper column; the top of the fourth copper-plated resin layer includes a first vertical hole corresponding to a plurality of beam-connected copper columns and a plurality of second vertical holes corresponding to the front-mounted chip electrodes; the metal beam is arranged on the top surface of the fourth copper-plated resin layer, the first end of the metal beam passes through the first vertical hole to be connected to the corresponding beam-connected copper column, and the second end of the metal beam passes through the second vertical hole to be connected to the corresponding front-mounted chip electrode; the plastic encapsulation layer covers the fourth copper-plated resin layer and the metal beam.

10. The packaging structure according to claim 9, wherein: The packaging process of the chip includes the following steps: 1001) Fixing the upright chip on the base island; 1002) Covering the top substrate layer, the front-mounted chip, and the lintel connecting copper pillars with a fourth copper-depositable resin layer; 1003) Photolithography or laser drilling is performed on the fourth copper-depositable resin layer to expose the top surface of the front-mounted chip electrode and the top surface of the lintel connecting copper pillar; 1004) Copper is deposited and electroplated on the top surface of the fourth copper-depositable resin layer, the top surface of the chip electrodes, and the top surface of the copper pillars connecting the lintels to form a second metal layer, and the second metal layer is etched to form a plurality of metal lintels. 1005) Covering the fourth copper-depositable resin layer and the metal lintel with a plastic encapsulant layer.

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