Electronic package and method for manufacturing the same

Abstract

The present invention relates to an electronic package and a manufacturing method thereof, which includes embedding a circuit board and a circuit block in a coating layer, forming circuit structures on two opposite surfaces of the coating layer, and disposing electronic components on one of the circuit structures, so as to separately embed the circuit block and the circuit board in the coating layer to separate current conduction paths, prevent the circuit board from overheating, avoid the problem of warping of the circuit board, and improve the structural strength of the coating layer through separately embedding the circuit block and the circuit board in the coating layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to an electronic package having a composite substrate and a manufacturing method thereof. Background Art

[0002] With the booming development of the electronics industry, electronic products are gradually moving towards the development trend of multi-function and high performance. Currently, there are many technologies applied in the field of chip packaging, such as flip-chip type packaging modules like Chip Scale Package (CSP for short), Direct Chip Attached (DCA for short), or Multi-Chip Module (MCM for short), or stacking chips three-dimensionally to integrate them into a three-dimensional integrated circuit (3D IC) chip stacking module.

[0003] Figure 1 FIG. 1 is a cross-sectional schematic view of a conventional semiconductor package 1. First, a silicon interposer (TSI for short) 10 having opposite transfer side 10a and chip placement side 10b is provided. The silicon interposer 10 has a plurality of through-silicon vias (TSV for short) 100 connecting the chip placement side 10b and the transfer side 10a. A circuit structure 11 such as an RDL (redistribution layer) type is formed on the chip placement side 10b for attaching a semiconductor chip 15 with a smaller pitch of solder bumps 150. Then, the silicon interposer 10 is disposed on a packaging substrate 13 with a larger line pitch through a plurality of conductive elements 18 at its transfer side 10a, and the packaging substrate 13 is electrically connected to these through-silicon vias 100. Next, a packaging colloid 16 is formed on the packaging substrate 13 to cover the semiconductor chip 15 and the silicon interposer 10. Finally, a plurality of solder balls 12 are formed on the under-side ball pads 130 of the packaging substrate 13 for being placed on a circuit board 1'.

[0004] In the conventional semiconductor package 1, power / signal transmission between the semiconductor chip 15 and the packaging substrate 13 is carried out via the circuit structure 11.

[0005] However, with the increasing demand for product functionality, the functional requirements of the semiconductor chip 15 also increase accordingly. Therefore, the pitch of the contacts (such as solder bumps 150) of the semiconductor chip 15 and the circuit layout density of the circuit structure 11 increase accordingly. In this case, the volume of the RDL type circuit structure 11 is too small, resulting in extremely weak structural strength, and thus it is easily affected by high temperature and warps, causing the circuit of the circuit structure 11 to break.

[0006] On the other hand, if in order to avoid the circuit breakage of the circuit structure 11, the circuit of the circuit structure 11 needs to be widened to strengthen its structural strength through the metal material of the circuit and avoid warping, but the circuit structure 11 will not be able to meet the requirements of fine circuits, so it is difficult to increase the circuit layout density of the circuit structure 11, resulting in the inability to meet the high-density (or multi-functional) contact requirements of the semiconductor chip 15.

[0007] Therefore, how to overcome the above-mentioned various problems of the prior art has actually become an urgent problem to be solved at present. Summary of the Invention

[0008] In view of the above-mentioned various defects of the prior art, the present invention provides an electronic package and a manufacturing method thereof, which can improve the structural strength.

[0009] The electronic package of the present invention includes: a coating layer having opposite first and second surfaces; a circuit board embedded in the coating layer; a circuit block embedded in the coating layer; a first circuit structure formed on the first surface of the coating layer and electrically connecting the circuit board and the circuit block; an electronic component disposed on the first circuit structure and electrically connecting the first circuit structure; and a second circuit structure formed on the second surface of the coating layer and electrically connecting the circuit board and the circuit block.

[0010] The present invention also provides a manufacturing method of an electronic package, including: separately disposing a circuit board and at least one circuit block on a carrier; forming a coating layer on the carrier to coat the circuit board and the circuit block, wherein the coating layer has opposite first and second surfaces, and the coating layer is bonded to the carrier with its second surface; forming a first circuit structure on the first surface of the coating layer to electrically connect the first circuit structure to the circuit board and the circuit block; disposing an electronic component on the first circuit structure and electrically connecting the electronic component to the first circuit structure; removing the carrier; and forming a second circuit structure on the second surface of the coating layer and electrically connecting the second circuit structure to the circuit board and the circuit block.

[0011] In the foregoing electronic package and its manufacturing method, a plurality of the circuit blocks are separately embedded in the coating layer.

[0012] In the foregoing electronic package and its manufacturing method, the circuit board and the circuit block are separated from each other.

[0013] In the foregoing electronic package and its manufacturing method, the circuit board is provided with a receiving space for disposing the circuit block, and the coating layer is further formed in the receiving space to coat the circuit block.

[0014] In the foregoing electronic package and its manufacturing method, the circuit board is formed with a plurality of grooves. For example, the plurality of grooves form a cross-shaped groove structure. Further, the coating layer is also formed in the grooves.

[0015] In the foregoing electronic package and its manufacturing method, a plurality of conductive structures are also embedded in the coating layer.

[0016] In the foregoing electronic package and its manufacturing method, it further includes encapsulating the electronic component with an encapsulation layer.

[0017] In the foregoing electronic package and its manufacturing method, it further includes forming a plurality of conductive elements on the second circuit structure.

[0018] In the foregoing electronic package and its manufacturing method, the circuit block has at least one insulator or at least one semiconductor base, and at least one conductive pillar embedded in the insulator or the semiconductor base. For example, a circuit portion electrically connecting the conductive pillar is formed on at least one of the opposite sides of the insulator or the semiconductor base.

[0019] In the foregoing electronic package and its manufacturing method, the insulator is an encapsulation material, and the semiconductor base contains silicon.

[0020] In the foregoing electronic package and its manufacturing method, the circuit board is a circuit structure without a core layer.

[0021] In the foregoing electronic package and its manufacturing method, a plurality of the electronic components are provided on the first circuit structure, and there is a gap between at least two of the plurality of electronic components, so that the circuit block is correspondingly located at the gap to electrically bridge the two electronic components.

[0022] As can be seen from the above, in the electronic package and its manufacturing method of the present invention, mainly by separately embedding the circuit block and the circuit board in the coating layer to separate the current conduction paths, therefore, compared with the prior art, the circuit board of the present invention will not overheat, thus avoiding the problem of warping of the circuit board, and further avoiding the problem of fracture of the circuit layer of the circuit board, and by separately embedding the circuit block and the circuit board in the coating layer, the structural strength of the coating layer can be improved. Description of the Drawings

[0023] Figure 1 It is a schematic cross-sectional view of a conventional semiconductor package.

[0024] Figures 2A to 2H It is a schematic cross-sectional view of the manufacturing method of the electronic package of the present invention.

[0025] Figure 2A-1 、 Figure 2A-2 、 Figure 2A-3 、 Figure 2A-4 、 Figure 2A-5 andFigure 2A-6 for Figure 2A Schematic cross-sectional views of various embodiments of circuit blocks.

[0026] Figure 3 for Figure 2H A cross-sectional schematic diagram of the subsequent process.

[0027] Figure 4A FIG. 1 is a top view of another embodiment of the composite substrate of the electronic package of the present invention.

[0028] Figure 4B FIG. 4 is a cross-sectional schematic diagram of another embodiment of the electronic package of the present invention.

[0029] Description of Reference Numerals

[0030] 1: Semiconductor package

[0031] 1': Circuit board

[0032] 10: Silicon interposer

[0033] 10a: Transfer side

[0034] 10b: Chip placement side

[0035] 100: Conductive silicon via

[0036] 11: Line structure

[0037] 12: Solder balls

[0038] 13,30: Package substrate

[0039] 130: Ball planting pad

[0040] 15: Semiconductor chips

[0041] 150: Solder bumps

[0042] 16: Encapsulation colloid

[0043] 18,28: Conductive components

[0044] 2,4: Electronic packaging

[0045] 2a, 4a: Composite substrate

[0046] 20,40: Circuit board

[0047] 200: Insulation layer

[0048] 201: Circuit layer

[0049] 21: First line block

[0050] 21': Line block

[0051] 21a, 21b, 21c: Circuit section

[0052] 210, 220: Insulator

[0053] 211, 221: Conductive post

[0054] 22: Second circuit block

[0055] 23: Coating layer

[0056] 23a: First surface

[0057] 23b: Second surface

[0058] 24: First circuit structure

[0059] 240: First insulating layer

[0060] 241: First circuit redistribution layer

[0061] 242: Insulating protective layer

[0062] 243: Under-bump metal layer

[0063] 25, 25’: Electronic component

[0064] 25a: Active surface

[0065] 25b: Non-active surface

[0066] 250: Electrode pad

[0067] 251: Conductive bump

[0068] 252, 31: Underfill

[0069] 26: Encapsulation layer

[0070] 26a: Surface

[0071] 27: Second circuit structure

[0072] 270: Second insulating layer

[0073] 271: Second circuit redistribution layer

[0074] 33: Heat sink

[0075] 330: Top sheet

[0076] 331: Support leg

[0077] 34: Thermal adhesive

[0078] 35: Adhesive layer

[0079] 41, 42, 43, 44: Block

[0080] 49: Conductive structure

[0081] 9: Carrier

[0082] 90: Release layer

[0083] 91: Bonding layer

[0084] D: Diameter

[0085] H, h1, h2: Height

[0086] L: Cutting path

[0087] S: Accommodating space

[0088] V: Cross-shaped groove structure

[0089] V1: First groove

[0090] V2: Second groove. Detailed implementation manners

[0091] The following describes the implementation manners of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0092] It should be noted that the structures, ratios, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limited conditions under which the present invention can be implemented. Therefore, they do not have technical substantive meanings. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope that can be covered by the technical content disclosed in the present invention. At the same time, the terms such as "upper", "first", "second", and "one" cited in this specification are only for the convenience of clear description and are not used to limit the scope under which the present invention can be implemented. The change or adjustment of their relative relationships, without substantial change in the technical content, should also be regarded as the scope within which the present invention can be implemented.

[0093] Figures 2A to 2H It is a schematic cross-sectional view of the manufacturing method of the electronic package 2 of the present invention.

[0094] As Figure 2A shown, a circuit board 20 having at least one accommodating space S is disposed on a carrier 9, and at least one first circuit block 21 and at least one second circuit block 22 are disposed in the accommodating space S, so that the circuit board 20, the first circuit block 21, and the second circuit block 22 are arranged at intervals and do not contact each other.

[0095] In this embodiment, the circuit board 20 has a coreless circuit structure, which includes at least one insulating layer 200 and a circuit layer 201 disposed on the insulating layer 200. For example, a fan out type circuit layer 201 is formed in the form of a redistribution layer (RDL), and its material is copper. The material for forming the insulating layer 200 is a dielectric material such as Polybenzoxazole (PBO), Polyimide (PI), Prepreg (PP), or a solder resist material such as green paint or graphite.

[0096] In addition, the first circuit block 21 is a substrate embodiment, which has an insulator 210 and at least one conductive pillar 211 embedded in the insulator 210. For example, the width (diameter) of the conductive pillar 211 is at most 50 micrometers (um). Specifically, at least one of the opposite sides of the insulator 210 can be formed with a circuit portion 21a (such as the single-sided circuit portion 21a shown in Figure 2A-2 or the double-sided circuit portions 21a, 21b shown in Figure 2A-1 ) for electrically connecting the conductive pillar 211 as in the form of a fanout type redistribution layer (RDL). The material for forming the insulator 210 is such as polyimide (PI), dry film, an encapsulation colloid or molding compound such as epoxy resin, which can be formed by lamination or molding, but is not limited to the above. It should be understood that the first circuit block 21 can also use a semiconductor base, which contains materials such as silicon (Si), glass or other suitable substrates to replace the insulator 210.

[0097] Furthermore, the second circuit block 22 is a substrate embodiment. Similar to the first circuit block 21, it has an insulator 220 and at least one conductive pillar 221 embedded in the insulator 220, but does not have the circuit portions 21a, 21b, as shown in Figure 2A-3 . For example, the conductive pillar 221 is only exposed on one side of the insulator 220 to bond with the carrier 9, and the height h2 of the second circuit block 22 is higher than the height h1 of the circuit board 20 and the height h1 of the first circuit block 21 (i.e., h2 > h1), and the height h1 of the circuit board 20 is approximately equal to the height h1 of the first circuit block 21. It should be understood that the form of the circuit block can be adjusted as needed to be the first circuit block 21 shown in Figure 2A-1 , the second circuit block 22 shown in Figure 2A-3 orFigure 2A-2 There is no particular limitation on embodiments such as the circuit block 21' shown.

[0098] In another embodiment, the first circuit block 21 may be formed by stacking a plurality of insulators 210 (or semiconductor bases) having the conductive posts 211 and a plurality of circuit portions 21c in the form of, for example, fan-out redistribution layers (RDLs), and the conductive posts 211 in each of the insulators 210 (or semiconductor bases) are electrically connected to the plurality of circuit portions 21c. Among them, the widths (diameters) of the conductive posts 211 in each of the insulators 210 (or semiconductor bases) may be of the same size or different sizes. As Figures 2A-4 to 2A-6 shown, the widths (diameters) of the conductive posts 211 in the upper insulator 210 (or semiconductor base) may be the same as or different from the widths (diameters) of the conductive posts 211 in the lower insulator 210 (or semiconductor base). For example, the widths (diameters) of the conductive posts 211 in the lowermost insulator 210 (or semiconductor base) are larger. In addition, at least one of the opposite outer sides of the first circuit block 21 may be formed with the circuit portions 21a, 21b as required to electrically connect the conductive posts 211 in the insulator 210 (or semiconductor base) (such as Figure 2A-4 the bilateral circuit portions 21a, 21b shown or as Figure 2A-5 the unilateral circuit portion 21a shown). It should be understood that the opposite outer sides of the first circuit block 21 may also be the insulators 210 (or semiconductor bases) without disposing the circuit portions 21a, 21b, 21c, as Figure 2A-6 shown.

[0099] In addition, the carrier 9 is, for example, a plate body of a semiconductor material (such as silicon or glass), on which a release layer 90 is formed for the circuit board 20 and these circuit blocks (such as the first circuit block 21, the second circuit block 22 or Figure 2A-2 the circuit block 21' shown) to be disposed on the release layer 90 via a bonding layer 91 such as an adhesive.

[0100] As Figure 2B shown, a coating layer 23 is formed on the carrier 9 (release layer 90) so that the coating layer 23 covers the circuit board 20, the first circuit block 21 and the second circuit block 22, and the coating layer 23, the circuit board 20, the first circuit block 21 and the second circuit block 22 form a composite substrate 2a, and the upper surfaces of the second circuit block 22, the first circuit block 21 and the circuit board 20 are all exposed outside the coating layer 23.

[0101] In this embodiment, the coating layer 23 is an insulating material, such as polyimide (PI for short), dry film, encapsulation colloid or encapsulation material (molding compound) such as epoxy resin. For example, the coating layer 23 can be formed on the carrier 9 (release layer 90) by methods such as liquid encapsulation, spraying, lamination or compression molding.

[0102] In addition, the coating layer 23 has opposite first and second surfaces 23a and 23b, and the coating layer 23 is bonded to the carrier 9 (release layer 90) with its second surface 23b, and a leveling process is performed as required, so that the conductive posts 221 of the second circuit block 22, the circuit portion 21a of the first circuit block 21, and the circuit layer 201 of the circuit board 20 are all exposed on the first surface 23a of the coating layer 23. For example, by grinding, part of the material of the second circuit block 22 and part of the material of the coating layer 23 are removed, so that the upper surfaces of the second circuit block 22, the first circuit block 21 and the circuit board 20 are flush with the first surface 23a of the coating layer 23.

[0103] Therefore, the composite substrate 2a is separated and embedded in the coating layer 23 via the first and second circuit blocks 21, 22 and the circuit board 20 to enhance the structural strength of the coating layer 23.

[0104] As Figure 2C shown, a first circuit structure 24 is formed on the first surface 23a of the coating layer 23, the circuit board 20, the first circuit block 21 and the second circuit block 22, and the first circuit structure 24 is electrically connected to the circuit board 20, the first circuit block 21 and the second circuit block 22.

[0105] In this embodiment, the first circuit structure 24 includes at least one first circuit redistribution layer (RDL) 241 that electrically connects the conductive posts 221, the circuit layer 201 and the circuit portion 21a. For example, the material for forming the first circuit redistribution layer 241 is copper.

[0106] In addition, the first circuit structure 24 may further include at least one first insulating layer 240 for disposing the first circuit redistribution layer 241, and the material for forming the first insulating layer 240 is a dielectric material such as polybenzoxazole (abbreviated as PBO), polyimide (abbreviated as PI), prepreg (abbreviated as PP), etc. It should be understood that multiple layers of the first circuit redistribution layer 241 can be formed via the first insulating layer 240. Further, an insulating protection layer 242 such as a solder mask can be formed on the outermost first insulating layer 240 of the first circuit structure 24, and a part of the outermost first circuit redistribution layer 241 is exposed.

[0107] Such as Figure 2D As shown, at least one electronic component 25, 25' is connected to the first circuit structure 24.

[0108] In this embodiment, a plurality of electronic components 25, 25' are arranged on the first circuit structure 24, and the electronic components 25, 25' are active components, passive components, or a combination of the two. Among them, the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor. For example, the electronic component 25, 25' is a semiconductor chip, which has opposite working surfaces 25a and non-working surfaces 25b, and the electrode pads 250 on its working surface 25a are disposed on the first circuit redistribution layer 241 in a flip-chip manner via a plurality of conductive bumps 251 such as solder materials and are electrically connected to the first circuit redistribution layer 241, and the conductive bumps 251 are coated with underfill 252; or, the electronic component 25, 25' is disposed on the first circuit structure 24 with its non-working surface 25b, and can be electrically connected to the first circuit redistribution layer 241 in a wire bonding manner via a plurality of bonding wires (not shown); or it is electrically connected to the first circuit redistribution layer 241 through a conductive material such as conductive adhesive or solder (not shown). However, the manner in which the electronic component 25, 25' is electrically connected to the first circuit redistribution layer 241 is not limited to the above.

[0109] In addition, there is a gap between at least two of the plurality of electronic components 25, 25', so that the first circuit block 21 is correspondingly located at the gap, and the first circuit block 21 electrically bridges the two electronic components 25, 25'.

[0110] Also, an under bump metallurgy (UBM) (not shown) can be formed on the outermost first circuit redistribution layer 241 to facilitate the bonding of the conductive bump 251.

[0111] Such as Figure 2EAs shown, a packaging layer 26 is formed on the first circuit structure 24 so that the packaging layer 26 covers the electronic components 25, 25' and the underfill 252. Then, the carrier 9 and the release layer 90 are removed to expose the bonding layer 91 and the second surface 23b of the coating layer 23.

[0112] In this embodiment, the packaging layer 26 is an insulating material, such as polyimide (PI for short), dry film, a packaging colloid or a molding compound such as epoxy resin, which can be formed on the first circuit structure 24 by lamination or molding. It should be understood that the material for forming the packaging layer 26 may be the same as or different from the material of the coating layer 23.

[0113] In addition, if the underfill 252 is not formed, the packaging layer 26 can cover the conductive bumps 251.

[0114] As Figure 2F shown, through a planarization process, such as grinding, part of the material on the second surface 23b of the coating layer 23 is removed to remove the bonding layer 91 together.

[0115] In this embodiment, the lower surfaces of the second circuit block 22, the first circuit block 21 and the circuit board 20 are flush with the second surface 23b of the coating layer 23, that is, the heights H of the second circuit block 22, the first circuit block 21, the circuit board 20 and the coating layer 23 are equal, so that the conductive posts 221 of the second circuit block 22, the circuit portions 21b of the first circuit block 21 and the circuit layer 201 of the circuit board 20 are all exposed on the second surface 23b of the coating layer 23.

[0116] As Figure 2G shown, a redistribution layer (RDL) process is performed to form a second circuit structure 27 on the second surface 23b of the coating layer 23, and the second circuit structure 27 is electrically connected to the conductive posts 221 of the second circuit block 22, the circuit portions 21b of the first circuit block 21 and the circuit layer 201 of the circuit board 20.

[0117] In this embodiment, the second circuit structure 27 includes at least one second insulating layer 270 and a second redistribution layer (RDL) 271 disposed on the second insulating layer 270, and the outermost second insulating layer 270 can be used as a solder mask layer so that the outermost second redistribution layer 271 is exposed from the solder mask layer.

[0118] In addition, the material forming the second circuit redistribution layer 271 is copper, and the material forming the second insulating layer 270 is a dielectric material such as poly(p - phenylene benzobisoxazole) (PBO), polyimide (PI), prepreg (PP), etc.

[0119] Furthermore, a plurality of conductive elements 28 electrically connecting to the second circuit redistribution layer 271 can be formed on the second circuit structure 27, and these conductive elements 28 are bonded to a support member (not shown). For example, the support member is a plate made of a semiconductor material, a dielectric material, a ceramic material, glass, or a metal material, but is not limited thereto, and the size of the support member can be selected as a wafer - form substrate or a general panel - form substrate according to requirements. An insulating temporary layer (not shown) such as a release film or an adhesive material can be provided thereon to embed these conductive elements 28 in the insulating temporary layer (not shown).

[0120] In addition, a planarization process can be performed to make the non - active surfaces 25b of the electronic components 25, 25' flush with the surface 26a of the encapsulation layer 26. For example, by means of grinding, part of the material of the electronic components 25, 25' and part of the material of the encapsulation layer 26 are removed.

[0121] As Figure 2H shown, the support member and the insulating temporary layer thereon are removed to expose the second circuit structure 27 and these conductive elements 28, and then a dicing process is performed along the dicing path L as Figure 2F shown to obtain the electronic package 2.

[0122] In subsequent processes, as Figure 3 shown, the electronic package 2 can be disposed on a package substrate 30 by using these conductive elements 28, and the conductive elements 28 are coated with an underfill 31. Then, a heat sink 33 is bonded to the non - active surfaces 25b of the electronic components 25, 25' of the electronic package 2 and the encapsulation layer 26 through its top sheet 330 by a heat - conductive adhesive 34, and the support legs 331 of the heat sink 33 are mounted on the package substrate 30 through an adhesive layer 35. Then, a plurality of solder balls (not shown) are formed on the lower side of the package substrate 30.

[0123] In this embodiment, the first circuit block 21 serves as a transfer part of the signal transfer path between these electronic components 25, 25' and the package substrate 30, and these second circuit blocks 22 serve as a transfer part of the power transfer path between these electronic components 25, 25' and the package substrate 30. For example, the first circuit block 21 transfers signals to the two electronic components 25, 25' respectively through the design of the circuit portions 21a, 21b (i.e., the first circuit block 21 serves as a bridging element between the two electronic components 25, 25').

[0124] Therefore, the manufacturing method of the present invention mainly relies on the design of the composite substrate 2a to embed the first circuit block 21 and the second circuit block 22 separately from the circuit board 20 in the coating layer 23. The first circuit block 21 serves as a signal transmission path, and the second circuit blocks 22 serve as power transmission paths. Therefore, compared with the prior art, the circuit layer 201 of the circuit board 20 of the present invention will not overheat, thus avoiding the problem of warping of the circuit board 20 and further avoiding the problem of fracture of the circuit layer 201 of the circuit board 20. In other words, when the functional requirements of the electronic components 25, 25' increase, the number of the first circuit block 21 and the second circuit blocks 22 can be increased according to the requirements, so that the circuit layer 201 of the circuit board 20 can be made into a fine circuit specification according to the requirements.

[0125] In addition, the electronic package 2 can be formed with a plurality of conductive structures 49 in the coating layer 23 according to requirements, such as Figure 4A and Figure 4B the composite substrate 4a shown. For example, the conductive structure 49 can be a metal column such as a copper pillar. Therefore, when the functional requirements of the electronic components 25, 25' increase, the number of the conductive structures 49 can be increased according to the requirements, so that the volume of the circuit board 40 can be miniaturized according to the requirements.

[0126] Furthermore, the first circuit block 21 can be located between two of the second circuit blocks 22, and the accommodation spaces S can be interconnected through a plurality of first grooves V1, such as Figure 4A and Figure 4B the electronic package 4 shown. For example, a plurality of second grooves V2 connecting the first circuit block 21 can be formed, so that the first grooves V1 and the second grooves V2 intersect perpendicularly to form a cross-shaped groove structure V. Therefore, the first circuit block 21 is located at the middle intersection of the cross-shaped groove structure V, and the second circuit blocks 22 are located on opposite sides of one of the grooves (i.e., the first groove V1) of the cross-shaped groove structure V, and the plurality of conductive structures 49 can be disposed in the cross-shaped groove structure V (i.e., the first groove V1 and the second groove V2). Specifically, the accommodation spaces S and the cross-shaped groove structure V divide the circuit board 40 into a plurality of (such as four) blocks 41, 42, 43, 44. It should be understood that the layout of the grooves can be designed according to requirements and is not limited to the cross-shaped groove structure V.

[0127] Therefore, through the design of these grooves, the bonding area of the coating layer 23 is increased, which helps to disperse the thermal stress and enhance the structural strength of the composite substrate 4a. Therefore, the sizes of the conductive posts 211 and 221 (and even the conductive structure 49) in the composite substrate 4a can be further reduced compared to other embodiments (such as the conductive posts 211 and 221 in the composite substrate 2a), thereby increasing the number of contacts (I / O) of the composite substrate 4a (or improving the density). In other words, when the functional requirements of the electronic components 25 and 25' increase, through the design of the grooves, the structural strength of the circuit board 40 can be strengthened, which is not only beneficial to the miniaturization design of the circuit board 40, but also can avoid the problem of warping caused by high temperature.

[0128] In addition, the composite substrates 2a and 4a of the present invention (which can be regarded as interposer boards) are made of insulating materials in cooperation with the RDL process, eliminating the use of existing silicon interposer boards, so the manufacturing cost can be significantly reduced and the incidence of warping can be reduced.

[0129] The present invention also provides an electronic package 2 and 4, including: a coating layer 23, a circuit board 20 and 40, a first circuit block 21 and a second circuit block 22, a first circuit structure 24, at least one electronic component 25 and 25', and a second circuit structure 27.

[0130] The coating layer 23 has opposite first and second surfaces 23a and 23b.

[0131] The circuit boards 20 and 40 are embedded in the coating layer 23.

[0132] The first circuit block 21 and the second circuit block 22 are embedded in the coating layer 23.

[0133] The first circuit structure 24 is formed on the first surface 23a of the coating layer 23 and is electrically connected to the circuit boards 20 and 40, the first circuit block 21, and the second circuit block 22.

[0134] The electronic components 25 and 25' are disposed on the first circuit structure 24 and are electrically connected to the first circuit structure 24.

[0135] The second circuit structure 27 is formed on the second surface 23b of the coating layer 23 and is electrically connected to the circuit boards 20 and 40, the first circuit block 21, and the second circuit block 22.

[0136] In one embodiment, the first circuit block 21 and the second circuit block 22 embedded in the coating layer 23 are arranged separately from each other.

[0137] In one embodiment, the circuit boards 20 and 40, the first circuit block 21, and the second circuit block 22 are separated from each other.

[0138] In one embodiment, the circuit boards 20, 40 have a receiving space S for disposing the first circuit block 21 and the second circuit block 22, and the coating layer 23 is further formed in the receiving space S to coat the first circuit block 21 and the second circuit block 22.

[0139] In one embodiment, the circuit board 40 is formed with a first groove V1 and a second groove V2. For example, the first groove V1 and the second groove V2 form a cross-shaped groove structure V. Further, the coating layer 23 is also formed in the first groove V1 and the second groove V2.

[0140] In one embodiment, a plurality of conductive structures 49 are embedded in the coating layer 23.

[0141] In one embodiment, the electronic packages 2, 4 further include a packaging layer 26 for coating the electronic components 25, 25'.

[0142] In one embodiment, the electronic packages 2, 4 further include a plurality of conductive elements 28 formed on the second circuit structure 27. [[ID=1S]]

[0143] In one embodiment, the first circuit block 21 has at least one insulator 210 (or semiconductor base), and at least one conductive column 211 embedded in the insulator 210 (or semiconductor base). For example, on at least one of the opposite sides of the insulator 210 (or semiconductor base), circuit portions 21a, 21b, 21c are formed to electrically connect the conductive column 211. Alternatively, the insulator 210 is a packaging material, and the semiconductor base contains silicon.

[0144] In one embodiment, the second circuit block 22 has at least one insulator 220 (or semiconductor base), and at least one conductive column 221 embedded in the insulator 220 (or semiconductor base). For example, on at least one of the opposite sides of the insulator 220 (or semiconductor base), circuit portions 21a, 21b, 21c are formed to electrically connect the conductive column 221. Alternatively, the insulator 220 is a packaging material, and the semiconductor base contains silicon.

[0145] In one embodiment, the circuit board 20 is a circuit structure without a core layer.

[0146] In one embodiment, a plurality of the electronic components 25, 25' are provided on the first circuit structure 24, and there is a gap between at least two of the plurality of electronic components 25, 25', so that the first circuit block 21 is correspondingly located at the gap to electrically bridge the two electronic components 25, 25'.

[0147] In summary, for the electronic package and its manufacturing method of the present invention, through the design of the composite substrate, the circuit block and the circuit board are separately embedded in the coating layer. Therefore, the circuit board of the present invention will not overheat, thus avoiding the problem of warping of the circuit board, and further avoiding the problem of fracture of the circuit layer of the circuit board. Moreover, by separately embedding the circuit block and the circuit board in the coating layer, the structural strength of the coating layer can be improved.

[0148] The above embodiments are used to exemplarily illustrate the principles and effects of the present invention, rather than to limit the present invention. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the rights protection of the present invention shall be as listed in the claims.

Claims

1. An electronic package, characterized in that, Comprising: A coating layer having opposite first and second surfaces; A circuit board formed with a plurality of grooves and embedded in the coating layer; A circuit block embedded in the coating layer; A first circuit structure formed on the first surface of the coating layer and electrically connecting the circuit board and the circuit block; An electronic component disposed on the first circuit structure and electrically connected to the first circuit structure; And A second circuit structure formed on the second surface of the coating layer and electrically connecting the circuit board and the circuit block, wherein the circuit board is provided with a receiving space for configuring the circuit block, and the coating layer is further formed in the receiving space and the plurality of grooves to coat the circuit block, and wherein the receiving space communicates with each other via the plurality of grooves.

2. The electronic package according to claim 1, wherein A plurality of the circuit blocks are embedded in the coating layer and are separately arranged.

3. The electronic package according to claim 1, wherein The circuit board and the circuit block are separated from each other.

4. The electronic package according to claim 1, wherein The plurality of grooves form a cross-shaped groove structure.

5. The electronic package according to claim 1, characterized in that, A plurality of conductive structures are also embedded in the coating layer.

6. The electronic package according to claim 1, wherein The electronic package further includes a packaging layer covering the electronic component.

7. The electronic package according to claim 1, wherein The electronic package further includes a plurality of conductive elements formed on the second circuit structure.

8. The electronic package according to claim 1, wherein The circuit block has at least one insulator or at least one semiconductor base, and at least one conductive post embedded in the insulator or the semiconductor base.

9. The electronic package according to claim 8, wherein, The insulator is a packaging material, and the semiconductor base contains silicon.

10. The electronic package according to claim 8, wherein A circuit portion electrically connecting the conductive post is formed on at least one of the opposite sides of the insulator or the semiconductor base.

11. The electronic package according to claim 1, characterized in that, The circuit board is a circuit structure without a core layer.

12. The electronic package according to claim 1, characterized in that, A plurality of the electronic components are disposed on the first circuit structure, and there is a gap between at least two of the plurality of electronic components, so that the circuit block is correspondingly located at the gap to electrically bridge the two electronic components.

13. A method for manufacturing an electronic package, characterized in that, Comprising: Separately disposing on a carrier a circuit board formed with a plurality of grooves and at least one circuit block; Forming a coating layer on the carrier to coat the circuit board and the circuit block, wherein the coating layer has opposite first and second surfaces, and the coating layer is bonded to the carrier with its second surface; Forming a first circuit structure on the first surface of the coating layer to electrically connect the first circuit structure to the circuit board and the circuit block; Disposing an electronic component on the first circuit structure and electrically connecting the electronic component to the first circuit structure; Removing the carrier; and Forming a second circuit structure on the second surface of the coating layer and electrically connecting the second circuit structure to the circuit board and the circuit block, wherein the circuit board is provided with a receiving space for configuring the circuit block, and the coating layer is further formed in the receiving space and the plurality of grooves to coat the circuit block, and wherein the receiving space communicates with each other via the plurality of grooves.

14. The method for manufacturing an electronic package as described in claim 13, wherein, A plurality of the circuit blocks are embedded in the coating layer and are separately arranged.

15. The method for manufacturing an electronic package as claimed in claim 13, wherein, The circuit board and the circuit block are separated from each other.

16. The method for manufacturing an electronic package according to claim 13, wherein, The plurality of grooves form a cross-shaped groove structure.

17. The method for manufacturing an electronic package according to claim 13, wherein, A plurality of conductive structures are also embedded in the coating layer.

18. The method for manufacturing an electronic package according to claim 13, wherein, The manufacturing method further includes coating the electronic component with a packaging layer.

19. The manufacturing method of the electronic package according to claim 13, characterized in that, The manufacturing method further includes forming a plurality of conductive elements on the second circuit structure.

20. The method for manufacturing an electronic package according to claim 13, wherein, The circuit block has at least one insulator or at least one semiconductor base, and at least one conductive post embedded in the insulator or the semiconductor base.

21. The method for manufacturing an electronic package as described in claim 20, characterized in that, The insulator is a packaging material, and the semiconductor base contains silicon.

22. The method for manufacturing an electronic package according to claim 20, wherein, A circuit portion electrically connecting the conductive posts is formed on at least one of the opposite sides of the insulator or the semiconductor base.

23. The method for manufacturing an electronic package according to claim 13, wherein, The circuit board has a circuit structure without a core layer.

24. The method for manufacturing an electronic package according to claim 13, wherein, A plurality of the electronic components are provided on the first circuit structure, and there is a gap between at least two of the plurality of electronic components, so that the circuit block is correspondingly located at the gap to electrically bridge the two electronic components.

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