Wafer having a local semiconductor-on-insulator region comprising a cavity structure

Abstract

The present invention relates to wafers having local semiconductor-on-insulator regions with cavity structures. The present disclosure relates to semiconductor structures, and more particularly to wafers with local cavity structures and methods of manufacture. One structure includes a bulk substrate having a local semiconductor-on-insulator (SOI) region and a bulk device region, the local SOI region including a substrate material of the bulk substrate and a plurality of cavity structures.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor structures, and more particularly to wafers having local cavity structures and methods of fabrication. BACKGROUND

[0002] When formed using a bulk semiconductor wafer, device structures such as radio frequency switches are susceptible to high capacitance and body-to-body leakage. To mitigate these issues, a silicon-on-insulator wafer can be used in place of a bulk wafer. A silicon-on-insulator wafer includes a buried insulator layer disposed between a body of an active device region providing a device structure and a body of a substrate located below the buried insulator layer. Another measure to mitigate the effects of high capacitance and body-to-body leakage is to provide a tri- well isolation around an active device region of a device structure. SUMMARY

[0003] In an aspect of the present disclosure, a structure includes a bulk substrate having a local silicon-on-insulator (SOI) region and a bulk device region, the local SOI region including a substrate material of the bulk substrate and a plurality of cavity structures.

[0004] In an aspect of the present disclosure, a structure includes at least one bulk device region including a bulk substrate material and a plurality of local silicon-on-insulator (SOI) device regions coplanar with the at least one bulk device region, the local SOI device regions including an upper layer of the bulk substrate material and a plurality of cavity structures having different depths within the bulk substrate material.

[0005] In an aspect of the present disclosure, a method includes forming an amorphous region of a first depth within a bulk substrate, forming an amorphous region of a second depth within the bulk substrate, removing the amorphous regions to form cavity structures at the first depth and the second depth, leaving a substrate material of the bulk substrate located above the cavity structures, and lining the cavity structures with an insulator material. BRIEF DESCRIPTION OF DRAWINGS

[0006] In the following detailed description, the present disclosure is described, by way of non-limiting example, with reference to the drawings mentioned.

[0007] Figure 1 A substrate and corresponding fabrication process are shown, among other features, in accordance with some aspects of the present disclosure.

[0008] Figure 2 An amorphous region in a substrate and corresponding fabrication process are shown, among other features, in accordance with some aspects of the present disclosure.

[0001] The present disclosure relates to semiconductor structures, and more particularly to wafers having local cavity structures and methods of fabrication. BACKGROUND

[0002] When formed using a bulk semiconductor wafer, device structures such as radio frequency switches are susceptible to high capacitance and body-to-body leakage. To mitigate these issues, a silicon-on-insulator wafer can be used in place of a bulk wafer. A silicon-on-insulator wafer includes a buried insulator layer disposed between a body of an active device region providing a device structure and a body of a substrate located below the buried insulator layer. Another measure to mitigate the effects of high capacitance and body-to-body leakage is to provide a tri- well isolation around an active device region of a device structure. SUMMARY

[0003] In an aspect of the present disclosure, a structure includes a bulk substrate having a local silicon-on-insulator (SOI) region and a bulk device region, the local SOI region including a substrate material of the bulk substrate and a plurality of cavity structures.

[0004] In an aspect of the present disclosure, a structure includes at least one bulk device region including a bulk substrate material and a plurality of local silicon-on-insulator (SOI) device regions coplanar with the at least one bulk device region, the local SOI device regions including an upper layer of the bulk substrate material and a plurality of cavity structures having different depths within the bulk substrate material.

[0005] In an aspect of the present disclosure, a method includes forming an amorphous region of a first depth within a bulk substrate, forming an amorphous region of a second depth within the bulk substrate, removing the amorphous regions to form cavity structures at the first depth and the second depth, leaving a substrate material of the bulk substrate located above the cavity structures, and lining the cavity structures with an insulator material. BRIEF DESCRIPTION OF DRAWINGS

[0006] In the following detailed description, the present disclosure is described, by way of non-limiting example, with reference to the drawings mentioned.

[0007] Figure 1 A substrate and corresponding fabrication process are shown, among other features, in accordance with some aspects of the present disclosure.

[0008] Figure 2 An amorphous region in a substrate and corresponding fabrication process are shown, among other features, in accordance with some aspects of the present disclosure.

[0001] The present disclosure relates to semiconductor structures, and more particularly to wafers having local cavity structures and methods of fabrication. BACKGROUND

[0002] When formed using a bulk semiconductor wafer, device structures such as radio frequency switches are susceptible to high capacitance and body-to-body leakage. To mitigate these issues, a silicon-on-insulator wafer can be used in place of a bulk wafer. A silicon-on-insulator wafer includes a buried insulator layer disposed between a body of an active device region providing a device structure and a body of a substrate located below the buried insulator layer. Another measure to mitigate the effects of high capacitance and body-to-body leakage is to provide a tri- well isolation around an active device region of a device structure. SUMMARY

[0003] In an aspect of the present disclosure, a structure includes a bulk substrate having a local silicon-on-insulator (SOI) region and a bulk device region, the local SOI region including a substrate material of the bulk substrate and a plurality of cavity structures.

[0004] In an aspect of the present disclosure, a structure includes at least one bulk device region including a bulk substrate material and a plurality of local silicon-on-insulator (SOI) device regions coplanar with the at least one bulk device region, the local SOI device regions including an upper layer of the bulk substrate material and a plurality of cavity structures having different depths within the bulk substrate material.

[0005] In an aspect of the present disclosure, a method includes forming an amorphous region of a first depth within a bulk substrate, forming an amorphous region of a second depth within the bulk substrate, removing the amorphous regions to form cavity structures at the first depth and the second depth, leaving a substrate material of the bulk substrate located above the cavity structures, and lining the cavity structures with an insulator material. BRIEF DESCRIPTION OF DRAWINGS

[0006] In the following detailed description, the present disclosure is described, by way of non-limiting example, with reference to the drawings mentioned.

[0007] Figure 1 A substrate and corresponding fabrication process are shown, among other features, in accordance with some aspects of the present disclosure.

[0008] Figure 2 An amorphous region in a substrate and corresponding fabrication process are shown, among other features, in accordance with some aspects of the present disclosure.

[0009] Figure 3 Additional amorphous regions in a substrate and corresponding fabrication processes are shown, among other features, in accordance with some aspects of the present disclosure.

[0010] Figure 4 Trenches in different device regions and corresponding fabrication processes are shown, among other features, in accordance with some aspects of the present disclosure.

[0011] Figure 5 Cavity structures in different device regions and corresponding fabrication processes are shown, among other features, in accordance with some aspects of the present disclosure.

[0012] Figure 6 Local semiconductor-on-insulator (SOI) regions with cavity structures filled with insulator material and corresponding fabrication processes are shown, among other features, in accordance with some aspects of the present disclosure.

[0013] Figure 7 Recrystallized semiconductor material of local SOI regions and corresponding fabrication processes are shown, among other features, in accordance with some aspects of the present disclosure.

[0014] Figure 8 Devices on recrystallized semiconductor material of bulk regions and local SOI regions and corresponding fabrication processes are shown, among other features, in accordance with some aspects of the present disclosure.

[0015] Figure 9 Structures are shown in accordance with further aspects of the present disclosure. DETAILED DESCRIPTION

[0016] The present disclosure relates to semiconductor structures, and more particularly to wafers with local cavity structures and methods of fabrication. More particularly, the present disclosure relates to local semiconductor-on-insulator (SOI) regions with cavity structures formed from bulk wafers (e.g., Si wafers). Advantageously, the present disclosure provides bulk and SOI devices on the same wafer, where the local SOI regions have cavity structures with different depths for variable design criteria.

[0017] In embodiments, local SOI regions with cavity structures are embedded within bulk wafers (e.g., Si). The local SOI regions with cavity structures will have variable substrate thicknesses (e.g., Tsi1, Tsi2, etc.). The thickness of the substrate in the local SOI regions can be varied by implant energy (e.g., argon implant energy). In embodiments, the cavity structures can be included in the buried oxide region of the local SOI regions, where the buried oxide also has a variable thickness. The cavity structures can also include partially oxidized pillars for heat spreading or bulk biasing.

[0018] The wafer also includes a bulk region that includes a buried poly region and / or a recrystallized region on the same wafer as the local SOI region. In this way, the bulk wafer (e.g., bulk region) can have a buried trap-rich / damage layer. The local SOI region and the bulk region are coplanar for device fabrication. For example, in embodiments, the bulk region can include passive devices, e.g., above the buried poly material; however, other regions of the wafer that include a local SOI region with a cavity structure can also include active devices.

[0019] The local SOI region with a cavity structure can be formed by an implantation process described in more detail herein. For example, an amorphous region can be formed using implantation of heavy species through a thin oxide layer. This leaves a thin c-Si layer above the amorphous region. After the amorphous Si region is removed by Si defect etching or similar etching during a shallow trench isolation (STI) process, a deep trench (DT) process, etc., the crystalline Si will be the upper semiconductor layer of the local SOI region.

[0020] The structures of the present disclosure can be manufactured in a variety of ways using a variety of tools. Generally, however, these methods and tools are used to form structures that are on the order of microns and nanometers in size. The methods (i.e., techniques) used to manufacture the structures of the present disclosure have been adopted from integrated circuit (IC) technology. For example, the structures are built on wafers and are realized in material films that are patterned by performing a photolithography process on top of the wafer. In particular, the manufacturing for the structures uses three basic building blocks: (i) deposition of a thin film of material on a substrate, (ii) application of a patterned mask on top of the film by photolithographic imaging, and (iii) selective etching of the film to the mask.

[0021] Figure 1 A substrate and corresponding manufacturing process are shown in accordance with some aspects of the present disclosure, among other features. More specifically, Figure 1 The structure 10 of FIG. 1 shows a substrate 12. The substrate 12 is a bulk wafer that is preferably composed of Si material. However, in embodiments, the substrate 12 can be composed of any suitable bulk substrate material, such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. In preferred embodiments, the substrate 12 includes any suitable crystal orientation (e.g., (100), (110), (111), or (001) crystal orientation).

[0022] Still referring to Figure 1, a pad material (e.g., oxide) 14 is deposited on the substrate 12. The pad oxide 14 may be deposited on the substrate 12 using any suitable deposition process. For example, the pad oxide 14 may be deposited on the substrate 12 using a chemical vapor deposition (CVD) process well known to those skilled in the art, and thus no further explanation is required.

[0023] Figure 2 Amorphous regions 20, 22 are shown in the substrate 12 and the corresponding fabrication process. As described in more detail below, the amorphous regions 20, 22 are formed at specific depths Tsi1 in the different device regions 100, 300 within the substrate 12 by an implantation process at a certain energy level. The implantation process causes the bulk material of the substrate 12 to be located above and below the amorphous regions 20, 22 in the different device regions 100, 300, effectively initiating the formation of local semiconductor-on-insulator (SOI) regions.

[0024] More specifically, in Figure 2 In the embodiment of the present invention, a mask 16 is deposited over the pad oxide material 14. The mask 16 is any known implantation mask and may include a layer of photosensitive material (e.g., an organic photoresist layer) applied by a spin coating process, then pre-baked, exposed to light projected through a photomask, post-baked, and developed using a chemical developer. It will be understood by those skilled in the art that the implantation mask 16 has a thickness and stopping power sufficient to prevent the masked area from receiving a certain dose of implanted ions.

[0025] The mask 16 is patterned to form openings 18 in the device regions 100, 300. The patterning of the mask 16 can be formed by conventional photolithography and etching methods known to those skilled in the art. For example, a resist formed above the mask 16 is exposed to energy (light) to form a pattern (opening). An etching process with selective chemistry (e.g., reactive ion etching (RIE)) is used to form one or more openings (patterns) 18 in the mask 16 through the openings in the resist. The resist can then be removed by a conventional oxygen ashing process or other known strippers. After the resist is removed, an implantation process is performed through the openings 18 to form amorphous regions 20, 22 in the different device regions 100, 300.

[0026] Still refer to Figure 2After patterning, an ion implantation process is performed through the openings 18 to form amorphous regions 20, 22. In an embodiment, the ion implantation process includes an argon implantation process to form the amorphous regions 20, 22 in the different device regions 100, 300. Depending on the energy level, the amorphous regions 20, 22 can be at different depths, e.g., the substrate 12 above the amorphous regions 20, 22 can have different thicknesses Tsi1. For example, the energy level of the argon implantation can be about 400 Kev, resulting in a thickness of about 50 nm. Those skilled in the art will appreciate that other energy levels and resulting thicknesses Tsi1are also contemplated herein, depending on the desired design performance of the final device formed in the different device regions 100, 200, 300.

[0027] Figure 3 Amorphous regions 24 at the device region 200 in the substrate 12 are shown, which are formed by another implantation process. In this implantation process, the amorphous regions 24 at the device region 200 in the substrate 12 will be formed at a different depth, e.g., the thickness of the substrate 12 above the amorphous regions 24 in the device region 200 can be a thickness Tsi2. In this embodiment, Tsi2> Tsi1. For example, using a different implantation energy (e.g., 300 Kev), a resulting thickness of Tsi2(e.g., 100 nm) can be achieved. This implantation process will effectively start to form a local silicon-on-insulator (SOI) region in the device region 200, which is of a different size than the one that will be achieved in the device region 100.

[0028] More specifically, in Figure 3 After peeling off the previous mask, a new implantation mask 16a is deposited over the pad oxide material 14. The mask 16a is patterned using conventional photolithography and etching methods known to those skilled in the art and already described herein to form openings 18 in the device region 200. After patterning, an argon ion implantation process is performed through the openings 18 to form amorphous regions 24 in the device region 200 at a depth of Tsi2. It will also be appreciated that by adjusting the energy level of the implantation process, the size of the amorphous regions 24 can also be adjusted, e.g., to make the amorphous regions 24 larger or smaller than the amorphous regions 20, 22.

[0029] In Figure 4, after the mask 16 is stripped, a liner material 26 is deposited on the liner material 14. In an embodiment, the liner material 26 can be a liner nitride material deposited by a conventional deposition method (e.g., CVD). After the liner material 26 is deposited, trenches 28a, 28b are formed in the structure using conventional photolithography and etching processes already described herein. In an embodiment, the trench 28 is provided in the device regions 100, 200 and extends into the amorphous regions 20, 24, or at least exposes the top surfaces of the amorphous regions 20, 24. On the other hand, the trench 28a is provided in the device region 300 and extends on the side of the amorphous region 22. In an embodiment, a sliver of c-Si (e.g., the crystalline substrate 12) is retained on the sidewalls of the trench 28a. As described with respect to Figure 5 As disclosed, during the liner oxidation step, the thin slice of c-Si (eg, crystalline substrate 12) will be fully oxidized.Trench 28a may serve as a deep trench isolation feature as described herein.

[0030] Figure 5 The formation of a cavity structure 30 and a corresponding manufacturing process are shown, among other features. In an embodiment, the cavity structure 30 extends from the trench 28 and is formed by removing the amorphous regions 20, 24. The cavity structure 30 can be formed by a selective etching process (e.g., a defect etching process). For example, the cavity structure 30 is formed by removing material from the amorphous regions 20, 24 using an etching chemistry that is selective to the amorphous material (e.g., the defect material) in the amorphous regions 20, 24. The etching process can be, for example, a secco etching process; however, other defect or amorphous material etching processes are contemplated herein.

[0031] Using a conventional oxidation process, trenches 28, 28 and cavity structures 30 are lined with oxide. The oxidation process results in the formation of partially or fully oxidized semiconductor (Si) pillars 12c between cavity structures 30. Pillars 12c can have different thicknesses, corresponding to different mask patterns. Furthermore, pillars 12c can be partially or fully oxidized based on their respective thicknesses, which can be adjusted through an implantation process. Partially or fully oxidized pillars 12c can provide heat dissipation or body biasing.

[0032] Figure 6An insulator (e.g., oxide) fill process of the cavity structures 30 and trenches 28, 28a is shown. The oxide fill process will partially fill the cavity structures 30 with oxide (or other insulator material) 34, while also forming shallow trench isolation structures 28' and deep trench isolation structures 28a'. In embodiments, the cavity structures 30 will not be completely filled with insulator material (e.g., oxide) due to pinch-off phenomena during the deposition process. Thus, the cavity structures 30 will include voids 36, providing additional insulating properties. A planarization process such as a chemical mechanical polishing (CMP) process can be performed to remove any excess insulator material on the surface of the structure.

[0033] In embodiments, a local SOI region is formed in the device regions 100, 200 by the combination of the cavity structures 30 (partially filled with insulator material) with the semiconductor material 12a above the cavity structures 30 and the substrate material 12 of the bulk wafer below the cavity structures 30. Those skilled in the art will appreciate that the cavity structures 30 partially filled with insulator material will form a buried oxide (BOX) 12b of the local SOI region.

[0034] Additionally, as Figure 6 shown, for example, the local SOI region will have upper semiconductor material 12a of different thicknesses (e.g., Tsi1 and Tsi2). As already described herein, the variable substrate thicknesses (e.g., Tsi1, Tsi2, etc.) are a result of the variable implant energies (e.g., argon implant energies). Further, in embodiments, the BOX region 12b (e.g., the partially filled cavity structures 30) can also have variable thicknesses, depending on the implant process, such as the depth of the implant used to form the amorphous region 24.

[0035] Figure 7 Re-crystallization of the semiconductor material of the local SOI region, among other features, and corresponding fabrication processes are shown. More specifically, as Figure 7 shown, the spacer materials 16, 26 are removed by an etch process and a subsequent rapid thermal anneal process. In embodiments, the etch process can be a hot phosphorous chemistry used to remove the spacer materials 16, 26. The removal of the spacer materials will form a coplanar surface for each of the device regions 100, 200, 300.

[0036] The rapid thermal anneal process will re-crystallize the upper semiconductor material 12a' of the local SOI region in the device regions 100, 200. Further, the rapid thermal anneal process will re-crystallize the amorphous material 22 in the device region 300, forming crystalline semiconductor material 38 between the deep trench isolation features 28a' in the bulk region (e.g., device region 300). In embodiments, the rapid thermal anneal process heats the substrate material to a high temperature (e.g., up to 1200 °C or higher) in a time range of several seconds or less.

[0037] In Figure 8 , devices 40 are formed in device regions 100, 200, 300. Devices 40 can be any active device formed by conventional fabrication processes, such as transistors. For example, devices 40 can be formed by either a gate-first or gate-last process well known to those skilled in the art, such that the present disclosure can be fully understood without further explanation. Devices 40 include gate dielectric material (e.g., high-k material) and sidewall spacers formed on sidewalls of gate electrode material, each of which can be implemented using conventional CMOS fabrication structures described herein. Source and drain regions are formed within the substrate material using conventional ion implantation processes or doped epitaxial material processes well known to those skilled in the art.

[0038] In embodiments, devices 40 in device region 300 will be disposed between deep trench isolation structures 28a' over recrystallized semiconductor material 38; however, depending on desired device performance, devices 40 in device regions 100, 200 (including local SOI regions with cavity structures) can be formed in alignment with cavity structures 30, 36 or pillars 12c. Thus, in this manner, different devices can now be formed in SOI technology and bulk technology by adjusting the substrate thickness (e.g., Tsi1, Tsi2, etc.) in SOI technology regions (e.g., device regions 100, 200).

[0039] Figure 9 Structures according to further aspects of the present disclosure are shown. In Figure 9 structure 10a, a further device region 400 is shown. This device region 400 includes a poly region 44 with passive devices 40a.

[0040] These structures can be utilized in system-on-a-chip (SoC) technology. As will be appreciated by those skilled in the art, an SoC is an integrated circuit (also known as a “chip”) that integrates all components of an electronic system onto a single chip or substrate. Because the components are integrated on a single substrate, an SoC consumes much less power and occupies much less area than a multi-chip design with equivalent functionality. As a result, SoCs are becoming a dominant force in the mobile computing (e.g., smartphones) and edge computing markets. SoCs are also commonly used in embedded systems and the Internet of Things.

[0041] The above-described process is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricant in raw wafer form (i.e., as a single wafer having many unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to the main board, or other higher level carrier) or in a multichip package (such as a ceramic carrier that has

[0042] The description of various embodiments of the present disclosure has been presented for purposes of illustration but is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure comprising a bulk substrate having a local semiconductor-on-insulator (SOI) region and a bulk device region, wherein the local SOI region comprises substrate material of the bulk substrate and a plurality of cavity structures, wherein the plurality of cavity structures have different sizes in different device regions of the local SOI region.

2. The semiconductor structure of claim 1, wherein the plurality of cavity structures are lined with an insulator material and include voids. 3 . The semiconductor structure of claim 2 , further comprising a shallow trench isolation structure extending to the plurality of cavity structures in the local SOI region. 4 . The semiconductor structure of claim 1 , wherein the substrate material above the cavity structure has a variable thickness in different device regions of the local SOI region. The structure of claim 4 , wherein the substrate material above the plurality of cavity structures is a crystalline Si material. 6 . The structure of claim 1 , wherein the bulk device region comprises a buried trap-rich / damage layer, a device located above the buried trap-rich / damage layer, and a deep trench isolation structure surrounding the buried trap-rich / damage layer. 7 . The semiconductor structure of claim 1 , wherein the bulk device region comprises a polycrystalline layer and passive devices located on the polycrystalline layer. The semiconductor structure of claim 1 , wherein the bulk device region and the local SOI region are coplanar. 9 . The semiconductor structure of claim 1 , further comprising partially oxidized semiconductor pillars located between the plurality of cavity structures.

10. A semiconductor structure comprising: at least one bulk device region comprising bulk substrate material; as well as a plurality of local semiconductor-on-insulator (SOI) device regions coplanar with the at least one bulk device region, the local SOI device regions comprising an upper layer of the bulk substrate material and a plurality of cavity structures having different depths within the bulk substrate material, The plurality of cavity structures located in different device regions have different sizes. The semiconductor structure of claim 10 , wherein the upper layer of the bulk substrate material is a crystalline Si material. 12 . The semiconductor structure of claim 10 , wherein the upper layer of the bulk substrate material in different device regions has different thicknesses over the plurality of cavity structures.

13. The semiconductor structure of claim 11, further comprising shallow trench isolation structures extending into the plurality of cavity structures, and the plurality of cavity structures are lined with the same insulator material used in the shallow trench isolation structures.

14. The semiconductor structure of claim 10, wherein the at least one bulk device region comprises a buried trap-rich / damage-rich layer and a device located above the buried trap-rich / damage-rich layer. 15 . The semiconductor structure of claim 10 , wherein the at least one bulk device region comprises a polycrystalline layer and passive devices located on the polycrystalline layer. 16 . The structure of claim 10 , further comprising one of fully oxidized semiconductor pillars and partially oxidized semiconductor pillars located between the plurality of cavity structures.

17. The structure of claim 10, further comprising a plurality of devices located in the plurality of local semiconductor-on-insulator (SOI) device regions and above the plurality of cavity structures, and at least one device located in the at least one bulk device region.

18. A method for manufacturing a semiconductor device, comprising: forming an amorphous region of a first depth within the bulk substrate; forming an amorphous region of a second depth within the bulk substrate; removing the amorphous region to form a cavity structure at the first depth and the second depth, leaving substrate material of the bulk substrate above the cavity structure; as well as lining the cavity structure with an insulator material, The cavity structure has different sizes in different device regions of the local SOI region.

Images