Resistive memory element having multiple input terminals

Abstract

The present invention relates to a resistive memory element having a plurality of input terminals, and discloses a structure of the resistive memory element and a method for forming the structure of the resistive memory element. The resistive memory element has a first electrode, a second electrode, a third electrode, and a switching layer. The first electrode is coupled to the switching layer, the second electrode is coupled to a side surface of the switching layer, and the third electrode is coupled to the switching layer.

Description

Technical Field

[0001] The present invention relates to the manufacture of integrated circuits and semiconductor devices, and more particularly to the structure of a resistive memory element and a method of forming the structure of a resistive memory element. Background Art

[0002] Resistive random access memory (ReRAM or RRAM) devices provide an embedded non-volatile memory technology. Since its resistive memory elements are non-volatile, the resistive random access memory device retains the stored data bits when these memory elements are not powered. The non-volatility of the resistive random access memory device is contrary to volatile memory technologies such as static random access memory (SRAM) devices (where the stored content is ultimately lost when power is turned off) and dynamic random access memory (DRAM) devices (where the stored content is lost if not refreshed regularly).

[0003] Different information storage states (high resistance state and low resistance state) representing the stored data bits are provided by changing the resistance on a switching layer, thereby storing data in the resistive memory element. To change the switching layer, a bias voltage can be applied, which is sufficient to create one or more filaments as conductive paths across the thickness of the switching layer, thereby writing the low resistance state. The filaments are also broken by applying a bias voltage to write the high resistance state.

[0004] There is a need for an improved structure of a resistive memory element and a method of forming the structure of a resistive memory element. Summary of the Invention

[0005] According to one embodiment of the present invention, a structure includes a resistive memory element having a first electrode, a second electrode, a third electrode, and a switching layer. The first electrode is coupled to the switching layer, the second electrode is coupled to a side surface of the switching layer, and the third electrode is coupled to the switching layer.

[0006] According to another embodiment of the present invention, a method includes forming a first electrode of a resistive memory element, forming a switching layer of the resistive memory element coupled to the first electrode, forming a second electrode of the resistive memory element coupled to a side surface of the switching layer, and forming a third electrode of the resistive memory element coupled to the switching layer. Brief Description of the Drawings

[0007] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate various embodiments of the invention and, together with the general description of the invention given above and the detailed description of the embodiments given below, serve to explain these embodiments of the invention. In these drawings, like reference numerals refer to like features in different views.

[0008] Figure 1-2 Schematic cross-sectional view showing a structure including a resistive memory element in a continuous manufacturing stage of a processing method according to an embodiment of the present invention.

[0009] Figure 3 Schematic cross-sectional view showing a structure including a resistive memory element according to an alternative embodiment of the present invention. Detailed Description of the Embodiments

[0010] Please refer to Figure 1 According to an embodiment of the present invention, structure 10 includes a resistive memory element 25, which can be disposed in a metallization level of the interconnect structure 30. The interconnect structure 30 can be fabricated by middle-of-line and back-end-of-line processing above the substrate 20. The resistive memory element 25 can be located above a metal feature 32 of one of the metallization levels (e.g., M2 metallization level) of the interconnect structure 30. The interconnect structure 30 includes interlayer dielectric layers 34, 36 that can be composed of a dielectric material such as silicon dioxide, and the metal feature 32 can be composed of a metal such as copper or aluminum.

[0011] The resistive memory element 25 includes a bottom electrode 44 in the interlayer dielectric layer 36 on the metal feature 32, a switching layer 46 above the bottom electrode 44, and an insulator layer 48 above the switching layer 46. The bottom electrode 44 can be composed of a metal, such as copper, platinum, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, or ruthenium, which can be selected based on factors such as oxidation resistance and work function difference with respect to the subsequently formed top electrode. The switching layer 46 can be composed of a metal oxide such as PCMO (Pr0.7Ca0.3MnO3), magnesium oxide, tantalum oxide, hafnium oxide, titanium oxide, or aluminum oxide, or can be composed of a transition metal nitride. The insulator layer 48 can be a dielectric layer composed of a dielectric material such as silicon dioxide or silicon nitride.

[0012] The bottom electrode 44 can be formed by depositing a layer of its constituent material and patterning the deposited layer using photolithography and etching processes. Then, the interlayer dielectric layer 36 is deposited and planarized to remove topography. To form the switching layer 46 and the insulator layer 48, layers of their constituent materials can be deposited above the interlayer dielectric layer 36 and the bottom electrode 44, and the deposited layers can be patterned using photolithography and etching processes.

[0013] The switching layer 46 may have a top surface 41, a bottom surface 43 opposite the top surface 41, side surfaces 45, and side surfaces 47 opposite the side surfaces 47. The insulator layer 48 may have side surfaces 49 aligned with the side surfaces 45, 47 of the switching layer 46 respectively, a bottom surface directly above the top surface 41 of the switching layer 46, and a top surface 51 opposite the bottom surface. The top surface 41 of the switching layer 46 contacts the insulator layer 48, and in one embodiment, the top surface 41 of the switching layer 46 may be in direct physical contact with the bottom surface of the insulator layer 48. In one embodiment, the insulator layer 48 may extend from the side surface 45 of the switching layer 46 to the side surface 47 of the switching layer 46. In one embodiment, the insulator layer 48 may completely cover the top surface 41 of the switching layer 46 so that the entire surface area of the top surface 41 is protected from, for example, subsequent processes for forming a top electrode.

[0014] The bottom electrode 44 is laterally located between the side surface 45 and the side surface 47 of the switching layer 46. The bottom electrode 44 is located below the bottom surface 43 of the switching layer 46. The bottom surface 43 of the switching layer 46 is coupled to the bottom electrode 44, and in one embodiment, the bottom surface 43 of the switching layer 46 may be in direct physical and electrical contact with the bottom electrode 44. The width of the bottom electrode 44 may be narrower than that of the switching layer 46. Thus, the bottom electrode 44 may only contact a portion of the bottom surface 43 of the switching layer 46. In this regard, the bottom electrode 44 may have a width W1, and the switching layer 46 and the insulator layer 48 may have a width W2 greater than the width W1 of the bottom electrode 44.

[0015] Please refer to Figure 2 wherein like reference numerals represent Figure 1 like features in, and in the next manufacturing stage of the processing method, an interlayer dielectric layer 38 of the interconnect structure 30 is formed above the partially completed resistive memory element 25. The interlayer dielectric layer 38 may be composed of a dielectric material similar to or the same as the dielectric materials of the interlayer dielectric layers 34, 36, such as silicon dioxide.

[0016] The top electrodes 50 and 52 of the resistive memory element 25 are formed in the interlayer dielectric layer 38. To form the top electrodes 50, 52, the interlayer dielectric layer 38 can be patterned using photolithography and etching processes to define openings 54, 56, a metal can be deposited in the openings 54, 56, and planarized using chemical mechanical polishing. The top electrodes 50, 52 can be composed of a metal deposited, for example, by physical vapor deposition, such as platinum, titanium, titanium nitride, tantalum, tantalum nitride, or ruthenium. In one embodiment, the top electrode 50 can be composed of the same metal as the top electrode 52, and the top electrodes 50, 52 can be formed simultaneously. In one embodiment, the top electrodes 50, 52 can be composed of different metals, and the top electrodes 50, 52 can be formed separately, for example, by the following process sequence: patterning the opening 54, forming the top electrode 50 by deposition and planarization, patterning the opening 56, and forming the top electrode 52 by deposition and planarization. The top electrodes 50, 52 are formed in a self-aligned manner because the top electrodes 50, 52 are not formed by depositing and patterning a conductor layer using photolithography and etching processes. A portion of the dielectric material of the interlayer dielectric layer 38 is located above the insulator layer 48 in the space between the top electrode 50 and the top electrode 52 and provides electrical isolation.

[0017] The top electrode 50 contacts the side surface 45 of the switching layer 46, and in one embodiment, the top electrode 50 can be in direct physical and electrical contact with the side surface 45 of the switching layer 46. The top electrode 52 contacts the side surface 47 of the switching layer 46, and in one embodiment, the top electrode 52 can be in direct physical and electrical contact with the side surface 47 of the switching layer 46. Thus, the bottom electrode 44 and the top electrodes 50, 52 contact different portions of the switching layer 46. The top electrode 50 can also overlap the top surface 51 of the insulator layer 48, the top electrode 52 can also overlap the top surface 51 of the insulator layer 48, and the top electrodes 50, 52 can contact the side surface 47 of the insulator layer 48. A portion of the interlayer dielectric layer 36 is located between the bottom electrode 44 and the top electrodes 50, 52 because the bottom electrode 44 is narrower than the switching layer 46. These portions of the interlayer dielectric layer 36 contribute to electrically isolating the bottom electrode 44 from the top electrodes 50, 52.

[0018] The resistive memory element 25 includes a plurality of terminals in the form of a bottom electrode 44, a top electrode 50, and a top electrode 52, which can be individually and separately biased at different bias voltages during operation. For example, the top electrode 50 and the top electrode 52 can be used as input terminals, which can be individually and separately biased at different bias voltages to provide low-resistance and high-resistance states during operation. In the setup operation of switching the switching layer 46 from the low-resistance state to the high-resistance state, the bias voltage applied from the voltage source 26 to the top electrode 50 can be used, while the bottom electrode 44 and the top electrode 52 are grounded. In the reset operation of switching the switching layer 46 from the high-resistance state to the low-resistance state, the bias voltage applied from the voltage source 28 to the top electrode 52 can be used, while the bottom electrode 44 and the top electrode 50 are grounded. To read the state of the resistive memory element 25, the bias voltage applied from another voltage source (not shown) to the bottom electrode 44 can be used, while the top electrode 50 and the top electrode 52 are floating.

[0019] The structure 10 can be used to implement logic gates. In this regard, the structure 10 can be used to provide in-memory computing capabilities. For example, the structure 10 can be used to implement an IMPLY gate, where the top electrode 50 and the top electrode 52 provide a plurality of input terminals for the resistive memory element 25, and these input terminals can be individually and separately biased at different bias voltages during operation. In this regard, a bipolar switching scheme can be used to apply the bias voltages to the top electrode 50 and the top electrode 52 to generate the truth table of the IMPLY gate. For example, initially, the resistive memory element 25 can be placed in the high-resistance state. Then, each of the top electrodes 50, 52 can receive a logic "1" equal to the set voltage, or be grounded to provide a logic "0", and the output of the bottom electrode 44 can be a logic "1", unless the top electrode 50 is grounded and the top electrode 52 is biased at the set voltage to output a logic "0".

[0020] Please refer to Figure 3 , where like reference numerals denote Figure 2similar features, and according to an alternative embodiment, the memory element 60 includes a switching layer 62 located on and in contact with the bottom electrode 44, electrodes 64, 66 coupled to the switching layer 62, and a top electrode 68 coupled to the switching layer 62. The switching layer 62 (functionally and compositionally similar to the switching layer 46) includes vertical segments 62a, 62b that are connected by a horizontal segment 62c to define a U-shaped non-planar configuration. The horizontal segment 62c of the switching layer 62 can be in direct physical and electrical contact with the bottom electrode 44. The electrode 64 can be in direct physical and electrical contact with the side surface 63 of the vertical segment 62a of the switching layer 62. The electrode 66 can be in direct physical and electrical contact with the side surface 65 of the vertical segment 62b of the switching layer 62. The top electrode 68 can be in direct physical and electrical contact with both vertical segments 62a, 62b of the switching layer 62. The space surrounded by the switching layer 62 and the top electrode 68 can be filled with the dielectric material of the interlayer dielectric layer 38.

[0021] The memory element 60 can be formed by depositing a partial thickness of the interlayer dielectric layer 38 after forming the bottom electrode 44. The electrodes 64, 66 can be formed by depositing and patterning a layer containing a metal (such as copper, platinum, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, or ruthenium). Then, the remaining thickness of the interlayer dielectric layer 38 is deposited and patterned using photolithography and etching processes to define an opening that is laterally located between the electrodes 64, 66. The switching layer 62 is deposited as a conformal coating within the opening, and then additional dielectric material is deposited and polished using chemical mechanical polishing to remove surface topography. The top electrode 68 is formed by depositing and patterning a metal layer.

[0022] The above method is used for the manufacture of integrated circuit chips. The manufacturer can distribute the resulting integrated circuit chips in the form of raw wafers (e.g., as a single wafer with multiple unpackaged chips), as bare chips, or in a packaged form. The chip can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate product or a final product. The final product can be any product that includes an integrated circuit chip, such as a computer product or a smartphone with a central processor.

[0023] Terms in this document that are modified by approximate language such as "about", "substantially", and "essentially" are not limited to the specified exact value. This approximate language can correspond to the precision of the instrument used to measure the value, and unless otherwise dependent on the precision of the instrument, can represent + / - 10% of the stated value.

[0024] In this document, terms such as "vertical" and "horizontal" are cited as examples to establish a reference framework and are not restrictive. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "orthogonal" refer to directions perpendicular to the horizontal plane as just defined. The term "lateral" refers to a direction within that horizontal plane.

[0025] A feature "connected" or "coupled" to another feature may be directly connected or coupled to the other feature, or there may be one or more intermediate features. If there are no intermediate features, the feature may be "directly connected" or "directly coupled" to the other feature. If there is at least one intermediate feature, the feature may be "indirectly connected" or "indirectly coupled" to the other feature. A feature "on" or "in contact with" another feature may be directly on or in direct contact with the other feature, or there may be one or more intermediate features. If there are no intermediate features, the feature may be directly "on" or "in direct contact with" the other feature. If there is at least one intermediate feature, the feature may be "not directly" "on" or "not in direct contact with" the other feature.

[0026] The descriptions of the various embodiments of the present invention are for illustrative purposes only and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are chosen to best explain the principles of the embodiments, practical applications, or technical improvements over technologies known in the market, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure of an integrated circuit, the structure comprising: A resistive memory element, comprising a first electrode, a second electrode, a third electrode, and a switching layer having a first side surface, a second side surface opposite to the first side surface, a bottom surface, and a top surface opposite to the bottom surface, the first electrode being coupled to the switching layer, the second electrode being coupled to the first side surface of the switching layer, and the third electrode being coupled to the second side surface of the switching layer; and An insulator layer, located on the top surface of the switching layer, wherein the second electrode overlaps with the insulator layer above the first side surface of the switching layer, and the third electrode overlaps with the insulator layer above the second side surface of the switching layer.

2. The structure according to claim 1, further comprising: An IMPLY gate, comprising the resistive memory element.

3. The structure according to claim 1, wherein, The insulator layer extends from the first side surface of the switching layer to the second side surface of the switching layer.

4. The structure according to claim 1, wherein, The first electrode is disposed below the bottom surface of the switching layer that is laterally located between the first side surface and the second side surface of the switching layer.

5. The structure according to claim 1, wherein, The insulator layer completely covers the top surface of the switching layer.

6. The structure according to claim 1, wherein, The bottom surface extends from the first side surface to the second side surface, and the first electrode is disposed below the bottom surface that is laterally located between the first side surface and the second side surface.

7. The structure according to claim 1, wherein, The second electrode is composed of a first metal, and the third electrode is composed of a second metal that is different in composition from the first metal.

8. A structure of an integrated circuit, the structure comprising: A resistive memory element, comprising a first electrode, a second electrode, a third electrode, and a switching layer having a first side surface, the first electrode being coupled to the switching layer, the second electrode being coupled to the first side surface of the switching layer, and the third electrode being coupled to the switching layer, wherein the resistive memory element includes a fourth electrode coupled to the switching layer, wherein the switching layer includes a first segment located on the first electrode, a second segment extending from the first segment to the fourth electrode, and a third segment extending from the first segment to the fourth electrode, wherein the first segment, the second segment, and the third segment of the switching layer and the fourth electrode surround a space filled with a dielectric material.

9. The structure according to claim 8, wherein, The second segment of the switching layer includes the first side surface, the third segment of the switching layer includes a second side surface, and the third electrode is coupled to the second side surface of the third segment of the switching layer.

10. The structure according to claim 8, wherein, The structure further includes: A substrate; and An interconnect structure, located above the substrate, wherein the resistive memory element is located in the interconnect structure, the first electrode is located in the interconnect structure below the second electrode and the third electrode, and the fourth electrode is located in the interconnect structure above the second electrode and the third electrode.

11. The structure according to claim 8, further comprising: An IMPLY gate, comprising the resistive memory element.

12. A method of forming a structure of an integrated circuit, the method comprising: Forming the first electrode of the resistive memory element; Forming the switching layer of the resistive memory element coupled to the first electrode, wherein the switching layer includes a first side surface, a second side surface opposite to the first side surface, a bottom surface, and a top surface opposite to the bottom surface; Forming an insulator layer on the top surface of the switching layer, Forming the second electrode of the resistive memory element coupled to the first side surface of the switching layer; and Form a third electrode of the resistive memory element coupled to the second side surface of the switching layer; Wherein, the second electrode overlaps with the insulator layer above the first side surface of the switching layer, and the third electrode overlaps with the insulator layer above the second side surface of the switching layer.

13. The method according to claim 12, further comprising: Form an interlayer dielectric layer above the switching layer and the first electrode; And Pattern a first opening and a second opening in the interlayer dielectric layer, Wherein, the second electrode is formed in the first opening patterned in the interlayer dielectric layer, and the third electrode is formed in the second opening patterned in the interlayer dielectric layer.

14. The method according to claim 12, wherein, The first electrode is located below the bottom surface of the switching layer, Wherein, the insulator layer extends from the first side surface of the switching layer to the second side surface of the switching layer.

15. The method according to claim 12, wherein, The second electrode is composed of a first metal, and the third electrode is composed of a second metal that is compositionally different from the first metal.

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